U.S. patent application number 16/690384 was filed with the patent office on 2020-03-19 for memory having different reliabilities.
The applicant listed for this patent is Infineon Technologies AG. Invention is credited to Michael Goessel, Thomas Kern, Albrecht Mayer.
Application Number | 20200089418 16/690384 |
Document ID | / |
Family ID | 61082276 |
Filed Date | 2020-03-19 |
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United States Patent
Application |
20200089418 |
Kind Code |
A1 |
Kern; Thomas ; et
al. |
March 19, 2020 |
MEMORY HAVING DIFFERENT RELIABILITIES
Abstract
The disclosure proposes a circuit including a memory which has a
multiplicity of memory cells, the memory having a first area and a
second area, at least one memory cell comprising a part of the
first area and a part of the second area, the first area having a
lower reliability than the second area, and the circuit being set
up in such a manner that first bits are stored in the first area
and second bits are stored in the second area. A circuit for
reading the memory and methods for writing to and reading the
memory are also disclosed.
Inventors: |
Kern; Thomas; (Aschheim,
DE) ; Goessel; Michael; (Mahlow, DE) ; Mayer;
Albrecht; (Deisenhofen, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Infineon Technologies AG |
Neubiberg |
|
DE |
|
|
Family ID: |
61082276 |
Appl. No.: |
16/690384 |
Filed: |
November 21, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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15670436 |
Aug 7, 2017 |
10489068 |
|
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16690384 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 11/5628 20130101;
G06F 11/076 20130101; G06F 11/073 20130101; G06F 11/079 20130101;
G06F 3/0619 20130101; G06F 11/1072 20130101 |
International
Class: |
G06F 3/06 20060101
G06F003/06; G11C 11/56 20060101 G11C011/56; G06F 11/10 20060101
G06F011/10; G06F 11/07 20060101 G06F011/07 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 17, 2016 |
DE |
102016115272.2 |
Claims
1. A circuit, comprising: a memory which comprises a multiplicity
of memory cells, wherein the memory comprises a first area and a
second area, wherein at least one memory cell of the multiplicity
of memory cells comprises a part of the first area and a part of
the second area, wherein the first area has a lower reliability
than the second area, wherein the circuit is configured such that
first bits are stored in the first area and second bits are stored
in the second area.
2. The circuit as claimed in claim 1, wherein the memory cells
assume physical values on the basis of the digital values stored
therein, frequency distributions of the physical values which
correspond to different digital values in the second area having a
smaller overlap than frequency distributions which correspond to
different digital values in the first area.
3. The circuit as claimed in claim 1, wherein more than two values
are stored for each memory cell.
4. The circuit as claimed in claim 1, wherein the memory is a
non-volatile memory.
5. The circuit as claimed in claim 1, wherein a second bit exists
for at least one first bit, which second bit is stored in the same
memory cell.
6. The circuit as claimed in claim 5, wherein a second bit exists
for each first bit, which second bit can be stored in the same
memory cell.
7. The circuit as claimed in claim 5, wherein the first bits and
the second bits are different.
8. The circuit as claimed in claim 1, wherein, in the error-free
case, one of the first bits stored in the memory and/or one of the
second bits stored in the memory is/are a bit of a code word of an
error code.
9. The circuit as claimed in claim 8, wherein, in the error-free
case, a code word of the error code is determined on the basis of
the first bits stored in the memory, address bits and/or bits
derived from address bits.
10. The circuit as claimed in claim 1, wherein, in the error-free
case, one of the first bits stored in the memory is a bit of a code
word of a first error code.
11. The circuit as claimed in claim 1, wherein, in the error-free
case, one of the second bits stored in the memory is a bit of a
code word of a second error code.
12. The circuit as claimed in claim 10, wherein the first error
code and the second error code are different or identical error
codes.
13. The circuit as claimed in claim 10, wherein the first error
code has a higher correction power than the second error code.
14. The circuit as claimed in claim 10, which is set up in such a
manner that first bits corrected using the first error code are
provided from the first area when reading the memory.
15. The circuit as claimed in claim 14, comprising a further
memory, the circuit configured such that the corrected first bits
are stored in the further memory.
16. The circuit as claimed in claim 15, the circuit configured such
that the corrected first bits are coded using a further error code
and are stored in the further memory.
17. The circuit as claimed in claim 16, wherein, in the error-free
case, a code word of the further error code can be determined on
the basis of the bits stored in the further memory, address bits
and/or bits derived from address bits.
18. The circuit as claimed in claim 1, wherein the further memory
is a volatile or non-volatile memory.
19. The circuit as claimed in claim 1, which is set up such that:
the memory cell of the memory is written to or read using at least
three reference values R.sub.l, R.sub.m, R.sub.r, where
R.sub.l<R.sub.m<R.sub.r, a value z being stored in the memory
cell, the value of one bit of the second bits being determined by
comparing the value z with the reference value R.sub.m, and the
value of one bit of the first bits being determined by comparing
the value z with the reference value R.sub.m and with at least one
further reference value which differs from the reference value
R.sub.m.
20. The circuit as claimed in claim 19, wherein the memory cell is
written to in such a manner that the following applies to the value
z in the error-free case: |R.sub.l-z|<|R.sub.m-z| for
z<R.sub.m and |R.sub.r-z|<|R.sub.m-z| for z>R.sub.m.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 15/670,436 filed Aug. 7, 2017 claims priority to German
Application number 10 2016 115 272.2 filed on Aug. 17, 2016, the
contents of which are incorporated by reference in their
entirety.
FIELD
[0002] This disclosure is directed to a memory and a method for
storing a plurality of values in individual memory cells of a
volatile or non-volatile memory.
BACKGROUND
[0003] It is known practice to store a plurality of values in
individual memory cells of a volatile or non-volatile memory.
SUMMARY
[0004] The disclosure is directed to storing bits in a memory.
[0005] The disclosure includes a circuit that comprises a memory
which has a multiplicity of memory cells. The memory has a first
area and a second area, and at least one memory cell comprises a
part of the first area and a part of the second area, wherein the
first area has a lower reliability than the second area. The
circuit is configured such that first bits are stored in the first
area and second bits are stored in the second area.
[0006] The circuit may be, for example, a memory apparatus,
possibly with additional wiring for writing and/or reading.
[0007] The first bits may also be considered to be a first piece of
information and the second bits may also be considered to be a
second piece of information. The first information may differ from
the second information. For example, the first information may
contain data and the second information may contain program code or
vice versa. On account of its subdivision into two areas, for
example LSB and MSB, the memory cell can be used to store the
different information. The first area having the lower reliability
can be provided with error correction, for example. The second area
can also be provided with (possibly less complicated) error
correction.
[0008] It is a development that the memory cells assume physical
values on the basis of the digital values stored therein, frequency
distributions of the physical values which correspond to different
digital values in the second area having a smaller overlap than
frequency distributions which correspond to different digital
values in the first area.
[0009] Each digital value stored in an area of a memory cell
corresponds (for example during reading) to a frequency
distribution of physical values. In order to be able to therefore
distinguish the stored digital value from another digital value
with a high degree of certainty during reading, the frequency
distributions of the physical values belonging to the two digital
values preferably do not have an overlap or have only a small
overlap. For the area which is intended to ensure the higher
reliability, the digital values stored in this area are converted
into physical values which are spaced sufficiently far apart from
one another in order to achieve (more) reliable detection during
reading.
[0010] Accordingly, it holds true for the digital values stored in
the first area of lower reliability that the associated frequency
distributions of the physical values belonging to these digital
values may have a greater overlap. For example, error detection
and/or error correction can be provided for these digital values
which can be read with lower reliability from the first area (in
comparison with the second area of higher reliability) in order to
thus increase the reliability. It is naturally also possible to
provide error detection and/or error correction for the second
area.
[0011] The areas are, for example, MSBs or LSBs of the memory
cells. For example, the LSBs may have a higher reliability than the
MSBs provided that the frequency distributions of the digital
values in which the LSBs are 0 differ from the frequency
distributions of the digital values in which the LSBs are 1. This
is the case when the frequency distributions do not have any
overlaps. A plurality of frequency distributions in which the LSBs
have the value 0 can therefore also be interpreted as the frequency
distribution in which the LSB=0. A corresponding situation applies
to LSB=1.
[0012] It is a development that more than two values can be stored
for each memory cell.
[0013] In particular, it is an option that more than two bits, in
particular more than four values, are stored for each memory
cell.
[0014] It is a development that the memory is a non-volatile
memory.
[0015] It is a development that a second bit exists for at least
one first bit, which second bit is stored in the same memory cell
of the memory.
[0016] It is a development that a second bit exists for each first
bit, which second bit can be stored in the same memory cell of the
memory.
[0017] It is a development that the first bits and the second bits
are different.
[0018] It is a development that, in the error-free case, one of the
first bits stored in the memory and/or one of the second bits
stored in the memory is/are a bit of a code word of an error
code.
[0019] The error code may be an error-detecting and/or
error-correcting code.
[0020] It is a development that, in the error-free case, a code
word of the error code can be determined on the basis of the first
bits stored in the memory, address bits and/or bits derived from
address bits.
[0021] In particular, the memory is therefore an addressable memory
and the bits of the address or bits derived therefrom can be taken
into account when determining the code word. Therefore, the first
bits or some of the first bits, in conjunction with the address
bits and/or the derived bits, constitute a code word in the
error-free case. In contrast, if there is a writing error, this can
be detected and possibly corrected on the basis of the error
code.
[0022] In particular, it is an option that the address bits or the
derived bits (from the address bits) are stored in the memory.
[0023] Address errors can be detected, for example, from the fact
that a code word is not present.
[0024] It is a development that, in the error-free case, one of the
first bits stored in the memory is a bit of a code word of a first
error code.
[0025] It is a development that, in the error-free case, one of the
second bits stored in the memory is a bit of a code word of a
second error code.
[0026] It is a development that the first error code and the second
error code are different or identical error codes.
[0027] It is a development that the first error code has a higher
correction power than the second error code.
[0028] Since the first area has a lower reliability than the second
area, the first error code can be designed in such a manner that it
enables corresponding higher error correction than the second error
code.
[0029] It is a development that the circuit is set up in such a
manner that first bits corrected using the first error code are
provided when reading the memory from the first area.
[0030] It is a development that the circuit comprises a further
memory, the circuit being set up in such a manner that the
corrected first bits are stored in the further memory.
[0031] It is a development that the circuit is set up in such a
manner that the corrected first bits are coded using a further
error code and are stored in the further memory.
[0032] In this case, it is advantageous that the bits which have
been read from the first area of the (first) memory are stored,
after correction with the first error code, in the further (second)
memory again in a manner protected with the further error code.
Despite the lower reliability of the first area of the first
memory, it is therefore ensured with a high degree of probability
that the first bits can be finally processed further in an
error-free (possibly corrected) manner.
[0033] It is a development that in the error-free case, a code word
of the further error code can be determined on the basis of the
bits stored in the further memory, address bits and/or bits derived
from address bits.
[0034] In particular, the memory is therefore an addressable memory
and the bits of the address or bits derived therefrom can be taken
into account when determining the code word. Therefore, the first
bits or some of the first bits corrected using the first error
code, in conjunction with the address bits and/or the derived bits,
constitute a code word of the further error code in the error-free
case. If there is a writing error, this can be detected and
possibly corrected on the basis of the further error code when
reading the data coded in this manner from the further memory.
[0035] In particular, it is an option that the address bits or the
derived bits (from the address bits) are stored in the memory.
[0036] It is a development that the further memory is a volatile or
non-volatile memory.
[0037] It is a development that the circuit is configured such that
the memory cell of the memory is written to or read using at least
three reference values R.sub.l, R.sub.m, R.sub.r, where
R.sub.l<R.sub.m<R.sub.r, and a value z being stored in the
memory cell. The value of one bit of the second bits is determined
by comparing the value z with the reference value R.sub.m, and the
value of one bit of the first bits being determined by comparing
the value z with the reference value R.sub.m and with at least one
further reference value which differs from the reference value
R.sub.m.
[0038] It is a development that the memory cell is written to in
such a manner that the following applies to the value z in the
error-free case:
|R.sub.l-z|<|R.sub.m-z| for z<R.sub.m and
|R.sub.r-z|<|R.sub.m-z| for z>R.sub.m.
[0039] A circuit is also disclosed, and comprises a memory which
has a multiplicity of memory cells. The memory has a first area and
a second area, with at least one memory cell comprising a part of
the first area and a part of the second area. The circuit further
comprises a first processing unit for the first area, the first
processing unit reading and processing first bits from the first
area, and a second processing unit for the second area, the second
processing unit reading and processing second bits from the second
area.
[0040] Therefore, there are two processing units which are
responsible for reading the bits from the memory cells of the
memory, one of the processing units reading and processing the bits
from some of the memory cells. The processing may comprise, for
example, error detection and/or error correction.
[0041] It is a development that error detection and/or error
correction can be carried out using the first processing unit.
[0042] It is a development that the first bits read using the first
processing unit are a code word of a first error code in the
error-free case.
[0043] It is a development that error detection and/or error
correction can be carried out using the second processing unit.
[0044] It is a development that the second bits read using the
second processing unit are a code word of a second error code in
the error-free case.
[0045] The first error code and the second error code may be
identical or different error codes.
[0046] It is development that the first area has a lower
reliability than the second area.
[0047] A method for storing bits in a memory is also stated,
wherein the memory has a multiplicity of memory cells, and has a
first area and a second area. At least one memory cell comprises a
part of the first area and a part of the second area, wherein the
first area has a lower reliability than the second area. The method
comprises storing first bits in the first area and second bits in
the second area.
[0048] It is a development that the memory cells assume physical
values on the basis of the digital values stored therein, frequency
distributions of the physical values which correspond to different
digital values in the second area having a smaller overlap than
frequency distributions which correspond to different digital
values in the first area.
[0049] A method for processing bits from a memory is also proposed,
wherein the memory has a multiplicity of memory cells, and wherein
the memory has a first area and a second area. Further, at least
one memory cell comprises a part of the first area and a part of
the second area. The method comprises reading and processing first
bits from the first area using a first processing unit, and reading
and processing second bits from the second area using a second
processing unit.
[0050] It is a development that the processing respectively
comprises error detection and/or error correction.
[0051] It is noted that the circuit or the processing unit
mentioned here may comprise, for example, a processor unit and/or
an at least partially hard-wired or logical circuit arrangement
which is set up, for example, in such a manner that the method as
described herein can be carried out.
[0052] In particular, any type of processor or computer with
accordingly required peripherals (memory, input/output interfaces,
input/output devices, etc.) may be provided for the circuit and/or
the processing unit.
[0053] The above explanations relating to the method accordingly
apply to the apparatus and conversely the features of the method
may be combined with the features of the apparatus (circuit).
[0054] Furthermore, the circuit may be implemented in one component
or in a manner distributed in a plurality of components.
[0055] The above-mentioned object is also achieved by means of a
system comprising at least one of the circuits described here.
[0056] Furthermore, in another embodiment the disclosure specifies
a computer program product which can be directly loaded into a
memory of a digital computer, comprising program code parts which
are suitable for carrying out steps of the method described
here.
[0057] In one embodiment the computer-readable storage medium
comprises instructions which can be executed by a computer and are
suitable for the computer to carry out the method(s) described
here.
[0058] The above-described properties, features and advantages of
this disclosure and the manner in which they are achieved are
described below in connection with a schematic description of
exemplary embodiments which are explained in more detail in
connection with the drawings. In this case, identical or
identically acting elements may be provided with identical
reference symbols for clarity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0059] In the drawings:
[0060] FIG. 1 shows a graph comprising two frequency distributions
of analog values, which may be obtained when reading binary memory
cells, and a reference value, the frequency distributions not
having an overlap area;
[0061] FIG. 2 shows a graph comprising two frequency distributions,
which may be obtained when reading binary memory cells, and a
reference value, the frequency distributions having an overlap
area;
[0062] FIG. 3 shows a graph comprising four frequency
distributions, which may be obtained when reading binary memory
cells, and three reference values between each two of the frequency
distributions and three overlap areas in the region of the
reference values;
[0063] FIG. 4 shows a graph comprising four frequency
distributions, which may be obtained when reading binary memory
cells, and three reference values between each two of the frequency
distributions and only two overlap areas;
[0064] FIG. 5 shows a graph comprising three frequency
distributions, which may be obtained when reading binary memory
cells, and two reference values between each two of the frequency
distributions and only one overlap area;
[0065] FIG. 6 shows an example diagram of a memory, wherein data
can be stored in 64 memory cells for each address, and wherein each
memory cell can store four different digital values;
[0066] FIG. 7 shows an alternative diagram of a memory, wherein
data can be stored in 72 memory cells for each address, and wherein
each memory cell can store four different digital values;
[0067] FIG. 8 shows an example diagram of a memory which can be
provided as a second memory and is possibly used to store the LSBs
read from a first memory;
[0068] FIG. 9 shows an example diagram of a first memory provided,
by way of example, for the second memory according to FIG. 8;
[0069] FIG. 10a shows an example circuit arrangement in which the
LSB is stored in a memory cell of a (first) memory with a greater
reliability than the MSB;
[0070] FIG. 10b shows an example circuit arrangement which is based
on FIG. 10a and additionally also provides the LSBs with an error
code and an associated correction possibility;
[0071] FIG. 10c shows an example circuit arrangement which is based
on FIG. 10a or FIG. 10b, wherein a further encoder and a further
correction unit are provided for the data stored in the second
memory;
[0072] FIG. 10d shows an example circuit arrangement which is based
on FIG. 10a, wherein the encoder and the correction unit also take
into account the address of the first memory;
[0073] FIG. 10e shows an example circuit arrangement which is based
on FIG. 10b, wherein the encoder and the correction unit of the
LSBs also take into account a function derived from the address of
the first memory;
[0074] FIG. 10f shows an example circuit arrangement which is based
on FIG. 10c, wherein the further encoder and the further correction
unit also take into account the address of the second memory;
[0075] FIG. 11 shows a graph for illustrating the threshold voltage
Vth with regard to the voltage VGS at the control gate of the
memory cell.
DETAILED DESCRIPTION
[0076] A memory cell may assume different physical values or states
which correspond to different digital values.
[0077] The following abbreviations, in particular, are used
below:
[0078] G: a physical value, for example a current, a voltage, a
resistance;
[0079] W.sub.G: a physical value of a memory cell;
[0080] W.sub.D: a digital value to be stored in a memory cell;
[0081] W.sub.A: a physical value read from a memory cell;
[0082] LSB: the least significant bit;
[0083] MSB: the most significant bit.
[0084] It is possible, for example, for a physical value of a
memory cell to be an electrical resistance. In this case, a larger
resistance may correspond to a digital binary value 0 and a smaller
resistance may correspond to a digital binary value 1. It is also
possible for the larger resistance to correspond to the binary
value 1 and for the smaller resistance to correspond to the binary
value 0.
[0085] When storing or writing a piece of information in/to a
memory cell, the physical value or state of the memory cell is
determined in such a manner that it corresponds to the digital
value to be stored.
[0086] It is possible, for example, for a duration of the operation
of writing to the memory cell and/or for a writing current to
determine the physical value W.sub.G or the state of the memory
cell and therefore the digital value stored therein.
[0087] When reading the memory cell, it is possible to determine a
physical analog value W.sub.A which depends on the state W.sub.G of
the memory cell which was determined when writing the information
to the memory cell. In the error-free case, the associated stored
value W.sub.D results from the value W.sub.A which has been read.
This value W.sub.D is also referred to herein as a digital value or
binary value, by way of example.
[0088] If, for example, different electrical resistance values
correspond to the different states, a current which depends on the
resistance of the memory cell and therefore on the stored digital
value may be output when reading the information stored in the
memory cell. For example: W.sub.G is a resistance value, W.sub.A is
a current intensity and W.sub.D is a binary value 0 or 1 (or
another digital value).
[0089] When reading a piece of information from a memory cell, the
value W.sub.A which has been read can be compared with a reference
value R.
[0090] If a larger resistance corresponds to the binary value 0 and
a smaller resistance corresponds to the binary value 1, the
following results for the value W.sub.A of the current intensity
which has been read: a smaller value of the current intensity
corresponds to the binary value 0 and a larger value of the current
intensity corresponds to the binary value 1.
[0091] Accordingly, a voltage can be determined when reading a
memory cell, the level of which voltage depends on whether the
binary value 0 or the binary value 1 has been previously written to
the memory cell.
[0092] Alternatively, it is possible for a value of another
physical variable to be determined during reading, which value
depends on whether the binary value 0 or the binary value 1 has
previously been written to the memory cell.
[0093] If the digital value W.sub.D is determined by comparing the
value W.sub.A which has been read with the reference value R, the
following may apply to the digital value W.sub.D:
W D = { 0 for W A < R 1 for W A .gtoreq. R ##EQU00001##
[0094] If the binary value 0 is written to a plurality of memory
cells, these memory cells assume different values of the physical
value W.sub.G, which are all assigned to the binary value W.sub.D=0
in the error-free case, for example on account of random effects.
The physical values W.sub.G can be described by means of a
frequency distribution having a mean value or expected value
E.sub.G(0). Accordingly, the values W.sub.A which are read from the
memory cells also assume different values which can be described by
means of a frequency distribution having an expected value
E.sub.A(0).
[0095] This analogously applies to memory cells to which the binary
value 1 is written. If the binary value 1 is written to a plurality
of memory cells, these memory cells assume different values of the
physical value W.sub.G, which all correspond to the binary value
W.sub.D=1 in the error-free case and can be described by means of a
frequency distribution having a mean value or expected value
E.sub.G(1), for example on account of random effects. The values
W.sub.A which are read from the memory cells also assume different
values which can be described by means of a frequency distribution
having an expected value E.sub.A(1).
[0096] These statements accordingly apply if it is possible to
store more than one bit in a memory cell.
[0097] FIG. 1 shows, by way of example, two frequency distributions
of analog values W.sub.A which can be obtained when reading binary
memory cells. One frequency distribution W.sub.A(0) has an expected
value E.sub.A(0) and one frequency distribution W.sub.A(1) has an
expected value E.sub.A(1). The frequency distribution W.sub.A(0)
corresponds to the digital value 0 and the frequency distribution
W.sub.A(1) corresponds to the digital value 1.
[0098] The range of values of the possible physical values W.sub.A
is subdivided into two ranges by means of a reference value R.
[0099] Since the frequency distribution W.sub.A(0) and the
frequency distribution W.sub.A(1) do not overlap in the example
shown in FIG. 1, incorrect assignment of the binary values 0 or 1
does not occur.
[0100] FIG. 2 shows, by way of example, two frequency distributions
of analog values W.sub.A comprising a frequency distribution
W.sub.A(0) and a frequency distribution W.sub.A(1) which are
subdivided into two ranges by means of a reference value R. Again,
the frequency distribution W.sub.A(0) corresponds to the binary
value 0 and the frequency distribution W.sub.A(1) corresponds to
the binary value 1. The frequency distributions W.sub.A(0) and
W.sub.A(1) have an overlap area 201, also referred to as overlap
area [0, 1]. For this overlap area 201, it is initially not clearly
determined whether an analog value W.sub.A therein should be
assigned to the binary value 0 or to the binary value 1.
[0101] If the binary value 0 is assigned to an analog value W.sub.A
which has been read, if W.sub.A<R, and if the binary value 1 is
assigned, if W.sub.A.gtoreq.R, it is possible that a value is
stored as a binary value 0 or 1 is incorrectly read if the analog
value W.sub.A is in the overlap area 201.
[0102] FIG. 3 shows, by way of example, frequency distributions of
analog values W.sub.A which may be obtained when reading polyvalent
memory cells (also referred to as multi-level memory cells). In
this case, it is assumed that four different values 0, 1, 2 and 3
can be stored in a memory cell. Accordingly, the frequency
distributions W.sub.A(0), W.sub.A(1), W.sub.A(2) and W.sub.A(3) are
shown for these values in FIG. 3, wherein
[0103] a reference value R.sub.-1 is present in an overlap area 301
between the frequency distribution W.sub.A(0) and the frequency
distribution W.sub.A(1),
[0104] a reference value R.sub.0 is present in an overlap area 302
between the frequency distribution W.sub.A(1) and the frequency
distribution W.sub.A(2), and
[0105] a reference value R.sub.1 is present in an overlap area 303
between the frequency distribution W.sub.A(2) and the frequency
distribution W.sub.A(3).
[0106] The range of values of the analog values W.sub.A is
therefore subdivided into four ranges using the three reference
values R.sub.0, R.sub.1 and R.sub.-1, where:
R.sub.-1<R.sub.0<R.sub.1.
[0107] If the digital value W.sub.D is determined by comparing the
analog value W.sub.A which has been read with the reference values
R.sub.0, R.sub.1 and R.sub.-1, the following applies according to
the example shown in FIG. 3:
W D = { 0 for W A < R - 1 1 for R - 1 .ltoreq. W A < R 0 2
for R 0 .ltoreq. W A < R 1 3 for W A .gtoreq. R 1
##EQU00002##
[0108] In the example shown in FIG. 3, the frequency distributions
overlap: the frequency distributions W.sub.A(0) and W.sub.A(1)
overlap in the overlap area 301 for the analog values which
correspond to the values 0 and 1; this overlap area 301 is also
referred to as overlap area [0, 1]. The frequency distributions
W.sub.A(1) and W.sub.A(2) overlap in the overlap area 302 for the
analog values which correspond to the values 1 and 2; this overlap
area 302 is also referred to as overlap area [1, 2]. The frequency
distributions W.sub.A(2) and W.sub.A(3) overlap in the overlap area
303 for the analog values which correspond to the values 2 and 3;
this overlap area 303 is also referred to as overlap area [2,
3].
[0109] On account of the overlap area 301, a value 1 may be
incorrectly determined from the analog value which is read even
though the value 0 was written to the memory cell. Conversely, a
value 0 may be incorrectly determined from the analog value which
is read even though the value 1 was written to the memory cell.
Corresponding statements apply to the pairs of values [1, 2] and
[2, 3].
[0110] If the overlap area 301 exists, it is possible for the
reliability of the correct storage of the values 0 and 1 to be
lower than if there were no overlap area 301. In particular, errors
may arise when reading the memory; these errors are also referred
to as read errors.
[0111] The relative frequency of an analog value W.sub.A(0) being
in the overlap area 301 influences the reliability of the correct
storage of the value 0. The relative frequency of an analog value
W.sub.A(1) being in the overlap area 301 likewise influences the
reliability of the correct storage of the value 1.
[0112] If no further errors have occurred, the reliability of the
correct storage of the value 0 is determined by the relative
frequency of the analog value W.sub.A(0) being in the overlap area
301. The following accordingly applies: if no further errors have
occurred, the reliability of the correct storage of the value 1 is
determined by the relative frequency of the analog value W.sub.A(1)
being in the overlap area 301.
[0113] A corresponding situation applies to the reliability of the
storage of all four digital values in a multi-level memory cell
which can assume the four values 0, 1, 2 or 3. The reliability is
influenced by the relative frequencies of the analog values
W.sub.A(0), W.sub.A(1), W.sub.A(2) and W.sub.A(3) being in the
corresponding overlap areas 301 to 303.
[0114] This approach can be expanded for any desired multi-level
memory cells: the reliability of the storage of digital values in a
multi-level memory cell having eight digital values 0, 1, 2, 3, 4,
5, 6 and 7 is thus influenced by the relative frequencies of the
values W.sub.A(0), W.sub.A(1), . . . , W.sub.A(7) being in the
corresponding overlap areas [0, 1], [1, 2], [2, 3], [3, 4], [4, 5],
[5, 6] and [6, 7].
[0115] The reliability of the storage of digital values in a
multi-level memory cell for storing N digital values 0, 1, . . . ,
N-1 generally depends on the relative frequencies of the analog
values [0116] W.sub.A(0), W.sub.A(1), . . . , W.sub.A(N-1)
belonging to the corresponding N-1 overlap areas [0117] [0, 1], [1,
2], . . . , [N-2, N-1] with N=2, 3, . . . .
[0118] FIG. 4 shows, by way of example, a plurality of frequency
distributions W.sub.A(00), W.sub.A(10), W.sub.A(01) and W.sub.A(11)
which result when four digital values 00, 10, 01 and 11 are stored
in memory cells. The frequency distribution W.sub.A(00) has an
expected value E.sub.A(00), the frequency distribution W.sub.A(01)
has an expected value E.sub.A(01), the frequency distribution
W.sub.A(10) has an expected value E.sub.A(10) and the frequency
distribution W.sub.A(11) has an expected value E.sub.A(11).
[0119] Reference values R.sub.0, R.sub.1 and R.sub.-1 are
indicated, by way of example, in FIG. 4, wherein
[0120] a reference value R.sub.-1 is present in an overlap area 401
(also referred to as overlap area [00, 10]) between the frequency
distribution W.sub.A(00) and the frequency distribution
W.sub.A(10),
[0121] a reference value R.sub.0 is present between the frequency
distribution W.sub.A(10) and the frequency distribution
W.sub.A(01), and
[0122] a reference value R.sub.1 is present in an overlap area 402
(also referred to as overlap area [01, 11]) between the frequency
distribution W.sub.A(01) and the frequency distribution
W.sub.A(11),
where the following applies:
E.sub.A(00)<R.sub.-1<E.sub.A(10)<R.sub.0<E.sub.A(01)<R.su-
b.1<E.sub.A (11).
[0123] According to the example in FIG. 4, the digital value
W.sub.D is written to a memory cell as an analog value W.sub.G such
that the following applies to the expected values of the analog
values which are read:
|E.sub.A(01)-E.sub.A(10)|>|E.sub.A(11)-E.sub.A(01)|
and
|E.sub.A(01)-E.sub.A(10)|>|E.sub.A(10)-E.sub.A(00)|.
[0124] In FIG. 4, the frequency distributions W.sub.A(00) and
W.sub.A(10) have the overlap area 401 and the frequency
distributions W.sub.A(01) and W.sub.A(11) have the overlap area
402. In contrast, the frequency distributions W.sub.A(00) and
W.sub.A(10) do not have an overlap area with the frequency
distributions W.sub.A(01) and W.sub.A(11).
[0125] In this case, it is noted that the frequency distributions
are illustrated in the explained examples in such a manner that an
overlap area or no overlap area arises. In particular, for the
embodiments shown here, a considerably smaller or weaker overlap
area may be present for frequency distributions which have "no
overlap area" than for the frequency distributions which have "an
overlap area". In other words, with respect to the selected
exemplary embodiments, "no overlap area" enables a considerably
more reliable reading operation than if an overlap area is
identified.
[0126] On account of the overlap area 401, it is possible for the
digital value 00 to be written to the memory and to be incorrectly
read as digital value 10 with a certain degree of probability.
Conversely, it is possible for the digital value 10 to be written
to the memory and to be incorrectly read as digital value 00.
[0127] On account of the overlap area 402, it is possible for the
digital value 01 to be written to the memory and to be incorrectly
read as digital value 11 with a certain degree of probability.
Conversely, it is possible for the digital value 11 to be written
to the memory and to be incorrectly read as digital value 01.
[0128] Is there is no overlap area of the frequency distributions
W.sub.A(00) and W.sub.A(10) with the frequency distributions
W.sub.A(01) and W.sub.A(11) in the example shown in FIG. 4, the
situation cannot occur in which a digital value 00 or 10 is written
to the memory and a digital value 01 or 11 is incorrectly read
provided that an additional error has not occurred.
[0129] The least significant bit (also referred to as LSB) of the
digital values 00 and 10 is the right-hand bit which has the value
0, that is to say [0130] LSB(00)=LSB(10)=0.
[0131] The LSB of the digital values 01 and 11 is the right-hand
bit which has the value 1, that is to say [0132]
LSB(01)=LSB(11)=1.
[0133] The most significant bit (also referred to as MSB) of the
digital value 00 is the left-hand bit having the value 0 and the
MSB of the digital value 10 is the left-hand bit having the value
1, that is to say [0134] MSB(00)=0 [0135] MSB(10)=1.
[0136] The following accordingly applies: [0137] MSB(01)=0 [0138]
MSB(11)=1.
[0139] In the example shown in FIG. 4, the digital values are
written to the memory cells in such a manner that they are stored
with different reliability in memory cells. The distributions of
the analog values W.sub.A(01) and W.sub.A(11), which correspond to
the digital values 01 and 11 with the same LSBs [0140]
LSB(01)=LSB(11)=1, have the overlap area 402. A digital value 01
written to the memory can therefore be incorrectly read as value 11
or a digital value 11 written to the memory can be incorrectly read
as value 01. In this case, the MSB changes and the LSB=1 does not
change. Therefore, the error has an effect only in the MSB.
[0141] The digital values 00 and 10 are written to memory cells and
stored in such a manner that the distributions of the analog values
W.sub.A(00) and W.sub.A(10), which correspond to the digital values
00 and 10 with the same LSBs [0142] LSB(00)=LSB(10)=0, have the
overlap area 401. A digital value 10 written to the memory can
therefore be incorrectly read as value 00 or a digital value 00
written to the memory can be incorrectly read as value 10. In this
case, the LSB=0 does not change, with the result that the error has
an effect only in the MSB.
[0143] Since the frequency distributions W.sub.A(00) and
W.sub.A(10) of the digital values 00 and 10 with LSB=0 do not have
an overlap area with the distributions W.sub.A(01) and W.sub.A(11)
of the digital values 01 and 11 with LSB=1 in this example, a
digital value which is written to the memory and has LSB=0 is not
incorrectly read as a digital value with LSB=1 on account of the
overlap of frequency distributions. A digital value which is
written to the memory and has the LSB=1 is likewise not incorrectly
read as a digital value with LSB=0 on account of the overlap of
frequency distributions, with the result that the LSB is stored
with a correspondingly high reliability.
[0144] In contrast, the MSB is stored with lower reliability since
the frequency distributions W.sub.A(01) and W.sub.A(11) with
different MSBs have the overlap area 402 and the frequency
distributions W.sub.A(00) and W.sub.A(10) with different MSBs have
the overlap area 401.
[0145] The LSB and the MSB can be written to the memory in
successive steps. For example, it is thus possible to write those
bits which require a particularly high reliability to memory cells
as LSBs. For example, a program code can be represented by
LSBs.
[0146] Image data which allow a lower reliability in comparison
with the program code can be stored as MSBs, for example. If
individual bits in the image data are incorrect, the image can
still be successfully displayed or individual bit errors in an
image display can remain undetected. In contrast, an individual
incorrect bit in a program code may result in the entire program no
longer being operational. Accordingly, other examples of more or
less error-tolerant data are known and can be combined with the
approach described here.
[0147] It is also an option that the reliability of the MSBs and/or
LSBs, for example, can be increased by means of an error code. If
the correction capability and/or the detection performance of the
error code is/are accordingly powerful, the MSBs and/or LSBs can be
stored, for example, with a predefinable (high) reliability using
such error correction. The error codes for the error correction
and/or error detection for the LSBs and/or MSBs may be identical or
different.
[0148] It is assumed below, by way of example, that the
corresponding analog value W.sub.A can be increased when writing a
digital value to a memory cell. It can also be assumed, by way of
example, that memory cells can be erased in blocks, in which case
the corresponding analog value in the erased memory cell assumes a
small, for example minimal, value during erasure. The block which
can be erased in an erase operation comprises a plurality of bits.
It is also possible for memory cells to be erased and/or
overwritten individually or continuously (for example
word-by-word).
[0149] For example, a memory cell which, according to the
illustration shown in FIG. 4, can store four digital values 00, 10,
01 and 11 is considered. After a block has been erased, all cells
in this block have analog values corresponding to the frequency
distribution W.sub.A(00). This corresponds to the digital value 00
provided that no error has occurred.
[0150] Starting from the value 00, it is possible to store one of
the values 00, 10, 01 or 11 in a memory cell. The state is not
changed when writing the value 00. The analog value of the memory
cell is increased when writing one of the values 10, 01 or 11. This
is possible since the digital value 00 corresponds to the lowest
analog value and the analog value W.sub.A can be increased starting
from the digital value 00, with the result that the memory cell (in
the error-free case) represents one of the values 10, 01 or 11.
[0151] In the example above, it was explained that four values (00,
10, 01, 11), by way of example, are represented by a memory cell.
These four values are written to the memory cell in such a manner
that a frequency distribution of the physically stored values
results for each of the four values; the frequency distributions
have partial overlaps. It is thus possible to use the range of
values of the memory cell on the basis of the plurality of
frequency distributions and to therefore enable a plurality of
values to be stored in the memory cell. Each of the frequency
distributions represents a physical value which can be assigned to
one of the digital values (00, 10, 01, 11).
[0152] The frequency distribution W.sub.A(10) therefore corresponds
to physical values which are read and are assigned to the digital
value 10. This digital value 10 consists of two bits, the MSB with
the value 1 and the LSB with the value 0.
[0153] When writing to the memory cell, the write voltage can be
set in such a manner that the frequency distribution W.sub.A(10)
around the expected value E.sub.A(10) results for the digital value
10 to be written.
[0154] A corresponding situation applies to the other digital
values 00, 01 and 11. It is therefore determined during writing
that the overlap area 401 arises between the digital values 00 and
10 and the overlap area 402 arises between the digital values 01
and 11. In contrast, there is no overlap area between the digital
values 00 and 10 and the digital values 01 and 11. This means that
the MSBs of the digital values are incorrect with a relatively high
degree of probability, but the LSBs can be read in a (more)
reliable manner.
[0155] The writing operation therefore specifies the practice of
providing a higher reliability for some areas (here the LSBs of the
memory cells) than for other areas (here the MSBs). Instead of the
areas (LSBs, MSBs) described here by way of example, memory cells
having a different subdivision may also be provided. In particular,
it is possible to store more than four values. For example,
2.sup.3=8 values could be stored in digital values 000, 001, 010,
011, 100, 101, 110, 111, these digital values being mapped to the
range of values of the physical values in such a manner that their
respective frequency distributions do not have an overlap at least
for one of the three bits.
[0156] In conventional memory cells of a flash memory, the
different cell states are set using a threshold voltage V.sub.th.
In order to program a cell to a target threshold voltage V.sub.th,
a corresponding voltage V.sub.CG is applied to a control gate (CG)
of the memory cell. The threshold voltage V.sub.th then follows
this voltage V.sub.CG directly, for example, that is to say [0157]
.DELTA.V.sub.th=.DELTA.V.sub.CG.
[0158] In order to achieve different reliabilities for the LSB and
MSB, it is possible to select, for example, a threshold voltage
.DELTA.V.sub.th2 considerably greater than threshold voltages
.DELTA.V.sub.th1 and .DELTA.V.sub.th3. A large signal-to-noise
ratio and a higher reliability in comparison with shifts of the
threshold voltages for the MSB (or LSB) and therefore a lower
reliability for the LSB (or MSB) are therefore achieved.
[0159] FIG. 11 shows, by way of example, a graph for illustrating
the threshold voltage V.sub.th with respect to the voltage V.sub.CG
at the control gate of the memory cell. A programming time is
plotted on the x axis and the threshold voltage V.sub.th is plotted
on the y axis. For a programming duration of 10 .rho.s, the
different threshold voltages .DELTA.V.sub.th1, .DELTA.V.sub.th2 and
.DELTA.V.sub.th3 are shown for the control gate voltages
V.sub.CG=10 V, 11 V, 12 V, 13 V.
[0160] It is therefore ensured, during writing, that the frequency
distributions of the associated physical values (substantially)
have no overlaps which would result in an ambiguity at least for
some (here one bit) of the digitally represented values.
[0161] The following therefore applies to such a reliable bit which
may have two values: the frequency distributions in which the
reliable bit has the first value do not overlap frequency
distributions in which the reliable bit has the second value. It is
not important which value the at least one further (possibly more
unreliable) bit has in this case. Therefore, the first value of the
reliable bit can be distinguished from its second value with a high
degree of certainty. This reliable bit can therefore be used in the
memory cell to store information there only in the reliable bits of
memory cells of the memory.
[0162] Accordingly, the lower reliability can be accepted for the
unreliable bit (the MSB in the example) of the memory cell; the
reliability can be improved by means of error correction. In
particular, the error-corrected values can be written to a fast
memory which is used during normal operation.
[0163] Writing Sequence: LSB then MSB
[0164] One option is to write the value of the LSB to memory cells
in a first writing operation and to then write any desired MSB to a
memory cell, to which the LSB has already been previously written
in the first writing operation, in a second writing operation.
[0165] If, for example, the value 0 of the LSB is to be stored in
an erased memory cell, the value 00 is written to this memory cell.
In this case, the analog value W.sub.A(00) of the memory cell is
not changed.
[0166] If the value 1 of the LSB is to be stored in an erased
memory cell, the value 01 is written to this memory cell which then
assumes an analog value W.sub.A(01).
[0167] The MSB can now be stored as follows, depending on the
situation:
[0168] The LSB with the value 0 was written in the first step, with
the result that the digital value 00 is stored in the memory
cell.
[0169] The MSB has the value 0. In this case, the memory cell is
not written to and the stored digital value is still 00.
[0170] The MSB has the value 1. In this case, the value 10 is
written to the memory cell.
[0171] The LSB with the value 1 was written in the first step, with
the result that the digital value 01 is stored in the memory
cell.
[0172] The MSB has the value 0. In this case, the memory cell is
not written to and the stored digital value is still 01.
[0173] The MSB has the value 1. In this case, the value 11 is
written to the memory cell.
[0174] When writing the MSB with the value 1, the state of the
memory cell after the LSB has been written to it determines whether
the digital value 10 or 11 is to be written to the memory cell.
This operation of writing the MSB with the value 1 is therefore
dependent on reading the previously written LSB of the memory cell.
When writing the MSB with the value 0, it is not important what
value was previously stored as the LSB. It is therefore possible to
dispense with reading the value (of the LSB) stored in the memory
cell in this case.
[0175] Writing Sequence: MSB then LSB
[0176] It is also possible to initially write only the value of the
MSB to memory cells in a first writing operation and then to write
any desired LSB to one of the memory cells, to which the MSB has
already been written in the first writing operation, in a second
writing operation.
[0177] If, for example, the value of the MSB is equal to 0, the
value 00 is written to this memory cell. If the value of the MSB is
equal to 1, the value 10 is written to the corresponding memory
cell.
[0178] The LSB can now be stored as follows, depending on the
situation:
[0179] The MSB with the value 0 was written in the first step, with
the result that the digital value 00 is stored in the memory
cell.
[0180] The LSB has the value 0. In this case, the memory cell is
not written to and the stored digital value is still 00.
[0181] The LSB has the value 1. In this case, the value 01 is
written to the memory cell.
[0182] The MSB with the value 1 was written in the first step, with
the result that the digital value 10 is stored in the memory
cell.
[0183] The LSB has the value 0. In this case, the memory cell is
not written to and the stored digital value is still 10.
[0184] The LSB has the value 1. In this case, the value 11 is
written to the memory cell.
[0185] When writing the LSB with the value 1, the state of the
memory cell after the MSB has been written to it determines whether
the digital value 01 or 11 is to be written to the cell. This
operation of writing the LSB with the value 1 is therefore
dependent on reading the previously written MSB of the memory cell.
When writing the LSB with the value 0, it is not important what
value was previously stored in the memory cell as the MSB. In this
case, it is not necessary to read the value of the previously
stored MSB.
[0186] In this case, it is noted that it is also possible to
directly write each of the digital values 00, 10, 01 or 11 to the
erased memory cell. In particular, it is an option to write the
digital value 00 to the memory cell even if the latter previously
also had the value 00. In this respect, it is an alternative to the
examples described above under numbers 1.1. and 2.1. that the value
00 is nevertheless written even if the previous state of the memory
cell does not change thereby.
Further Example Frequency Distributions
[0187] FIG. 5 shows example frequency distributions W.sub.A(0),
W.sub.A(1) and W.sub.A(2) of analog values which may arise if three
digital values 0, 1 and 2 are stored in memory cells. The frequency
distribution W.sub.A(0) has an expected value E.sub.A(0), the
frequency distribution W.sub.A(1) has an expected value E.sub.A(1)
and the frequency distribution W.sub.A(2) has an expected value
E.sub.A(2).
[0188] Reference values R.sub.0 and R.sub.1 are indicated, by way
of example, in FIG. 5, wherein
[0189] the reference value R.sub.0 is present between the frequency
distribution W.sub.A(0) and the frequency distribution W.sub.A(1),
and
[0190] the reference value R.sub.1 is present in an overlap area
501 (also referred to as overlap area [1, 2]) between the frequency
distribution W.sub.A(1) and the frequency distribution
W.sub.A(2),
wherein the following applies:
E.sub.A(0)<R.sub.0<E.sub.A(1)<R.sub.1<E.sub.A(2).
[0191] According to the example selected in FIG. 5, the frequency
distributions W.sub.A(0) and W.sub.A(1) do not have an overlap area
and the frequency distributions W.sub.A(1) and W.sub.A(2) have the
overlap area 501.
[0192] In the overlap area 501, it is possible, with a certain
degree of probability, for the digital value 1 to be written to the
memory and to be incorrectly read as digital value 2.
[0193] Since there is no overlap area between the frequency
distribution W.sub.A(0) and the frequency distributions W.sub.A(1)
and W.sub.A(2), it is possible, only with a low degree of
probability, for the digital value 0 to be written to a memory cell
and for a digital value 1 or 2 different from this value 0 to be
read.
[0194] Addressing Data in a Memory
[0195] FIG. 6 shows an example diagram of a memory having an
address 601 and data 602. Data 602 can be stored in 64 memory cells
for each address 601, each memory cell being able to store four
different digital values. FIG. 6 shows, by way of example,
assignments of the memory for nine addresses a.sup.1, a.sup.2, . .
. , a.sup.9.
[0196] Each of the addresses a.sup.i, i=1, 2, . . . , 9, addresses
64 memory cells, four different binary-coded values being able to
be stored in a memory cell. These four different values are
represented as tuples xy of two binary values x and y. The bit x is
the MSB and the bit y is the LSB of the tuple xy. A value stored in
a memory cell therefore has an MSB and an LSB.
[0197] It is assumed, by way of example, that the LSB is stored
with a higher reliability than the MSB.
[0198] In this example, the addresses a.sup.1 to a.sup.4 are
assigned values as follows: [0199] a.sup.1:
v.sub.1.sup.1u.sub.1.sup.1, . . . , v.sub.64.sup.1u.sub.64.sup.1;
[0200] a.sup.2: v.sub.65.sup.1u.sub.1.sup.2, . . . ,
v.sub.128.sup.1u.sub.64.sup.2; [0201] a.sup.3:
v.sub.129.sup.1u.sub.1.sup.3, . . . ,
v.sub.192.sup.1u.sub.64.sup.3; [0202] a.sup.4:
v.sub.193.sup.1u.sub.1.sup.4, . . . ,
v.sub.256.sup.1u.sub.64.sup.4.
[0203] These are xy tuples with the bits u and v, the values of the
v bits being stored as MSBs and the values of the u bits being
stored as LSBs.
[0204] The bits u.sup.1 stored with high reliability as LSBs under
the address a.sup.1 form a data word having the word width of 64
bits. This accordingly also applies to the LSBs u.sup.2, u.sup.3
and u.sup.4 stored under the addresses a.sup.2, a.sup.3 and a.sup.4
according to [0205] u.sup.1=u.sub.1.sup.1, . . . , u.sub.64.sup.1;
[0206] u.sup.2=u.sub.1.sup.2, . . . , u.sub.64.sup.2; [0207]
u.sup.3=u.sub.1.sup.3, . . . , u.sub.64.sup.3; [0208]
u.sup.4=u.sub.1.sup.4, . . . , u.sub.64.sup.4.
[0209] The bits v.sup.1=v.sub.1.sup.1, . . . , v.sub.256.sup.1
which are stored with a lower reliability as MSBs under the
addresses a.sup.1, a.sup.2, a.sup.3 and a.sup.4 form a first data
word of the word width of 256 bits.
[0210] By way of example, the bits v.sup.1 are protected by means
of check bits of an error code having 28 check bits c.sub.1.sup.v1,
. . . , c.sub.28.sup.v1. The bits u.sup.1, u.sup.2, u.sup.3 and
u.sup.4 are not protected by additional check bits in this
example.
[0211] The 28 check bits c.sub.1.sup.v1, . . . , c.sub.28.sup.v1
are stored as MSBs with 36 data bits v.sub.1.sup.2, . . . ,
v.sub.36.sup.2 under the address a.sup.5 and as LSBs with 64 data
bits u.sup.5=u.sub.1.sup.5, . . . , u.sub.64.sup.5.
[0212] In the error-free case, the bits [0213] v.sub.1.sup.1, . . .
, v.sub.256.sup.1, c.sub.1.sup.v1, . . . , c.sub.28.sup.v1 form a
code word of a first error code Cod.sub.1.
[0214] An error code can generally be an error-detecting and/or
error-correcting code.
[0215] For example, the error code Cod.sub.1 may be a known 3-bit
error-correcting BCH code over the Galois field GF (2.sup.9) with
additional overall parity with a total of 28 check bits for 256
data bits, which also detects each 4-bit error.
[0216] Accordingly, the addresses a.sup.5 to a.sup.9 are assigned
values as follows: [0217] a.sup.5: c.sub.1.sup.v1u.sub.1.sup.5, . .
. , c.sub.28.sup.v1u.sub.28.sup.5, v.sub.1.sup.2u.sub.29.sup.5, . .
. , v.sub.36.sup.2u.sub.64.sup.5; [0218] a.sup.6:
v.sub.37.sup.2u.sub.1.sup.6, . . . ,
v.sub.100.sup.2,u.sub.64.sup.6; [0219] a.sup.7:
v.sub.101.sup.2u.sub.1.sup.7, . . . , v.sub.164.sup.2,
u.sub.64.sup.7; [0220] a.sup.8: v.sub.165.sup.2u.sub.1.sup.8, . . .
, v.sub.228.sup.2, u.sub.64.sup.8; [0221] a.sup.9:
v.sub.229.sup.2u.sub.1.sup.9, . . . , v.sub.256.sup.2,
u.sub.28.sup.9, c.sub.1.sup.v2u.sub.29.sup.9, . . . ,
c.sub.28.sup.v2u.sub.56.sup.9, v.sub.1.sup.3u.sub.57.sup.9, . . . ,
v.sub.8.sup.3u.sub.64.sup.9
[0222] The bits v.sup.2=v.sub.1.sup.2, . . . , v.sub.256.sup.2
which are stored under the addresses a.sup.5, a.sup.6, a.sup.7,
a.sup.8 and a.sup.9 as MSBs with lower reliability form a second
data word of the word width 256. These 256 bits v.sup.2 are
protected by 28 check bits c.sub.1.sup.v2, . . . ,
c.sub.28.sup.v2.
[0223] In the error-free case, the bits [0224] v.sub.1.sup.2, . . .
, v.sub.256.sup.2, c.sub.1.sup.v2, . . . , c.sub.28.sup.v2 form a
code word of the first error code Cod.sub.1.
[0225] The bits u.sup.5 stored under the address a.sup.5 as LSBs
with high reliability form a data word having the word width of 64
bits. This accordingly also applies to the LSBs u.sup.6, u.sup.7,
u.sup.8 and u.sup.9 stored under the addresses a.sup.6, a.sup.7,
a.sup.8 and a.sup.9 with [0226] u.sup.5=u.sub.1.sup.5, . . . ,
u.sub.64.sup.5; [0227] u.sup.6=u.sub.1.sup.6, . . . ,
u.sub.64.sup.6; [0228] u.sup.7=u.sub.1.sup.7, . . . ,
u.sub.64.sup.7; [0229] u.sup.8=u.sub.1.sup.8, . . . ,
u.sub.64.sup.8; [0230] u.sup.9=u.sub.1.sup.9, . . . ,
u.sub.64.sup.9. The bits u.sup.5, u.sup.6, u.sup.7, u.sup.8 and
u.sup.9 are not protected by additional check bits of an error code
in this example.
[0231] FIG. 7 shows an exemplary diagram of a memory having an
address 701 and data 702. Data 702 can be stored in 72 memory cells
for each address 701, each memory cell being able to store four
different digital values. Each digital value stored for each memory
cell can be stated as a tuple xy of two binary values x and y.
[0232] The bit x is the MSB and the bit y is the LSB of the tuple
xy. A value stored in a memory cell therefore has an MSB and an
LSB.
[0233] It is assumed by way of example that the MSB is stored with
a higher reliability than the LSB.
[0234] 72 memory cells are respectively available under the
addresses a.sup.1 to a.sup.8. In this case, the addresses a.sup.1
to a.sup.4 are assigned values as follows: [0235] a.sup.1:
u.sub.1.sup.1v.sub.1.sup.1, . . . , u.sub.64.sup.1v.sub.64.sup.1,
c.sub.1.sup.u1v.sub.65.sup.1, . . . , c.sub.8.sup.u1v.sub.72.sup.1;
[0236] a.sup.2: u.sub.1.sup.2v.sub.73.sup.1, . . . ,
u.sub.64.sup.2v.sub.136.sup.1, c.sub.1.sup.u2v.sub.137.sup.1, . . .
, c.sub.8.sup.u2v.sub.144.sup.1; [0237] a.sup.3:
u.sub.1.sup.3v.sub.145.sup.1, . . . ,
u.sub.64.sup.3v.sub.208.sup.1, c.sub.1.sup.u3v.sub.209.sup.1, . . .
, c.sub.8.sup.u3v.sub.216.sup.1; [0238] a.sup.4:
u.sub.1.sup.4v.sub.217.sup.1, . . . ,
u.sub.40.sup.4v.sub.256.sup.1, u.sub.41.sup.4c.sub.1.sup.v1, . . .
, u.sub.64.sup.4c.sub.24.sup.v1, c.sub.1.sup.u4c.sub.25.sup.v1, . .
. , c.sub.4.sup.u4c.sub.28.sup.v1, c.sub.5.sup.u4-, . . .
c.sub.8.sup.u4-
[0239] In the error-free case, the 256 data bits v.sub.1.sup.1, . .
. , v.sub.256.sup.1 and the 28 check bits c.sub.1.sup.v1, . . . ,
c.sub.28.sup.v1 form a code word [0240] v.sub.1.sup.1, . . . ,
v.sub.256.sup.1, c.sub.1.sup.v1, . . . , c.sub.28.sup.v1
[0241] of the first error code Cod.sub.1. These bits are stored as
LSBs with lower reliability. In the example above, bits whose value
assignments are not important are indicated with "-". The last four
values of the LSBs therefore remain undetermined under the address
a.sup.4. These last four values can be assigned zeros or other
binary values, for example.
The bits [0242] u.sub.1.sup.1, . . . , u.sub.64.sup.1,
c.sub.1.sup.u1, . . . , c.sub.8.sup.u1; [0243] u.sub.1.sup.2, . . .
, u.sub.64.sup.2, c.sub.1.sup.u2, . . . , c.sub.8.sup.u2; [0244]
u.sub.1.sup.3, . . . , u.sub.64.sup.3, c.sub.1.sup.u3, . . . ,
c.sub.8.sup.u3; [0245] u.sub.1.sup.4, . . . , u.sub.64.sup.4,
c.sub.1.sup.u4, . . . , c.sub.8.sup.u4 each form a code word of a
second error code Cod.sub.2 in the error-free case. In this case,
for i=1, . . . , 4, the bits u.sub.1.sup.i, . . . u.sub.64.sup.i
are data bits and the bits c.sub.1.sup.ui, . . . , c.sub.8.sup.ui
are check bits.
[0246] Accordingly, the addresses a.sup.5 to a.sup.8 are assigned
values as follows: [0247] a.sup.5: u.sub.1.sup.5v.sub.1.sup.2, . .
. , u.sub.64.sup.5v.sub.64.sup.2, c.sub.1.sup.u5v.sub.65.sup.2, . .
. , c.sub.8.sup.u5v.sub.72.sup.2; [0248] a.sup.6:
u.sub.1.sup.6v.sub.73.sup.2, . . . , u.sub.64.sup.6v.sub.136.sup.2,
c.sub.1.sup.u6v.sub.137.sup.2, . . . ,
c.sub.8.sup.u6v.sub.144.sup.2; [0249] a.sup.7:
u.sub.1.sup.7v.sub.145.sup.2, . . . ,
u.sub.64.sup.7v.sub.208.sup.2, c.sub.1.sup.u7v.sub.209.sup.2, . . .
, c.sub.8.sup.u7v.sub.216.sup.2; [0250] a.sup.8:
u.sub.1.sup.8v.sub.217.sup.2, . . . u.sub.40.sup.8v.sub.256.sup.2,
u.sub.41.sup.8c.sub.1.sup.v2, . . . u.sub.64.sup.8c.sub.24.sup.v2,
c.sub.1.sup.u8c.sub.25.sup.v2, . . . ,
c.sub.4.sup.u8c.sub.28.sup.v2, c.sub.5.sup.u8-, . . . ,
c.sub.8.sup.u8-.
[0251] In the error-free case, the 256 data bits v.sub.1.sup.2, . .
. , v.sub.256.sup.2 and the 28 check bits c.sub.1.sup.v2, . . . ,
c.sub.28.sup.v2 form a code word [0252] v.sub.1.sup.2, . . . ,
v.sub.256.sup.2, c.sub.1.sup.v2, . . . , c.sub.28.sup.v2 of the
first error code Cod.sub.1. These bits are stored as LSBs with
lower reliability. The bits [0253] u.sub.1.sup.5, . . . ,
u.sub.64.sup.5, c.sub.1.sup.u5, . . . , c.sub.8.sup.u5; [0254]
u.sub.1.sup.6, . . . , u.sub.64.sup.6, c.sub.1.sup.u6, . . . ,
c.sub.8.sup.u6; [0255] u.sub.1.sup.7, . . . , u.sub.64.sup.7,
c.sub.1.sup.u7, . . . , c.sub.8.sup.u7; [0256] u.sub.1.sup.8, . . .
, u.sub.64.sup.8, c.sub.1.sup.u8, . . . , c.sub.8.sup.u8 each form
a code word of the second error code Cod.sub.2 in the error-free
case. In this case, for i=5, . . . , 8, the bits u.sub.1.sup.i, . .
. , u.sub.64.sup.i are data bits and the bits are check bits.
[0257] In the example cited here, the last four values of the LSB
remain undetermined under the address a.sup.8; these bits are
indicated with the symbol "-".
Additional Memory
[0258] FIG. 8 shows an example diagram of a memory having an
address 801 and data 802. The memory shown in FIG. 8 may be
provided as an (additional) second memory. This second memory can
be used, for example, to store the LSBs read from a first memory.
For example, the LSBs may be stored with a lower reliability than
the MSBs.
[0259] For example, LSBs which have possibly been incorrectly read
can be corrected using a first error code Cod.sub.1 and the
corrected bits can then be stored in the second memory.
[0260] Optionally, the data bits of the LSBs can be corrected using
the error code Cod.sub.1 and check bits of a third error code
Cod.sub.3 can be formed using these corrected data bits. The data
bits corrected using the code Cod.sub.1 and the check bits formed
therefrom using the third error code Cod.sub.3 can be stored in the
second binary memory.
[0261] It is assumed, for example, that FIG. 7 shows a
corresponding first memory and FIG. 8 shows the second memory. It
is assumed that the data stored in the first memory form possibly
incorrect LSBs [0262] v.sub.1.sup.1', . . . , v.sub.256.sup.1',
v.sub.1.sup.2', . . . , v.sub.256.sup.2', . . . of the word width
256 and that, for each of the 256 bits of data v.sup.i', there are
28 check bits of the first error code Cod.sub.1 c.sub.1.sup.v1', .
. . , c.sub.28.sup.v1', c.sub.1.sup.v2', . . . , c.sub.28.sup.v2',
. . . , with the result that incorrect data bits are corrected,
during reading from the first memory, with the aid of a correction
unit using the first error code Cod.sub.1, into corrected data bits
[0263] v.sub.1.sup.1cor, . . . , v.sub.256.sup.1cor,
v.sub.1.sup.2cor, . . . , v.sub.256.sup.2cor, . . . .
[0264] FIG. 8 illustrates that the data bits v.sup.icor corrected
using the first error code are stored, together with the
corresponding check bits C.sup.i of the third error code Cod.sub.3,
under the following addresses A.sub.1 to A.sub.32: [0265] A.sub.1:
v.sub.1.sup.1cor, . . . , v.sub.16.sup.1cor; [0266] A.sub.2:
v.sub.17.sup.1cor, . . . , v.sub.32.sup.1cor; [0267] : [0268]
A.sub.16: v.sub.241.sup.1cor, . . . , v.sub.256.sup.1cor; [0269]
A.sub.17: v.sub.1.sup.2cor, . . . , v.sub.16.sup.2cor; [0270] :
[0271] A.sub.32: v.sub.241.sup.2cor, . . . , v.sub.256.sup.2cor.
The check bits [0272] C.sup.1=C.sub.1.sup.1, . . . , C.sub.4.sup.1;
[0273] C.sup.2=C.sub.1.sup.2, . . . , C.sub.4.sup.2; [0274] :
[0275] C.sup.32=C.sub.1.sup.32, . . . , C.sub.4.sup.32 are
determined with the aid of an encoder for the third error code
Cod.sub.3 in such a manner that, in the error-free case, the
following bit combinations respectively form code words of the
third error code Cod.sub.3: [0276] v.sub.1.sup.1cor, . . . ,
v.sub.16.sup.1cor, C.sub.1.sup.1, . . . , C.sub.4.sup.1; [0277] :
[0278] v.sub.241.sup.1cor, . . . , v.sub.256.sup.1cor,
C.sub.1.sup.16, . . . , C.sub.4.sup.16; [0279] v.sub.1.sup.2cor, .
. . , v.sub.16.sup.2cor, C.sub.1.sup.17, . . . , C.sub.4.sup.17;
[0280] : [0281] v.sub.241.sup.2cor, . . . , v.sub.256.sup.2cor,
C.sub.1.sup.32, . . . , C.sub.4.sup.32.
[0282] The second memory may comprise a volatile memory, for
example an SRAM, an MRAM or the like, and/or a non-volatile memory.
The first memory may comprise a non-volatile memory, for example a
flash memory or the like. In particular, it is an option for the
first memory and second memory to be any desired memories of the
same type or of different types.
[0283] One option is for bits which are stored in the first memory
and have a lower reliability to be read from the first memory with
a large word width and to be corrected using the first error code
Cod.sub.1. In this case, the first error code Cod.sub.1 may have a
relatively large code distance in order to correct a multiplicity
of errors. The errors can be corrected sequentially, as described,
for example, for a BCH code in [Lin, S., Costello, D.: "Error
Control Coding, Fundamentals and Applications", Pearson Education,
London, 2004, pages 205 to 217].
[0284] In this case, it is advantageous that the number of check
bits may be comparatively small for a large word width of the data
bits. For example, 33 check bits may thus be required for a
three-bit-error-correcting BCH code with 1024 data bits, whereas 27
check bits are already required for 256 data bits. The increase in
the number of data bits by 768 data bits therefore only requires an
increase in the number of check bits by 6. For example, n+1 check
bits are required for a code having 2.sup.n data bits in order to
be able to correct a one-bit error. Therefore, n=10 and 11 check
bits arise for 1024 data bits. If the intention is to correct t-bit
errors, a t-bit-error-correcting BCH code can be used. For example,
t (n+1) check bits arise. For three-bit errors (t=3), 33 check bits
are required for the 1024 data bits mentioned above and 3 (8+1)=27
check bits are required for 256 data bits.
[0285] It is also possible to use a so-called low-density parity
code as the error code (for example for the first error code
Cod.sub.1) according to [Lin, S., Costello, D.: "Error Control
Coding, Fundamentals and Applications", Pearson Education, London,
2004, pages 852 to 855].
[0286] It is possible to code the bits corrected using the first
error code Cod.sub.1 as code words of the third error code using
the third error code Cods and to store the code words in the second
memory. It is possible to access the bits stored in the second
memory quickly and reliably during ongoing operation of an
application, for example, whereas errors which occur during storage
in the second memory can be corrected using the third error code.
It is likewise possible to update and/or restore the bits stored in
the memories in different ways.
[0287] FIG. 9 shows an example diagram of a memory having an
address 901 and data 902. The memory shown in FIG. 9 can be used as
a first memory according to the statements above.
[0288] Data 902 can be stored in 8 memory cells for each address
901, each memory cell being able to store four different digital
values. Each digital value stored for each memory cell can be
stated as a tuple xy of two binary values x and y.
[0289] The bit x is the MSB and the bit y is the LSB of the tuple
xy. A value stored in a memory cell therefore has an MSB (the bit
x) and an LSB (the bit y).
[0290] It is assumed by way of example that the LSB is stored with
a higher reliability than the MSB.
[0291] 8 memory cells are respectively available under the
addresses a.sup.1 to a.sup.6. In this case, the addresses a.sup.1
to a.sup.6 are assigned values as follows: [0292] a.sup.1: v.sub.1
u.sub.1.sup.1, v.sub.2 u.sub.2.sup.1, v.sub.3 u.sub.3.sup.1,
v.sub.4 u.sub.4.sup.1, v.sub.5 u.sub.5.sup.1, v.sub.6
c.sub.1.sup.1, v.sub.7 c.sub.2.sup.1, v.sub.8c.sub.3.sup.1; [0293]
a.sup.2: v.sub.1 u.sub.1.sup.2, v.sub.2 u.sub.2.sup.2, v.sub.3
u.sub.3.sup.2, v.sub.4 u.sub.4.sup.2, v.sub.5 u.sub.5.sup.2,
v.sub.6 c.sub.1.sup.2, v.sub.7 c.sub.2.sup.2, v.sub.8c.sub.3.sup.2;
[0294] a.sup.3: v.sub.1 u.sub.1.sup.3, v.sub.2 u.sub.2.sup.3,
v.sub.3 u.sub.3.sup.3, v.sub.4 u.sub.4.sup.3, v.sub.5
u.sub.5.sup.3, v.sub.6 c.sub.1.sup.3, v.sub.7 c.sub.2.sup.3,
v.sub.8c.sub.3.sup.3; [0295] a.sup.4: v.sub.9 u.sub.1.sup.4,
v.sub.10 u.sub.2.sup.4, v.sub.11 u.sub.3.sup.4, v.sub.12
u.sub.4.sup.4, v.sub.13 u.sub.5.sup.4, v.sub.14 c.sub.1.sup.4,
v.sub.15 c.sub.2.sup.4, v.sub.16c.sub.3.sup.4; [0296] a.sup.5:
v.sub.9 u.sub.1.sup.5, v.sub.10 u.sub.2.sup.5, v.sub.11
u.sub.3.sup.5, v.sub.12 u.sub.4.sup.5, v.sub.13 u.sub.5.sup.5,
v.sub.14 c.sub.1.sup.5, v.sub.15 c.sub.2.sup.5,
v.sub.16c.sub.3.sup.5; [0297] a.sup.6: v.sub.9 u.sub.1.sup.6,
v.sub.10 u.sub.2.sup.6, v.sub.11 u.sub.3.sup.6, v.sub.12
u.sub.4.sup.6, v.sub.13 u.sub.5.sup.6, v.sub.14 c.sub.1.sup.6,
v.sub.15 c.sub.2.sup.6, v.sub.16c.sub.3.sup.6.
[0298] In the error-free case, the data bits u.sub.1.sup.1, . . . ,
u.sub.5.sup.1 and the check bits c.sub.1.sup.1, c.sub.2.sup.1,
c.sub.3.sup.1 form a code word u.sub.1.sup.1, . . . ,
u.sub.5.sup.1, c.sub.1.sup.1, c.sub.2.sup.1, c.sub.3.sup.1 of an
error code Cod.sub.2 for correcting possible errors of the LSBs.
The error code Cod.sub.2 may be a Hamming code for correcting
one-bit errors, for example.
[0299] In the error-free case, the data bits u.sub.1.sup.2, . . . ,
u.sub.5.sup.2 and the check bits c.sub.1.sup.2, c.sub.2.sup.2,
c.sub.3.sup.2 form a code word u.sub.1.sup.2, . . . ,
u.sub.5.sup.2, c.sub.1.sup.2, c.sub.2.sup.2, c.sub.3.sup.2 of the
error code Cod.sub.2 for correcting possible errors of the
LSBs.
[0300] In the error-free case, the data bits u.sub.1.sup.3, . . . ,
u.sub.5.sup.3 and the check bits c.sub.1.sup.3, c.sub.2.sup.3,
c.sub.3.sup.3 form a code word u.sub.1.sup.3, . . . ,
u.sub.5.sup.3, c.sub.1.sup.3, c.sub.2.sup.3, c.sub.3.sup.3 of the
error code Cod.sub.2 for correcting possible errors of the
LSBs.
[0301] The bits v.sub.1, . . . , v.sub.8 are each stored as MSBs
under the addresses a.sub.1, a.sub.2 and a.sub.3 and are therefore
stored (redundantly) three times. In this case, a double repeat
code can be used as the error code Cod.sub.1 for correcting the
MSBs, with the result that possibly incorrect values can be
corrected, for example, by a majority decision.
[0302] In the error-free case, the data bits u.sub.1.sup.4, . . . ,
u.sub.5.sup.4 and the check bits c.sub.1.sup.4, c.sub.2.sup.4,
c.sub.3.sup.4 form a code word u.sub.1.sup.4, . . . ,
u.sub.5.sup.4, c.sub.1.sup.4, c.sub.3.sup.4 of the error code
Cod.sub.2 for correcting possible errors of the LSBs.
[0303] In the error-free case, the data bits u.sub.1.sup.5, . . . ,
u.sub.5.sup.5 and the check bits c.sub.1.sup.5, c.sub.2.sup.5,
c.sub.3.sup.5 form a code word u.sub.1.sup.5, . . . ,
u.sub.5.sup.5, c.sub.1.sup.5, c.sub.2.sup.5, c.sub.3.sup.5 of the
error code Cod.sub.2 for correcting possible errors of the
LSBs.
[0304] In the error-free case, the data bits u.sub.1.sup.6, . . . ,
u.sub.5.sup.6 and the check bits c.sub.1.sup.6, c.sub.2.sup.6,
c.sub.3.sup.6 form a code word u.sub.1.sup.6, . . . ,
u.sub.5.sup.6, c.sub.1.sup.6, c.sub.2.sup.6, c.sub.3.sup.6 the
error code Cod.sub.2 for correcting possible errors of the
LSBs.
[0305] The bits v.sub.9, . . . , v.sub.16 are each stored as MSBs
under the addresses a.sub.4, a.sub.5 and a.sub.6 and are therefore
stored (redundantly) three times. In this case, the double repeat
code can be used as the error code Cod.sub.1 for correcting the
MSBs.
Exemplary Circuit Arrangements
[0306] FIG. 10a shows an example circuit arrangement in which the
LSB is stored in a memory cell of a memory 103 (first memory
according to the statements above) with a higher reliability than
the MSB.
[0307] Data bits v are present at an input of an encoder 101, at
the output of which a code word of the error code Cod.sub.1 with
the data bits v is provided. The encoder 101 therefore determines
the check bits c on the basis of the data bits v in such a manner
that the bit combination v, c is a code word of the error code
Cod.sub.1 in the error-free case.
[0308] In this case, it is possible for the encoder 101 to code the
data bits v in a parallel or sequential manner into code words of
the error code Cod.sub.1. These code words are stored as MSBs in
the memory 103.
[0309] The output of the encoder 101 is connected to the 0 input of
a multiplexer 102, the output of which is connected to the data
input of the memory 103. Data bits u are present at the 1 input of
the multiplexer 102 and are stored as LSBs in the memory 103.
[0310] The multiplexer 102 is controlled via a binary control
signal st1; depending on the value of the control signal st1, the
multiplexer 102 connects its 0 input or 1 input to its output.
[0311] By way of example, the MSBs are stored with a lower
reliability than the LSBs in the memory cells of the memory
103.
[0312] The data bits v are bits of code words of the error code
Cod.sub.1. They are stored as MSBs in the memory 103. As a result
of the coding using the error code Cod.sub.1, additional check bits
are generated and the lower reliability of the MSBs in the memory
103 is at least partially compensated for. Errors which occur when
storing the MSBs can therefore be corrected by means of a
correction unit 105 when reading the MSBs from the memory 103. The
data bits corrected in this manner are then stored in a memory 106
(the second memory according to the statements above).
[0313] The memory 103 may be in the form of a multi-level memory
which stores four digital values for each memory cell, for
example.
[0314] The LSBs can be read quickly, for example by comparing them
with only one reference value, with the result that the LSBs can be
read reliably and quickly from the memory 103.
[0315] The reading of the MSBs requires a comparison with two
reference values, which is more time-consuming in comparison with
the LSBs. Furthermore, the storage of the MSBs is less reliable
than the storage of the LSBs, which possibly requires error
correction for multi-bit errors. For example, the error correction
for multi-bit errors can be implemented sequentially.
[0316] After their error correction, the MSBs stored in the memory
103 can thus be stored in the memory 106. For example, the memory
106 is configured in such a manner that it enables fast read
access. The memory 106 may be a volatile memory, for example an
SRAM. The memory 103 may be in the form of a non-volatile
memory.
[0317] The output of the memory 103 is connected to a demultiplexer
104. If the LSBs are read from the memory 103, the demultiplexer
104 connects its input to its 1 output, with the result that the
LSBs u can be output. If the MSBs in the memory 103 are read, the
demultiplexer 104 connects its input to its 0 output, with the
result that the possibly incorrect MSBs v' which are read from the
memory 103 are passed to the input of the correction unit 105. The
correction unit 105 can correct the possibly incorrect bits v' into
corrected data bits v.sup.cor using the error code Cod.sub.1 and
can store them in the memory 106.
[0318] The demultiplexer 104 is controlled via a binary control
signal st2; depending on the value of the control signal st2, the
demultiplexer 104 connects its input to the 0 output or to the 1
output.
[0319] The corrected data bits can then be read from the memory
106.
[0320] FIG. 10a also indicates that the memory 103 can be addressed
by means of an address a and that the memory 106 can be addressed
by means of an address A.
[0321] FIG. 10b shows an example circuit arrangement which is
largely based on FIG. 10a. In this respect, identical reference
symbols are used and reference is made to the explanation with
respect to FIG. 10a.
[0322] In contrast to FIG. 10a, the data bits u which are stored as
LSBs in the memory cells of the memory 103 are coded, before being
stored, into a bit string u.sub.cod2 by an encoder 107 using an
error code Cod.sub.2. In the error-free case, the bit string
u.sub.cod2 corresponds to a code word of the error code Cod.sub.2.
Reading errors during reading from the memory 103 or writing errors
during writing to the memory 103 or other writing errors can
therefore be detected and possibly corrected by virtue of the
correction unit 108 determining whether the bits u'.sub.cod2 which
are read from the memory and are possibly incorrect constitute a
code word of the code Cod.sub.2. If there is no code word, the
incorrect bits u'.sub.cod2 which have been stored as LSBs in the
memory 103 can be corrected using a correction unit 108. For this
purpose, the 1 output of the demultiplexer 104 is connected to the
input of the correction unit 108. The data u.sup.cor2 which have
possibly been corrected are provided at the output of the
correction unit 108.
[0323] FIG. 10c shows an example circuit arrangement based on FIG.
10a or FIG. 10b, a further encoder 109 being provided between the
correction unit 105 and the memory 106, which encoder codes
corrected bits v.sup.cor1 output by the correction unit 105 into
code words v.sub.Cod3.sup.cor1 using an error code Cod.sub.3, with
the result that bits corrected using the error code Cod.sub.1 and
coded using the error code Cod.sub.3 are stored in the binary
memory 106.
[0324] Possibly incorrect bits v.sub.Cod3.sup.cor1' can now be read
from the memory 106 (the error may have occurred, for example,
during storage, during reading or during storage by means of
radiation or heating, for example) using a correction unit 110
which is connected downstream of the memory 106 and can be
corrected into corrected bits v.sup.cor3 using the error code
Cod.sub.3.
[0325] The error code Cod.sub.3 may be, for example, a Hamming
code, a Hsiao code or another code which makes it possible, in
particular, to quickly correct the bits stored in the memory
106.
[0326] FIG. 10d shows an example circuit arrangement which is
largely based on the circuit arrangement shown in FIG. 10a. Unlike
the circuit arrangement shown in FIG. 10a, an encoder 111 is
provided instead of the encoder 101 and a correction unit 112 is
provided instead of the correction unit 105.
[0327] The encoder 111 has an additional input to which the address
a of the memory 103 is passed. The encoder 111 provides, at its
outputs, check bits which are based on the data bits v present at
the encoder 111 and the address bits of the address a. In this
case, the check bits can be determined in such a manner that the
data bits, the address bits and the check bits form a code word of
the error code Cod.sub.1. Optionally, the address bits or bits
derived from the address bits cannot be stored in the memory 103;
it is also possible for the address bits or bits derived from the
address bits to be stored in the memory 103. For example, the
parity of the address bits can be stored in the memory 103.
[0328] The correction unit 112 likewise has (in comparison with the
correction unit 105) an additional input to which the address a of
the memory 103 is passed. The same address bits are therefore
respectively available to the encoder 111 and to the correction
unit 105 and can be accordingly taken into account during
correction.
[0329] FIG. 10e shows another example circuit arrangement which is
largely based on the circuit arrangement shown in FIG. 10b. Unlike
the circuit arrangement shown in FIG. 10b, an encoder 113 is
provided instead of the encoder 107 and a correction unit 114 is
provided instead of the correction unit 108.
[0330] The encoder 113 and the correction unit 114 each have an
additional input at which bits are present, which bits are
determined on the basis of the address a of the memory 103. In this
context, a block 115 is provided, which block determines bits f(a)
which are derived from the address bits of the address a and are
then applied to the encoder 113 or to the correction unit 114.
[0331] The encoder 113 provides, at its outputs, check bits which
are based on the data bits u present at the encoder 113 and the
derived bits f(a). In this case, the check bits may be determined
in such a manner that the data bits, the bits formed from the
address bits and the check bits form a code word of the error code
Cod.sub.2. Optionally, the address bits or bits derived from the
address bits cannot be stored in the memory 103.
[0332] The correction unit 114 forms corrected data bits on the
basis of derived bits f(a).
[0333] The block 115 provides, for example, a uniquely determined
function which maps the address bits of the address a to bits
derived therefrom. For example, the function f(a) can determine the
parity of the address bits of the address a.
[0334] FIG. 10f shows a modification of the circuit arrangement
from FIG. 10c. Unlike the circuit arrangement shown in FIG. 10c, an
encoder 116 is provided instead of the encoder 109 and a correction
unit 117 is provided instead of the correction unit 110 in FIG.
10f.
[0335] The encoder 116 and the correction unit 117 each have an
additional input to which address bits of the address A of the
memory 106 are applied. At its outputs, the encoder 116 provides
check bits which can be determined on the basis of the data bits
present at the encoder 116 and the address bits. The correction
unit 117 forms corrected data bits on the basis of the provided
address bits.
Further Advantages, Uses and Examples
[0336] The approach described here enables different fields of
application. For example, it is possible to provide a flash memory
array having a multiplicity of memory cells which are read using a
sense amplifier. The memory cells each comprise a first area and a
second area, the second area having a higher reliability than the
first area. In this case, the sense amplifier can be operated in
different modes.
[0337] For example, the sense amplifier can be operated in a first
mode for reading the second area by carrying out, for example, a
threshold value comparison with a reference value, which allows the
physical values which have been read to be correctly assigned to
the stored digital values in a very reliable manner. This is due to
the fact that the frequency distributions of the physical values
for the digital values stored in the second area of the memory
cells do not have an overlap or have only a small overlap.
[0338] In a second mode of the sense amplifier, both areas (or only
the first area) can be read. In this case, additional reference
values can be used to distinguish the digital data which have been
stored in the first area in a manner corresponding to the frequency
distributions of physical values, and subsequent error detection
and/or error correction can at least partially (or else completely)
compensate for a possibly greater overlap of these frequency
distributions.
[0339] The examples described here therefore make it possible to
use memories with different reading windows in order to make it
possible to quickly access an area of the memory cells which has a
higher reliability than another area of the memory cells. The area
of the memory cells with the reduced reliability can be read in
combination with error correction, for example by means of
buffering in a further memory, and the possible reading errors can
therefore be at least partially corrected.
[0340] Another embodiment involves distributing an odd number of
bits to the memory cell, some of these bits being stored with a
higher reliability than the remainder of the bits. For example,
three bits can be stored in the memory cells as follows: two bits
are stored in the first area and one bit is stored in the second
area (or vice versa). Reference is additionally made to the
documents U.S. Pat. Nos. 8,935,590 and 9,203,437. The extent to
which individual memory cells can assume at least three different
states is explained there.
* * * * *