U.S. patent application number 16/667132 was filed with the patent office on 2020-03-05 for local wiring in between stacked devices.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Effendi Leobandung.
Application Number | 20200075429 16/667132 |
Document ID | / |
Family ID | 65322759 |
Filed Date | 2020-03-05 |
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United States Patent
Application |
20200075429 |
Kind Code |
A1 |
Leobandung; Effendi |
March 5, 2020 |
LOCAL WIRING IN BETWEEN STACKED DEVICES
Abstract
Semiconductor devices and methods are provided to fabricate
field effect transistor (FET) devices having local wiring between
the stacked devices. For example, a semiconductor device includes a
first FET device on a semiconductor substrate, the FET device
comprising a first source/drain layer, and a first gate structure
comprising a gate dielectric layer and a metal gate layer. The
semiconductor device further includes a second FET device
comprising a second source/drain layer, and a second gate structure
comprising a gate dielectric layer and a metal gate layer, wherein
the first and second FET devices are in a stacked configuration.
The semiconductor device further includes one or more conductive
vias in communication with either the first gate structure of the
first FET device or the second gate structure of the second FET
device.
Inventors: |
Leobandung; Effendi;
(Stormville, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
65322759 |
Appl. No.: |
16/667132 |
Filed: |
October 29, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16238142 |
Jan 2, 2019 |
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16667132 |
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15826076 |
Nov 29, 2017 |
10211109 |
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16238142 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/78696 20130101;
H01L 29/78618 20130101; H01L 25/0657 20130101; H01L 25/074
20130101; H01L 29/1079 20130101; H01L 27/0928 20130101; H01L
21/823418 20130101; H01L 29/0676 20130101; H01L 21/823885 20130101;
H01L 29/78642 20130101; H01L 21/823835 20130101; H01L 29/66666
20130101; H01L 29/775 20130101; H01L 25/50 20130101; H01L 29/4232
20130101; H01L 29/0653 20130101; H01L 29/42376 20130101; H01L
21/306 20130101; H01L 21/02603 20130101; B82Y 10/00 20130101; H01L
29/66439 20130101; H01L 21/28123 20130101; H01L 23/535 20130101;
H01L 21/823871 20130101; H01L 29/0847 20130101; H01L 21/823828
20130101; H01L 21/02642 20130101; H01L 21/76895 20130101; H01L
29/7827 20130101; H01L 29/401 20130101 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238; H01L 25/07 20060101 H01L025/07; H01L 29/423 20060101
H01L029/423; H01L 29/06 20060101 H01L029/06; H01L 29/40 20060101
H01L029/40; H01L 29/786 20060101 H01L029/786; H01L 25/00 20060101
H01L025/00; H01L 29/66 20060101 H01L029/66; B82Y 10/00 20060101
B82Y010/00; H01L 29/775 20060101 H01L029/775; H01L 29/08 20060101
H01L029/08; H01L 23/535 20060101 H01L023/535; H01L 27/092 20060101
H01L027/092; H01L 25/065 20060101 H01L025/065; H01L 21/02 20060101
H01L021/02; H01L 21/8234 20060101 H01L021/8234; H01L 29/78 20060101
H01L029/78; H01L 21/768 20060101 H01L021/768 |
Claims
1. A semiconductor device, comprising: a first field-effect
transistor (FET) device on a semiconductor substrate, the FET
device comprising a first source/drain layer, and a first gate
structure comprising a gate dielectric layer and a metal gate
layer; a second FET device comprising a second source/drain layer,
and a second gate structure comprising a gate dielectric layer and
a metal gate layer; wherein the first and second FET devices are in
a stacked configuration and further wherein the second source/drain
layer is disposed on the first source/drain layer; and one or more
conductive vias in communication with either the first gate
structure of the first FET device or the second gate structure of
the second FET device.
2. The semiconductor device of claim 1, wherein the first FET
device is a PFET device and the second FET device is a NFET
device.
3. The semiconductor device of claim 1, wherein the first FET
device is a NFET device and the second FET device is a PFET
device.
4. The semiconductor device of claim 1, wherein the one or more
conductive vias contain a conductive material comprising one of
cobalt, copper, nickel and tungsten.
5. The semiconductor device of claim 1, wherein the one or more
conductive vias comprise a first conductive via communicative with
the first gate structure of the first FET device.
6. The semiconductor device of claim 5, wherein the one or more
conductive vias comprise a second conductive via communicative with
the second source region of the second FET device.
7. The semiconductor device of claim 6, wherein the one or more
conductive vias comprise a third conductive via communicative with
the second gate structure of the second FET device.
8. The semiconductor device of claim 1, wherein the one or more
conductive vias comprise: a first conductive via communicative with
the first gate structure of the first FET device; a second
conductive via communicative with the second source region of the
second FET device; and a third conductive via communicative with
the second gate structure of the second FET device.
9. The semiconductor device of claim 1, wherein the first
source/drain layer and the second source/drain layer are disposed
in an interconnect metal layer.
10. The semiconductor device of claim 9, wherein the interconnect
metal layer is disposed on an insulator layer.
11. A stacked vertical FET comprising: one or more semiconductor
devices, wherein one of the semiconductor devices comprises: a
first FET device on a semiconductor substrate, the FET device
comprising a first source/drain layer, and a first gate structure
comprising a gate dielectric layer and a metal gate layer; a second
FET device comprising a second source/drain layer, and a second
gate structure comprising a gate dielectric layer and a metal gate
layer; wherein the first and second FET devices are in a stacked
configuration and further wherein the second source/drain layer is
disposed on the first source/drain layer; and one or more
conductive vias in communication with either the first gate
structure of the first FET device or the second gate structure of
the second FET device.
12. The stacked vertical FET of claim 11, wherein the first FET
device is a PFET device and the second FET device is a NFET
device.
13. The stacked vertical FET of claim 11, wherein the first FET
device is a NFET device and the second FET device is a PFET
device.
14. The stacked vertical FET of claim 11, wherein the one or more
conductive vias contain a conductive material comprising one of
cobalt, copper, nickel and tungsten.
15. The stacked vertical FET of claim 11, wherein the one or more
conductive vias comprise a first conductive via communicative with
the first gate structure of the first FET device.
16. The stacked vertical FET of claim 15, wherein the one or more
conductive vias comprise a second conductive via communicative with
the second source region of the second FET device.
17. The stacked vertical FET of claim 16, wherein the one or more
conductive vias comprise a third conductive via communicative with
the second gate structure of the second FET device.
18. The stacked vertical FET of claim 11, wherein the one or more
conductive vias comprise: a first conductive via communicative with
the first gate structure of the first FET device; a second
conductive via communicative with the second source region of the
second FET device; and a third conductive via communicative with
the second gate structure of the second FET device.
19. The stacked vertical FET of claim 11, wherein the first
source/drain layer and the second source/drain layer are disposed
in an interconnect metal layer.
20. The stacked vertical FET of claim 19, wherein the interconnect
metal layer is disposed on an insulator layer.
Description
BACKGROUND
[0001] This disclosure relates generally to semiconductor
fabrication techniques and, in particular, to structures and
methods for fabricating stacked field-effect transistor (FET)
devices.
[0002] In a typical complementary metal-oxide-semiconductor (CMOS)
layout, ninety percent of the time a first transistor is connected
to at least a second transistor. For example, a drain of an n-type
transistor is connected to the drain of a p-type transistor to form
an inverter. Other arrangements, such as connections between the
drain of a first transistor connected to the source of a second
transistor, a drain of a first transistor connected to the drain of
a second transistor, or a source of a first transistor connected to
the source of a second transistor are also considered, where the
first and second transistors may be any combination of n-type or
p-type transistors. Hence, stacking transistors one on top of
another is attractive in order to reduce the area required to
accommodate the multiple transistors. However, with normal planar
transistors, stacking is difficult and may involve bonding.
SUMMARY
[0003] Embodiments of the invention include structures and methods
for forming stacked vertical FET devices having local wiring
between the stacked devices.
[0004] For example, one exemplary embodiment includes a method for
fabricating a semiconductor device, comprising:
[0005] forming a first field effect transistor (FET) device on a
semiconductor substrate, the FET device comprising a first
source/drain layer, and a first gate structure comprising a gate
dielectric layer and a metal gate layer;
[0006] forming a second FET device comprising a second source/drain
layer, and a second gate structure comprising a gate dielectric
layer and a metal gate layer; wherein the first and second FET
devices are in a stacked configuration; and
[0007] forming a conductive via communicative with the first gate
structure of the first FET device and the second gate structure of
the second FET device.
[0008] Another exemplary embodiment includes a semiconductor device
which comprises a first FET device on a semiconductor substrate,
the FET device comprising a first source/drain layer, and a first
gate structure comprising a gate dielectric layer and a metal gate
layer. The semiconductor device further comprises a second FET
device comprising a second source/drain layer, and a second gate
structure comprising a gate dielectric layer and a metal gate
layer; wherein the first and second FET devices are in a stacked
configuration. The semiconductor device further comprises one or
more conductive vias in communication with either the first gate
structure of the first FET device or the second gate structure of
the second FET device.
[0009] These and other features, objects and advantages of the
present invention will become apparent from the following detailed
description of illustrative embodiments thereof, which is to be
read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a cross-sectional view of a semiconductor device
after the formation of a set of nanowires and a hard mask on a
semiconductor substrate, in accordance with an embodiment of the
present invention;
[0011] FIG. 2 is a cross-sectional view of the semiconductor device
after depositing a shallow trench isolation (STI) insulator,
according to an embodiment of the invention.
[0012] FIG. 3 is a cross-sectional view of the semiconductor device
after depositing a first set of spacers, according to an embodiment
of the invention.
[0013] FIG. 4 is a cross-sectional view of the semiconductor device
after forming a PFET source region, according to an embodiment of
the invention.
[0014] FIG. 5 is a cross-sectional view of the semiconductor device
after oxidizing the PFET source region, according to an embodiment
of the invention.
[0015] FIG. 6 is a cross-sectional view of the semiconductor device
after selectively removing the first set of spacers, according to
an embodiment of the invention.
[0016] FIG. 7 is a cross-sectional view of the semiconductor device
after forming a PFET gate, according to an embodiment of the
invention.
[0017] FIG. 8 is a cross-sectional view of the semiconductor device
after depositing a first insulator layer, according to an
embodiment of the invention.
[0018] FIG. 9 is a cross-sectional view of the semiconductor device
after depositing a second set of spacers, according to an
embodiment of the invention.
[0019] FIG. 10 is a cross-sectional view of the semiconductor
device after forming a PFET drain region, according to an
embodiment of the invention.
[0020] FIG. 11 is a cross-sectional view of the semiconductor
device after removing the second set of spacers and depositing a
second insulator layer, according to an embodiment of the
invention.
[0021] FIG. 12 is a cross-sectional view of the semiconductor
device after depositing a third set of spacers, according to an
embodiment of the invention.
[0022] FIG. 13 is a cross-sectional view of the semiconductor
device after recessing the second insulator layer, according to an
embodiment of the invention.
[0023] FIG. 14 is a cross-sectional view of the semiconductor
device after forming a NFET drain region, according to an
embodiment of the invention.
[0024] FIGS. 15A and 15B are cross-sectional and top views,
respectively, after deposing a first metal layer, according to an
embodiment of the invention.
[0025] FIGS. 16A and 16B are cross-sectional and top views,
respectively, after patterning the metal gate layer, according to
an embodiment of the invention.
[0026] FIG. 17 is a cross-sectional view after depositing a third
insulator layer, according to an embodiment of the invention.
[0027] FIGS. 18A and 18B are cross-sectional and top views,
respectively, after depositing a second metal layer, according to
an embodiment of the invention.
[0028] FIGS. 19A and 19B are cross-sectional and top views,
respectively, after depositing a spacer layer, according to an
embodiment of the invention.
[0029] FIGS. 20A and 20B are cross-sectional and top views,
respectively, after forming a NFET source region, according to an
embodiment of the invention.
[0030] FIGS. 21A and 21B are cross-sectional and top views,
respectively, after forming local wiring in between the stacked
PFET source/drain region and NFET source/drain region, according to
an embodiment of the invention.
DETAILED DESCRIPTION
[0031] It is to be understood that the various layers, structures,
and regions shown in the accompanying drawings are schematic
illustrations that are not drawn to scale. In addition, for ease of
explanation, one or more layers, structures, and regions of a type
commonly used to form semiconductor devices or structures may not
be explicitly shown in a given drawing. This does not imply that
any layers, structures, and regions not explicitly shown are
omitted from the actual semiconductor structures.
[0032] Furthermore, it is to be understood that the embodiments
discussed herein are not limited to the particular materials,
features, and processing steps shown and described herein. In
particular, with respect to semiconductor processing steps, it is
to be emphasized that the descriptions provided herein are not
intended to encompass all of the processing steps that may be
required to form a functional semiconductor integrated circuit
device. Rather, certain processing steps that are commonly used in
forming semiconductor devices, such as, for example, wet cleaning
and annealing steps, are purposefully not described herein for
economy of description.
[0033] Moreover, the same or similar reference numbers are used
throughout the drawings to denote the same or similar features,
elements, or structures, and thus, a detailed explanation of the
same or similar features, elements, or structures will not be
repeated for each of the drawings. It is to be understood that the
terms "about" or "substantially" as used herein with regard to
thicknesses, widths, percentages, ranges, etc., are meant to denote
being close or approximate to, but not exactly. For example, the
term "about" or "substantially" as used herein implies that a small
margin of error may be present, such as 1% or less than the stated
amount.
[0034] An illustrative embodiment for forming a semiconductor
device will be discussed below with reference to FIGS. 1-21B.
Referring now to the figures, FIG. 1 is a cross-sectional view of
semiconductor structure 100 illustrating an initial step in forming
vertically stacked transistors. The figure illustrates an exemplary
semiconductor substrate 102 and a hard mask layer 106 arranged on
vertical nanowires 104 of semiconductor substrate 102. Suitable
substrate materials include, for example, Si (silicon), strained
Si, SiC (silicon carbide), Ge (geranium), SiGe (silicon germanium),
SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, GaAs
(gallium arsenide), InAs (indium arsenide), InP (indium phosphide),
or any combination thereof.
[0035] Hard mask material 106 can be, for example, an oxide or
nitride material. Hard mask 106 is deposited using a suitable
deposition process such as, for example, chemical vapor deposition
(CVD) and remains on the top surface of vertical nanowires 104
after patterning and etching processes (not shown) are
completed.
[0036] The vertical nanowires 104 have sidewalls that are
substantially vertical. Although two vertical nanowires 104 are
shown in FIG. 1, the number of vertical nanowires 104 should not be
considered limiting. To form the vertical nanowires 104,
lithography and etching are performed. Lithography can include
forming a photoresist (not shown) on the hard mask layer 106,
exposing the photoresist to a desired pattern of radiation, and
then developing the exposed photoresist with a resist developer to
provide a patterned photoresist on top of the hard mask layer 106.
At least one etch is employed to transfer the pattern from the
patterned photoresist into hard mask layer 106 and the substrate
102. The etching process may be a dry etch (e.g., reactive ion
etching, plasma etching, ion beam etching, or laser ablation). The
etching process may be a wet chemical etch (e.g., with potassium
hydroxide, or sulfuric acid and hydrogen peroxide). Both dry
etching and wet chemical etching processes may be used. After
transferring the pattern, the patterned photoresist is removed
utilizing resist stripping processes, for example, ashing. Ashing
is performed using a suitable reaction gas, for example, O.sub.2,
N.sub.2, H.sub.2/N.sub.2, O.sub.3, CF.sub.4, or any combination
thereof.
[0037] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 2 in which a
shallow trench isolation (STI) insulator region 108 is formed on
substrate 102 and around vertical nanowires 104. As is known in the
art, an STI oxide region is used to prevent interaction between
adjacent components of a semiconductor device. For example, the STI
oxide region may be used to prevent electronic current leakage
between the adjacent components of the semiconductor device. The
deposited STI insulator region 108 is then planarized and recessed
(steps not shown) as illustrated in FIG. 2. Suitable STI insulators
include, for example, oxides such as silicon dioxide,
tetraethylorthosilicate (TEOS) oxide, or other insulator material.
In some embodiments, planarizing includes CMP.
[0038] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 3 in which spacers
110 are formed on the sidewalls of vertical nanowires 104 and hard
mask 106. The spacers 110 can be an insulator spacer material such
as a dielectric material, which can be, for example, silicon
nitride, silicon oxide, silicon oxynitride, a dielectric metal
oxide, a dielectric metal nitride, or a combination thereof. The
spacers 110 can be formed, for example, by depositing an insulator
spacer material layer, and anisotropically etching the insulator
spacer material layer. Horizontal portions of the insulator spacer
material layer are removed by the anisotropic etch, and remaining
vertical portions of the insulator spacer material layer constitute
the spacers 110.
[0039] A next step in forming vertically stacked transistors is
illustrated in FIG. 4 in which portions of STI insulator 108 are
recessed which reduces the thickness of STI insulator 108, and
exposes a portion of nanowires 104. Portions of the STI insulator
108 may be removed by, for example, an anisotropic etching process
such as reactive ion etching or wet etching that selectively
removes the STI insulator 108 material. In this exemplary
embodiment, a source region 112 is then formed by, for example,
growing epitaxial semiconductor material on the exposed surface of
STI insulator 108 and on exposed sidewall portions of nanowires
104. The epitaxial growth process is performed to deposit a
crystalline layer onto a crystalline substrate beneath. The
underlying substrate acts as a seed crystal. Epitaxial layers may
be grown from gaseous or liquid precursors. Epitaxial silicon
material may be grown using vapor-phase epitaxy (VPE),
molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other
suitable process. The type of epitaxial material and dopant used to
form the source region 112 will vary depending on whether the FET
devices are P-type or N-type devices. Examples of semiconductor
materials that may be suitable for the epitaxial growth of the
source region 112 include, but are not limited to, silicon (single
crystal, polysilicon, or amorphous), germanium (single crystal,
polycrystalline, or amorphous), or a combination thereof.
[0040] After the semiconductor material is grown, it will be doped
with dopant atoms using, for example, in-situ doping or ion
implantation or in-situ doping during epitaxy. In this illustrative
embodiment, the semiconductor material is doped with a p-type
dopant such as, for example, boron, aluminum, gallium, indium, or
alloys thereof, to form a PFET source region. In other embodiments
as discussed below, the semiconductor material may be doped with a
n-type dopant such as, for example, phosphorus, antimony, arsenic,
or alloys thereof. After the doping process, the semiconductor
material may have dopant a concentration ranging from approximately
1.times.10.sup.19 atoms/cm.sup.3 to approximately 5.times.10.sup.21
atoms/cm.sup.3.
[0041] As one skilled in the art will appreciate, FIGS. 1-21
illustrate forming vertically stacked transistors for semiconductor
device 100 in which the transistor at the bottom of the stack is a
PFET transistor and the transistor at the top of the stack is an
NFET transistor. However, the invention is not so limited and may
include structures in which the transistor at the bottom of the
stack and the transistor at the top of the stack may be a PFET and
PFET, an NFET and NFET, or a NFET and PFET respectively.
[0042] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 5 in which a hard
mask 114 is formed by, for example, growing an oxide film on the
surface of source region 112 to prevent further epitaxial growth.
The oxidized hard mask 114 is formed for example, using a low
temperature plasma oxidation process which helps prevent damage to
source region 112. In one embodiment, hard mask 114 may be formed
by oxidizing source region 112 in an oxygen ambient or by
nitridizing in a nitrogen containing ambient.
[0043] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 6 in which spacers
110 are removed by; for example, an anisotropic etching process
such as reactive ion etching that selectively removes the spacers
110 from semiconductor device 100.
[0044] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 7 in which a PFET
gate structure is formed by, for example, gate dielectric
deposition and gate metal deposition. For example, a gate
dielectric layer 116 can be formed along the outer surface, or
exterior, of each nanowire 104, and along the top surface of hard
mask 114. Gate dielectric layer 116 can be a layer of a high
dielectric constant (high-k) material comprising a dielectric metal
oxide and having a dielectric constant that is greater than, for
example, the dielectric constant of silicon nitride (7.5). The
high-k dielectric layer may be formed by methods well known in the
art including, for example, chemical vapor deposition (CVD), ALD,
molecular beam deposition (MBD), pulsed laser deposition (PLD) and
liquid source misted chemical deposition (LSMCD), etc. The
dielectric metal oxide comprises a metal and oxygen, and optionally
nitrogen and/or silicon. Suitable high-k dielectric materials
include, for example, HfO.sub.2, ZrO.sub.2, La.sub.2O.sub.3,
Al.sub.2O.sub.3, TiO.sub.2, SrTiO.sub.3, LaAlO.sub.3,
Y.sub.2O.sub.3, HfO.sub.xN.sub.y, ZrO.sub.xN.sub.y,
La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y, TiO.sub.xN.sub.y,
SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y, Y.sub.2O.sub.xN.sub.y, a
silicate thereof, and an alloy thereof. Each value of x is
independently established from about 0.5 to about 3.0 and each
value of y is independently established from about 0 to about 2.0.
The thickness of the high-k dielectric layer may be from about 1 nm
to about 10 nm, or from about 1.5 nm to about 3 nm. The high-k
dielectric layer can have an effective oxide thickness (EOT) on the
order of, or less than, about 1 nm.
[0045] The gate metal 118 can be deposited directly on a top
surface of the high-k dielectric layer by, for example, CVD, ALD or
physical vapor deposition (PVD). Suitable gate metals include, for
example, a metal system selected from one or more of TiN, TiC, TaN,
TaC, TaSiN, HiN, W, Al and Ru, and may be selected at least in part
based on the desired work function (WF) of the device (NFET or
PFET), as is known. The metal gate may be recessed within the PFET
gate and a gate cap may be deposited upon the recessed metal gate
within the PFET gate (not shown).
[0046] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 8 in which a
planarized first insulator layer 120 is deposited on the PFET gate.
The first insulator layer 120 can be formed using suitable
dielectric materials including, for example, silicon oxide,
hydrogenated silicon carbon oxide (SiCOH), SiCH, SiCNH, or other
types of silicon based low-k dielectrics (e.g., k less than about
4.0), porous dielectrics, or known ULK (ultra-low-k) dielectric
materials (with k less than about 2.5). For example, the insulator
layer 120 may comprise a single deposited layer of insulating
material, or multiple layers of insulating material (e.g., a first
layer of a flowable oxide and a second layer of insulating material
formed on the first layer). The insulator layer 120 may be
deposited using known deposition techniques, such as, for example,
ALD, plasma-enhanced chemical vapor deposition (PECVD), PVD, or
spin-on deposition.
[0047] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 9 in which spacers
122 are formed on the sidewalls of vertical nanowires 104 and hard
mask 106. The spacers 122 can be formed as discussed above with
respect to spacers 110 and be of the same or similar insulator
spacer material.
[0048] A next step in forming vertically stacked transistors for
semiconductor device 100 is illustrated in FIG. 10 in which a drain
region 124 is formed on insulator layer 120 and on exposed sidewall
portions of nanowires 104. Drain 124 can be formed by, for example,
growing epitaxial semiconductor material and then doping the
epitaxial layer in a similar manner as source region 112 as
discussed above. For example, a semiconductor material suitable for
the epitaxial growth of a PFET drain is grown. Next, the epitaxial
layer will be doped with a p-type dopant. In other embodiments, the
epitaxial layer may be doped with a n-type dopant. Prior to forming
the PFET drain 124, insulator layer 120 is first recessed (not
shown) to reduce the thickness of insulator layer 120 in a similar
manner as with insulator layer 108 discussed above.
[0049] FIGS. 11-20A/B illustrate an embodiment for forming the
vertical NFET transistor stacked on top of the vertical PFET
transistor formed as discussed above. FIG. 11 illustrates first
selectively removing spacers 122 from the sidewalls of nanowires
104 and hard mask 106 in a similar manner as spacers 110 discussed
above. Next, planarized second insulator layer 126 is deposited on
first insulator layer 120, and PFET drain 124. Planarized insulator
layer 126 is formed in a similar manner and of similar material as
first insulator layer 120 discussed above.
[0050] FIG. 12 illustrates a side view of the next step of forming
the top NFET transistor following deposition of spacers 128 on the
exposed portions of vertical nanowires 104 and hard mask 106.
Spacers 128 can be deposited in a similar manner and be of similar
insulator spacer material as spacers 110 and 122 discussed
above.
[0051] FIG. 13 illustrates a side view of the next step of forming
the top NFET transistor following recessing insulator layer 126 and
exposing the top surface of PFET drain 124. Insulator layer 126 is
recessed to reduce the thickness of insulator layer 126 in a
similar manner as with insulator layers 108 and 120 discussed
above.
[0052] FIG. 14 illustrates a side view of the next step of forming
the top NFET transistor following forming the drain region 130.
Drain 130 can be formed by, for example, growing a drain epi and
then doping the drain epi in a similar manner as drain 124 as
discussed above. In this exemplary embodiment, a semiconductor
material suitable for the epitaxial growth of an NFET drain is
grown. Next, the drain epi will be doped with a n-type dopant as
discussed above. In other embodiments, the semiconductor material
may be doped with a p-type dopant.
[0053] FIGS. 15A and 15B illustrate a cross-sectional view and a
top view, respectively, of the next step of forming the top NFET
transistor. In this illustrative embodiment, second insulator layer
126 is first recessed to reduce the thickness of second insulator
layer 126 in a similar manner as with insulator layers 108 and 120
discussed above. Next, interconnect metal layer 132 is deposited on
the top surface of second insulator layer 126 and the exposed
sidewalls of drains 124 and 130. Interconnect metal layer 132 is
then planarized to a uniform height as the top surface of drain
130. Interconnect metal layer 132 provides the connection to both
the p+ drain and the n+ drain of the stacked vertical PFET and NFET
devices to other devices or area. Suitable metal for interconnect
metal layer 132 may include, for example, W, Ni, Co, Ti, and
Pt.
[0054] FIGS. 16A and 16B illustrate a cross-sectional view and a
top view, respectively, of the next step of forming the top NFET
transistor. In this illustrative embodiment, interconnect metal
layer 132 is patterned using known lithography and etching as
necessary to provide for a local device interconnect as illustrated
in FIGS. 16A and 16B.
[0055] FIG. 17 illustrates a cross-sectional view of the next step
of forming the top NFET transistor. In this illustrative
embodiment, spacers 128 are selectively removed in a similar manner
as with spacers 110 and 122 discussed above. Next, a first NFET
spacer layer 134 is deposited on second insulator layer 126 and
over the top surface of drain 130 and the top and side surfaces of
interconnect metal layer 132. Spacer layer 134 is a thin insulating
layer, such as for example, an oxide, SiNx, SiBCN, or SiOCN, used
to separate drain region 130 from gate metal region that will be
deposited on semiconductor structure 100. The spacer layer 134 is
then planarized and recessed as necessary.
[0056] FIGS. 18A and 18B illustrate a cross-sectional view and a
top view, respectively, of the next step of forming the top NFET
transistor. In this illustrative embodiment, an NFET gate structure
is formed by, for example, gate dielectric deposition and gate
metal deposition. For example, a gate dielectric layer 136 can be
formed along the outer surface, or exterior, of each nanowire 104,
and along the top surface of NFET spacer layer 134. Gate dielectric
layer 136 can be formed in a same or similar manner and material as
gate dielectric layer 116 discussed above. Metal gate layer 138 is
then formed on at least a portion of the top surface of gate
dielectric layer 136 and on the sidewalls of gate dielectric layer
136 on nanowires 104. Metal gate layer 138 can be formed in a
similar manner and of similar material as metal gate layer 118
discussed above. Metal gate layer 138 is then planarized to a
height that is uniform with the gate dielectric layer 136 formed on
the sidewalls of nanowires 104.
[0057] FIGS. 19A and 19B illustrate a cross-sectional view and a
top view, respectively, of the next step of forming the top NFET
transistor. In this illustrative embodiment, a second NFET spacer
layer 140 is deposited over the top surfaces of gate dielectric
layer 136 and metal gate layer 138. Second NFET spacer layer 140
can be formed in a similar manner and of similar material as first
NFET spacer layer 134. The second NFET spacer layer 140 is then
planarized and recessed as necessary.
[0058] FIGS. 20A and 20B illustrate a cross-sectional view and a
top view, respectively, of the next step of forming the top NFET
transistor. In this illustrative embodiment, the NFET device is
completed by forming a second source region 142 on semiconductor
device 100. Source region 142 is formed by, for example, growing
epitaxial semiconductor material on the top surface of second NFET
spacer layer 140 and on exposed sidewall portions of nanowires 104
in a similar manner as source region 112 discussed above. In this
exemplary embodiment, a semiconductor material suitable for the
epitaxial growth of an NFET source is grown as further discussed
above. Next, the epitaxial layer will be doped with a n-type dopant
as also discussed above. In other embodiments, the semiconductor
material may be doped with a p-type dopant. The portion of the
semiconductor nanowire between the source region 142 and drain
region 130 may be referred to herein as a NFET channel portion (or
channel region) 144. Likewise, the portion of the semiconductor
nanowire between the source region 141 and drain region 124 may be
referred to herein as a PFET channel portion (or channel region)
146.
[0059] FIGS. 21A and 21B illustrate the completed vertically
stacked semiconductor device 100 with metal contacts including vias
148, 152 and 154 and metal contact 150. In one illustrative
embodiment, a conductive via 148 is formed as a communicative node.
In one illustrative embodiment, a conductive via 150 communicative
with the second source region 142 of the second FET device is
formed. In one illustrative embodiment, a conductive via 152
communicative with the second gate structure of the second FET
device is formed. In one illustrative embodiment, a conductive via
154 communicative with the first gate structure of the first FET
device is formed. For example, conductive via 152 can be formed by
first depositing a third insulator layer 141 on the second spacer
layer 140 and over a top surface of the second source region 142.
Third insulator layer 141 is formed in a similar manner and of
similar material as second insulator layer 126 discussed above.
Next, conductive via 152 is formed by selectively etching third
insulator layer 141, and second spacer layer 140 such that the via
is communicative with the second gate structure, i.e., metal gate
138 of the second FET device. A conductive material is then
deposited within the via. Suitable conductive material includes,
for example, cobalt, copper, nickel or tungsten. The depositing
step may be followed by or accompanied with an annealing step. As
one skilled in the art will readily appreciate, conductive vias
148, 150 and 154 can be formed in a similar manner as conductive
via 152.
[0060] It is to be understood that the methods discussed herein for
fabricating semiconductor structures can be incorporated within
semiconductor processing flows for fabricating other types of
semiconductor devices and integrated circuits with various analog
and digital circuitry or mixed-signal circuitry. In particular,
integrated circuit dies can be fabricated with various devices such
as transistors, diodes, capacitors, inductors, etc. An integrated
circuit in accordance with embodiments can be employed in
applications, hardware, and/or electronic systems. Suitable
hardware and systems for implementing embodiments of the invention
may include, but are not limited to, personal computers,
communication networks, electronic commerce systems, portable
communications devices (e.g., cell phones), solid-state media
storage devices, functional circuitry, etc. Systems and hardware
incorporating such integrated circuits are considered part of the
embodiments described herein.
[0061] Furthermore, various layers, regions, and/or structures
described above may be implemented in integrated circuits (chips).
The resulting integrated circuit chips can be distributed by the
fabricator in raw wafer form (that is, as a single wafer that has
multiple unpackaged chips), as a bare die, or in a packaged form.
In the latter case, the chip is mounted in a single chip package
(such as a plastic carrier, with leads that are affixed to a
motherboard or other higher level carrier) or in a multichip
package (such as a ceramic carrier that has either or both surface
interconnections or buried interconnections). In any case, the chip
is then integrated with other chips, discrete circuit elements,
and/or other signal processing devices as part of either (a) an
intermediate product, such as a motherboard, or (b) an end product.
The end product can be any product that includes integrated circuit
chips, ranging from toys and other low-end applications to advanced
computer products having a display, a keyboard or other input
device, and a central processor.
[0062] Although illustrative embodiments have been described herein
with reference to the accompanying drawings, it is to be understood
that the invention is not limited to those precise embodiments, and
that various other changes and modifications may be made by one
skilled in art without departing from the scope or spirit of the
invention.
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