U.S. patent application number 16/432413 was filed with the patent office on 2019-12-05 for methods for performing multiple memory operations in response to a single command and memory devices and systems employing the s.
The applicant listed for this patent is Micron Technology, Inc.. Invention is credited to Matthew A. Prather, Randall J. Rooney, Frank F. Ross.
Application Number | 20190370195 16/432413 |
Document ID | / |
Family ID | 68617727 |
Filed Date | 2019-12-05 |
United States Patent
Application |
20190370195 |
Kind Code |
A1 |
Prather; Matthew A. ; et
al. |
December 5, 2019 |
METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A
SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE
SAME
Abstract
Memory devices, memory systems, and methods of operating memory
devices and systems are disclosed in which a single command can
trigger a memory device to perform multiple operations, such as a
single refresh command that triggers the memory device to both
perform a refresh command and to perform a mode register read. One
such memory device comprises a memory, a mode register, and
circuitry configured, in response to receiving a command to perform
a refresh operation at the memory, to perform the refresh operation
at the memory, and to perform a read of the mode register. The
memory can be a first memory portion, the memory device can
comprise a second memory portion, and the circuitry can be further
configured, in response to the command, to provide on-die
termination at the second memory portion of the memory system
during at least a portion of the read of the mode register.
Inventors: |
Prather; Matthew A.; (Boise,
ID) ; Ross; Frank F.; (Boise, ID) ; Rooney;
Randall J.; (Boise, ID) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Family ID: |
68617727 |
Appl. No.: |
16/432413 |
Filed: |
June 5, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16030746 |
Jul 9, 2018 |
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16432413 |
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62680422 |
Jun 4, 2018 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 13/1689 20130101;
G11C 11/4093 20130101; G11C 11/40626 20130101; G06F 13/4086
20130101; G06F 3/0673 20130101; G06F 3/0604 20130101; G11C 11/40603
20130101; G06F 3/0625 20130101; G11C 11/40611 20130101; G11C 11/406
20130101; G11C 7/22 20130101; G06F 3/0659 20130101 |
International
Class: |
G06F 13/16 20060101
G06F013/16; G11C 11/406 20060101 G11C011/406 |
Claims
1. A memory device, comprising: a first memory portion; a second
memory portion; a mode register; and circuitry configured, in
response to receiving a command to perform a refresh operation at
the first memory portion, to: perform the refresh operation at the
first memory portion, perform a read of the mode register, and
provide on-die termination at the second memory portion during at
least a portion of the read of the mode register.
2. The memory device of claim 1, wherein the read of the mode
register includes outputting data from the mode register from the
memory device.
3. The memory device of claim 2, wherein the outputted data
includes information corresponding to a temperature of the first
memory portion.
4. The memory device of claim 2, wherein the outputted data
includes information corresponding to a refresh rate of the first
memory portion.
5. The memory device of claim 1, wherein the command has a duration
on a command/address bus of the memory device of a single clock
cycle of the memory device.
6. The memory device of claim 1, wherein the mode register
corresponds to the first memory portion.
7. A method of operating a memory system, comprising: receiving a
command instructing a first portion of the memory system to perform
a refresh operation; in response to the command, performing the
refresh operation at the first portion of the memory system,
performing a read of a mode register of the memory system, and
providing on-die termination at a second portion of the memory
system during at least a portion of the read of the mode
register.
8. The method of claim 7, wherein the read of the mode register
includes outputting data from the mode register from the memory
system.
9. The method of claim 8, wherein the outputted data includes
information corresponding to a temperature of the first
portion.
10. The method of claim 8, wherein the outputted data includes
information corresponding to a refresh rate of the first
portion.
11. The method of claim 7, wherein the command has a duration on a
command/address bus of the memory system of a single clock cycle of
the memory system.
12. The method of claim 7, further comprising: receiving at least a
first chip select signal indicating which of the first and second
portions are to perform the refresh operation.
13. The method of claim 7, further comprising: receiving at least a
first enable signal indicating that the second portion is to
provide the on-die termination.
14. A method of operating a memory system, comprising: sending a
command instructing a first portion of the memory system to perform
a refresh operation; in response to the command to perform a
refresh operation, receiving data output from a mode register of
the memory system while a second portion of the memory system
provides on-die termination.
15. The method of claim 14, wherein the outputted data includes
information corresponding to a temperature and/or a refresh rate of
the first portion.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 16/030,746, filed Jul. 9, 2018; which claims the benefit of
U.S. Provisional Application No. 62/680,422, filed Jun. 4, 2018;
each of which is incorporated herein by reference in its
entirety.
[0002] This application contains subject matter related to an U.S.
patent application by Matthew A. Prather et al. titled "METHODS FOR
PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE
COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME". The
related application is assigned to Micron Technology, Inc., and is
identified as U.S. application Ser. No. 16/030,740, filed Jul. 9,
2018. The subject matter thereof is incorporated herein by
reference thereto.
TECHNICAL FIELD
[0003] The present disclosure generally relates to memory devices
and systems, and more particularly to methods for performing
multiple memory operations in response to a single command memory
devices and systems employing the same.
BACKGROUND
[0004] Memory devices are widely used to store information related
to various electronic devices such as computers, wireless
communication devices, cameras, digital displays, and the like.
Information is stored by programming different states of a memory
cell. Various types of memory devices exist, including magnetic
hard disks, random access memory (RAM), read only memory (ROM),
dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and others.
Memory devices may be volatile or non-volatile. Improving memory
devices, generally, may include increasing memory cell density,
increasing read/write speeds or otherwise reducing operational
latency, increasing reliability, increasing data retention,
reducing power consumption, or reducing manufacturing costs, among
other metrics.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is a simplified block diagram schematically
illustrating a memory device in accordance with an embodiment of
the present technology.
[0006] FIGS. 2 and 3 are simplified timing diagrams schematically
illustrating the operation of memory devices and systems.
[0007] FIGS. 4 through 6 are simplified timing diagrams
schematically illustrating the operation of memory devices and
systems in accordance with embodiments of the present
technology.
[0008] FIG. 7 is a flow chart illustrating a method of operating a
memory system in accordance with an embodiment of the present
technology.
DETAILED DESCRIPTION
[0009] Many memory devices, such as double data rate (DDR) DRAM
devices, are capable of operating in a variety of modes (e.g., at
different clock speeds, with different refresh rates, etc.). In
many cases, various operating parameters of the memory device
(e.g., voltage, temperature, device age, etc.) may be utilized to
determine an appropriate mode. In some memory devices, a connected
host may periodically poll one or more of these operating
parameters of a memory device to determine whether to adjust the
mode. For example, a connected host may poll the device temperature
(e.g., or information corresponding to the device temperature) to
determine whether to modify the refresh rate of the device. The
polling of the device temperature may require a dedicated command
on the command/address bus of the memory device, and the polling
may be frequent enough to adversely impact (e.g., via congestion)
the command/address bus.
[0010] Accordingly, several embodiments of the present technology
are directed to memory devices, systems including memory devices,
and methods of operating memory devices in which a single command
on the command/address bus can trigger a memory device to perform
more than one operation, such as a single refresh command that
triggers the memory device to both perform a refresh command and to
perform a mode register read (e.g., and to output information
therefrom to the host device). In one embodiment, a memory device
comprises a memory, a mode register, and circuitry configured, in
response to receiving a command to perform a refresh operation at
the memory, to perform the refresh operation at the memory, and to
perform a read of the mode register. In some embodiments, the
memory can be a first memory portion, the memory device can
comprise a second memory portion, and the circuitry can be further
configured, in response to the command, to provide on-die
termination at the second memory portion of the memory system
during at least a portion of the read of the mode register.
[0011] FIG. 1 is a block diagram schematically illustrating a
memory device 100 in accordance with an embodiment of the present
technology. The memory device 100 may include an array of memory
cells, such as memory array 150. The memory array 150 may include a
plurality of banks (e.g., banks 0-15 in the example of FIG. 1), and
each bank may include a plurality of word lines (WL), a plurality
of bit lines (BL), and a plurality of memory cells arranged at
intersections of the word lines and the bit lines. The selection of
a word line WL may be performed by a row decoder 140, and the
selection of a bit line BL may be performed by a column decoder
145. Sense amplifiers (SAMP) may be provided for corresponding bit
lines BL and connected to at least one respective local I/O line
pair (LIOT/B), which may in turn be coupled to at least respective
one main I/O line pair (MIOT/B), via transfer gates (TG), which can
function as switches.
[0012] The memory device 100 may employ a plurality of external
terminals that include command and address terminals coupled to a
command bus and an address bus to receive command signals CMD and
address signals ADDR, respectively. The memory device may further
include a chip select terminal to receive a chip select signal CS,
clock terminals to receive clock signals CK and CKF, data clock
terminals to receive data clock signals WCK and WCKF, data
terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS,
VDDQ, and VSSQ.
[0013] The command terminals and address terminals may be supplied
with an address signal and a bank address signal from outside. The
address signal and the bank address signal supplied to the address
terminals can be transferred, via a command/address input circuit
105, to an address decoder 110. The address decoder 110 can receive
the address signals and supply a decoded row address signal (XADD)
to the row decoder 140, and a decoded column address signal (YADD)
to the column decoder 145. The address decoder 110 can also receive
the bank address signal (BADD) and supply the bank address signal
to both the row decoder 140 and the column decoder 145.
[0014] The command and address terminals may be supplied with
command signals CMD, address signals ADDR, and chip selection
signals CS, from a memory controller. The command signals may
represent various memory commands from the memory controller (e.g.,
including access commands, which can include read commands and
write commands). The select signal CS may be used to select the
memory device 100 to respond to commands and addresses provided to
the command and address terminals. When an active CS signal is
provided to the memory device 100, the commands and addresses can
be decoded and memory operations can be performed. The command
signals CMD may be provided as internal command signals ICMD to a
command decoder 115 via the command/address input circuit 105. The
command decoder 115 may include circuits to decode the internal
command signals ICMD to generate various internal signals and
commands for performing memory operations, for example, a row
command signal to select a word line and a column command signal to
select a bit line. The internal command signals can also include
output and input activation commands, such as clocked command
CMDCK.
[0015] When a read command is issued and a row address and a column
address are timely supplied with the read command, read data can be
read from memory cells in the memory array 150 designated by these
row address and column address. The read command may be received by
the command decoder 115, which can provide internal commands to
input/output circuit 160 so that read data can be output from the
data terminals DQ, RDQS, DBI, and DMI via read/write amplifiers 155
and the input/output circuit 160 according to the RDQS clock
signals. The read data may be provided at a time defined by read
latency information RL that can be programmed in the memory device
100, for example, in a mode register (not shown in FIG. 1). The
read latency information RL can be defined in terms of clock cycles
of the CK clock signal. For example, the read latency information
RL can be a number of clock cycles of the CK signal after the read
command is received by the memory device 100 when the associated
read data is provided.
[0016] When a write command is issued and a row address and a
column address are timely supplied with the command, write data can
be supplied to the data terminals DQ, DBI, and DMI according to the
WCK and WCKF clock signals. The write command may be received by
the command decoder 115, which can provide internal commands to the
input/output circuit 160 so that the write data can be received by
data receivers in the input/output circuit 160, and supplied via
the input/output circuit 160 and the read/write amplifiers 155 to
the memory array 150. The write data may be written in the memory
cell designated by the row address and the column address. The
write data may be provided to the data terminals at a time that is
defined by write latency WL information. The write latency WL
information can be programmed in the memory device 100, for
example, in the mode register (not shown in FIG. 1). The write
latency WL information can be defined in terms of clock cycles of
the CK clock signal. For example, the write latency information WL
can be a number of clock cycles of the CK signal after the write
command is received by the memory device 100 when the associated
write data is received.
[0017] The power supply terminals may be supplied with power supply
potentials VDD and VSS. These power supply potentials VDD and VSS
can be supplied to an internal voltage generator circuit 170. The
internal voltage generator circuit 170 can generate various
internal potentials VPP, VOD, VARY, VPERI, and the like based on
the power supply potentials VDD and VSS. The internal potential VPP
can be used in the row decoder 140, the internal potentials VOD and
VARY can be used in the sense amplifiers included in the memory
array 150, and the internal potential VPERI can be used in many
other circuit blocks.
[0018] The power supply terminal may also be supplied with power
supply potential VDDQ. The power supply potential VDDQ can be
supplied to the input/output circuit 160 together with the power
supply potential VSS. The power supply potential VDDQ can be the
same potential as the power supply potential VDD in an embodiment
of the present technology. The power supply potential VDDQ can be a
different potential from the power supply potential VDD in another
embodiment of the present technology. However, the dedicated power
supply potential VDDQ can be used for the input/output circuit 160
so that power supply noise generated by the input/output circuit
160 does not propagate to the other circuit blocks.
[0019] The clock terminals and data clock terminals may be supplied
with external clock signals and complementary external clock
signals. The external clock signals CK, CKF, WCK, WCKF can be
supplied to a clock input circuit 120. The CK and CKF signals can
be complementary, and the WCK and WCKF signals can also be
complementary. Complementary clock signals can have opposite clock
levels and transition between the opposite clock levels at the same
time. For example, when a clock signal is at a low clock level a
complementary clock signal is at a high level, and when the clock
signal is at a high clock level the complementary clock signal is
at a low clock level. Moreover, when the clock signal transitions
from the low clock level to the high clock level the complementary
clock signal transitions from the high clock level to the low clock
level, and when the clock signal transitions from the high clock
level to the low clock level the complementary clock signal
transitions from the low clock level to the high clock level.
[0020] Input buffers included in the clock input circuit 120 can
receive the external clock signals. For example, when enabled by a
CKE signal from the command decoder 115, an input buffer can
receive the CK and CKF signals and the WCK and WCKF signals. The
clock input circuit 120 can receive the external clock signals to
generate internal clock signals ICLK. The internal clock signals
ICLK can be supplied to an internal clock circuit 130. The internal
clock circuit 130 can provide various phase and frequency
controlled internal clock signal based on the received internal
clock signals ICLK and a clock enable signal CKE from the
command/address input circuit 105. For example, the internal clock
circuit 130 can include a clock path (not shown in FIG. 1) that
receives the internal clock signal ICLK and provides various clock
signals to the command decoder 115. The internal clock circuit 130
can further provide input/output (IO) clock signals. The 10 clock
signals can be supplied to the input/output circuit 160 and can be
used as a timing signal for determining an output timing of read
data and the input timing of write data. The 10 clock signals can
be provided at multiple clock frequencies so that data can be
output from and input to the memory device 100 at different data
rates. A higher clock frequency may be desirable when high memory
speed is desired. A lower clock frequency may be desirable when
lower power consumption is desired. The internal clock signals ICLK
can also be supplied to a timing generator 135 and thus various
internal clock signals can be generated.
[0021] Memory devices such as the memory device 100 of FIG. 1 can
be capable of operating in a variety of modes (e.g., at different
clock speeds, with different refresh rates, etc.). In many cases,
various operating parameters of the memory device 100 (e.g.,
voltage, temperature, device age, etc.) may be stored in a mode
register thereof and utilized (e.g., by a connected host device) to
determine an appropriate mode. For example, a connected host may
periodically poll one or more of these operating parameters of the
memory device 100 to determine whether to adjust the mode (e.g.,
increasing the refresh rate due to an elevated device temperature,
or reducing the refresh rate due to a reduced device
temperature).
[0022] One approach to polling operating parameters of a memory
device includes a host sending a dedicated command to the memory
device to perform a mode register read operation and to output
values therefrom on the data bus of the memory device. For example,
as can be seen with reference to the simplified timing diagram 200
illustrated in FIG. 2, in response to a host device providing, on a
command/address bus 220, a mode register read command (comprising
first a first MRR.sub.1 portion 222 and a second MRR.sub.2 portion
223), the memory device outputs (e.g., after a predetermined delay)
mode register read (MRR) data 251 to the host device over a data
bus 250 thereof. As can be seen with reference to FIG. 2, the mode
register read command follows shortly (e.g., immediately) after a
refresh command 221, as is a common practice for polling memory
devices for operating parameters that may impact the desired
refresh rate thereof. As can be further seen with reference to FIG.
2, the mode register read command consumes two cycles of the device
clock 210 on the command/address bus.
[0023] FIG. 3 is likewise a simplified timing diagram schematically
300 illustrating the operation of a memory system with multiple
memory portions (e.g., channels, dies, ranks, banks, etc.). As can
be seen with reference FIG. 3, in response to a host device
providing, on a command/address bus 320, a mode register read
command (comprising first a first MRR.sub.1 portion 322 and a
second MRR.sub.2 portion 323) to a first memory portion (e.g., as
indicated by asserting a low chip-select signal 331 on a first chip
select terminal 330 during the first clock cycle of the mode
register read command), the first memory portion outputs (e.g.,
after a predetermined delay) MRR data 351 to the host device over a
data bus 350 of the memory device. The mode register read command
can follow shortly (e.g., immediately) after a refresh command 321
directed to the same memory portion (as is indicated by the
assertion of a low chip-select signal 331 on the first chip select
terminal 330 during the refresh command 321), as is a common
practice for polling memory devices for operating parameters that
may impact the desired refresh rate thereof. To prevent degradation
of the MRR data 351 over the shared data bus, the second memory
portion can be instructed (e.g., by asserting low chip-select
signal 341 on a second chip select terminal 340 during both clock
cycles of the mode register read command) to provide on-die
termination (ODT) 361 (e.g., via a termination resistor (RTT_2) 360
of the second memory portion) during the transmission of the MRR
data 351. As can be further seen with reference to FIG. 3, the mode
register read command consumes two cycles of the device clock 310
on the command/address bus.
[0024] In view of the frequency with which the operating parameters
of the memory device stored in a mode register may be polled by a
connected host device (e.g., in some cases as frequently as refresh
commands are sent), the consumption of command/address bus
bandwidth by mode register read commands may rise to
disadvantageous levels. Accordingly, embodiments of the present
technology may solve the foregoing problems by providing a way for
a connected host device to poll operating parameters of a memory
device without providing a dedicate mode register read command,
thereby reducing the consumption of command/address bandwidth.
[0025] Turning to FIG. 4, a simplified timing diagram 400
schematically illustrates the operation of a memory device in
accordance with an embodiment of the present technology. As can be
seen with reference to FIG. 4, in response to a host device
providing, on a command/address bus 420, a refresh command 421, in
addition to performing the commanded refresh operation (not
illustrated), the memory device outputs (e.g., after a
predetermined delay) mode register read (MRR) data 451 to the host
device over a data bus 450 thereof. By configuring the memory
device to perform, in addition to a refresh operation, a mode
register read operation in response to a refresh command, the
amount of command/address bus bandwidth consumed can be greatly
reduced (e.g., utilizing one cycle worth of clock 410 to send a
single command triggering the same operations that previously took
three cycles worth of clock 410 to trigger).
[0026] In accordance with one aspect of the disclosure, the refresh
command 421 can be a standard refresh command, without any
additional information indicating the additional mode register read
operation to be performed, as in an embodiment in which the memory
device is configured (e.g., via a mode register setting or other
configuration mechanism) to interpret all received refresh commands
as though they were refresh commands accompanied by mode register
read commands. Alternatively, the refresh command 421 can be a
modified refresh command in which one or more bit flags are
provided to indicate to the memory device that the mode register
read operation is to be performed.
[0027] Turning to FIG. 5, a simplified timing diagram 500
schematically illustrates the operation of a memory system
including multiple memory portions (e.g., dies, devices, channels,
ranks, banks, etc.) in accordance with an embodiment of the present
technology. As can be seen with reference to FIG. 5, in a memory
device or system with two or more separately-addressable portions
(e.g., two channels of a memory device, two memory devices of a
memory system), a common command/address bus 520 can be used to
indicate to the portions that a refresh operation and a mode
register read is to be performed by one of the portions (e.g., via
a refresh command 521). Unlike the approach illustrated in FIG. 3,
however, in the approach illustrated in FIG. 5, in response to an
indication to a memory portion that it is not the target of the
refresh/mode register read command, the memory portion enters an
on-die termination mode for the duration of the communication of
the mode register contents on the common data bus.
[0028] In the example of FIG. 5, a refresh command 521 is sent with
a corresponding indication 531 on the first chip select terminal
530 that the target of the refresh command corresponds to the first
portion of the memory device (e.g., by pulsing the first chip
select terminal 530 low for one cycle of a clock 510 to indicate
the targeted portion, and by leaving the second chip select
terminal 540 corresponding to the non-targeted portion high to
indicate that it is not the targeted portion). In response, the
first portion of the memory device both performs the refresh
operation (not illustrated), and also outputs (e.g., after a
predetermined delay) MRR data 551 to the host device over a data
bus 550 thereof. Moreover, in response to the same refresh command
521, the second portion of the memory device enters an on-die
termination mode 561 (e.g., via a termination resistor (RTT_2) 560
of the second memory portion) for the duration of a communication
551 of the first channel 550.
[0029] In accordance with one aspect of the disclosure, the refresh
command 521 can be a standard refresh command, without any
additional information indicating the additional mode register read
operation to be performed, as in an embodiment in which the memory
device is configured (e.g., via a mode register setting or other
configuration mechanism) to interpret all received refresh commands
as though they were refresh commands accompanied by mode register
read commands. Alternatively, the refresh command 521 can be a
modified refresh command in which one or more bit flags are
provided to indicate to the memory device that the mode register
read operation is to be performed. The refresh command 521 may
further include one or more bit flags indicating to the memory
device that on-die termination is to be performed by non-targeted
portions of the memory device during output of mode register read
data.
[0030] As the approach illustrated in FIG. 5, in which a refresh
command conveys information to memory portions that are not
targeted for a refresh operation (as indicated by corresponding
chip select signals) may involve non-targeted portions of the
memory device decoding commands, this approach can involve
additional power consumption that, for certain power-sensitive
memory environments (e.g., mobile), may not be desirable.
Accordingly, FIG. 6 illustrates with a simplified timing diagram
600 the operation of a memory system including multiple memory
portions (e.g., dies, devices, channels, ranks, banks, etc.) in
accordance with an embodiment of the present technology in which
the decoding of commands by non-targeted memory portions can be
avoided.
[0031] As can be seen with reference to FIG. 6, in a memory device
or system with two or more separately-addressable portions (e.g.,
two channels of a memory device, two memory devices of a memory
system), a common command/address bus 620 can be used to indicate
to the portions that a refresh operation and a mode register read
is to be performed by one of the portions (e.g., via a refresh
command 621). Unlike the approach illustrated in FIG. 5, however,
in the approach illustrated in FIG. 6, a refresh command 621 is
sent with not only a corresponding indication 631 on the first chip
select terminal 630 that the target of the refresh command
corresponds to the first portion of the memory device (e.g., by
pulsing the first chip select terminal 630 low for one cycle of a
clock 610 to indicate the targeted portion, and by leaving the
second chip select terminal 640 corresponding to the non-targeted
portion high to indicate that it is not the targeted portion), but
also with an indication 646 on a dedicated "mode register read
enabled" terminal 645 that the refresh command 621 should be
decoded even by non-targeted memory portions (e.g., to enable the
non-targeted portions to provide on-die termination). In response,
the first portion of the memory device both performs the refresh
operation (not illustrated), and also outputs (e.g., after a
predetermined delay) MRR data 651 to the host device over a data
bus 650 thereof. Moreover, in response to the same refresh command
621, which the second portion of the memory device is configured to
decode in response to the indication 646 on the mode register read
enabled terminal 645, the second portion of the memory device
enters an on-die termination mode 661 (e.g., via a termination
resistor (RTT_2) 660 of the second memory portion) for the duration
of a communication 651 of the first channel 650.
[0032] This arrangement, in which commands are only decoded by
non-targeted portions when an enable signal is asserted, permits
non-targeted portions of a memory device to avoid having to decode
other commands (read commands, write commands, etc.), but still
allows for the proper on-die termination during a mode register
read output, providing a desirable power savings, albeit at the
cost of dedicating a terminal to the enable signal. In some
embodiments, however, the enable signal may be provided on a shared
terminal also dedicated to other functions, such as loopback DQ
(LBDQ) and/or loopback DQS (LBDQS) terminals.
[0033] Although in the foregoing examples, memory devices have been
illustrated and described as responding to refresh commands with
both refresh operations and mode register read operations, in other
embodiments of the present technology other commands can be
configured to trigger other combinations of operations to provide
similar savings in command/address bus bandwidth. Moreover,
although the memory devices in the foregoing examples have been
described and illustrated as responding to every refresh command
with both a refresh operation and a mode register read operation,
in other embodiments of the present technology the response of a
memory device to such a command can be configured (e.g., with mode
register settings, applied enable signals, etc. indicating whether
or not the multiple operation in response to a single command mode
is enabled).
[0034] FIG. 7 is a flow chart illustrating a method of operating a
memory device in accordance with an embodiment of the present
technology. The method includes receiving a command to refresh a
memory device (box 710). According to one aspect of the present
disclosure, the receiving features of box 710 may be implemented
with command/address input circuit 105, terminals connected
thereto, and/or command decoder 115, as illustrated in FIG. 1 in
greater detail, above. The method further includes, in response to
the command, refreshing the memory device (box 720), and performing
a read of a mode register of the memory device (box 730). According
to one aspect of the present disclosure, the refreshing features
and mode register reading features of boxes 720 and 730 may be
implemented with memory array 150, read/write amplifiers 155,
input/output circuit 160, terminals connected thereto, and/or other
circuit elements of memory device 100, as illustrated in FIG. 1 in
greater detail, above.
[0035] It should be noted that the methods described above describe
possible implementations, and that the operations and the steps may
be rearranged or otherwise modified and that other implementations
are possible. Furthermore, embodiments from two or more of the
methods may be combined.
[0036] Information and signals described herein may be represented
using any of a variety of different technologies and techniques.
For example, data, instructions, commands, information, signals,
bits, symbols, and chips that may be referenced throughout the
above description may be represented by voltages, currents,
electromagnetic waves, magnetic fields or particles, optical fields
or particles, or any combination thereof. Some drawings may
illustrate signals as a single signal; however, it will be
understood by a person of ordinary skill in the art that the signal
may represent a bus of signals, where the bus may have a variety of
bit widths.
[0037] The devices discussed herein, including a memory device, may
be formed on a semiconductor substrate or die, such as silicon,
germanium, silicon-germanium alloy, gallium arsenide, gallium
nitride, etc. In some cases, the substrate is a semiconductor
wafer. In other cases, the substrate may be a silicon-on-insulator
(SOI) substrate, such as silicon-on-glass (SOG) or
silicon-on-sapphire (SOP), or epitaxial layers of semiconductor
materials on another substrate. The conductivity of the substrate,
or sub-regions of the substrate, may be controlled through doping
using various chemical species including, but not limited to,
phosphorous, boron, or arsenic. Doping may be performed during the
initial formation or growth of the substrate, by ion-implantation,
or by any other doping means.
[0038] The functions described herein may be implemented in
hardware, software executed by a processor, firmware, or any
combination thereof. Other examples and implementations are within
the scope of the disclosure and appended claims. Features
implementing functions may also be physically located at various
positions, including being distributed such that portions of
functions are implemented at different physical locations.
[0039] As used herein, including in the claims, "or" as used in a
list of items (for example, a list of items prefaced by a phrase
such as "at least one of" or "one or more of") indicates an
inclusive list such that, for example, a list of at least one of A,
B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B
and C). Also, as used herein, the phrase "based on" shall not be
construed as a reference to a closed set of conditions. For
example, an exemplary step that is described as "based on condition
A" may be based on both a condition A and a condition B without
departing from the scope of the present disclosure. In other words,
as used herein, the phrase "based on" shall be construed in the
same manner as the phrase "based at least in part on."
[0040] From the foregoing, it will be appreciated that specific
embodiments of the invention have been described herein for
purposes of illustration, but that various modifications may be
made without deviating from the scope of the invention. Rather, in
the foregoing description, numerous specific details are discussed
to provide a thorough and enabling description for embodiments of
the present technology. One skilled in the relevant art, however,
will recognize that the disclosure can be practiced without one or
more of the specific details. In other instances, well-known
structures or operations often associated with memory systems and
devices are not shown, or are not described in detail, to avoid
obscuring other aspects of the technology. In general, it should be
understood that various other devices, systems, and methods in
addition to those specific embodiments disclosed herein may be
within the scope of the present technology.
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