U.S. patent application number 15/987867 was filed with the patent office on 2019-11-28 for phase transition based resistive random-access memory.
This patent application is currently assigned to Purdue Research Foundation. The applicant listed for this patent is Purdue Research Foundation. Invention is credited to Joerg Appenzeller, Feng Zhang, Yuqi Zhu.
Application Number | 20190363252 15/987867 |
Document ID | / |
Family ID | 68614090 |
Filed Date | 2019-11-28 |
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United States Patent
Application |
20190363252 |
Kind Code |
A1 |
Appenzeller; Joerg ; et
al. |
November 28, 2019 |
PHASE TRANSITION BASED RESISTIVE RANDOM-ACCESS MEMORY
Abstract
A resistive random access memory (Device) is disclosed. The
Device includes a substrate, a first electrode formed atop the
substrate, a tunneling barrier layer formed atop the first
electrode, an active material formed atop the tunneling barrier
layer, an isolation layer formed atop the active material, and a
second electrode formed atop the isolation layer, the first
electrode and the second electrode provide electrical connectivity
to external components, where the active material is a phase change
material which undergoes phase transition in the presence of an
electric field, Joule heating, or a combination thereof.
Inventors: |
Appenzeller; Joerg; (West
Lafayette, IN) ; Zhang; Feng; (West Lafayette,
IN) ; Zhu; Yuqi; (West Lafayette, IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Purdue Research Foundation |
West Lafayette |
IN |
US |
|
|
Assignee: |
Purdue Research Foundation
West Lafayette
IN
|
Family ID: |
68614090 |
Appl. No.: |
15/987867 |
Filed: |
May 23, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 2213/15 20130101;
H01L 45/146 20130101; G11C 2013/0083 20130101; H01L 45/1246
20130101; H01L 45/143 20130101; H01L 45/144 20130101; G11C 2013/009
20130101; G11C 13/0069 20130101; H01L 45/142 20130101; G11C 13/0016
20130101; H01L 45/1253 20130101; G11C 2013/0073 20130101; G11C
2213/54 20130101; H01L 45/065 20130101; H01L 45/1233 20130101; H01L
45/1616 20130101; G11C 13/0007 20130101 |
International
Class: |
H01L 45/00 20060101
H01L045/00; G11C 13/00 20060101 G11C013/00 |
Goverment Interests
STATEMENT REGARDING GOVERNMENT FUNDING
[0001] This invention was made with government support under
HR0011-13-3-0002 awarded by the Department of Defense/Defense
Advanced Research Projects Agency (DARPA). The government has
certain rights in the invention.
Claims
1. A resistive random access memory, comprising: a substrate; a
first electrode formed atop the substrate; an active material
formed atop the first electrode, an isolation layer formed atop the
active material; and a second electrode formed atop the isolation
layer, the first electrode and the second electrode provide
electrical connectivity to external components, wherein the active
material is a phase change material which undergoes phase
transition in the presence of an electric field, Joule heating, or
a combination thereof, the isolation layer includes a current path
arrangement between the second electrode and the active material,
wherein the current path arrangement includes a window about 20 nm
to about 2 .mu.m in width and about 20 nm to about 2 .mu.m in
length, and the isolation layer is made of a material selected from
the group consisting essentially of silicon dioxide (SiO.sub.2),
boron nitride (BN), aluminum oxide (Al.sub.2O.sub.3), hafnium
dioxide (HfO.sub.2), polymers and combinations thereof.
2. The resistive random access memory of claim 1, wherein once a
forming voltage is applied to the first and second electrode causes
the active material to transition from an unformed state
representing a pristine atomic disposition of the active material
to a formed state representing a realignment of atoms in the active
material.
3. The resistive random access memory of claim 1, wherein the
active material is an electric filed induced phase transition
material selected from the group consisting essentially of
MoTe.sub.2, GaTe, ReSe.sub.2, and ReS.sub.2.
4. The resistive random access memory of claim 1, wherein when the
active material is MoTe.sub.2 the set voltage is between about 0.4
V and about 2.3 V for a thickness of between about 3 nm to about 40
nm.
5. The resistive random access memory of claim 3, wherein the set
voltage is determined based on the thickness of the active material
based on:
V.sub.Forming=E.sub.CRT.sub.MoTe.sub.2-qn.sub.1/2k.sub.s.epsilon..sub.0T.-
sub.MoTe.sub.2.sup.2,
V.sub.Set=E.sub.CRT.sub.MoTe.sub.2-qn.sub.2/2k.sub.s.epsilon..sub.0(T.sub-
.MoTe.sub.2-d.sub.gap).sup.2, wherein where V.sub.Forming is the
forming voltage and V.sub.set is the set voltage, E.sub.CR is
electric field and is about 0.16V/nm, d.sub.Gap represents the
distance of ruptured filament during the reset and is about 2.1 nm,
K.sub.s is relative permittivity and is about 8 for MoTe.sub.2, q
is electric charge and is about 1.610.sup.-19 C, n.sub.1 is charge
concentration in the MoTe.sub.2 material is about 1.810.sup.24
m.sup.-3, n.sub.2 is charge concentration in the formed filament
and is about 2.510.sup.24 m.sup.-3, .epsilon..sub.0 is permittivity
in vacuum which is about 8.8510.sup.-14 F/cm, and T.sub.MoTe2 is
the flake thickness which is between about 0.6 nm and 40 nm.
6. The resistive random access memory of claim 5, the substrate is
made from material selected form the group consisting of silicon,
silicon dioxide, glass, sapphire, germanium, gallium arsenide,
indium phosphate, alloys of silicon and germanium, titanium oxide,
polyethylene (PE), biaxially oriented polypropylene (BOPP),
polyethylene terephthalate (PET), polyvinyl chloride (PVC) and
combinations thereof.
7. The resistive random access memory of claim 6, the first and
second electrodes are made from material selected from the group
consisting essentially of aluminum, copper, gold, silver,
polysilicon, molybdenum, nickel, indium tin oxide (ITO), graphene,
carbon nanotubes (CNT), silver nanowires (AgNWs), conductive
polymer, and combinations thereof.
8. (canceled)
9. (canceled)
10. (canceled)
11. The resistive random access memory of claim 1, wherein the
window of the current path arrangement is replaced with a plurality
of vias providing substantially same amount of surface area.
12. A resistive random access memory, comprising: a substrate; a
first electrode formed atop the substrate; a tunneling barrier
layer formed atop the first electrode; an active material formed
atop the tunneling barrier layer; an isolation layer formed atop
the active material; and a second electrode formed atop the
isolation layer, the first electrode and the second electrode
provide electrical connectivity to external components, the
isolation layer is made of a material selected from the group
consisting essentially of silicon dioxide (SiO.sub.2), boron
nitride (BN), aluminum oxide (Al.sub.2O.sub.3), hafnium dioxide
(HfO.sub.2), polymers, and combinations thereof, the isolation
layer includes a current path arrangement between the second
electrode and the active material, wherein the current path
arrangement includes a window about 20 nm to about 2 .mu.m in width
and about 20 nm to about 2 .mu.m in length, wherein the active
material is a phase change material which undergoes phase
transition in the presence of an electric field, Joule heating, or
a combination thereof.
13. The resistive random access memory of claim 12, wherein once a
forming voltage is applied to the first and second electrode causes
the active material to transition from an unformed state
representing a pristine atomic disposition of the active material
to a formed state representing a realignment of atoms in the active
material.
14. The resistive random access memory of claim 12, wherein the
substrate is made from material selected form the group consisting
of silicon, silicon dioxide, glass, sapphire, germanium, gallium
arsenide, indium phosphate, alloys of silicon and germanium,
titanium oxide, polyethylene (PE), biaxially oriented polypropylene
(BOPP), polyethylene terephthalate (PET), polyvinyl chloride (PVC),
and combinations thereof.
15. The resistive random access memory of claim 14, wherein the
tunneling barrier layer is made of material selected from the group
consisting essentially of silicon dioxide (SiO.sub.2), aluminum
oxide (Al.sub.2O.sub.3), hafnium dioxide (HfO.sub.2), boron nitride
(BN), MoS.sub.2, WSe.sub.2, MoSe.sub.2, and a combination
thereof.
16. The resistive random access memory of claim 15, wherein the
active material is MoTe.sub.2.
17. The resistive random access memory of claim 16, the first and
second electrodes are made from material selected from the group
consisting essentially of aluminum, copper, gold, silver,
polysilicon, molybdenum, nickel, indium tin oxide (ITO), graphene,
carbon nanotubes (CNT), silver nanowires (AgNWs), conductive
polymer, and combinations thereof.
18. (canceled)
19. The resistive random access memory of claim 12, wherein the
window of the current path arrangement is replaced with a plurality
of vias providing substantially same amount of surface area.
Description
TECHNICAL FIELD
[0002] The present disclosure generally relates to memory devices,
and in particular, to resistive random-access memory (RRAM)
cells.
BACKGROUND
[0003] This section introduces aspects that may help facilitate a
better understanding of the disclosure. Accordingly, these
statements are to be read in this light and are not to be
understood as admissions about what is or is not prior art.
[0004] Resistive random-access memory (RRAM)-based technology has
gained attention of the semiconductor industry and researchers
working at the forefront of emerging technologies due to its
potential scalability, high operation speed, high endurance and
ease of process flow. RRAM devices are typically two-terminal cells
whose operation are based on changing the resistive state of an
internal element to thereby store information in a nonvolatile
fashion by applying a sufficiently high voltage or by driving a
large enough current through the cell.
[0005] Typically, two types of switching mechanisms are
distinguished in RRAM devices. According to one type, valence
change memory (VCM), oxide-based resistive random-access memory
cells follow a resistive switching mechanism in which a cluster of
localized valence changes lead to formation of a filament from a
high resistive state to a low resistive state resulting in the
electromigration of induced anions which modifies the valence
states of the cations. According to another type, RRAM devices
operating based on the electrochemical metallization rely on the
anodic dissolution (oxidation) of an active metal electrode and
electrodeposition (reduction) of the metal ions inside the active
switching material.
[0006] However, the observed RRAM behavior in both of the above
described instances involves an uncontrollable movement of
individual atoms. Accordingly, reliability aspects represent a
substantial challenge.
[0007] Therefore, there is an unmet need in the art for a new
switching mechanism that can be used in RRAM cells and systems.
SUMMARY
[0008] A resistive random access memory is disclosed. The resistive
random access memory includes a substrate, a first electrode formed
atop the substrate, a tunneling barrier layer formed atop the first
electrode, an active material formed atop the tunneling barrier
layer, an isolation layer formed atop the active material, and a
second electrode formed atop the isolation layer, the first
electrode and the second electrode provide electrical connectivity
to external components. The active material is a phase change
material which undergoes phase transition in the presence of an
electric field, Joule heating, or a combination thereof.
[0009] A resistive random access memory is disclosed. The resistive
random access memory includes a substrate, a first electrode formed
atop the substrate, an active material formed atop the first
electrode, an isolation layer formed atop the active material, and
a second electrode formed atop the isolation layer, the first
electrode and the second electrode provide electrical connectivity
to external components. The active material is a phase change
material which undergoes phase transition in the presence of an
electric field, Joule heating, or a combination thereof.
BRIEF DESCRIPTION OF DRAWINGS
[0010] FIG. 1 is a schematic view of a cross section of a resistive
random-access memory (RRAM) cell according to the present
disclosure.
[0011] FIG. 2 is a schematic view of a cross section of another
RRAM cell according to the present disclosure.
[0012] FIG. 3 is a schematic of a system, according to the present
disclosure, where a cell according to the present disclosure is
coupled to a selectable source via a switch.
[0013] FIG. 4 is a flowchart depicting a method that represents an
exemplary process for making the cells, according to the present
disclosure.
[0014] FIG. 5 is an exemplary IV graph illustrating characteristics
of the RRAM device of FIG. 1 for a vertical MoTe.sub.2 device.
[0015] FIG. 6 is an exemplary IV graph illustrating characteristics
of the RRAM device of FIG. 2.
[0016] FIG. 7A is a perspective schematic of a vertical transition
metal dichalcogenide (TMD) RRAM device of FIG. 1.
[0017] FIG. 7B is an optical image of the cell shown in FIG.
7A.
[0018] FIG. 7C is a scanning electron microscopy (SEM) image of the
cell shown in FIG. 7A.
[0019] FIG. 8 is a graph of forming/set voltage in volts vs. flake
thickness in nm for MoTe.sub.2.
[0020] FIG. 9 is a graph of current (I) in A/cm.sup.2 vs. voltage
(V) in volts representing normalized IV curves of an exemplary
vertical MoTe.sub.2 device lacking tunneling barriers.
[0021] FIG. 10A is a graph of an exemplary IV graph illustrating
current compliance characteristics of a MoTe.sub.2-based RRAM
device.
[0022] FIG. 10B is a graph of an exemplary current vs. time graph
showing read disturb measurements on a representative MoTe.sub.2
device.
[0023] FIG. 11 shows representative IV curves for various
MoTe.sub.2 thicknesses corresponding to moderate fields.
DETAILED DESCRIPTION
[0024] For the purposes of promoting an understanding of the
principles of the present disclosure, reference will now be made to
the embodiments illustrated in the drawings, and specific language
will be used to describe the same. It will nevertheless be
understood that no limitation of the scope of this disclosure is
thereby intended.
[0025] In the present disclosure, the term "about" can allow for a
degree of variability in a value or range, for example, within 10%,
within 5%, or within 1% of a stated value or of a stated limit of a
range.
[0026] In the present disclosure, the term "substantially" can
allow for a degree of variability in a value or range, for example,
within 90%, within 95%, or within 99% of a stated value or of a
stated limit of a range.
[0027] The present disclosure relates to a new resistive
random-access memory (RRAM) device arrangement. The active material
is made from phase transition materials, e.g. MoTe.sub.2, GaTe,
ReSe.sub.2, ReS.sub.2, or other such materials known to a person
having ordinary skill in the art. These classes of materials may be
used in fabrication of neuromorphic computing, in-memory computing
or memristor-based nonvolatile logic circuits and devices.
[0028] A novel switching mechanism that can be used in RRAM cells
and systems. A method for fabricating this novel switching
mechanism is also provided.
[0029] The RRAM topology described in the present disclosure is
based on a class of electric field induced phase transition
materials (also referred to as the active material, herein). By
applying an electrical field to this active material, the cell is
transformed from a high resistive state (HRS) to a low resistive
state (LRS). This transformation can be viewed as setting the cell
to a value of "1". By reversing the electrical field, the cell can
be transformed from the LRS back to the HRS, i.e., resetting the
cell back to "0".
[0030] Now referring to FIG. 1, an exemplary embodiment of a cell
100 according to the present disclosure is provided. The cell 100
includes a substrate 102, a first electrode 104 formed atop the
substrate 102 and an active material 108 formed atop the first
electrode 104. On the active material (also referred to as the
active material layer) 108 is an isolation layer 110 atop and
within which is a second electrode 112 formed. The first electrode
104 and the second electrode 112 provide electrical connectivity to
the cell 100. A perspective view of the cell 100 is shown in FIG.
7A representing one exemplary embodiment of the second 112
electrode and its disposition with respect to the active material
layer 108 and the isolation layer 110.
[0031] The substrate 102 in FIG. 1 can be made from a variety of
suitable materials known to a person having ordinary skill in the
semiconductor art. For example, the substrate 102 can be made from
silicon, silicon dioxide, glass, sapphire, germanium, gallium
arsenide, indium phosphate, alloys of silicon and germanium,
titanium oxide, single polymer, such as polyethylene (PE),
biaxially oriented polypropylene (BOPP), polyethylene terephthalate
(PET), polyvinyl chloride (PVC) and the like including flexible
substrates. The electrodes 104 and 112 are made from typical
material suitable for electrodes known to a person having ordinary
skill in the semiconductor art. For example, the electrodes 104 and
112 can be made from aluminum, copper, gold, silver, polysilicon,
molybdenum, nickel, indium tin oxide (ITO), graphene, carbon
nanotubes (CNT), silver nanowires (AgNWs), conductive polymer and
the like including flexible conductors. The electrodes 104 and 112
are formed by, e.g., deposition, e.g., by chemical vapor deposition
(CVD), e.g., thermal CVD or plasma-enhanced CVD; or physical vapor
deposition (PVD), e.g., sputtering or evaporation. The electrodes
104 and 112 make Schottky contacts between the electrode material
and the neighboring semiconductor material.
[0032] The active material 108 is formed on the first electrode
104. The active material 108 is made from electric field induced
phase transition materials, e.g. MoTe.sub.2, GaTe, ReSe.sub.2,
ReS.sub.2, or other such materials known to a person having
ordinary skill in the art. The phase transition materials discussed
herein can change phase based on inducement of electric field, by
joules heating, or a combination thereof. Suitable methods for
forming the active material 108 include CVD growth or exfoliated
from bulk materials. The thickness of the active material layer 108
depends on what set/reset voltage RRAM devices require as will be
discussed below. However, suffice it to say that according to one
embodiment of the present disclosure the thickness is between about
0.6 nm and 40 nm.
[0033] The isolation layer 110 is used to ensure that only vertical
transport occurs from the first electrode 104 to the second
electrode 112 without any lateral transport contributions. The
thickness of the isolation layer 110 depends on the applied voltage
(described in FIG. 3) to ensure that no leakage current exists in
the chosen layout. An open window 114 can be formed in the
isolation layer 110 which size depends on the need of device area.
The isolation layer 110 may be formed from silicon dioxide
(SiO.sub.2), boron nitride (BN) or metal oxide materials, such as
aluminum oxide (Al.sub.2O.sub.3), hafnium dioxide (HfO.sub.2), or
polymers and other isolation material used in the semiconductor
industry known to a person having ordinary skill in the art. The
open window 114 can be formed by first applying a selective
protective (resist) layer and then applying a buffered hydrofluoric
acid (HF) to dissolve unprotected regions of the isolation material
in case of SiO.sub.2. The photoresist is removed by a chemical
solution or by oxidizing in an oxygen plasma or a UV ozone system,
as known to a person having ordinary skill in the art. An
alternative way is reactive-ion etching (RIE), known to a person
having ordinary skill in the art.
[0034] The window 114 allows electrical contact between the second
electrode 112 and the active material layer 108. While a window is
shown, it should be appreciated that a network of vias can also be
used, as known to a person having ordinary skill in the art. In one
embodiment, the window 114 can be sized as small as the minimum
feature size of the technology utilized, however, according to one
embodiment between about 20 nm to about 2 .mu.m in width and about
20 nm to about 2 .mu.m in length. Alternatively, a network of vias
providing substantially the same amount of surface area can also be
used.
[0035] Referring to FIG. 2, another exemplary embodiment of a cell
200 according to the present disclosure is provided. The cell 200
includes a substrate 202, a first electrode 204 formed atop the
substrate 202 and a tunneling barrier layer 206 formed atop the
first electrode 204. The tunneling barrier 206 works to reduce the
set/reset current level in the device 200, as will be discussed in
greater detail below. The tunneling barrier 206 may be formed from
silicon dioxide (SiO.sub.2) or metal oxide materials, such as
aluminum oxide (Al.sub.2O.sub.3), hafnium dioxide (HfO.sub.2),
boron nitride (BN), other two-dimensional (2D) materials such as
MoS.sub.2, WSe.sub.2, MoSe.sub.2 and the like including 2D
insulators that do not undergo a phase transition. The thickness of
the tunneling barrier 206 depends on the requirement of set/reset
current levels. Atop the tunneling barrier layer 206 is a layer of
active material 208. Atop the active material (also referred to as
the active material layer) 208 is an isolation layer 210 atop which
is a second electrode 212 formed. The first electrode 204 and the
second electrode 212 provide electrical connectivity to the cell
200. The tunneling barrier layer 206 and the active material layer
208 can swap positions. Additionally, the tunneling barrier layer
206 can be provided on both sides of the active material layer 208
referring to a construction including the first electrode 204-the
tunneling layer 206-the active material layer 208-the tunneling
layer 206.
[0036] The substrate 202 can be made from a variety of suitable
materials known to a person having ordinary skill in the
semiconductor art. For example, the substrate 202 can be made from
silicon, silicon dioxide, glass, sapphire, germanium, gallium
arsenide, indium phosphate, alloys of silicon and germanium,
titanium oxide, single polymer, such as polyethylene (PE),
biaxially oriented polypropylene (BOPP), polyethylene terephthalate
(PET), polyvinyl chloride (PVC) and the like including flexible
substrates. The electrodes 204 and 212 are made from typical
materials suitable for electrodes known to a person having ordinary
skill in the semiconductor art. For example, the electrodes 204 and
212 can be made from aluminum, copper, gold, silver, polysilicon,
molybdenum, nickel, indium tin oxide (ITO), graphene, carbon
nanotubes (CNT), silver nanowires (AgNWs), conductive polymer and
the like including flexible conductors. The electrodes 204 and 212
are formed by, e.g., deposition, e.g., by chemical vapor deposition
(CVD), e.g., thermal CVD or plasma-enhanced CVD; or physical vapor
deposition (PVD), e.g., sputtering or evaporation. The electrodes
204 and 212 make Schottky contacts between the electrode material
and the neighboring semiconductor material.
[0037] The active material 208 is formed on the first electrode
204. The active material 208 is made from electric field induced
phase transition materials, e.g. MoTe.sub.2, GaTe, ReSe.sub.2,
ReS.sub.2, or other such materials known to a person having
ordinary skill in the art. Suitable methods for forming the active
material 208 include CVD growth or exfoliated from bulk materials.
The thickness of the active material layer 208 depends on what
set/reset voltage RRAM devices require as will be discussed below.
However, suffice it to say that according to one embodiment of the
present disclosure the thickness is between about 0.6 nm and 40
nm.
[0038] The isolation layer 210 is used to ensure that only vertical
transport occurs from the first electrode 204 to the second
electrode 212 without any lateral transport contributions. The
thickness of the isolation layer 210 depends on the applied voltage
(described in FIG. 3) to ensure that no leakage current exists in
the chosen layout. An open window 214 can be formed in the
isolation layer 210 which size depends on the need of device area.
The isolation layer 210 may be formed from silicon dioxide
(SiO.sub.2), boron nitride (BN) or metal oxide material, such as
aluminum oxide (Al.sub.2O.sub.3), hafnium dioxide (HfO.sub.2),
other two-dimensional (2D) materials such as MoS.sub.2, WSe.sub.2,
MoSe.sub.2 and the like including 2D insulators that do not undergo
a phase transition or polymers and other isolation material used in
the semiconductor industry known to a person having ordinary skill
in the art. The open window 214 can be formed by first applying a
selective protective (resist) layer and then applying a buffered
hydrofluoric acid (HF) in case of SiO.sub.2 to dissolve unprotected
regions of the isolation material. The photoresist is removed by a
chemical solution or by oxidizing in an oxygen plasma or a UV ozone
system, as known to a person having ordinary skill in the art.
[0039] The window 214 allows electrical contact between the second
electrode 212 and the active material layer 208. While a window is
shown, it should be appreciated that a network of vias can also be
used, as known to a person having ordinary skill in the art. In one
embodiment, the window 214 can be sized between about 20 nm to
about 2 .mu.m in width and about 20 nm to about 2 .mu.m in length
in length. Alternatively, a network of vias providing substantially
the same amount of surface area can also be used.
[0040] Referring to FIG. 3, a system 300 is shown where a cell 302
is coupled to a selectable source 304 via a switch 306. The source
304 is configured to provide a positive and a negative voltage in
order to set and reset the cell 302. The cell 302 as described
above can be any of the exemplary embodiments 100 or 200. The
switch 306 isolates the device 302 from the source 304, allowing
the device 302 to remain in its non-volatile state. In operation,
the source 304 applies controlled positive potentials (or
alternatively negative potentials) to the second electrode (112 or
212 in FIG. 1 or 2). Note that the cell 302 shown may be part of a
larger cross bar geometry or other high-density memory array.
[0041] Referring to FIG. 4, a method 400 is shown that represents
an exemplary process for making the cells 100 and 200, according to
the present disclosure. The method 400 is based on a flow diagram
for one embodiment of the present disclosure of fabricating phase
transition-based RRAMs. The method 400 includes process steps that
are performed upon a substrate (102, 202 in FIGS. 1 and 2). In one
illustrative embodiment, such processing steps are sequentially
performed in the depicted order. In alternate embodiments, at least
two processing steps may be performed contemporaneously or in a
different order. For the device without tunneling barriers (e.g.,
the device 100 of FIG. 1), the step 404 of FIG. 4 is eliminated.
Conventional sub-processes, such as application and removal of
lithographic masks or sacrificial and protective layers, cleaning
processes, and the like, are well known in the art and are not
shown in the method 400. At step 402 of FIG. 4, a first electrode
(104 or 204 in FIG. 1 or 2) is formed on the substrate (102 or 202
in FIG. 1 or 2).
[0042] At step 406 of FIG. 4, the active material layer (108 or 208
in FIG. 1 or 2) is formed on the first electrode (104 or 204 in
FIG. 1 or 2). Methods suitable for forming such active material
layer, e.g. MoTe.sub.2, GaTe, ReSe.sub.2, ReS.sub.2, are CVD growth
or exfoliated from bulk materials. The thickness of the active
layer (108 or 208 in FIG. 1 or 2) depends on set/reset voltage
which RRAM devices require, as described in fuller detail below. At
step 408 of FIG. 4, an isolation layer (110 or 210 in FIG. 1 or 2)
is formed upon the active material layer (108 or 208 in FIG. 1 or
2). The isolation layer (110 or 210 in FIG. 1 or 2) is used to
ensure that only vertical transport occurs from the first electrode
(104 or 204 in FIG. 1 or 2) to the second electrode (112 or 212 in
FIG. 1 or 2) without any lateral transport contributions. The
thickness of the isolation layer (110 or 210 in FIG. 1 or 2)
depends on the voltage of the voltage source 304 (shown in FIG. 3)
to ensure that no leakage current exists in the chosen layout. At
step 410 of FIG. 4, a contact window (114 or 214 in FIG. 1 or 2) is
formed in isolation layer (110 or 210 in FIG. 1 or 2) upon the
active material layer (108 or 208 in FIG. 1 or 2). The window
allows electrical contact between the second electrode (112 or 212
in FIG. 1 or 2) and the active material layer (108 or 208 in FIG. 1
or 2).
[0043] At step 412 of FIG. 4, the second electrode (112 or 212 in
FIG. 1 or 2) is formed upon the isolation layer (110 or 210 in FIG.
1 or 2), coupling to the active material layer (108 or 208 in FIG.
1 or 2). The first electrode (104 or 204 in FIG. 1 or 2) and the
second electrode (112 or 212 in FIG. 1 or 2) may be formed from at
least one conductive material (e.g., a metal, an alloy of the
metal, or a conductive compound) that is compatible with respective
underlying and overlying material layers, as discussed above. In
step 404 of FIG. 4, the tunneling barrier layer (206 in FIG. 2) is
formed upon the first electrode (204 in FIG. 2) to reduce the
set/reset current level in device 200. The tunneling barrier layer
(206 in FIG. 2) may be formed from silicon dioxide (SiO.sub.2) or
metal oxide materials, such as aluminum oxide (Al.sub.2O.sub.3),
hafnium dioxide (HfO.sub.2), boron nitride (BN), other
two-dimensional (2D) materials such as MoS.sub.2, WSe.sub.2,
MoSe.sub.2 and the like including 2D insulators that do not undergo
a phase transition or polymers and other isolation material used in
the semiconductor industry known to a person having ordinary skill
in the art. The thickness of the tunneling barrier (206 in FIG. 2)
depends on the requirement of set/reset current levels. In one
exemplary embodiment, the tunneling barrier (206 in FIG. 2)
comprises 4.5 nm thick aluminum oxide (Al.sub.2O.sub.3). A 3 nm
thick aluminum (Al) layer was deposited onto the first electrode
(204 in FIG. 2) prior to oxidation of the Al in an oxygen rich
environment at around 250.degree. C. for 6 h. The set/reset current
for this embodiment is 10.sup.-7 A. It should be appreciated that
the structures discussed herein are symmetrical with respect to the
first electrode (104 or 204 in FIG. 1 or 2) and the second
electrode (112 or 212 in FIG. 1 or 2). Therefore, the same
procedures and structures discussed can be repeated with the
tunneling barrier layer (206 in FIG. 2) being formed against the
second electrode (212 in FIG. 2).
[0044] Referring to FIG. 5, an exemplary IV graph illustrating
characteristics of the RRAM device of FIG. 1 is provided for a
vertical MoTe.sub.2 device from a flake with a thickness of about
24 nm. More specifically, the graphs in FIG. 5 show the dependence
of current I on the applied voltage V initially in an unformed
state 603 as shown by a curve of hollow circles and then the device
transitioning to a formed state 604 including a high resistance
state (HRS) 604-1 and a low resistive state (LRS) 604-2 as shown by
a curve of solid circles. The characteristic 603 of FIG. 1 is
reproducible and substantially does not change after multiple scans
between -1 V and 1 V as shown by hollow circles. The situation
however changes when the voltage range is extended to a forming
voltage. While not fully shown in FIG. 5, the forming voltage
V.sub.Forming is described in fuller detail below. The cell 100 of
FIG. 1 can transition into a formed state 604 and remain in that
state indefinitely as illustrated. The formed state includes a set
voltage represented by 604-3 at which point the cell 100
transitions from the HRS 604-1 to LRS 604-2 and a reset voltage
604-4 at which point the cell 100 transitions from the LRS 604-2
back to the HRS 604-1. Once the cell 100 is transitioned into the
formed state 604, it remains in that state indefinitely and by
sweeping the voltage it can be set and reset (i.e., transition from
the HRS 604-1 to LRS 604-2 and back to HRS 604-1). The set voltage
depends on the active material layer 108 thickness. In the depicted
embodiment, the cell 100 has a set voltage V.sub.SET of between
about 1 V to about 1.2 V. After the forming event, device
characteristics can be cycled to exhibit typical bipolar RRAM type
of behavior in terms of: a) remaining in their LRS 604-2 when no
voltage is applied, b) preserving the low resistive state over an
appreciable voltage range until a sufficient reset voltage (here
V.sub.RESET is between about -0.9 V and -1.1 V) of polarity
opposite to the set voltage is reached, and c) remaining in their
respective HRS 604-1 until the set voltage is reached. In this
case, the MoTe.sub.2 flake thickness is about 7 nm. Note, the
device can be formed by negative voltage, then the set voltage
polarity would be negative and reset voltage polarity would be
positive. It should be appreciated that the entirety of the cycle
described herein could have started with negative voltages instead
of positive voltages resulting in negative set and reset negative
voltages.
[0045] Referring to FIG. 6, an exemplary IV graph illustrating
characteristics of the cell 200 (shown in FIG. 2) is provided. More
specifically, the graph in FIG. 6 shows dependence of current I
from the applied voltage V. With the tunneling barrier 206 (see
FIG. 2) in place, the current I through the cell 200 is reduced to
0.1 .mu.A (shown in FIG. 6) in the depicted embodiment. The cell
200 is set into LRS without the transitioning from an unformed
state into a formed state described above with respect to FIG. 5
(called forming-free) and the LRS does not require introducing any
current compliance through an external circuitry (not shown,
however, can be accomplished by a semiconductor parameter analyzer
or even by a simple circuit including a biased transistor or a
switching field effect transistor, as known to a person having
ordinary skill in the art), another desirable feature in RRAM
cells. The set/reset voltage depends on the thicknesses of the
active layer material 208 and the tunneling barrier 206. It should
be appreciated that wherever in the present disclosure samples are
discussed with respect to the forming process, that such samples
refer to FIGS. 1 and 7A, in which no tunneling barrier layer 206
(see FIG. 2) exists. However, where samples are discussed with such
tunneling barrier 206, those portions refer to samples whereby no
forming is needed.
[0046] Referring to FIG. 7A, a perspective schematic of a vertical
transition metal dichalcogenide (TMD) RRAM device also shown in
FIG. 1 is shown, according to the present disclosure.
Correspondingly, referring to FIGS. 7B and 7C optical and scanning
electron microscopy (SEM) images of the cell shown in FIG. 7A are
shown, respectively. The second electrode 112 (FIG. 7A) contact
area is between about 0.01 .mu.m.sup.2 to about 0.5 .mu.m.sup.2
according to one exemplary embodiment. The cell shown in FIG. 7A
ensures that only vertical transport occurs from the first
electrode 104 to the second electrode 112 without any lateral
transport contributions. Because of the large aspect ratio between
the second electrode 112 area and the flake thickness of the active
material 108, spreading resistance contributions can be ignored and
the active device area is substantially identical to the top
contact area.
[0047] The relationship below provides a relationship between
forming/set voltage vs. flake thickness which is shown FIG. 8. The
curve fit is based on the following formula:
V.sub.Forming=E.sub.CRT.sub.MoTe.sub.2-qn.sub.1/2k.sub.s.epsilon..sub.0T-
.sub.MoTe.sub.2.sup.2,
V.sub.Set=E.sub.CRT.sub.MoTe.sub.2-qn.sub.2/2k.sub.s.epsilon..sub.0(T.su-
b.MoTe.sub.2-d.sub.gap).sup.2,
where V.sub.Forming is the forming voltage and V.sub.set is the set
voltage, E.sub.CR is electric field and according to one embodiment
is about 0.16 V/nm, d.sub.Gap represents the distance of ruptured
filament during the reset process and according to one embodiment
is about 2.1 nm, K.sub.s is relative permittivity and according to
one embodiment is about 8 for MoTe.sub.2, q is electric charge and
is about 1.610.sup.-19 C, n.sub.1 is charge concentration in the
MoTe.sub.2 material and according to one embodiment is about
1.810.sup.24 m.sup.-3, n.sub.2 is charge concentration in the
formed filament and according to one embodiment is about
2.510.sup.24 m.sup.-3, .epsilon..sub.0 is permittivity in vacuum
which is about 8.8510.sup.-14 F/cm, and T.sub.MoTe2 is the flake
thickness which according to one embodiment is between about 0.6 nm
and 40 nm. The relationship provided in the above equation can be
used to determine V.sub.Forming and V.sub.set voltages for
differing characteristics.
[0048] Referring to FIG. 9 area normalized IV curves of exemplary
vertical MoTe.sub.2 device before forming are shown for devices
lacking a tunneling barrier (example cell 100 in FIG. 1). The first
electrode (104 in FIG. 1) is grounded. The results shown confirm
the expected trend of current densities with thickness, i.e., the
thinner the flakes the higher current densities. The device
characteristics shown are reproducible and they remain
substantially the same after several scans between -1 V and 1 V.
However, when the voltage range is extended beyond -1 V to 1 V, the
results change. In particular, vertical MoTe.sub.2 TMD devices
transition into LRS as discussed in FIG. 5.
[0049] The details on the forming process are discussed below. As
long as a critical forming voltage which depends on TMD thickness
is not reached, the pristine metal-MoTe.sub.2-metal devices exhibit
reproducible IV curves shown as hollow circles in FIG. 5.
Progressing beyond this forming voltage results in the RRAM
behavior as described above, resulting in the resistive switching
behavior. Two factors contribute to the forming: external electric
fields and Joule heating are both factors during the formation of
conductive filaments. However, once a filament is formed, a voltage
lower than the forming voltage (i.e., a set voltage) is used to
switch between the HRS and LRS of the cell. A transition back to
the HRS occurs when a reverse polarity electric field is applied,
due to a rupture of filaments. It should be appreciated that the
set voltage discussed here depends monotonically on the flake
thickness for flakes with thicknesses below about 15 nm (see FIG.
8) necessitating in that a critical electric field is needed to
trigger the memristive behavior. Set values as shown in FIG. 8 have
been experimentally found to vary by about 0.2 V due to
device-to-device variations in these prototype structures. It
should also be appreciated that after the aforementioned forming
process has occurred, the state defined by the HRS remains more
conductive than the original state of the device (i.e., solid
circles in HRS 604-1 state are higher on the current curve than
hollow circles representing pre-formation in FIG. 5) which is
indicative that a permanent electronic change has occurred in the
device. Along the same line, with reference to FIG. 5, the current
ratio between the HRS and the LRS is about 50 but can be between
about 10 and about 100 when the compliance is set to about 400
.mu.A.
[0050] To further understand the switching mechanism in TMDs,
exfoliated MoTe.sub.2 based RRAM cells with thicknesses between
about 6 nm and about 36 nm were fabricated. All cells were
nonvolatile and stable. When considering a metal oxide-based RRAM
cell, a set current compliance can be used to control the LRS
resistance which then determines the diameter and/or the number of
conductive filaments formed in the LRS. Conversely, the reset
voltage through the modulation of the ruptured filament length can
be used to change the HRS resistance. Referring to FIG. 10A, IV
curves for different current compliance values (1 mA, 600 .mu.A,
and 400 .mu.A) are provided for MoTe.sub.2-based RRAM cells. As
discussed above, the current compliance is inversely related to the
LRS resistance, which means that a higher current compliance
results in a lower LRS resistance. In FIG. 10A the flake thickness
for the device is about 15 nm. FIG. 10B is a graph of current vs.
time (s) which shows the performance of the same device under a 0.5
V read disturb with the current compliance set to 1 mA. As shown,
both states show a stable resistance over a period of time (e.g.,
1000 s) at room temperature.
[0051] For flake thicknesses from about 6 nm to about 36 nm, the
set voltages can be tuned from 0.9 V to 2.3 V. Referring to FIG. 11
the set voltages in the representative IV curves are shown
corresponding to moderate fields in the range of about 10.sup.6
V/cm. It should be appreciated that the RRAM behavior is
independent of the choice of contact metal. As an example, using Ni
instead of Ti/Ni as top electrode resulted in the same RRAM
performance.
[0052] The inventive novel phase transition-based RRAM disclosed
herein has favorable combination of characteristic for use in the
realm of neuromorphic computing. Although embodiments have been
disclosed for a novel switching mechanism RRAM, it should be
understood that the fabrication techniques and resulting structures
and architecture are also used in in-memory computing or
memristor-based nonvolatile logics circuits and devices, such as
nonvolatile-SRAM (nvSRAM), nonvolatile flip-flops (nVFF), and
nonvolatile TCAM (nvTCAM).
[0053] Those having ordinary skill in the art will recognize that
numerous modifications can be made to the specific implementations
described above. The implementations should not be limited to the
particular limitations described. Other implementations may be
possible.
* * * * *