U.S. patent application number 15/977409 was filed with the patent office on 2019-11-14 for high performance isfet with ferroelectric material.
The applicant listed for this patent is GLOBALFOUNDRIES Singapore Pte. Ltd.. Invention is credited to Kiok Boone Elgin QUEK, Shyue Seng TAN, Eng Huat TOH, Lanxiang WANG.
Application Number | 20190346404 15/977409 |
Document ID | / |
Family ID | 68464563 |
Filed Date | 2019-11-14 |
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United States Patent
Application |
20190346404 |
Kind Code |
A1 |
TAN; Shyue Seng ; et
al. |
November 14, 2019 |
HIGH PERFORMANCE ISFET WITH FERROELECTRIC MATERIAL
Abstract
The present disclosure relates to semiconductor structures and,
more particularly, to high performance ion sensitive field effect
transistor (ISFET) with ferroelectric material and methods of
manufacture. The structure includes: a substrate comprising a doped
region; a gate dielectric material over the doped region; a
ferroelectric material over the gate dielectric material; and a
sensing membrane over the ferroelectric material.
Inventors: |
TAN; Shyue Seng; (Singapore,
SG) ; QUEK; Kiok Boone Elgin; (Singapore, SG)
; TOH; Eng Huat; (Singapore, SG) ; WANG;
Lanxiang; (Singapore, SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES Singapore Pte. Ltd. |
Singapore |
|
SG |
|
|
Family ID: |
68464563 |
Appl. No.: |
15/977409 |
Filed: |
May 11, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0669 20130101;
H01L 29/78391 20140902; G01N 27/4145 20130101; G01N 27/4146
20130101; H01L 29/40111 20190801; H01L 29/78648 20130101 |
International
Class: |
G01N 27/414 20060101
G01N027/414; H01L 29/786 20060101 H01L029/786; H01L 29/06 20060101
H01L029/06; H01L 29/78 20060101 H01L029/78; H01L 21/28 20060101
H01L021/28 |
Claims
1. A structure comprising: a substrate comprising a doped region; a
gate dielectric material directly on the doped region; a
ferroelectric material directly on the gate dielectric material; a
dielectric layer directly on the substrate and surrounding the gate
dielectric material and the ferroelectric material; a trench in the
dielectric layer; and a sensing membrane lining the trench of the
dielectric layer and directly on the ferroelectric material within
the trench.
2. The structure of claim 1, wherein the gate dielectric material,
the ferroelectric material and the sensing membrane are connected
in series.
3. The structure of claim 2, wherein the series connection of the
gate dielectric material, the ferroelectric material and the
sensing membrane form a negative capacitance ion sensitive field
effect transistor (ISFET).
4. The structure of claim 1, wherein the gate dielectric material
is SiO.sub.2.
5. The structure of claim 1, wherein the ferroelectric material is
one of lead zirconate titanate (PZT), PbZr/TiO.sub.3, BaTiO.sub.3,
PbTiO.sub.3, lead lanthanum zirconate titanate (PLZT), and
SrBi.sub.2Ta.sub.2O.sub.9.
6. The structure of claim 1, wherein the sensing membrane is one of
Al.sub.2O.sub.3, HfO.sub.3 and TiO.sub.2.
7. The structure of claim 1, wherein the structure achieves an
amplification of 2.1.
8. The structure of claim 1, wherein C.sub.sense is representative
of a capacitance of the sensing membrane, |C.sub.fe| is
representative of a capacitance of the ferroelectric material and
C.sub.cmos is representative of the capacitance of the gate
dielectric material and/or substrate, and
0<C.sub.cmos/|C.sub.fe|<1 and
C.sub.sense/C.sub.cmos>1.
9. The structure of claim 1, wherein the doped region is a
p-well.
10. A structure comprising: a substrate comprising a doped region;
a gate dielectric material over the doped region; a ferroelectric
material over the gate dielectric material; and a sensing membrane
over the ferroelectric material, wherein the substrate, gate
dielectric material, the ferroelectric material and the sensing
membrane are a nanowire.
11. A negative capacitance ion sensitive device comprising a gate
dielectric material, a ferroelectric material and a sensing
membrane electrically connected in series wherein: the gate
dielectric material is over a doped region of a substrate; the
ferroelectric material is over the gate dielectric material; the
sensing membrane is over the ferroelectric material; and the
substrate, gate dielectric material, the ferroelectric material and
the sensing membrane are a nanowire.
12. (canceled)
13. (canceled)
14. The negative capacitance ion sensitive device of claim 11,
wherein the gate dielectric material is SiO.sub.2.
15. The negative capacitance ion sensitive device of claim 11,
wherein the ferroelectric material is one of lead zirconate
titanate (PZT), PbZr/TiO.sub.3, BaTiO.sub.3, PbTiO.sub.3, lead
lanthanum zirconate titanate (PLZT), and
SrBi.sub.2Ta.sub.2O.sub.9.
16. The negative capacitance ion sensitive device of claim 11,
wherein the sensing membrane is one of Al.sub.2O.sub.3, HfO.sub.3
and TiO.sub.2.
17. The negative capacitance ion sensitive device of claim 11,
wherein C.sub.sense is representative of a capacitance of the
sensing membrane, |C.sub.fe| is representative of a capacitance of
the ferroelectric material and C.sub.cmos is representative of the
capacitance of the gate dielectric material and/or substrate, and
0<C.sub.cmos/|C.sub.fe|<1 and
C.sub.sense/C.sub.cmos>1.
18.-20. (canceled)
21. The structure of claim 1, further comprising a passivation
layer on the dielectric layer.
22. The structure of claim 21, wherein the trench is in the
passivation layer.
23. The structure of claim 22, wherein the sensing membrane lines
the passivation layer within the trench.
Description
FIELD OF THE INVENTION
[0001] The present disclosure relates to semiconductor structures
and, more particularly, to a high performance ion sensitive field
effect transistor (ISFET) with ferroelectric material and methods
of manufacture.
BACKGROUND
[0002] An ion-sensitive field-effect transistor (ISFET) is a
field-effect transistor used for measuring ion concentrations in
solution. ISFET is a key device used in DNA sequencing. The ISFET
device can detect pH changes in the solution through DNA polymerase
synthesis. For example, the changes monitored by a sensing membrane
(e.g., SiO.sub.2, Si.sub.3N.sub.4, Al.sub.2O.sub.3,
Ta.sub.2O.sub.5, etc.) of the ISFET can be converted to electrical
signals for measurements. More specifically, when the ion
concentration (such as H.sup.+) changes, the current through the
transistor will change accordingly. A voltage between substrate and
oxide surfaces arises due to an ion sheath.
SUMMARY
[0003] In an aspect of the disclosure, a structure comprises: a
substrate comprising a doped region; a gate dielectric material
over the doped region; a ferroelectric material over the gate
dielectric material; and a sensing membrane over the ferroelectric
material.
[0004] In an aspect of the disclosure, a negative capacitance ion
sensitive device comprising a gate dielectric material, a
ferroelectric material and a sensing membrane electrically
connected in series.
[0005] In an aspect of the disclosure, a method comprises:
depositing a gate dielectric material on a doped portion of a
substrate; depositing a ferroelectric material on the gate
dielectric material; depositing a dummy gate material on the
ferroelectric material; depositing an interlevel dielectric
material over the dummy gate material; forming contacts to source
and drain regions of the substrate; opening the interlevel
dielectric material to expose the dummy gate material; removing the
dummy gate material to expose the ferroelectric material; and
depositing a sensing membrane over the ferroelectric material and
sidewalls of the opening.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The present disclosure is described in the detailed
description which follows, in reference to the noted plurality of
drawings by way of non-limiting examples of exemplary embodiments
of the present disclosure.
[0007] FIG. 1 shows a structure with ferroelectric material,
amongst other features, and respective fabrication processes in
accordance with aspects of the present disclosure.
[0008] FIG. 2 shows a patterned ferroelectric material, amongst
other features, and respective fabrication processes in accordance
with aspects of the present disclosure.
[0009] FIG. 3 shows contacts to source and drain regions, amongst
other features, and respective fabrication processes in accordance
with aspects of the present disclosure.
[0010] FIG. 4 shows removal of a dummy gate material to expose the
patterned ferroelectric material, amongst other features, and
respective fabrication processes in accordance with aspects of the
present disclosure.
[0011] FIG. 5 shows a sensing membrane on the patterned
ferroelectric material, amongst other features, and respective
fabrication processes in accordance with aspects of the present
disclosure.
[0012] FIG. 6 shows a nanowire structure with ferroelectric
material, amongst other features, and respective fabrication
processes in accordance with aspects of the present disclosure.
[0013] FIG. 7 shows a representative circuit of the structures
shown in FIGS. 5 and 6.
[0014] FIG. 8 shows a graph of V.sub.2 vs. Vg with a varying layer
of ferroelectric material.
[0015] FIG. 9 shows a graph of V.sub.2 vs. Vg with a varying
sensing membrane.
DETAILED DESCRIPTION
[0016] The present disclosure relates to semiconductor structures
and, more particularly, to a high performance ion sensitive field
effect transistor (ISFET) with ferroelectric material and methods
of manufacture. More specifically, the present disclosure describes
a negative-capacitance ion-sensitive FET (NC-ISFET) with high
sensitive to pH change by utilizing a stack of sensing
layer/ferroelectric material/dielectric configuration to achieve
voltage amplification and flexibility without hysteresis, and
voltage division capability. Advantageously, the present disclosure
provides a high sensitivity ISFET device with fast and accurate
response.
[0017] In embodiments, the ISFET device includes a stack of sensing
membrane, a ferroelectric layer and gate dielectric layer connected
in series to form a negative capacitance ISFET device. In
embodiments, the ferroelectric layer achieves a high pH
sensitivity, compared to a conventional ISFET device. In further
embodiments, the ISFET scheme can include a floating-gate type
ISFET or other ISFET structures. The transistor channel material
can include two-dimensional semiconductor (2D semiconductor),
particularly transition metal dichalcogenides (TMDCs) and black
phosphorus. For example, MoS.sub.2, MoSe.sub.2, MoTe.sub.2,
WS.sub.2 and WSe.sub.2 can be 2D semiconductor material implemented
with the ISFET device.
[0018] The method of fabricating the ISFET device, as described in
greater detail below, includes, e.g., forming a gate dielectric
layer, followed by deposition of a ferroelectric layer and a dummy
gate material on an active area. After patterning of the material,
source and drain regions are formed in the underlying substrate,
followed by contact formation, e.g., deposition of an interlevel
dielectric material, contact etch and metal deposition in the
interlevel dielectric material. A deposition of a passivation layer
is provided over the interlevel dielectric material. A cavity
(trench) is then opened in the interlevel dielectric material to
expose and remove the dummy gate material, which then exposes the
ferroelectric material. A sensing membrane is formed on the
ferroelectric material. In this way, it is possible to form a
high-sensitive NC-ISFET by 0<C.sub.cmos/|C.sub.fe| and
C.sub.sense/C.sub.cmos>1, respectively.
[0019] The ISFET device of the present disclosure can be
manufactured in a number of ways using a number of different tools.
In general, though, the methodologies and tools are used to form
structures with dimensions in the micrometer and nanometer scale.
The methodologies, i.e., technologies, employed to manufacture the
ISFET device of the present disclosure have been adopted from
integrated circuit (IC) technology. For example, the structures are
built on wafers and are realized in films of material patterned by
photolithographic processes on the top of a wafer. In particular,
the fabrication of the ISFET device uses three basic building
blocks: (i) deposition of thin films of material on a substrate,
(ii) applying a patterned mask on top of the films by
photolithographic imaging, and (iii) etching the films selectively
to the mask.
[0020] FIG. 1 shows a structure with ferroelectric material,
amongst other features, and respective fabrication processes in
accordance with aspects of the present disclosure. In particular,
the structure 10 includes a substrate 12 with shallow trench
isolation regions 14. In embodiments, the substrate 12 is any
suitable semiconductor material. For example, the substrate 12 can
be composed of any suitable material including, but not limited to,
Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI
compound semiconductors. In embodiments, the substrate 12 includes
a P-well 12a formed using conventional implantation methods such
that no further explanation is required for an understanding of the
present disclosure. In alternate embodiments, the well can also be
an N-well.
[0021] In embodiments, the shallow trench isolation regions 14 can
be formed by conventional lithography, etching and deposition
methods. For example, a resist formed over the substrate 12 is
exposed to energy (light) to form a pattern (opening). An etching
process with a selective chemistry, e.g., reactive ion etching
(RIE), will be used to form one or more trenches in the substrate
12 through the openings of the resist. The resist can then be
removed by a conventional oxygen ashing process or other known
stripants. Following the resist removal, insulator material (e.g.,
oxide) can be deposited by any conventional deposition processes,
e.g., chemical vapor deposition (CVD) processes. Any residual
insulator material on the surface of the substrate 12 can be
removed by conventional chemical mechanical polishing (CMP)
processes.
[0022] Still referring to FIG. 1, a gate dielectric material 16 is
deposited on the substrate 12. In embodiments, the gate dielectric
material 16 can be deposited by conventional deposition processes,
e.g., atomic layer deposition (ALD) or plasma enhanced vapor
deposition (PEVD) methods. The gate dielectric material 16 can be
an oxide material (SiO.sub.2) or a high-k dielectric material. For
example, the gate dielectric material 16 can be e.g., HfO.sub.2
Al.sub.2O.sub.3, Ta.sub.2O.sub.3, TiO.sub.2, La.sub.2O.sub.3,
SrTiO.sub.3, LaAlO.sub.3, ZrO.sub.2, Y.sub.2O.sub.3,
Gd.sub.2O.sub.3, and combinations including multilayers thereof.
The gate dielectric material 16 can be deposited to a thickness of
about 10 nm or less, as one example, depending on the technology
node.
[0023] A ferroelectric material 18 is deposited on the gate
dielectric material 16. In embodiments, the ferroelectric material
18 can be any ferroelectric material. For example, the
ferroelectric material 18 can be lead zirconate titanate (PZT),
PbZr/TiO.sub.3, BaTiO.sub.3, PbTiO.sub.3, lead lanthanum zirconate
titanate (PLZT), SrBi.sub.2Ta.sub.2O.sub.9, etc. In embodiments,
high-k materials also can be ferroelectric including, e.g.,
HfO.sub.2, HfAlOx, and HfZrOx. The ferroelectric material 18 can be
deposited to a thickness of about 10 nm or less, as one example,
depending on the technology node. In embodiments, the ferroelectric
material 18 is deposited by ALD or PEVD, as examples. A dummy gate
material 20 is deposited on the ferroelectric material 18. The
dummy gate material can be, e.g., poly material.
[0024] Referring to FIG. 2, the gate dielectric material 16,
ferroelectric material 18 and dummy gate material 20 are patterned
by conventional lithography and etching processes. Source and drain
regions 22 are then implanted into the substrate 12 by conventional
ion implantation processes. The source and drain regions 22 are
provided between the shallow trench isolation regions 14 and the
patterned materials 16, 18, 20. The source and drain regions 22 can
then undergo a silicide process.
[0025] As should be understood by those of skill in the art, the
silicide process begins with deposition of a thin transition metal
layer, e.g., nickel, cobalt or titanium, over the doped or ion
implanted source and drain regions 22. After deposition of the
material, the structure is heated allowing the transition metal to
react with exposed silicon (or other semiconductor material as
described herein) in the active regions of the semiconductor device
(e.g., source, drain, gate contact region) forming a low-resistance
transition metal silicide. Following the reaction, any remaining
transition metal is removed by chemical etching, leaving silicide
contacts in the active regions of the device. It should be
understood by those of skill in the art that silicide contacts will
not be required on the devices, when a gate structure is composed
of a metal material.
[0026] In FIG. 3, an interlevel dielectric material 24 (e.g.,
oxide) is deposited over the patterned materials 16, 18, 20 using
conventional deposition processes, e.g., chemical vapor deposition
(CVD) process. Source and drain contacts and wiring layers 16 are
formed in the interlevel dielectric material 24. In embodiments,
the source and drain contacts and wiring layers 16 can be formed by
single or dual damascene processes using conventional lithography,
etching and deposition processes. In embodiments, the source and
drain contacts and wiring layers 16 will be in direct contact with
the source and drain regions 22 (e.g., silicide contacts), and
extend to upper wiring layers or bond pads, etc.
[0027] A passivation layer 28 is formed over the source and drain
contacts and wiring layers 16 and interlevel dielectric material
24. The passivation layer 28 can be SiN, for example, deposited by
a conventional CVD process. In alternative embodiments, the
passivation layer can be nitride, SiO.sub.2 or oxide as further
examples.
[0028] As shown in FIG. 4, a trench or cavity 30 is formed in the
passivation layer 28 and the interlevel dielectric material 24,
exposing the dummy gate material 20. The dummy gate material 20 is
then removed by a conventional etching process, e.g., RIE, with a
selective chemistry to the material of the dummy gate material 20.
The removal of the dummy gate material 20 will expose the
ferroelectric material 18.
[0029] In FIG. 5, a sensing membrane 32 is deposited in the trench
30, covering the ferroelectric material 18. In embodiments, the
sensing membrane 32 can be Al.sub.2O.sub.3 deposited by an ALD
process, as an example. The sensing membrane 32 can also be other
materials such as, e.g., SiO.sub.2, Si.sub.3N.sub.4,
Al.sub.2O.sub.3, Ta.sub.2O.sub.5, HfO.sub.3 or TiO.sub.2, etc.
Following the deposition of the sensing membrane 32, any excess
material on the passivation layer 28 will be removed by a CMP
process. In this way, the sensing membrane 32 is only in the trench
30 (e.g., over the ferroelectric material 18 and sidewalls of the
trench 30). By using the combination of the sensing membrane 32 and
the ferroelectric material 18, it is now possible to achieve
>2.times. higher sensitive of pH change compared to a
conventional structure.
[0030] FIG. 6 shows a nanowire structure with ferroelectric
material, amongst other features, and respective fabrication
processes in accordance with aspects of the present disclosure. In
particular, the nanowire 10' includes a core material 12b of doped
semiconductor material. In embodiments, the dopant can be a p-type
dopant (e.g., phosphorous or arsenic) or an n-type dopant (e.g.,
boron or other group III species). A gate dielectric material 16 is
deposited about the core material 12b. A ferroelectric material 18
is deposited about the gate dielectric material 16, with the
sensing membrane 32 deposited about the ferroelectric material 18.
The materials 12b, 16, 18 and 32 can be the same materials as
described above, deposited in conventional deposition processes to
form the nanowire 10'. In embodiments, the nanowire 10' can boost
sensitivity by a change of conductance, e.g., 85 nS/pH.
[0031] FIG. 7 shows a representative circuit of the structures
shown in FIGS. 5 and 6. In particular, the circuit includes
capacitors C.sub.sense, |Cfe| and C.sub.cmos, in series. It should
be understood by those of skill in the art that capacitor
C.sub.sense is representative of the capacitance of the sensing
membrane 32, |Cfe| is representative of the capacitance of the
ferroelectric material 18 and C.sub.cmos is representative of the
capacitance of the gate dielectric material 16 and/or substrate 12.
Vg is voltage to ground; whereas, V.sub.1 and V.sub.2 are voltages
to the source and drain regions.
[0032] The following shows proof of concept that the use of the
ferroelectric material 18 will increase sensitivity of the ISFET
and nanowire described herein.
[0033] Using a capacitor divider:
C.sub.sense(Vg-V.sub.1)=|Cfe|(V.sub.1-V.sub.2)=C.sub.cmos(V.sub.2)
(Eq. 1)
For |Cfe|(V.sub.1-V.sub.2)=C.sub.cmos(V.sub.2) (Eq. 2)
|Cfe|V.sub.1=C.sub.cmosV.sub.2+|C.sub.fe|V.sub.2
V.sub.1/V.sub.2=(|C.sub.fe|+C.sub.cmos)/|C.sub.fe|
V.sub.2/V.sub.1=|C.sub.fe|/(|C.sub.fe|+C.sub.cmos) (Eq. 2)
[0034] With |C.sub.fe| negative and close and larger than
C.sub.cmos, the denominator of Eq. 3 becomes smaller and makes
V.sub.2/V.sub.1>>1.
[0035] To demonstrate voltage amplification is achieved in the
ISFET with the negative charge layer:
C.sub.sense(Vg-V.sub.1)=C.sub.cmos(V.sub.2)
Vg-V.sub.1=(C.sub.cmosV.sub.2)/C.sub.sense
Vg/V.sub.2-V.sub.1/V.sub.2=C.sub.cmos/C.sub.sense
Vg/V.sub.2=C.sub.cmos/C.sub.sense+V.sub.1/V.sub.2 (Eq. 4).
[0036] To ensure that V.sub.2>Vg, C.sub.sense has to be
>>C.sub.cmos and V.sub.1/V.sub.2<<1 so that the sum of
terms in Eq. 4 is <1.
V.sub.1/V.sub.2=|C.sub.fe|/(C.sub.cmos+|C.sub.fe|) and voltage gain
of 2-10 has been demonstrated. For a 50 .ANG. sensing membrane of
Al.sub.2O.sub.3 and a gate oxide of SiO.sub.2 of 70 .ANG. and
V.sub.2/V.sub.1=5, it is shown from Eq. 4 that Vg/V.sub.2=0.48,
i.e., amplification of 2.1 can be achieved. Also,
0<C.sub.cmos/|C.sub.fe|<1 and
C.sub.sense/C.sub.cmos>1.
[0037] FIG. 8 shows a graph of V.sub.2 vs. Vg with a varying layer
of ferroelectric material. In the graph of FIG. 8, the y-axis is
V.sub.2 in volts and the x-axis is Vg in volts. In the structure
used for the graph of FIG. 8, the gate dielectric material is oxide
material having a thickness of 70 .ANG. and the sensing membrane is
Al.sub.2O.sub.3 having a thickness of 50 .ANG.. By varying the
layer of the ferroelectric material, it is shown that the ratio of
C.sub.cmos/|C.sub.fe| increases: 0.8, 0.88 and 0.98.
[0038] FIG. 9 shows a graph of V.sub.2 vs. Vg with a varying
sensing membrane. In the graph of FIG. 9, the y-axis is V.sub.2 in
volts and the x-axis is Vg in volts. In the structure used for the
graph of FIG. 9, the gate dielectric material is oxide material
having a thickness of 70 .ANG. and the sensing membrane is
Al.sub.2O.sub.3, HfO.sub.3 or TiO.sub.2. As shown in this graph,
the k-value of the different sensing members will increase. Even
larger voltage amplification (V.sub.2/Vg) can be achieved by:
increasing C.sub.cmos/|C.sub.fe| ratio (|C.sub.fe|>C.sub.cmos),
and/or increasing C.sub.sense (using higher-k materials, e.g.,
HfO.sub.2 (.epsilon.r=25) or TiO.sub.2 (.epsilon.r=80)) over
Ccmos.
[0039] The method(s) as described above is used in the fabrication
of integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0040] The descriptions of the various embodiments of the present
disclosure have been presented for purposes of illustration, but
are not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
* * * * *