U.S. patent application number 16/317837 was filed with the patent office on 2019-09-26 for complementary dual-modular redundancy memory cell.
This patent application is currently assigned to Bar-llan University. The applicant listed for this patent is Bar-llan University. Invention is credited to Lior ATIAS, Alexander FISH, Robert GITERMAN, Adam TEMAN.
Application Number | 20190295633 16/317837 |
Document ID | / |
Family ID | 61619370 |
Filed Date | 2019-09-26 |
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United States Patent
Application |
20190295633 |
Kind Code |
A1 |
GITERMAN; Robert ; et
al. |
September 26, 2019 |
COMPLEMENTARY DUAL-MODULAR REDUNDANCY MEMORY CELL
Abstract
A CDMR memory cell, includes a first bitcell which is used to
store a current data level and a second bitcell which is used to
store the complementary data level. When a read operation is
performed, a comparator compares the data levels read from the two
bitcells. If these two levels are not complementary, the comparator
outputs an indicator. This indicator serves as an alert that a
storage error has, or may have, occurred.
Inventors: |
GITERMAN; Robert;
(Beer-Sheva, IL) ; ATIAS; Lior; (Ramat-Gan,
IL) ; TEMAN; Adam; (Tel-Mond, IL) ; FISH;
Alexander; (Tel-Mond, IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Bar-llan University |
Ramat-Gan |
|
IL |
|
|
Assignee: |
Bar-llan University
Ramat-Gan
IL
|
Family ID: |
61619370 |
Appl. No.: |
16/317837 |
Filed: |
September 19, 2017 |
PCT Filed: |
September 19, 2017 |
PCT NO: |
PCT/IL2017/051059 |
371 Date: |
January 15, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62396256 |
Sep 19, 2016 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 5/005 20130101;
G11C 2211/4013 20130101; G11C 11/4093 20130101; G11C 5/02 20130101;
G11C 11/403 20130101; G11C 11/405 20130101; G06F 11/1068 20130101;
G11C 11/4125 20130101; G11C 11/419 20130101; G11C 29/52 20130101;
G11C 11/4097 20130101 |
International
Class: |
G11C 11/412 20060101
G11C011/412; G11C 11/419 20060101 G11C011/419; G11C 11/4093
20060101 G11C011/4093; G06F 11/10 20060101 G06F011/10; G11C 29/52
20060101 G11C029/52 |
Claims
1. A memory cell, comprising: a data write input, configured to
input data levels for storing in said memory cell; a data read
output; an indicator output; a first bitcell connected to said data
write input and said data read output, configured to store a first
data level input from said data write input and to output a first
read data level to said data read output; and a second bitcell
connected to said data write input, configured to store a second
data level input from said data write input to output a second read
data level; and a comparator associated with said first bitcell,
said second bitcell and said indicator output, configured to
compare a data level read from said first bitcell and a data level
read from said second bitcell and to provide, at said indicator
output, an indicator when said first read data level and said
second read data level are non-complementary.
2. A memory cell according to claim 1, wherein said first and
second data levels are input at said data write input in
series.
3. A memory cell according to claim 1, wherein said first and
second data levels are input at said data write input in
parallel.
4. A memory cell according to claim 1, further comprising at least
one processor adapted to execute code instructions to provide said
first data level to said first bitcell and a complementary data
level to said second bitcell.
5. A memory cell according to claim 1, further comprising an
inverter connected to said data write input, configured to invert
said first data level and to provide said inverted data level as
said second data level to said second bitcell.
6. A memory cell according to claim 1, further comprising at least
one processor adapted to execute code instructions to determine, in
accordance with said indicator, a correct data level from at least
one of said read data levels.
7. A memory cell according to claim 6, further comprising a parity
bit, and said code instructions for determining a correct data
level use said parity bit for said correcting.
8. A memory cell according to claim 1, wherein said memory cell is
a static memory.
9. A memory cell according to claim 1, wherein said memory cell is
a dynamic memory.
10. A memory cell according to claim 1, wherein write operations
for said first and second bitcells are triggered from a write
trigger input and read operations for said first and second
bitcells are triggered from a read trigger input.
11. A memory cell according to claim 1, wherein said first bitcell
and said second bitcell comprise respective write transistors
triggered from a write trigger input and respective read
transistors triggered from a read trigger input.
12. A memory cell according to claim 11, wherein write transistors
of said first and second bitcells are a same transistor type.
13. A memory cell according to claim 11, wherein read transistors
of said first and second bitcells are a same transistor type.
14. A memory cell according to claim 11, wherein all transistors of
said first and second bitcells are a same transistor type.
15. A memory cell according to claim 11, wherein all transistors of
said first and second bitcells are gain cell embedded DRAM
(GC-eDRAM) transistors.
16. A memory cell according to claim 1, wherein: said data write
input is configured to input said first and said second data levels
in parallel to said respective first and second bitcells; said
first bitcell comprises a write transistor and a read transistor,
and wherein: a first diffusion connection of said write transistor
is connected to said data write input, a gate connection of said
write transistor is connected to a write trigger input, a first
diffusion connection of said write transistor is connected to a
first comparator input, a second diffusion connection of said write
transistor is connected to a write trigger input, and a second
diffusion connection of said write transistor is connected to a
gate connection of said read transistor to form a first storage
node; and said second bitcell comprises a write transistor and a
read transistor, and wherein: a first diffusion connection of said
write transistor is connected to said data write input, a gate
connection of said write transistor is connected to said write
trigger input, a first diffusion connection of said write
transistor is connected to a second comparator input, a second
diffusion connection of said write transistor connected to said
write trigger input, and a second diffusion connection of said
write transistor is connected to a gate connection of said read
transistor to form a second storage node.
17. A memory cell according to claim 16, wherein said first bitcell
comprises a read bit line output configured to output said first
read data level read from said first bitcell.
18. A memory cell according to claim 16, wherein all of said first
bitcell transistors and said second bitcell transistors are gain
cell embedded GC-eDRAM transistors.
19. A memory array comprising: a data write input port, configured
to input data levels for storing in said array; a data read output
port, configured to output data levels from said memory array; an
indicator output port; a plurality of memory cells, each of said
memory cells comprising: a first bitcell connected to said data
write input port and said data read output port, configured to
store first data levels and to output first read data levels; and a
second bitcell connected to said data write input port, configured
to store second data levels and to output a second read data
levels; and at least one comparator, configured to compare
respective first and second read data levels a selected memory cell
and to provide, at said indicator output port, a respective
indicator when said first read data level and said second read data
level are non-complementary.
20. A memory array according to claim 19, further comprising at
least one non-transitory computer readable storage medium storing
instructions and at least one processor configured to execute said
instructions to provide, at said write input port, first data
levels for storing in said first bitcells and complementary data
levels for storing in respective second bitcells.
21. A memory array according to claim 19, further comprising at
least one non-transitory computer readable storage medium storing
instructions and at least one processor configured to execute said
instructions to correct memory cell errors by applying error
correction logic to at least one data level read from a memory cell
and a respective indicator.
22. A memory array according to claim 21, further comprising a
parity array comprising at least one parity bit per column of said
memory cells, wherein said error correction logic uses said parity
array for said correcting said memory cell read errors.
23. A memory array according to claim 21, wherein said memory array
is a static memory array.
24. A memory array according to claim 21, wherein said memory array
is a dynamic memory array.
25. A memory array according to claim 21, wherein said first
bitcells and said second bitcells are stored in different rows of
said memory array.
26. A memory array according to claim 21, wherein said first
bitcells and said second bitcells are stored in different portions
of said memory array.
27. A method comprising: providing a memory cell comprising: a
first bitcell configured to store a first input data level and to
output said stored first data level to a data read output; and a
second bitcell configured to store a second input data level;
storing a first data level in said first bitcell and a
complementary data level in said second bitcell; reading first and
second data levels from said first and second bitcells
respectively; and providing an indicator when first and second read
data levels are non-complementary.
28. A method according to claim 27, further comprising performing
error correction on said first and second read data levels to
determine a correct first data level when said indicator is
provided.
Description
FIELD AND BACKGROUND OF THE INVENTION
[0001] The present invention, in some embodiments thereof, relates
to a memory cell and, more particularly, but not exclusively, to a
4-transistor memory cell.
[0002] In accordance with Moore's Law, the size, density, and power
consumption of static random-access memories (SRAMs) has grown
exponentially over the past four and a half decades. This trend is
expected to continue, as SRAMs occupy over 50% of the total area
and static power consumption of high performance microprocessors
and are one of the primary components of most types of modern
ASICs. Traditionally, the primary goals of SRAM design were density
and high performance, whereas power was a secondary concern and
stability was easily achieved. However, at deep sub-micron
technologies, frequency has been replaced by power and stability as
the primary factors in SRAM design. As device dimensions continue
to scale, conventional SRAM memories experience poor read and write
stabilities, resulting in an ever growing error rate. This results
of higher process variations and device mismatch, lowering the
static noise margins of SRAM memories, resulting in a higher
susceptibility to noise. Furthermore, embedded memory arrays are
often operated at highly scaled supply voltages in order to reduce
their power consumption, which results in even lower noise margin
and a much higher susceptibility to radiation effects, such as soft
errors or single event upsets (SEUs).
[0003] SEUs occur when an energetic particle passes through a
silicon substrate and its energy is transferred into the creation
of electron-hole pairs along its path, as illustrated in FIG. 1.
When such a particle hits a reversed-biased junction inside a
storage node, the resulting transient current pulse may inject
enough charge into the junctions to cause a data flip of a memory
cell.
[0004] Embedded memory errors are typically handled at an
architectural level using redundancy schemes, such as error
correcting codes (ECCs) and triple modular redundancy (TMR).
However, these solutions are extremely costly in terms of area
overhead, while also adding complexity and delay, and are
incompatible with sub-threshold operating memories. Furthermore,
conventional error correction codes (ECCs) can only detect two
errors and correct a single bit, otherwise requiring an even larger
area overhead and complexity. Circuit level techniques such as DICE
and Quatro 10T may efficiently increase SEU tolerance, however they
require a much higher transistor-count, resulting in an even larger
area and power consumption of these memory arrays.
[0005] Virtually all of the previously proposed solutions for error
tolerant embedded memories are based on SRAM technology, adding
additional devices and area consumption to the standard six
transistors (6T) that are at the core of these memory arrays. One
increasingly popular alternative to SRAM is gain cell embedded DRAM
(GC-eDRAM), which offers much smaller area, lower leakage, and the
option of low voltage operation. The main drawback of GC-eDRAM is
the need for periodic refresh cycles to ensure data retention.
However, it has been shown that its retention power, which is the
sum of leakage and refresh power, may be lower than the leakage
power of a conventional 6T SRAM cell.
[0006] State of the art error tolerant solutions can be divided to
two approaches, circuit and architectural levels. Circuit level
solutions are implemented by modification of the memory cell with
increased noise margins, resulting in higher robustness to
failures. In addition, SEUs tolerance may be improved by
multiplication of the storage nodes and increased critical charge,
thus enabling the recovery of the data following SEUs. Architecture
level solutions include various error correcting schemes, mostly
implemented by error correction codes. ECCs may be integrated
without any modification to the memory array and are capable of
correcting several errors according to the ECCs scheme used. In
fact, ECCs are integrated in most embedded memories today.
Circuit Level Solutions
[0007] The conventional 6T SRAM memory cell utilizes an active
feedback loop between cross-coupled inverters in order to retain
its stored data value. This circuit is very sensitive to SEUs, as
any upset that causes one of the data nodes to cross the switching
threshold of the adjacent inverter will result in a bit flip. This
failure risk increases with process scaling, where the critical
charge of the memory cell decreases resulting in a higher soft
error rates (SERs). Furthermore, static noise margins decrease
significantly and therefore the memory cell is more susceptible to
read and write errors. In addition, SRAM design for low-voltage
operation has become increasingly popular over the past few years.
However, when operating at low voltages, the switching threshold
decreases, thereby increasing the circuit's error susceptibility.
Various bitcell designs have been proposed to improve the noise
margins of the cell in order to be compatible with low-voltage
operation at scaled CMOS nodes. These designs generally incorporate
the addition of a number of transistors into the bitcell topology,
trading off density with robust, low-voltage functionality. However
they do not offer self error detection and correction
capability.
[0008] Many alternative error-tolerant SRAM circuits have been
proposed in recent years. These solutions are directly aimed at
improving the soft error susceptibility. Recently proposed error
tolerant designs include the temporal latch, DICE, the Quatro-10T
and 12T bitcells, the 13T sub-threshold bitcell, and SHIELD. These
solutions may be fabricated in commercially available
state-of-the-art manufacturing processes at the expense of an
increase in the silicon area of the bitcell. The following three
solutions reported high error tolerance and incorporate low-voltage
operation.
[0009] 1) DICE: The dual interlocked storage cell (DICE) is the
best known SEU hardened bitcell. The concept of the DICE design is
using the dual modular redundancy (DMR) of its internal circuit
nodes to achieve immunity to errors affecting a single node. This
is achieved with 12 transistors, implementing a dual node feedback
control mechanism, as seen in FIG. 2A. The storage element utilizes
four internal circuit nodes to store one memory bit. When a single
event temporarily upsets one of these four nodes, only one
additional node is affected by the upset through positive feedback.
In this way a single node upset (SNU) will not propagate the error
to the other nodes, and the unaffected nodes can correct the
circuit value. However, it still remains sensitive to multi-node
upsets (MNU) and also suffers from high power consumption, due to
its many transistors and leakage paths. Additionally, the cell
recovery time severely increases with supply voltage scaling,
making the DICE bitcell inefficient for ultra low power (ULP)
operation.
[0010] 2) The 13T and SHIELD: While all of the previously proposed
rad-hard bitcells were designed for error resilience under nominal
supply voltages, the circuits proposed in "A 13T radiation hardened
SRAM bitcell for low-voltage operation," by L. Atias, A. Teman, and
A. Fish [25] and in "A novel low power bitcell design featuring
inherent seu prevention and self correction capabilities," by O.
Chertkow, A. Pescovsky, L. Atias, and A. Fish [26] specifically
target ULP space applications, operated at scaled voltages. The 13T
bitcell, shown in FIG. 2B, achieves radiation hardening by
employing a dual-feedback, separated storage mechanism to overcome
the increased vulnerability due to supply voltage scaling. By
driving the acute data level with a pair of equipotentially driven,
but independent, inverters, a strong, dual-driven feedback
mechanism is applied with node separation for SEU protection. This
setup effectively protects Q from an upset on QB1 or QB2, while
achieving a high critical charge at node Q. The 13T bitcell was
shown to be fully functional at sub-threshold voltages in [25] for
a 0.18 .mu.m implementation.
[0011] Another approach to ULP rad-hard operation is taken by the
SHIELD bitcell [26], shown in FIG. 2C. This bitcell uses a pair of
gated inverters (M5-M1-M2-M6 and M7-M3-M4-M8) to mitigate SEUs.
These inverters incorporate an additional input gate that
dynamically latches the previous output state when the primary and
secondary inputs are different. A pair of these gated inverters is
cross-coupled through a cutoff network (M11-M12 and M13-M14) to
provide radiation tolerance. This results in two sets of separate
dual-data nodes, which exhibit high SEU tolerance under scaled
supply voltages.
Architectural Solutions
[0012] The main approach to error mitigation over the past two
decades has been to provide full immunity to errors through circuit
redundancy. The simplest way of error detection is using an
additional parity bit, indicating whether a single error has
occurred by comparing the parity of the stored data in the word to
the parity bit. While this method is simple and requires minimal
area cost, it can only detect up to one error per word and cannot
correct it. For large memory arrays, ECCs can be used to detect and
correct data errors in the memory array. They are typically
implemented by the addition of extra bits per word and encoding the
data to be able to detect and correct several bits, based on the
used code. The number of bits which can be corrected comes in the
expense of complexity and area overhead. One of the mostly used
ECCs is single error correcting (SEC) Hamming code, which has the
ability to correct single upsets with a reduced area and
performance overhead. However, single error correcting ECCs may not
be sufficient to meet reliability goals. Extended Hamming codes
enable a single error correction-double error detection (SECDED).
However, multiple errors occurring in a single word cannot be
corrected. More advanced ECCs schemes include Reed-Solomon encoding
and decoding, which enables the error correction and detection of
multiple errors. Although this code copes with multiple errors, it
does not correct double faults located in two adjacent blocks;
which requires the use of Reed-Solomon code with double block
correction capability. The cost of double block correction code is
too high compared to the single block correction code, which makes
this alternative inappropriate for hardware implementation.
[0013] The most popular technique in use today involves replicating
a storage node three times and adding a three-input majority gate
to filter out unwanted SEUs. This technique assumes that the
probability of an error at two separate places on the chip within a
defined time span is extremely low. When a single error occurs at
any of the three storage nodes, a three-input majority gate acts as
a voting circuit to recover the correct value. TMR is popular among
ASIC and FPGA designers, since it does not introduce any new
circuit elements to the existing standard cell library. However,
TMR requires an increase in both area and power of at least
3.times.. In addition, TMR institutes a non-negligible delay
overhead, due to the triplication of the sequential cells and the
addition of the delay elements and majority gate.
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[0047] [34] P. Dodd and F. Sexton, "Critical charge concepts for
CMOS SRAMs," IEEE Transactions on Nuclear Science, vol. 42, no. 6,
pp. 1764-1771, 1995.
SUMMARY OF THE INVENTION
[0048] Embodiments of the complementary dual-modular redundancy
(CDMR) memory cell presented herein include two bitcells which
store complementary data levels. During a write operation, the data
level being stored is written to one bitcell and the complementary
data level is written to the second bitcell. When a read operation
is performed, the data level is read from both bitcells. A
comparator then compares the two read data levels. If these two
levels are not complementary, the comparator outputs an indicator
which serves as an alert that a storage error has (or may have)
occurred. Further error detection and/or error correction
techniques may then be employed on the data read from the CDMR
memory cell. In further embodiments a memory array is formed from
multiple complementary CDMR memory cells, according to any memory
array architecture known in the art.
[0049] According to an aspect of some embodiments of the present
invention there is provided a memory cell, which includes: [0050] a
data write input, configured to input data levels for storing in
the memory cell; [0051] a data read output; [0052] an indicator
output; [0053] a first bitcell connected to the data write input
and the data read output, configured to store a first data level
input from the data write input and to output a first read data
level to the data read output; and [0054] a second bitcell
connected to the data write input, configured to store a second
data level input from the data write input to output a second read
data level; and [0055] a comparator associated with the first
bitcell, the second bitcell and the indicator output, configured to
compare a data level read from the first bitcell and a data level
read from the second bitcell and to provide, at the indicator
output, an indicator when the first read data level and the second
read data level are non-complementary.
[0056] According to some embodiments of the invention, the first
and second data levels are input at the data write input in
series.
[0057] According to some embodiments of the invention, the first
and second data levels are input at the data write input in
parallel.
[0058] According to some embodiments of the invention, the memory
cell further includes at least one processor adapted to execute
code instructions to provide the first data level to the first
bitcell and a complementary data level to the second bitcell.
[0059] According to some embodiments of the invention, the memory
cell further includes an inverter connected to the data write
input, configured to invert the first data level and to provide the
inverted data level as the second data level to the second
bitcell.
[0060] According to some embodiments of the invention, the memory
cell further includes at least one processor adapted to execute
code instructions to determine, in accordance with the indicator, a
correct data level from at least one of the read data levels.
[0061] According to some embodiments of the invention, the memory
cell further includes a parity bit, and code instructions for
execution by at least one processor for determining a correct data
level use the parity bit for the correcting.
[0062] According to some embodiments of the invention, the memory
cell is a static memory.
[0063] According to some embodiments of the invention, the memory
cell is a dynamic memory.
[0064] According to some embodiments of the invention, write
operations for the first and second bitcells are triggered from a
write trigger input and read operations for the first and second
bitcells are triggered from a read trigger input.
[0065] According to some embodiments of the invention, the first
bitcell and the second bitcell include respective write transistors
triggered from a write trigger input and respective read
transistors triggered from a read trigger input.
[0066] According to some embodiments of the invention, the write
transistors of the first and second bitcells are the same
transistor type.
[0067] According to some embodiments of the invention, the read
transistors of the first and second bitcells are the same
transistor type.
[0068] According to some embodiments of the invention, all the
transistors of the first and second bitcells are the same
transistor type.
[0069] According to some embodiments of the invention, all the
transistors of the first and second bitcells are gain cell embedded
DRAM (GC-eDRAM) transistors.
[0070] According to some embodiments of the invention: [0071] the
data write input is configured to input the first and the second
data levels in parallel to the respective first and second
bitcells; [0072] the first bitcell includes a write transistor and
a read transistor, and wherein: a first diffusion connection of the
write transistor is connected to the data write input, a gate
connection of the write transistor is connected to a write trigger
input, a first diffusion connection of the write transistor is
connected to a first comparator input, a second diffusion
connection of the write transistor is connected to a write trigger
input, and a second diffusion connection of the write transistor is
connected to a gate connection of the read transistor to form a
first storage node; and [0073] the second bitcell includes a write
transistor and a read transistor, and wherein: a first diffusion
connection of the write transistor is connected to the data write
input, a gate connection of the write transistor is connected to
the write trigger input, a first diffusion connection of the write
transistor is connected to a second comparator input, a second
diffusion connection of the write transistor connected to the write
trigger input, and a second diffusion connection of the write
transistor is connected to a gate connection of the read transistor
to form a second storage node.
[0074] According to some embodiments of the invention, the first
bitcell comprises a read bit line output configured to output the
first read data level read from the first bitcell.
[0075] According to some embodiments of the invention, all of the
first bitcell transistors and the second bitcell transistors are
gain cell embedded GC-eDRAM transistors.
[0076] According to an aspect of some embodiments of the present
invention there is provided a memory array which includes: [0077] a
data write input port, configured to input data levels for storing
in the array; [0078] a data read output port, configured to output
data levels from the memory array; [0079] an indicator output port;
[0080] multiple memory cells, each of the memory cells comprising:
[0081] a first bitcell connected to the data write input port and
the data read output port, configured to store first data levels
and to output first read data levels; and [0082] a second bitcell
connected to the data write input port, configured to store second
data levels and to output a second read data levels; and [0083] at
least one comparator, configured to compare respective first and
second read data levels a selected memory cell and to provide, at
the indicator output port, a respective indicator when the first
read data level and the second read data level are
non-complementary.
[0084] According to some embodiments of the invention, the memory
array further includes at least one non-transitory computer
readable storage medium storing instructions and at least one
processor configured to execute the instructions to provide, at the
write input port, first data levels for storing in the first
bitcells and complementary data levels for storing in respective
second bitcells.
[0085] According to some embodiments of the invention, the memory
array further includes at least one non-transitory computer
readable storage medium storing instructions and at least one
processor configured to execute the instructions to correct memory
cell errors by applying error correction logic to at least one data
level read from a memory cell and a respective indicator.
[0086] According to some embodiments of the invention, the memory
array further includes a parity array comprising at least one
parity bit per column of the memory cells, wherein the error
correction logic uses the parity array for the correcting the
memory cell read errors.
[0087] According to some embodiments of the invention, the memory
array is a static memory array.
[0088] According to some embodiments of the invention, the memory
array is a dynamic memory array.
[0089] According to some embodiments of the invention, the first
bitcells and the second bitcells are stored in different rows of
the memory array.
[0090] According to some embodiments of the invention, the first
bitcells and the second bitcells are stored in different portions
of the memory array.
[0091] According to an aspect of some embodiments of the present
invention there is provided a method which includes:
[0092] providing a memory cell comprising: [0093] a first bitcell
configured to store a first input data level and to output the
stored first data level to a data read output; and [0094] a second
bitcell configured to store a second input data level;
[0095] storing a first data level in the first bitcell and a
complementary data level in the second bitcell;
[0096] reading first and second data levels from the first and
second bitcells respectively; and
[0097] providing an indicator when first and second read data
levels are non-complementary.
[0098] According to some embodiments of the invention, the method
further includes performing error correction on the first and
second read data levels to determine a correct first data level
when the indicator is provided.
[0099] Unless otherwise defined, all technical and/or scientific
terms used herein have the same meaning as commonly understood by
one of ordinary skill in the art to which the invention pertains.
Although methods and materials similar or equivalent to those
described herein can be used in the practice or testing of
embodiments of the invention, exemplary methods and/or materials
are described below. In case of conflict, the patent specification,
including definitions, will control. In addition, the materials,
methods, and examples are illustrative only and are not intended to
be necessarily limiting.
[0100] Implementation of the method and/or system of embodiments of
the invention can involve performing or completing selected tasks
manually, automatically, or a combination thereof. Moreover,
according to actual instrumentation and equipment of embodiments of
the method and/or system of the invention, several selected tasks
could be implemented by hardware, by software or by firmware or by
a combination thereof using an operating system.
[0101] For example, hardware for performing selected tasks
according to embodiments of the invention could be implemented as a
chip or a circuit. As software, selected tasks according to
embodiments of the invention could be implemented as a plurality of
software instructions being executed by a computer using any
suitable operating system. In an exemplary embodiment of the
invention, one or more tasks according to exemplary embodiments of
method and/or system as described herein are performed by a data
processor, such as a computing platform for executing a plurality
of instructions. Optionally, the data processor includes a volatile
memory for storing instructions and/or data and/or a non-volatile
storage, for example, a magnetic hard-disk and/or removable media,
for storing instructions and/or data. Optionally, a network
connection is provided as well. A display and/or a user input
device such as a keyboard or mouse are optionally provided as
well.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0102] Some embodiments of the invention are herein described, by
way of example only, with reference to the accompanying drawings.
With specific reference now to the drawings in detail, it is
stressed that the particulars shown are by way of example and for
purposes of illustrative discussion of embodiments of the
invention. In this regard, the description taken with the drawings
makes apparent to those skilled in the art how embodiments of the
invention may be practiced.
[0103] In the drawings:
[0104] FIG. 1 illustrates a particle strike hitting a silicon
substrate junction;
[0105] FIG. 2A is a simplified layout of a DICE bitcell;
[0106] FIG. 2B is a simplified layout of a 13T radiation hardened
SRAM;
[0107] FIG. 2C is a simplified layout of a SHIELD SRAM;
[0108] FIG. 3A is a simplified block diagram of a CDMR memory cell,
according to embodiments of the invention;
[0109] FIG. 3B is a simplified block diagram of a CDMR memory cell
with read/write triggering, according to embodiments of the
invention;
[0110] FIG. 3C is a simplified layout of a four transistor PMOS
CDMR memory cell, according to embodiments of the invention;
[0111] FIG. 3D is a simplified layout of a four transistor NMOS
CDMR memory cell, according to embodiments of the invention;
[0112] FIG. 4 is a waveform demonstration of write-upset-read
events;
[0113] FIG. 5 is a simplified block diagram of a memory array of 4T
CDMR memory cells, according to embodiments of the invention;
[0114] FIG. 6A is a simplified circuit diagram of a CDMR memory
cell with differential sense amplifier, according to exemplary
embodiments of the invention;
[0115] FIG. 6B is a simplified circuit diagram of a CDMR memory
cell with single-ended readout with error detection, according to
exemplary embodiments of the invention;
[0116] FIG. 6C is a histogram showing read access time distribution
for single-ended readout;
[0117] FIG. 6D is a histogram showing read access time distribution
for differential readout;
[0118] FIG. 7 is a graph showing storage node degradation of a
simulated 4T CDMR memory cell following a write operation under
worst case WBL bias conditions;
[0119] FIG. 8 is a histogram showing DRT distribution of a
simulated 4T CDMR memory cell; and
[0120] FIG. 9 is a graph comparing the retention power of a
simulated 4T CDMR memory cell and prior art solutions;
[0121] FIG. 10A is a graph of the refresh rate of a simulated 4T
CDMR memory cell;
[0122] FIG. 10B is a graph of the refresh power consumption of a
simulated 4T CDMR memory cell; and
[0123] FIG. 11 is a graph of critical charge as a function of the
time after write.
DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION
[0124] The present invention, in some embodiments thereof, relates
to a CDMR memory cell and, more particularly, but not exclusively,
to a 4-transistor CDMR memory cell.
[0125] Embodiments of the CDMR memory cell presented herein include
two bitcells which store complementary data levels. One of the
bitcells holds the actual data level being stored and the other
bitcell holds the complementary data level. When a read operation
is performed, a comparator compares the data levels read from the
two bitcells contained in the CDMR memory cell. If these two levels
are not complementary, the comparator outputs an indicator which
serves as an alert that a storage error has (or may have) occurred.
Further error detection and/or error correction techniques may then
be employed on the data read from the CDMR memory cell.
[0126] In the most general case, the indicator does not detect
storage errors with 100% probability. If an error occurs in both
bitcells, the output levels will still be complementary and no
error will be indicated. However, for some transistor types an
error in both bitcells is unlikely, and relatively simple error
detection and correction logic may be used to determine the correct
data level.
[0127] As used herein the terms "complementary dual-modular
redundancy memory cell", "CDMR memory cell" and "memory cell" mean
a one-bit memory which stores two data level values, where each
data level may be read independently without changing the other
data level. Optionally the two data levels are stored in respective
bitcells.
[0128] As used herein the term "bitcell" means a one-bit
memory.
[0129] As used herein the terms "complementary data level" means
the data level of the opposite logic value. For example, if the
data level stored in the first bitcell corresponds to a logic "0"
the complementary data level corresponds to a logic "1".
[0130] Before explaining at least one embodiment of the invention
in detail, it is to be understood that the invention is not
necessarily limited in its application to the details of
construction and the arrangement of the components and/or methods
set forth in the following description and/or illustrated in the
drawings and/or the Examples. The invention is capable of other
embodiments or of being practiced or carried out in various
ways.
I. CDMR Memory Cell
[0131] Referring now to the drawings, FIG. 3A is a simplified block
diagram of a CDMR memory cell, according to embodiments of the
invention. CDMR memory cell 300 includes two bitcells, 310 and 320,
and comparator 330. For correct operation of the CDMR memory cell,
the data level of the data actually being stored is written to
bitcell 310 and the complementary data level is written to bitcell
320.
[0132] When a read operation is performed, comparator 330 compares
the data level read from said first bitcell to the data level read
from the second bitcell. Comparator 330 outputs an indicator which
shows if the two read data levels are or are not complementary. If
the data level in a single bitcell has flipped, the indicator will
show that the data levels are not complementary. Optionally, an
indicator showing non-complementary levels serves as an alert that
error detection and/or error correction and/or other operations
should be performed.
[0133] Optionally, the comparator is an XOR gate which compares
logic levels read from memory cell. Alternately, the comparator is
an analog comparator which compares analog levels output from the
memory cell.
[0134] Comparator 330 may be located adjacent to the bitcells, or
may be located in a different location on the circuit (e.g.
ASIC).
[0135] Optionally, the timing of the read and/or write operations
are controlled to ensure that in each read cycle corresponding data
levels are provided to comparator 330 for comparison (so that the
data level written to bitcell 320 was complementary to the data
written to bitcell 310 and therefore should be complementary at
read time).
[0136] Optionally, the data write input includes separate input
lines for bitcells 310 and 320, and the complementary data levels
are provided to the memory cell in parallel to be stored in the
memory cell in a single cycle. Alternately, the complementary data
levels are provided to memory cell 300 in series via a single input
line and stored in the respective bitcell in separate cycles.
Optionally, CDMR memory cell 300 includes an inverter. In the
exemplary embodiment shown in FIG. 3B, inverter 340 inverts the
logic level at WBL, thereby obtaining the complementary data level,
and provides the complementary data level to bitcell 320. There is
then no need to provide the complementary data level separately to
WBLB.
[0137] Optionally, based on the indicator, error detection and/or
correction operations are performed on the data levels read from
one or both of bitcells 310 and 320. The memory detection and/or
correction operations may be performed by any suitable techniques
known in the art.
[0138] Optionally, CDMR memory cell 300 includes, or is associated
with, a parity bit and the error detection and/or correction
operations use the parity bit. Optionally, the parity bit is stored
in a parity bitcell which is integrated in CDMR memory cell 300.
Alternately or additionally, the parity bit is stored externally to
CDMR memory cell 300.
[0139] Optionally, the parity bit is stored in a separate CDMR
memory cell. Alternately or additionally, the parity bit is stored
in a different type of bitcell. Optionally, other error detection
and/or correction techniques known in the art are used for a single
CDMR memory cell or for a memory array formed from multiple CDMR
memory cells. These techniques may include using parity bit(s),
data replication, error correction coding and so forth.
[0140] Optionally, CDMR memory cell 300 is a dynamic memory cell.
Alternately, CDMR memory cell 300 is a static memory cell.
[0141] Reference is now made to FIG. 3B, which is a simplified
block diagram of a CDMR memory cell with read write triggering,
according to an exemplary embodiment of the invention. CDMR memory
cell 305 includes two bitcells and a comparator configured as shown
above, and additionally includes write and read trigger inputs (WWL
and RWL respectively).
[0142] Bitcell 310 stores the data level which is at the data write
input (WBL) during a write operation. Bitcell 320 stores the data
level which is at the complementary data write input (WBLB) for the
same write operation. Write operations to bitcells 310 and 320 are
triggered by a common write trigger input (WWL). Read operations
from bitcells 310 and 320 are triggered by a common write trigger
input (RWL). The data read from bitcell 310 is output at data read
output RBL. Optionally, CDMR memory cell 305 also includes a second
data read output (RBLB) for bitcell 320.
[0143] When the CDMR memory cell does not include inverter 340 and
the write operation is triggered by a common trigger (WWL), the
data levels at WBL and WBLB should be complementary at the time of
the write operation.
[0144] Optionally, write and read operations to CDMR memory cell
305 are performed in parallel.
[0145] Alternately, write and/or read operations to CDMR memory
cell 305 are performed in series. Optionally, for parallel write
operations, bitcells 310 and 320 are triggered independently by
respective write triggers (i.e. not by common write trigger WWL as
shown in FIG. 3B). Optionally, for parallel read operations,
bitcells 310 and 320 are triggered independently by respective read
triggers (i.e. not by common read trigger RWL as shown in FIG.
3B).
[0146] Optionally, bitcells 310 and 320 are two-transistor (2T)
bitcells which include respective write and read transistors.
Further optionally, write operations to the two write transistors
are triggered together by a write trigger (e.g. WWL in FIG. 3B) and
read operations from the two read transistors are triggered
together by a read trigger (e.g. RWL in FIG. 3B).
[0147] Optionally the two write transistors are the same transistor
type. Alternately or additionally, the two read transistors are the
same transistor type.
[0148] Optionally, all four transistors are the same transistor
type. Further optionally, all four transistors are gain cell
embedded DRAM (GC-eDRAM) transistors.
[0149] Different embodiments of the CDMR memory cells may use
different types of transistors. Optional types of transistors which
may be used to construct the CDMR memory cell include, but are not
limited to:
[0150] i) Ultra-high Vt;
[0151] ii) High Vt;
[0152] iii) Regular Vt;
[0153] iv) Low Vt;
[0154] v) Ultra-low Vt;
[0155] vi) Native; and
[0156] vii) I/O NMOS/PMOS.
[0157] Embodiments of CDMR memory cells may be implemented in
circuits, including, but not limited to:
[0158] a) An integrated circuit (IC) customized for a particular
use, such as an Application-Specific Integrated Circuit (ASIC);
[0159] b) A programmable logic device intended for general-purpose
use. Examples of such programmable logic devices include, but are
not limited to: Field-Programmable Gate Array (FPGA), Gate Array,
Uncommitted Logic Array (ULA), Programmable Logic Array (PLA),
Programmable Array Logic (PAL), Complex Programmable Logic Device
(CPLD), Erasable Programmable Logic Device (EPLD) and Structured
ASIC.
II. Four Transistor (4T) CDMR Memory Cell
[0160] Optionally, the CDMR memory cell is a four-transistor (4T)
memory cell which includes two 2T bitcells and a comparator. In the
4T embodiment, each of the bitcells includes a respective write
transistor and a respective read transistor.
[0161] Reference is now made to FIG. 3C, which is a simplified
layout of a four transistor (4T) PMOS CDMR memory cell, according
to exemplary embodiments of the invention. The 4T CDMR memory cell
includes two write transistors (MW1, MW2) and two read transistors
(MR1, MR2). The two read data levels, at RBL and RBLB, are provided
to the comparator (not shown).
[0162] FIG. 3D is a simplified layout of a 4T NMOS CDMR memory
cell, according to exemplary embodiments of the invention. The
layout of the NMOS CDMR memory cell is very similar to the NMOS
layout, and includes two write transistors (MW1, MW2) and two read
transistors (MR1, MR2) interconnected as shown in FIG. 3D.
[0163] During normal operation, the output of a read operation from
the MR1 and MR2 would provide two opposite levels. Therefore, if
both storage nodes provide the same read out level, it may be
concluded (or suspected) that a read error has occurred.
[0164] The data and its complementary values are stored on the
parasitic capacitances at the storage nodes (SN and SNB),
comprising the gate capacitance of MR1/MR2 and the diffusion
capacitance of MW1/MW2, respectively. Writing to the cell is
performed by driving the write word line (WWL) to a negative
voltage and passing the data and its complementary level from the
write bit lines (WBL and WBLB) to SN and SNB, respectively. Readout
is performed by pre-discharging the read bit lines (RBL and RBLB)
to GND and driving the read word lines (RWL and RWLB) to VDD,
thereby charging RBL/RBLB only if SN/SNB holds a data `0`. The
RBL/RBLB of each column is connected to a sensing circuit, which
may be implemented with a simple inverter, in order to output the
digital levels of the data and its complementary level stored in
the selected cell.
III. CDMR Memory Array
[0165] Optionally, CDMR memory cells are combined to form a CDMR
memory array. The memory array architecture may be any architecture
known in the art that is suitable for the type of transistors
forming the CDMR memory cells. An exemplary embodiment of a memory
array architecture is illustrated in FIG. 5 below.
[0166] The CDMR memory array includes multiple CDMR memory cells,
each of which includes respective first and second bitcells for
storing complementary logic levels. The CDMR memory array further
includes one or more comparators which compare the data levels read
from the first and second bitcells of a respective CDMR memory
cell, and provides respective indicators showing when the read data
levels are non-complementary.
[0167] There are multiple options for positioning the respective
bitcell pairs within the memory array. Optional arrangements
include:
[0168] i) The memory array is laid out as an array of CDMR memory
cells, with the first and second bitcells interconnected within the
respective memory cell.
[0169] ii) The first bitcells and the second bitcells are located
on different rows of the memory array.
[0170] iii) The first bitcells and the second bitcells are located
in different portions of the memory array.
[0171] iv) The first bitcells and the second bitcells are located
on separate sub-arrays.
[0172] Optionally, the memory array is read in multi-bit data words
along with a corresponding indicator word having a respective
indicator for each bit in the data word.
[0173] Optionally, write bit line inputs of the memory cells are
connected to form a common write bit line and respective
complementary write bit line inputs of the memory cells are
connected to form a common complementary write bit line.
[0174] In itself, the CDMR characteristic of the memory cells in
the memory array provides a reduced area implementation with
inherent error detection capabilities. However, while the location
of the error is known, it is not inherently clear if the data or
its complementary value was corrupted, which may prevent correction
of the error. This may be addressed by adding a parity bit to each
set of bits. If the parity is maintained despite the error, the
complementary value of the erroneous bit (SNB) has been corrupted
and should be corrected, while if the parity is incorrect, the SN
value should be corrected.
[0175] Optionally, the CDMR memory array includes a parity array
which stores at least one parity bit per column of CDMR memory
cells. Error correction logic may use the parity array for the
correcting the memory cell read errors.
[0176] Optionally, the CDMR memory array according to claim
includes at least one processor which applies error correction
logic to the data levels read from the CDMR memory cell in the
array along with the respective indicators obtained from the
comparator(s).
[0177] Optionally the CDMR memory array is a static memory.
Alternately, the CDMR memory array is a dynamic memory.
IV. Exemplary 4T GC-eDRAM CDMR Memory Cell
[0178] Optionally, the 4T CDMR memory cell uses GC-eDRAM
transistors. A 4T GC-eDRAM CDMR memory cell is robust against SEUs
and data deterioration errors.
[0179] In general, the primary risk of an SEU triggered data flip
in a conventional SRAM cell is due to the positive feedback between
the two internal storage nodes. The SRAM structure is highly
susceptible to a particle strike, as any voltage shift which causes
one of the storage nodes to cross the switching threshold of the
adjacent inverter will result in a bit flip.
[0180] Gain-cell eDRAM (GC-eDRAM) is a fully logic-compatible
implementation of eDRAM, which provides a reduced silicon footprint
as compared to SRAM, but lacks the internal feedback that ensures
strong storage levels, in spite of deteriorating leakage currents.
Intuitively, such a topology is much more susceptible to SERs, as
the circuit lacks any mechanism to mitigate a level change induced
by a particle strike. However, with complementary dual-modular
redundancy both the data value and its inverse (i.e. complementary)
value are stored for each bit. Based on this concept, SEUs in the
CDMR memory cell or a CDMR memory array may be both detected and
corrected, while still achieving the low area and power aspirations
of the target applications.
[0181] The 4T GC-eDRAM CDMR memory cell lacks the internal feedback
mechanism of the SRAM cell. Therefore, the complementary storage
nodes (SN and SNB) are affected separately by a particle strike. In
the case of a particle changing the data in one of the storage
nodes, the complementary node will remain unaffected and both nodes
will store the same data level. Therefore, by simply comparing the
outputs (e.g. with an XOR gate) an error may be detected in any
given bit.
[0182] For example, in the all-PMOS cell of FIG. 3C the only nodes
susceptible to a strike are the reverse-biased p+n junctions at SN
and SNB. For such a junction, only a positive voltage shift can
occur due to a particle strike, and therefore only a stored data
`0` may be flipped. If the particle strike occurs just after a
write `0` operation to the cell, the level might get deteriorated
and its retention time would get decreased. On the other hand, a
particle strike close to the retention time of the cell will quite
surely flip its state and cause an error during readout. On the
other hand, a particle strike on a node storing a data `1` would
only strengthen the stored level, since MR1 would be more cut off
during a readout. Furthermore, its retention time would be
increased as a result of the positive voltage shift.
[0183] The operation of the 4T GC-eDRAM CDMR memory cell under SEUs
is demonstrated in FIG. 4. FIG. 4 shows consecutive write, upset,
and read events for data `1` and `0` with a 400 mV supply voltage.
The SEU was modeled by connecting a current source to the SN node
of the bitcell and applying a double-exponential current pulse
during the standby states of the cell, according to the model
presented in [18]. The physical composition of the cell only allows
a positively charged upset [15], and therefore, in the example,
only this type of particle strike is shown. In the first
demonstrated strike (particle strike 1), the cell is storing a `1`,
and the positive charge only strengthens the stored level, leaving
RBL discharged during readout and not leading to an error. On the
hand, when data `0` is stored, the applied pulse (particle strike
2) causes an increase in the voltage level stored at SN, causing
the RBL to erroneously charge during readout. Since the
complementary value, stored in SNB, is also a data `1`, both RBL
and RBLB provide a logic `1` at the output, indicating that an
error has occurred. In addition, the parity will no longer be
correct, which implies that the error occurred in the SN of the
erroneous bit, and therefore, this node should be pulled back down
to `0` to correct the error.
[0184] The sensitivity of a memory bitcell to particle strikes is
commonly quantified using the C.sub.crit metric, which is
determined by integrating the applied current source at the point
where it causes a read failure following an SEU. However, the
inherent error detection and correction capabilities of the
proposed topology and architecture significantly reduce the
relevance of the C.sub.crit metric and make it inappropriate for
comparison with other solutions. Nonetheless, the C.sub.crit of the
4T bitcell was extracted through simulation under particle strikes,
as described in Sec. V-D below.
V. Exemplary CDMR Memory Array
[0185] Reference is now made to FIG. 5, which is a simplified block
diagram of a CDMR Memory Array, according to embodiments of the
invention. It is noted that the invention is not limited to a
particular type of memory cell, or memory array size, architecture
and/or structure. The CDMR memory array may be implemented in any
size or architecture which incorporates CDMR memory cells as
described herein. The analysis and results presented below are for
a CDMR Memory Array comprising a 64.times.32 array of 4T GC-eDRAM
CDMR memory cells.
[0186] Optionally, in order to enable recovery of the correct level
from a flipped cell at least one parity column is integrated to the
CDMR memory array. These parity cells hold the parity bit of the
corresponding word. For the 4T GC-eDRAM CDMR memory cell, the
correct data may be recovered from an error detected cell using
simple comparison logic. In general, any number of errors may be
recovered from the accessed row depending on the number of parity
columns. Every parity bit enables the recovery of an additional
error, compromising area overhead due to additional parity
bitcells. These parity cells are optionally 4T CDMR memory
cells.
[0187] For proof of concept, the results presented below used a
single parity bit in every row consisting of 32 bits, corresponding
to a single error recovery per row, resulting in an area overhead
of less than 3%.
A. Single-Ended and Differential Readout Schemes
[0188] One of the drawbacks of conventional GC-eDRAM arrays is
their relatively slow read access time due to a single ended
readout scheme.
[0189] In contrast, embodiments of the 4T CDMR memory cell produce
both BL and BLB signals, corresponding to the two opposite level
stored in the cell. Therefore, a differential readout scheme may be
employed, resulting in a faster access time and reliability. To
illustrate this, the read access time of a single ended and
differential readout schemes was post-layout simulated and
compared.
[0190] For the comparisons presented below, a conventional latching
sense amplifier was used for the differential readout mode, while a
simple inverter was used for the single-ended readout mode. Only
minimal sized regular V.sub.T transistors were used. The
differential sense amplifier circuit and single-ended readout with
error detection circuits are shown in FIGS. 6A and 6B
respectively.
[0191] FIGS. 6C and 6D are histograms showing the read access times
of single-ended readout mode and differential readout mode
respectively. The read access times were extracted from 1K
Monte-Carlo simulations modeling both global and local variations
(mismatch) under a 700 mV supply voltage. As seen in FIGS. 6C-6D
the differential sense amplifier has a faster access time. Both
readout schemes may also be used independently without affecting
the RBL level, due to the high input impedance of both sense
circuits. While the differential readout provides better
performance, the two single ended sense inverters may be used to
produce delayed results, indicating whether an error has
occurred.
VI. Comparison Results
[0192] In order to demonstrate the advantages of the 4T GC-eDRAM
CDMR memory cell over conventional 6T SRAM and other error tolerant
solutions, section VI presents CDMR memory cell layout and error
tolerance comparisons.
A. Layout Comparison
[0193] One of the most important factors in memory design is a
small bitcell area, in order to be able to integrate as much memory
as possible with a small area cost. As a result, conventional SRAM
memories are usually implemented in dense design rules, trading off
stability and soft error tolerance. Therefore, one of the main
goals in the design bitcells is to maintain a small area penalty,
while still maintaining a soft error tolerance.
[0194] The layout of a 65 nm 4T CDMR memory cell, implemented with
standard-VT PMOS transistors, comprises an area of 1.01
.mu.m.sup.2. The CDMR memory cell is 47% smaller than the standard
non-SEU tolerant memory circuit, and between 2.5.times.-5.times.
smaller than the other considered bitcells (see Table 1 below).
[0195] In an exemplary embodiment of the 4T GC-eDRAM CDMR memory
array, the parity bits are stored in 4T GC-eDRAM CDMR memory cells
and therefore they consume less than 3% of the total array size.
Use of a single parity cell enables the error correction of one bit
per row. Additional parity cells may enhance the error correction
capabilities, therefore presenting a trade off with the resulting
array size as described below. The extra periphery needed for error
correction is implemented using an additional AND gate per every
two columns and standard error correction circuitry, used in
conventional ECCs.
B. Error Detection and Correction
[0196] State-of-the-art circuit level solutions, such as DICE,
Quatro 10T and SHIELD, are mainly targeted at high-radiation
environments such as space, where memories are likely to encounter
SEUs caused by alpha particle strikes. While these memories are
more immune to SEUs, they do not detect any number of errors in
case an SEU has occurred. Moreover, errors caused by process,
voltage, or temperature (PVT) variations cannot be detected or
corrected. In order to be able to detect errors, ECC must be
integrated into the memory array as well, requiring even more area
and complexity to the already modified memory. Nonetheless, ECCs
can only detect a limited number of errors based on the used ECC
scheme, as described in section II-B.
[0197] In contrast, the CDMR memory array presented herein may
detect all the errors of an accessed row, independent of the number
of bits per row and without the need for extra hardware. This may
be done using the dual single-ended readout structure, indicating
an error has occurred if both outputs are `1`, as described in
section III-D. The error correction capability depends on the
amount of extra bitcells holding the parity bits of the row. For
example, the addition of two parity cells provides a capability of
correcting up to two errors per row, similar to single error
correction-double error detection (SECDED) and at a much smaller
area overhead.
V. Simulation Results
A. Data Retention Time Analysis
[0198] The data retention time (DRT) of GC-eDRAMs is a dominant
factor in the memory design, affecting both the power consumption
and the availability of the memory array. It is primarily limited
by the level set by the initial charge stored in the bitcell and
the leakage currents that degrade this level. After write, the
stored data starts deteriorating due to leakage currents from the
storage node, and therefore it requires periodic refresh cycles.
Depending on the type of write transistor (WT), one of the data
levels has a much higher retention time than the other (`1` for a
PMOS WT, `0` for a NMOS WT). However, when determining the refresh
frequency, one must consider the deterioration of the weaker data
level under worst-case conditions, i.e. when the write bitline
(WBL) is driven to the opposite level of the stored data during
retention periods.
[0199] The exemplary 4T all-PMOS CDMR memory cell presented herein,
displays asymmetric retention characteristics with highly
advantageous retention of data `1` over data `0`. This is
illustrated in FIG. 7, which shows the storage node degradation
following a write operation under worst case WBL bias condition.
The plot was extracted from 1K Monte-Carlo simulations modeling
both process variations and mismatch. The result of the above
phenomenon indicate that a read failure can only occur due to a
deteriorated `0` level in the cell. The DRT of the 4T cell was
determined as the time after write when the voltage difference
between the degraded `1` and `0` levels deteriorates to 200 mV. The
resulting DRT distribution is given in FIG. 8, with a worst case
DRT of 50 us.
B. Static Power Consumption
[0200] The static power of memory arrays is often considered the
most important aspect of chip power consumption, due to the large
number of bitcells in a standby state at any given time. Whereas
leakage is the dominant static power component of a standard SRAM,
when considering a dynamic memory such as the CDMR memory cell, the
static power comprises both the leakage and the refresh power of
the array, and in most cases, the refresh power is the dominant
factor. Since the refresh power is a function of the data retention
time (DRT), extraction of the DRT is essential for static power
estimation.
[0201] The standby power of a GC-eDRAM comprises the leakage power
of the array and the dynamic refresh energy, consumed during every
refresh period. This total standby power is often referred to as
the retention power of the array. For correct power analysis, the
refresh period for the simulation was chosen to be 50 .mu.s, and
the reciprocal of this value was used as the refresh rate in
calculation of the refresh power.
[0202] FIG. 9 compares the retention power of the exemplary 4T
GC-eDRAM CDMR memory cell with the static power consumption of a
conventional 6T SRAM cell and other circuit level SEU hardened
bitcells. The refresh power constituted 40% to 60% of the total
power consumption of the 4T GC-eDRAM CDMR memory cell, depending on
the supply voltage. Simulations were made under worst-case biasing
during retention with WBL and WBLB kept at the opposite voltage
levels to those stored at SN and SNB, resulting in the highest
leakage currents. Nevertheless, the 4T GC-eDRAM CDMR memory cell
clearly has the lowest standby power consumption across the entire
range of simulated supply voltages. This is a reduction of 59%-87%
at nominal conditions (1.2 V) and 48% lower than the SHIELD
solution at 0.4V, which is the only other functional solution at
such a scaled operating voltage.
C. Refresh Power Reduction Using Error Correcting Scheme
[0203] The error correcting nature of embodiments of the GC-eDRAM
CDMR memory cell array relies on the fact that only data `0` is
subject to errors. This is due to several factors. Since a particle
strike may only cause a positive voltage shift on the storage nodes
of the cell, SEU can only affect data `0`, causing a readout
failure. Furthermore, as discussed in section VI-A, data `0` is the
weaker level in terms of retention time characteristics, making it
susceptible to errors due to data deterioration resulting from
leakage currents. As a result, the power consuming refresh cycles
rate is set by the DRT of data `0`.
[0204] This phenomenon indicates that using the error correcting
scheme of the memory array and lowering the refresh rate, allowing
a number of possible errors which may be corrected, may result in
substantial power savings. As previously discussed, the number of
allowable errors is set by the number of parity bits per row,
corresponding to the error correcting capability of the memory
array. FIG. 10A shows the refresh rate as a function of the parity
bits per row, indicating that a single parity bit may reduce the
refresh rate by almost two times, while extending the number of
parity bits to 4 results in a 2.5 times reduction in the refresh
rate. This results in substantial power reduction, illustrated in
FIG. 10B, where the power consumption per cycle for a 2 Kb array is
reduced by almost 3 times using 4 parity bits.
D. Critical Charge
[0205] The critical charge is a commonly used design metric in
determining the tolerance level of a cell to SEU, occurring due to
a particle strike at a cell's internal node. While the CDMR memory
array error detecting and correcting schemes enable the recovery of
an error due to a SEU, for fair comparison to other bitcell
solutions, this section will analyze the 4T GC-eDRAM CDMR memory
cell critical charge and compare it to other SEU hardened bitcells.
In order to mimic the event of a particle strike, SEUs are modeled
by injecting the current pulse at the sensitive nodes. The current
pulse has fast rise time and gradual fall time. The shape of the
current pulse is approximated by:
I ( t ) = Q coll t f - t r ( e - t t f - e - t t r ) , ( 1 )
##EQU00001##
where Q is the charge collected due to particle strike, t.sub.r is
the rise time and t.sub.f is the fall time. The sensitivity of a
device described by the minimum charge needed to upset the
function. This minimum charge is called the critical charge
(Q.sub.crit). The simplest approach is to consider the critical
charge as the product of the total capacity C.sub.i at a given node
by the power supply voltage V.sub.DD, therefore,
Q.sub.crit=C.sub.i.times.V.sub.DD. This approach is very useful to
obtain a rough estimation of the critical charge. A more precise
approach to obtain the critical charge is to use a circuit
simulator and to describe the collected charge by a double
exponential current generator of short duration applied at the
sensitive node. The total charge deposited by a particle strike may
be calculated by numerically integrating the transient current
pulse, and Q.sub.crit is defined as the minimum charge deposited in
a sensitive node that results in a memory bit-flip.
[0206] In the case of the 4T GC-eDRAM bitcell, a bit flip may only
be determined at the point where a read operation fails, similarly
to the calculation of the retention time of the cell. Moreover, the
critical charge varies with time due to the deterioration of the
stored voltage in the cell, specifically for data `0`, which is
susceptible to SEU. Simulation of a particle strike with the SEU
model of (1) is the most popular technique for evaluation of the
rad-hardening ability of a memory bitcell. For the 4T GC-eDRAM CDMR
memory cell, the critical charge was simulated in this method at
different times after a write operation, and determined at the
point where a readout failure was detected following the injected
current pulse. The results are shown in FIG. 11 for a under
GC-eDRAM CDMR memory cell worst-case retention time conditions. As
expected, the critical charge has the highest value following a
write `0` operation and it degrades as time passes due to a
deteriorated `0` level as a result of leakage. After 50 us the
critical charge is equal to 0 since the retention time has passed
and any particle strike may cause a readout error. While these
values are significantly smaller than those presented by other
circuit level solutions, the error-correction and detection
capabilities of the cell make them sufficient for high-radiation
operation.
[0207] Table I summarizes the comparison between the 4T CDMR memory
and other considered solutions. The table clearly emphasizes the
benefits of the proposed solution, achieving much lower static
power and area consumption compared to other memory options and
including inherent error detection capability and a low overhead
error correction capability.
TABLE-US-00001 TABLE 1 Comparison of Memory Solutions for Space
Applications Memory type 6T SRAM 12T DICE Quatro 10T SHIELD 4T CDMR
memory Cell size 451 f.sup.2 861 f.sup.2 1159 f.sup.2 947 f.sup.2
240 f.sup.2 Cell static power 54.9 pW 58.3 pW 110.6 pW 35.7 pW 14.7
pW @ 1.2 V Protection -- Increased Increased Increased CDMR
mechanism C.sub.crit C.sub.crit C.sub.crit Error detection requires
parity or ECC for each detection inherent per-bit detection Error
correction requires ECC (e.g., 7 bits for 1 error in 32-bit word)
1-bit parity per error
[0208] In summary, some embodiments of the invention described
herein provide error tolerant CDMR memory cells and CDMR memory
arrays, optionally based on GC-eDRAM transistors. Both circuit and
architectural techniques may be used to provide a soft error
tolerant memory. Embodiments of a CDMR memory array formed from
CDMR memory cells are fully compatible with low voltage operation,
consume less area than any other soft-error tolerant solution and
are capable of detecting any number of errors during a readout
operation. Furthermore, multi-bit error correction may be done with
only a modest increase in the area overhead. In addition, the CDMR
memory array is compatible with differential readout schemes,
resulting in a better performance and reliability than conventional
GC eDRAM arrays.
[0209] It is expected that during the life of a patent maturing
from this application many relevant transistors, types of
transistors, bitcells, memory arrays, memory array architectures,
error detection techniques and error correction techniques will be
developed and the scope of the terms transistor, transistor type,
bitcell, memory array, memory array architecture, error detection
and error correction are intended to include all such new
technologies a priori.
[0210] The terms "comprises", "comprising", "includes",
"including", "having" and their conjugates mean "including but not
limited to".
[0211] The term "consisting of" means "including and limited
to".
[0212] The term "consisting essentially of" means that the
composition, method or structure may include additional
ingredients, steps and/or parts, but only if the additional
ingredients, steps and/or parts do not materially alter the basic
and novel characteristics of the claimed composition, method or
structure.
[0213] As used herein, the singular form "a", "an" and "the"
include plural references unless the context clearly dictates
otherwise. For example, the term "a compound" or "at least one
compound" may include a plurality of compounds, including mixtures
thereof.
[0214] Throughout this application, various embodiments of this
invention may be presented in a range format. It should be
understood that the description in range format is merely for
convenience and brevity and should not be construed as an
inflexible limitation on the scope of the invention. Accordingly,
the description of a range should be considered to have
specifically disclosed all the possible subranges as well as
individual numerical values within that range. For example,
description of a range such as from 1 to 6 should be considered to
have specifically disclosed subranges such as from 1 to 3, from 1
to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as
well as individual numbers within that range, for example, 1, 2, 3,
4, 5, and 6. This applies regardless of the breadth of the
range.
[0215] Whenever a numerical range is indicated herein, it is meant
to include any cited numeral (fractional or integral) within the
indicated range. The phrases "ranging/ranges between" a first
indicate number and a second indicate number and "ranging/ranges
from" a first indicate number "to" a second indicate number are
used herein interchangeably and are meant to include the first and
second indicated numbers and all the fractional and integral
numerals therebetween.
[0216] It is appreciated that certain features of the invention,
which are, for clarity, described in the context of separate
embodiments, may also be provided in combination in a single
embodiment. Conversely, various features of the invention, which
are, for brevity, described in the context of a single embodiment,
may also be provided separately or in any suitable subcombination
or as suitable in any other described embodiment of the invention.
Certain features described in the context of various embodiments
are not to be considered essential features of those embodiments,
unless the embodiment is inoperative without those elements.
[0217] Although the invention has been described in conjunction
with specific embodiments thereof, it is evident that many
alternatives, modifications and variations will be apparent to
those skilled in the art. Accordingly, it is intended to embrace
all such alternatives, modifications and variations that fall
within the spirit and broad scope of the appended claims.
[0218] All publications, patents and patent applications mentioned
in this specification are herein incorporated in their entirety by
reference into the specification, to the same extent as if each
individual publication, patent or patent application was
specifically and individually indicated to be incorporated herein
by reference. In addition, citation or identification of any
reference in this application shall not be construed as an
admission that such reference is available as prior art to the
present invention. To the extent that section headings are used,
they should not be construed as necessarily limiting.
* * * * *