U.S. patent application number 16/419947 was filed with the patent office on 2019-09-19 for semiconductor memory device.
The applicant listed for this patent is SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Augustin HONG, Yoosang HWANG, Sungho JANG, Kiwook JUNG, Bong-Soo KIM, Dongoh KIM, Keunnam KIM, Hoin LEE, Kiseok LEE, Jemin PARK, Chan-Sic YOON.
Application Number | 20190287977 16/419947 |
Document ID | / |
Family ID | 62243489 |
Filed Date | 2019-09-19 |
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United States Patent
Application |
20190287977 |
Kind Code |
A1 |
LEE; Kiseok ; et
al. |
September 19, 2019 |
SEMICONDUCTOR MEMORY DEVICE
Abstract
A method of manufacturing a semiconductor memory device and a
semiconductor memory device, the method including providing a
substrate that includes a cell array region and a peripheral
circuit region; forming a mask pattern that covers the cell array
region and exposes the peripheral circuit region; growing a
semiconductor layer on the peripheral circuit region exposed by the
mask pattern such that the semiconductor layer has a different
lattice constant from the substrate; forming a buffer layer that
covers the cell array region and exposes the semiconductor layer;
forming a conductive layer that covers the buffer layer and the
semiconductor layer; and patterning the conductive layer to form
conductive lines on the cell array region and to form a gate
electrode on the peripheral circuit region.
Inventors: |
LEE; Kiseok; (Hwaseong-si,
KR) ; YOON; Chan-Sic; (Anyang-si, KR) ; HONG;
Augustin; (Seoul, KR) ; KIM; Keunnam;
(Yongin-si, KR) ; KIM; Dongoh; (Daegu, KR)
; KIM; Bong-Soo; (Yongin-si, KR) ; PARK;
Jemin; (Suwon-si, KR) ; LEE; Hoin; (Suwon-si,
KR) ; JANG; Sungho; (Seoul, KR) ; JUNG;
Kiwook; (Seoul, KR) ; HWANG; Yoosang;
(Suwon-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRONICS CO., LTD. |
Suwon-si |
|
KR |
|
|
Family ID: |
62243489 |
Appl. No.: |
16/419947 |
Filed: |
May 22, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15653198 |
Jul 18, 2017 |
10332890 |
|
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16419947 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/10897 20130101;
H01L 27/228 20130101; H01L 27/10894 20130101; H01L 27/2436
20130101; H01L 27/10844 20130101; H01L 27/10876 20130101; H01L
27/10823 20130101 |
International
Class: |
H01L 27/108 20060101
H01L027/108 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 2, 2016 |
KR |
10-2016-0163757 |
Claims
1.-24. (canceled)
25. A semiconductor memory device, comprising: a substrate that
includes active regions defined by a device isolation layer; word
line structures filling trenches formed in an upper portion of the
substrate, the word line structures intersecting the active regions
to divide the active regions into first dopant regions and second
dopant regions; bit lines intersecting the word line structures,
the bit lines being connected to the first dopant regions; and data
storage parts connected to the second dopant regions, wherein each
of the word line structures includes a word line, a capping
pattern, and a remaining pattern, which are sequentially stacked in
each of the trenches.
26. The semiconductor memory device as claimed in claim 25, wherein
the remaining pattern extends along a top surface of the word
line.
27. The semiconductor memory device as claimed in claim 25, further
comprising a buffer pattern between the substrate and the bit
lines, wherein a top surface of the remaining pattern is in contact
with a bottom surface of the buffer pattern.
28. The semiconductor memory device as claimed in claim 27, further
comprising first contacts connecting the bit lines to the first
dopant regions, wherein the first contacts penetrate the buffer
pattern so as to be connected to the remaining pattern.
29. The semiconductor memory device as claimed in claim 28, wherein
each of bottom surfaces of the first contacts is higher than a top
surface of the capping pattern.
30. The semiconductor memory device as claimed in claim 28, wherein
each of bottom surfaces of the first contacts is lower than a
bottom surface of the remaining pattern.
31. The semiconductor memory device as claimed in claim 27, further
comprising an interlayer insulating layer covering side surfaces of
the bit lines, wherein the interlayer insulating layer penetrates
the buffer pattern so as to be connected to the device isolation
layer.
32. The semiconductor memory device as claimed in claim 27, wherein
the buffer pattern comprises a first buffer pattern and a second
buffer pattern, the first buffer pattern and the second buffer
pattern are formed of different materials.
33. The semiconductor memory device as claimed in claim 25, wherein
the remaining pattern comprises a stepwise structure including a
side surface and a bottom surface.
34. The semiconductor memory device as claimed in claim 33, further
comprising a first contact connecting each of the bit lines to the
first dopant regions, wherein the bottom surface of the stepwise
structure contacts a bottom surface of the first contact.
35. The semiconductor memory device as claimed in claim 25, wherein
a width of the remaining pattern decreases from a top surface of
the remaining pattern to a bottom surface of the remaining
pattern.
36. The semiconductor memory device as claimed in claim 25, wherein
a side surface of the remaining pattern aligns with a side surface
of the capping pattern.
37. The semiconductor memory device as claimed in claim 25, wherein
a bottom surface of the remaining pattern is higher than bottom
surfaces of the first dopant regions.
38. A semiconductor memory device, comprising: a substrate that
includes active regions defined by a device isolation layer; a word
line structure filling a trench formed in an upper portion of the
substrate, the word line structure intersecting the active regions
to divide the active regions into a first dopant region and a
second dopant region; a bit line intersecting the word line
structure, the bit line being connected to the first dopant region;
a buffer pattern between the substrate and the bit lines; and a
first contact connecting the bit line to the first dopant region,
wherein the word line structure includes a word line, a capping
pattern, and a remaining pattern, which are sequentially stacked in
the trench, and the first contacts penetrate the buffer pattern so
as to be connected to the remaining pattern.
39. The semiconductor memory device as claimed in claim 38, wherein
a bottom surface of the first contact is higher than a top surface
of the capping pattern.
40. The semiconductor memory device as claimed in claim 38, wherein
the remaining pattern comprises a stepwise structure including a
side surface and a bottom surface, the bottom surface of the
stepwise structure contacts a bottom surface of the first
contact.
41. The semiconductor memory device as claimed in claim 38, wherein
the remaining pattern extends along a top surface of the word
line.
42. A semiconductor memory device, comprising: a substrate that
includes active regions defined by a device isolation layer; word
line structures filling trenches formed in an upper portion of the
substrate, the word line structures intersecting the active regions
to divide the active regions into first dopant regions and second
dopant regions; bit lines intersecting the word line structures,
the bit lines being connected to the first dopant regions; a first
contact connecting the bit line to the first dopant region; and
data storage parts connected to the second dopant regions, wherein
each of the word line structures includes a word line, a capping
pattern, and a remaining pattern, which are sequentially stacked in
each of the trenches, and the remaining pattern comprises a
stepwise structure connected to a bottom portion of the first
contact.
43. The semiconductor memory device as claimed in claim 42, wherein
the remaining pattern extends along a top surface of the word
line.
44. The semiconductor memory device as claimed in claim 42, wherein
a bottom surface of the first contact is higher than a top surface
of the capping pattern.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation application based on pending
application Ser. No. 15/653,198, filed Jul. 18, 2017, the entire
contents of which is hereby incorporated by reference.
[0002] Korean Patent Application No. 10-2016-0163757, filed on Dec.
2, 2016, in the Korean Intellectual Property Office, and entitled:
"Semiconductor Memory Device and Method of Manufacturing the Same,"
is incorporated by reference herein in its entirety.
BACKGROUND
1. Field
[0003] Embodiments relate to a semiconductor memory device and a
method of manufacturing the same.
2. Description of the Related Art
[0004] Semiconductor devices are widely used in an electronic
industry because of their small sizes, multi-functional
characteristics, and/or low manufacture costs. Semiconductor
devices have been highly integrated with the development of the
electronic industry. Widths of patterns included in semiconductor
devices have been reduced to help increase the integration density
of semiconductor devices.
SUMMARY
[0005] The embodiments may be realized by providing a method of
manufacturing a semiconductor memory device, the method including
providing a substrate that includes a cell array region and a
peripheral circuit region; forming a mask pattern that covers the
cell array region and exposes the peripheral circuit region;
growing a semiconductor layer on the peripheral circuit region
exposed by the mask pattern such that the semiconductor layer has a
different lattice constant from the substrate; forming a buffer
layer that covers the cell array region and exposes the
semiconductor layer; forming a conductive layer that covers the
buffer layer and the semiconductor layer; and patterning the
conductive layer to form conductive lines on the cell array region
and to form a gate electrode on the peripheral circuit region.
[0006] The embodiments may be realized by providing a semiconductor
memory device including a substrate that includes active regions
defined by a device isolation layer; word line structures filling
trenches formed in an upper portion of the substrate, the word line
structures intersecting the active regions to divide the active
regions into first dopant regions and second dopant regions; bit
lines intersecting the word line structures, the bit lines being
connected to the first dopant regions; and data storage parts
connected to the second dopant regions, wherein each of the word
line structures includes a word line, a capping pattern, and a
remaining pattern, which are sequentially stacked in each of the
trenches.
[0007] The embodiments may be realized by providing a method of
manufacturing a semiconductor memory device, the method including
providing a substrate such that the substrate includes a cell array
region and a peripheral circuit region such that the substrate
includes a trench in the cell array region; forming a capping
pattern in the trench such that the capping pattern extends to an
opening of the trench; removing a portion of the capping pattern at
the opening of the trench such that a recess region is formed at
the opening of the trench; forming a mask pattern that covers the
cell array region and exposes the peripheral circuit region such
that the mask pattern is in the recess region at the opening of the
trench; growing a semiconductor layer on the peripheral circuit
region such that the semiconductor layer has a different lattice
constant from the substrate; removing portions of the mask pattern
such that a remaining pattern of the mask pattern remains in the
trench adjacent to the opening of the trench; forming a buffer
layer that covers the cell array region and exposes the
semiconductor layer; forming conductive lines on the cell array
region and a gate electrode on the peripheral circuit region.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Features will be apparent to those of skill in the art by
describing in detail exemplary embodiments with reference to the
attached drawings in which:
[0009] FIG. 1 illustrates a plan view of a semiconductor memory
device according to some embodiments.
[0010] FIG. 2 illustrates an enlarged view of a cell array region
illustrated in FIG. 1.
[0011] FIGS. 3A to 11A illustrate cross-sectional views taken along
a line A-A' of FIG. 2 to show stages in a method of manufacturing a
semiconductor memory device, according to some embodiments.
[0012] FIGS. 3B to 11B illustrate cross-sectional views taken along
lines B-B' and C-C' of FIG. 1 to show stages in a method of
manufacturing a semiconductor memory device, according to some
embodiments.
[0013] FIGS. 3C to 11C illustrate cross-sectional views taken along
lines D-D' and E-E' of FIG. 1 to show stages in a method of
manufacturing a semiconductor memory device, according to some
embodiments.
[0014] FIG. 11D illustrates a cross-sectional view taken along a
line F-F' of FIG. 2.
[0015] FIG. 12A illustrates an enlarged view of a region `Q` of
FIG. 11A according to some embodiments.
[0016] FIG. 12B illustrates an enlarged view of a comparative
example corresponding to the region `Q` of FIG. 11A.
[0017] FIGS. 13A and 13B illustrate cross-sectional views taken
along the lines A-A' and F-F' of FIG. 2 of a semiconductor memory
device according to some embodiments.
DETAILED DESCRIPTION
[0018] FIG. 1 illustrates a plan view of a semiconductor memory
device according to some embodiments. FIG. 2 illustrates an
enlarged view of a cell array region CAR illustrated in FIG. 1.
FIGS. 3A to 11A, 3B to 11B, and 3C to 11C illustrate
cross-sectional views taken along a line A-A' of FIG. 2 and B-B',
C-C', D-D', and E-E' of FIG. 1 to show stages in a method of
manufacturing a semiconductor memory device, according to some
embodiments. FIG. 11D illustrates a cross-sectional view taken
along a line F-F' of FIG. 2.
[0019] Referring to FIGS. 1, 2, and 3A to 3C, a substrate 100
including a cell array region CAR and a peripheral circuit region
PCR may be provided. The cell array region CAR may be a region on
which memory cells are disposed. The peripheral circuit region PCR
may be a region on which, e.g., a word line driver, a sense
amplifier, row and column decoders, and control circuits are
disposed. The peripheral circuit region PCR may include an NMOSFET
region NR and a PMOSFET region PR. The NMOSFET region NR may
include a first region PCR1 and a second region PCR2. The PMOSFET
region PR may include a third region PCR3 and a fourth region PCR4.
The first and third regions PCR1 and PCR3 may be regions on which
high-voltage transistors are formed. The second and fourth regions
PCR2 and PCR4 may be regions on which low-voltage transistors are
formed.
[0020] Device isolation layers 101 may be formed in the substrate
100 to define active regions AR in the cell array region CAR. In an
implementation, the substrate 100 may be a silicon substrate. The
active regions AR may have bar shapes laterally separated from each
other, and each of the active regions AR may extend in a third
direction (hereinafter, referred to as `a D3 direction`)
non-perpendicular to a first direction (hereinafter, referred to as
`a D1 direction`) and a second direction (hereinafter, referred to
as `a D2 direction`). The D1 direction and the D2 direction may
intersect each other and may be parallel to a top surface of the
substrate 100.
[0021] A dopant region (see 21 and 22 of FIGS. 2 and 11D) may be
formed in an upper portion (e.g., one end or side) of each of the
active regions AR. The dopant region may be formed by implanting
dopant ions, which have a different conductivity type from the
substrate 100, into an upper portion (e.g., one surface or side) of
the substrate 100. In an implementation, a depth of the dopant
region may be smaller than depths of the device isolation layers
101 (e.g., from the one surface or side of the substrate 100). The
dopant region may be formed after or before the formation of the
device isolation layers 101. In an implementation, the dopant
region may be formed in a subsequent process rather than the
present process. The dopant region may be confinedly formed in the
cell array region CAR, e.g., only in the cell array region CAR. For
example, the peripheral circuit region PCR may be covered with a
mask layer when the dopant region is formed, and the dopant region
may not be formed in the peripheral circuit region PCR.
[0022] Trenches 11 may be formed in an upper portion (e.g., the one
surface or side) of the substrate 100 of the cell array region CAR.
The trenches 11 may extend in the D1 direction and may be spaced
apart from each other in the D2 direction, and the dopant region
may be divided into first and second dopant regions 21 and 22 by
the trenches 11. For example, the first dopant region 21 may be
between a pair of the second dopant regions 22 in one active region
AR, and the first dopant region 21 and the second dopant regions 22
may be separated from each other by the trenches 11 in the one
active region AR.
[0023] In an implementation, a first mask pattern MP may be formed
on the top surface (e.g., the one surface or side) of the substrate
100, and the trenches 11 may be formed by dry and/or wet etching
process using the first mask pattern MP as an etch mask. The first
mask pattern MP may cover the peripheral circuit region PCR, and
the etching process may not be performed on the peripheral circuit
region PCR. In an implementation, the first mask pattern MP may
include, e.g., at least one of a silicon oxide layer, a silicon
nitride layer, or a silicon oxynitride layer. Depths of the
trenches 11 may be smaller than the depths of the device isolation
layers 101.
[0024] Cell gate insulating patterns 126, cell gate conductive
patterns 121, and capping patterns 129 may be sequentially formed
on the resultant structure having the trenches 11. In an
implementation, the cell gate conductive patterns 121 may be word
lines WL. In an implementation, a cell gate insulating layer and a
cell gate conductive layer may be formed in the trenches 11, and
then, the cell gate insulating layer and the cell gate conductive
layer may be etched to form the cell gate insulating patterns 126
and the cell gate conductive patterns 121 in lower regions of the
trenches 11. The capping patterns 129 may be formed on the cell
gate conductive patterns 121. An insulating layer may fill residual
regions or remaining portions of the trenches 11 (e.g., in which
the cell gate conductive patterns 121 have already formed), and
then, an etch-back process may be performed on the insulating layer
to form the capping patterns 129 (e.g., filling an upper portion
near an opening of the trench).
[0025] For example, the cell gate insulating patterns 126 may
include at least one of a silicon oxide layer, a silicon nitride
layer, or a silicon oxynitride layer. The cell gate conductive
patterns 121 may include at least one of a doped semiconductor
material, a conductive metal nitride, a metal, or a
metal-semiconductor compound (e.g., a metal silicide). The capping
pattern 129 may include at least one of a silicon nitride layer, a
silicon oxide layer, or a silicon oxynitride layer. Each of the
cell gate insulating patterns 126, the cell gate conductive
patterns 121, and the capping patterns 129 may be formed using at
least one of a chemical vapor deposition (CVD) process, a physical
vapor deposition (PVD) process, or an atomic layer deposition (ALD)
process.
[0026] Referring to FIGS. 1, 2, and 4A to 4C, the first mask
pattern MP may be removed. The first mask pattern MP may be removed
by a wet etching process. During the removal process of the first
mask pattern MP, upper portions of the capping patterns 129 may
also be etched to form recess regions RS on or overlying the cell
gate conductive patterns 121. The recess regions RS may extend in
the D1 direction along the trenches 11 and may be spaced apart from
each other in the D2 direction. Depths of the recess regions RS may
be about 10% to about 40% of the depth of the trench 11.
[0027] Referring to FIGS. 1, 2, and 5A to 5C, a mask layer 130 may
be formed to cover an entire region of the substrate 100, and then,
a photoresist pattern 135 may be formed to cover the cell array
region CAR. The photoresist pattern 135 may cover a portion of the
peripheral circuit region PCR. In an implementation, the
photoresist pattern 135 may cover the NMOSFET region NR (e.g., the
first and second regions PCR1 and PCR2) of the peripheral circuit
region PCR and may expose the PMOSFET region PR (e.g., the third
and fourth regions PCR3 and PCR4) of the peripheral circuit region
PCR. The mask layer 130 may fill the recess regions RS. In an
implementation, the mask layer 130 may include a silicon oxide
layer. The mask layer 130 may completely fill the recess regions RS
and may extend onto the top or upper surface of the substrate 100
between the recess regions RS.
[0028] Referring to FIGS. 1, 2, and 6A to 6C, the mask layer 130
may be patterned using the photoresist pattern 135 as an etch mask
to form a second mask pattern 131. The second mask pattern 131 may
cover the cell array region CAR and the NMOSFET region NR and may
expose the PMOSFET region PR. During the patterning process, an
upper portion of the PMOSFET region PR may also be etched and
removed. As a result, a top or upper surface of the PMOSFET region
PR may be lower than top or upper surfaces of the cell array region
CAR and the NMOSFET region NR. In an implementation, the upper
portion of the PMOSFET region PR may not be removed.
[0029] A semiconductor layer SP may be formed on the substrate 100
of the exposed PMOSFET region PR. The semiconductor layer SP may be
formed by a selective epitaxial growth (SEG) process. The cell
array region CAR and the NMOSFET region PR may be covered by the
second mask pattern 131, and the semiconductor layer SP may not be
formed thereon. The semiconductor layer SP may include a
semiconductor material of which a carrier mobility is higher than
that of silicon. For example, the semiconductor layer SP may be a
silicon-germanium layer of which a lattice constant is different
from that of the substrate 100. In an implementation, the
semiconductor layer SP may have a thickness of about 80 .ANG. to
about 120 .ANG..
[0030] Referring to FIGS. 1, 2, and 7A to 7C, the second mask
pattern 131 may be removed from the cell array region CAR and the
NMOSFET region NR. Portions of the second mask pattern 131 may
remain in the recess regions RS, and remaining patterns 132 may be
formed in the recess regions RS. A buffer pattern BP may be formed
to cover the cell array region CAR and to expose the peripheral
circuit region PCR. A bottom (e.g., substrate-facing) surface of
the buffer pattern BP may be in contact with a top or upper surface
of the remaining pattern 132. In an implementation, the buffer
pattern BP may include a first buffer pattern 137 and a second
buffer pattern 138 on the first buffer pattern 137. The first
buffer pattern 137 and the second buffer pattern 138 may be formed
of different materials. For example, the first buffer pattern 137
may be a silicon oxide layer, and the second buffer pattern 138 may
be a silicon nitride layer. In an implementation, a silicon oxide
layer and a silicon nitride layer may be sequentially formed on an
entire surface of the substrate 100, and a patterning process may
be performed on the silicon nitride layer and the silicon oxide
layer by using a photoresist pattern covering the cell array region
CAR and exposing the peripheral circuit region PCR, thereby forming
the buffer pattern BP. In an implementation, an additional silicon
oxide layer may be provided between the second buffer pattern 138
and the photoresist pattern.
[0031] Referring to FIGS. 1, 2, and 8A to 8C, a first gate
insulating layer 31 may be formed on the first and third regions
PCR1 and PCR3 corresponding to the high-voltage transistor regions.
Thereafter, a second gate insulating layer 32 may be formed on an
entire surface of the substrate 100. In an implementation, before
the formation of the second gate insulating layer 32, a third gate
insulating layer 30 may be formed on the second and fourth regions
PCR2 and PCR4 corresponding to the low-voltage transistor regions.
The first and second gate insulating layers 31 and 32 may also be
formed on the cell array region CAR.
[0032] A dielectric constant of the first gate insulating layer 31
may be lower than dielectric constants of the second and third gate
insulating layers 32 and 30. In an implementation, the first gate
insulating layer 31 may include a silicon oxide layer and/or a
silicon oxynitride layer. The first gate insulating layer 31 may be
thicker than the second and third gate insulating layers 30 and 32.
The second gate insulating layer 32 may be a high-k dielectric
layer of which a dielectric constant is higher than that of a
silicon oxide layer. The dielectric constant of the second gate
insulating layer 32 may be higher than the dielectric constants of
the first and third gate insulating layers 31 and 30. In an
implementation, the second gate insulating layer 32 may include an
oxide, nitride, silicide, oxynitride, or silicide-oxynitride that
includes hafnium (Hf), aluminum (Al), zirconium (Zr), or lanthanum
(La). Each of the first and second gate insulating layers 31 and 32
may be formed using an ALD process, a CVD process, or a PVD
process. In an implementation, the third gate insulating layer 30
may include a silicon oxide layer or a silicon oxynitride layer. In
an implementation, the third gate insulating layer 30 may be formed
by a thermal oxidation and/or thermal nitrification process
consuming the exposed substrate 100 or the exposed semiconductor
layer SP.
[0033] Referring to FIGS. 1, 2, and 9A to 9C, a first work-function
adjustment layer 33 may be formed on the NMOSFET region NR, and a
second work-function adjustment layer 34 may be formed on the
PMOSFET region PR. The first and second gate insulating layers 31
and 32 on the cell array region CAR may be removed. The first and
second work-function adjustment layers 33 and 34 may help implement
a desired threshold voltage and other performances of each of
transistors. Each of the first and second work-function adjustment
layers 33 and 34 may be a single-layered or multi-layered metal
containing layer having a specific work-function.
[0034] In an implementation, the second work-function adjustment
layer 34 may include TiN, TiN/TaN, Al.sub.2O.sub.3/TiN, Al/TiN,
TiN/Al/TiN, TiN/TiON, Ta/TiN, or TaN/TiN. In an implementation, TiN
of these materials may be replaced with TaN, TaCN, TiCN, CoN, or
CoCN. The second work-function adjustment layer 34 may have a
thickness of 30 .ANG. to 60 .ANG.. The first work-function
adjustment layer 33 may include the same layer as the second
work-function adjustment layer 34 and may further include layers
including La/TiN, Mg/TiN, or Sr/TiN disposed on the same layer. In
an implementation, La may be replaced with LaO or LaON.
[0035] Referring to FIGS. 1, 2, and 10A to 10C, a first conductive
layer 141 may be formed on the cell array region CAR and the
peripheral circuit region PCR. The first conductive layer 141 may
include a doped semiconductor layer. In an implementation, the
first conductive layer 141 may include a poly-silicon layer doped
with P-type dopants. A first contact CT1 may be formed to penetrate
the first conductive layer 141 and the buffer pattern BP. The first
contact CT1 may be connected to the first dopant region 21. The
first contact CT1 may include at least one of a doped semiconductor
material, a conductive metal nitride, or a metal. After the
formation of the first contact CT1, a barrier layer 142 and a
second conductive layer 143 may be sequentially formed on the cell
array region CAR and the peripheral circuit region PCR. The barrier
layer 142 may include at least one of a conductive metal nitride, a
metal-silicon compound, or a metal-silicon nitride. The second
conductive layer 143 may include at least one of a metal, a
conductive metal nitride, or a metal-silicon compound. In an
implementation, the second conductive layer 143 may include at
least one of tungsten (W), titanium (Ti), or tantalum (Ta). Each of
the first conductive layer 141, the barrier layer 142, and the
second conductive layer 143 may be formed using an ALD process or a
PVD process.
[0036] Referring to FIGS. 1, 2, and 11A to 11D, a capping layer 151
may be formed, and then, a patterning process may be performed to
form conductive lines on the cell array region CAR and to form
first to fourth transistors TR1 to TR4 (e.g., gate patterns,
including gate electrodes, of the first to fourth transistors TR1
to TR4) on the peripheral circuit region PCR. In an implementation,
the conductive lines may be bit lines BL. The first conductive
layer 141, the barrier layer 142, and the second conductive layer
143 may be formed into a first conductive pattern 145, a barrier
pattern 146, and a second conductive pattern 147, respectively, by
the patterning process. The patterning process may be performed
using the buffer pattern BP as an etch stop layer. Thereafter,
first source/drain regions 161 may be formed in the NMOSFET region
NR, and second source/drain regions 162 may be formed in the
PMOSFET region PR. In an implementation, the first source/drain
regions 161 may be N-type dopant regions, and the second
source/drain regions 162 may be P-type dopant regions. Spacers 152
may be formed on sidewalls of the bit lines BL and the first to
fourth transistors TR1 to TR4. In an implementation, the spacers
152 may include silicon oxide.
[0037] Contact holes may be formed to expose the second dopant
regions 22, and second contacts CT2 may fill the contact holes. The
second contacts CT2 may include at least one of a metal, a
conductive metal nitride, or a metal-silicon compound. In an
implementation, each of the second contacts CT2 may include a
poly-silicon pattern and a metal pattern that are sequentially
stacked. Data storage structures or parts DS may be formed on the
second contacts CT2. In an implementation, when the semiconductor
memory device of the inventive concepts is a dynamic random access
memory (DRAM) device, the data storage part DS may be a capacitor
including a lower electrode, a dielectric layer, and an upper
electrode. In an implementation, the data storage part DS may
include a phase-change layer, a variable resistance layer, or a
magnetic tunnel junction layer.
[0038] FIG. 12A illustrates an enlarged view of a region `Q` of
FIG. 11A according to some embodiments, and FIG. 12B illustrates an
enlarged view of a comparative example corresponding to the region
`Q` of FIG. 11A. The region `Q` may correspond to a boundary region
of the cell array region CAR and the peripheral circuit region PCR.
End portions of the bit lines BL may be provided in the region `Q`.
The comparative example of FIG. 12B illustrates a resultant
structure in which the buffer pattern BP is formed before the
formation of the semiconductor layer SP. A portion of the first
mask pattern MP may not be completely removed, as shown in the
comparative example of FIG. 12B. Thus, sidewalls of the remaining
parts first mask pattern MP and the first buffer pattern 137
disposed thereon may be excessively recessed in the patterning
process described with reference to FIGS. 11A to 11D, and thus an
undercut region UC may be formed. Therefore, a conductive residue
MS may occur or result in an interlayer insulating layer 157
covering the undercut region UC. The conductive residue MS may
occur by or during a deposition process of a conductive material
for forming a contact or electrode formed after the formation of
the undercut region UC. For example, the conductive residue MS may
include a metal material such as La, Ti, Al, or Hf. The conductive
residue MS may extend along a boundary of the cell array region CAR
and the peripheral circuit region PCR, and thus an electrical short
could be caused between interconnection lines of a semiconductor
memory device.
[0039] Referring to FIG. 12A, according to some embodiments, the
buffer pattern BP may be formed after the formation of the
semiconductor layer SP. Thus, an undercut region and a conductive
residue may not be present, as illustrated in FIG. 12A. To
completely remove the remaining first mask pattern MP, the etching
process may be performed until the recess regions RS are formed, as
described with reference to FIGS. 4A to 4C. If the buffer pattern
BP were to be formed before the formation of the semiconductor
layer SP, like the comparative example, the recess regions RS may
not be completely filled due to the buffer pattern BP having a
relatively thin thickness. In an implementation, the semiconductor
layer SP may be formed after the formation of the recess regions RS
and before the formation of the buffer pattern BP. The recess
regions RS may be filled with the portions of the second mask
pattern 131 for forming the semiconductor layer SP, and the
electrical short between interconnection lines of a semiconductor
memory device of FIG. 12B may be avoided. Thus, reliability of the
semiconductor memory device may be improved.
[0040] The semiconductor memory device according to some
embodiments may include word line structures in the trenches 11
formed in the upper portion of the substrate 100, and each of the
word line structures may include the word line WL, the capping
pattern 129 and the remaining pattern 132, which are sequentially
stacked in each of the trenches 11. The remaining pattern 132 may
extend along the top surface of the word line WL. The word line
structures may intersect the active regions AR to divide the active
regions AR into the first dopant regions 21 and the second dopant
regions 22. The bit lines BL may extend in the D2 direction and may
be connected to the first dopant regions 21 through the first
contacts CT1. The second dopant regions 22 may be connected to the
data storage parts DS through the second contacts CT2. The buffer
pattern BP may be provided between the substrate 100 and the bit
lines BL, and the first contacts CT1 and the second contacts CT2
may penetrate the buffer pattern BP. The first contacts CT1 may
penetrate the buffer pattern BP so as to be connected to the
remaining pattern 132.
[0041] The semiconductor memory device according to some
embodiments may include the first transistor TR1 and the second
transistor TR2 on the NMOSFET region NR and may include the third
transistor TR3 and the fourth transistor TR4 on the PMOSFET region
PR. The third and fourth transistors TR3 and TR4 may use the
semiconductor layer SP including the semiconductor material (e.g.,
silicon-germanium) having a high carrier mobility as channel
regions. Each of the first and third transistors TR1 and TR3
corresponding to the high-voltage transistors may include the first
gate insulating layer 31 and the second gate insulating layer 32,
and each of the second and fourth transistors TR2 and TR4
corresponding to the low-voltage transistors may include the third
gate insulating layer 30 and the second gate insulating layer 32.
Each of the first and second transistors TR1 and TR2 may include
the first work-function adjustment layer 33, and each of the third
and fourth transistors TR3 and TR4 may include the second
work-function adjustment layer 34. Each of the first to fourth
transistors TR1 to TR4 may include the first conductive pattern
145, the barrier pattern 146, the second conductive pattern 147,
and the capping layer 151.
[0042] FIGS. 13A and 13B illustrate cross-sectional views taken
along the lines A-A' and F-F' of FIG. 2 to show a semiconductor
memory device according to some embodiments. Hereinafter, repeated
descriptions to the same elements as in the above embodiments may
be omitted for the purpose of ease and convenience in
explanation.
[0043] Referring to FIGS. 13A and 13B, a buffer pattern BP may be a
single layer of the first buffer pattern 137 without the second
buffer pattern 138. For example, the first buffer patterns 137 may
be a silicon oxide layer.
[0044] As is traditional in the field, embodiments are described,
and illustrated in the drawings, in terms of functional blocks,
units and/or modules. Those skilled in the art will appreciate that
these blocks, units and/or modules are physically implemented by
electronic (or optical) circuits such as logic circuits, discrete
components, microprocessors, hard-wired circuits, memory elements,
wiring connections, and the like, which may be formed using
semiconductor-based fabrication techniques or other manufacturing
technologies. In the case of the blocks, units and/or modules being
implemented by microprocessors or similar, they may be programmed
using software (e.g., microcode) to perform various functions
discussed herein and may optionally be driven by firmware and/or
software. Alternatively, each block, unit and/or module may be
implemented by dedicated hardware, or as a combination of dedicated
hardware to perform some functions and a processor (e.g., one or
more programmed microprocessors and associated circuitry) to
perform other functions. Also, each block, unit and/or module of
the embodiments may be physically separated into two or more
interacting and discrete blocks, units and/or modules without
departing from the scope herein. Further, the blocks, units and/or
modules of the embodiments may be physically combined into more
complex blocks, units and/or modules without departing from the
scope herein.
[0045] By way of summation and review, new exposure techniques
and/or expensive exposure techniques may be needed to form fine
patterns, and it may be difficult to highly integrate semiconductor
devices. Thus, new integration techniques are being considered.
[0046] According to some embodiments, it is possible to help
prevent the conductive residue from being formed between the cell
array region and the peripheral circuit region. Thus, the
reliability of the semiconductor memory device may be improved.
[0047] The embodiments may provide a semiconductor memory device
with improved reliability.
[0048] Example embodiments have been disclosed herein, and although
specific terms are employed, they are used and are to be
interpreted in a generic and descriptive sense only and not for
purpose of limitation. In some instances, as would be apparent to
one of ordinary skill in the art as of the filing of the present
application, features, characteristics, and/or elements described
in connection with a particular embodiment may be used singly or in
combination with features, characteristics, and/or elements
described in connection with other embodiments unless otherwise
specifically indicated. Accordingly, it will be understood by those
of skill in the art that various changes in form and details may be
made without departing from the spirit and scope of the present
invention as set forth in the following claims.
* * * * *