U.S. patent application number 16/366715 was filed with the patent office on 2019-07-18 for selectable parallel processing of dispersed storage error encoding.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Andrew D. Baptist, Greg R. Dhuse, Jason K. Resch, Ilya Volvovski.
Application Number | 20190220354 16/366715 |
Document ID | / |
Family ID | 58257441 |
Filed Date | 2019-07-18 |
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United States Patent
Application |
20190220354 |
Kind Code |
A1 |
Baptist; Andrew D. ; et
al. |
July 18, 2019 |
SELECTABLE PARALLEL PROCESSING OF DISPERSED STORAGE ERROR
ENCODING
Abstract
A method includes a computing device determining error coding
dispersal storage function parameters to be utilized in a dispersed
storage error encoding process of a data object. The method further
includes the computing device dividing the dispersed storage error
encoding process into a plurality of dispersed storage error
encoding tasks. The method further includes allocating, by the
computing device, the plurality of dispersed storage error encoding
tasks to a plurality of central processing units (CPUs) available
to the computing device. The method further includes dispersed
storage error encoding, by the CPUs, the data segments into the
plurality of sets of encoded data slices in accordance with the
dispersed storage error encoding tasks. The method further includes
sending, by the computing device, the plurality of sets of encoded
data slices to storage units of the DSN for storage therein.
Inventors: |
Baptist; Andrew D.; (Mt.
Pleasant, WI) ; Dhuse; Greg R.; (Chicago, IL)
; Resch; Jason K.; (Chicago, IL) ; Volvovski;
Ilya; (Chicago, IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
58257441 |
Appl. No.: |
16/366715 |
Filed: |
March 27, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15362460 |
Nov 28, 2016 |
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16366715 |
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13270528 |
Oct 11, 2011 |
10216647 |
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15362460 |
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61408980 |
Nov 1, 2010 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 3/0619 20130101;
H04L 67/1097 20130101; G06F 3/0629 20130101; G06F 3/0652 20130101;
G06F 2212/7205 20130101; G06F 11/1076 20130101; G06F 11/00
20130101; H04L 67/306 20130101; G06F 9/50 20130101; H04L 67/02
20130101; G06F 3/0689 20130101; H04L 67/22 20130101; G06F 12/1408
20130101 |
International
Class: |
G06F 11/10 20060101
G06F011/10; H04L 29/08 20060101 H04L029/08; G06F 11/00 20060101
G06F011/00; G06F 12/14 20060101 G06F012/14; G06F 3/06 20060101
G06F003/06 |
Claims
1. A method comprises: determining, by a computing device of a
dispersed storage network (DSN), error coding dispersal storage
function parameters, wherein the error coding dispersal storage
function parameters are to be utilized in a dispersed storage error
encoding process of a data object; dividing, by the computing
device, the dispersed storage error encoding into a plurality of
dispersed storage error encoding tasks; allocating, by the
computing device, the plurality of dispersed storage error encoding
tasks to a plurality of central processing units (CPUs) available
to the computing device; dispersed storage error encoding, by the
plurality of CPUs, a plurality of data segments of the data object
into the plurality of sets of encoded data slices in accordance
with the plurality of dispersed storage error encoding tasks; and
sending, by the computing device, the plurality of sets of encoded
data slices to storage units of the DSN for storage therein.
2. The method of claim 1 further comprises: determining a number of
central processing units available for the dispersed storage error
encoding process of the data object; and selecting the plurality of
CPUs from the number of central processing units.
3. The method of claim 1, wherein dividing the dispersed storage
error encoding process into the plurality of dispersed storage
error encoding tasks comprises: creating a dispersed storage error
encoding task of the plurality of dispersed storage error encoding
tasks to be the dividing of the data object into the plurality of
data segments.
4. The method of claim 1, wherein dividing the dispersed storage
error encoding process into the plurality of dispersed storage
error encoding tasks comprises: creating a dispersed storage error
encoding task of the plurality of dispersed storage error encoding
tasks to generate a data matrix for a data segment of the plurality
of data segments.
5. The method of claim 1, wherein dividing the dispersed storage
error encoding process into the plurality of dispersed storage
error encoding tasks comprises: creating a first dispersed storage
error encoding task of the plurality of dispersed storage error
encoding tasks to perform a first matrix multiplication on a first
portion of an encoded matrix and a first portion of a data matrix
to produce one or more encoded data slices of a set of encoded data
slices of the plurality of sets of encoded data slices; and
creating a second dispersed storage error encoding task of the
plurality of dispersed storage error encoding tasks to perform a
second matrix multiplication on a second portion of the encoded
matrix and a second portion of the data matrix to produce another
one or more encoded data slices of the set of encoded data
slices.
6. The method of claim 1, wherein dividing the dispersed storage
error encoding process into the plurality of encoding tasks
comprises: creating a first plurality of encoding sub-tasks of the
plurality of dispersed storage error encoding tasks to perform a
plurality of component level matrix multiplications on coefficients
of an encoding matrix and data blocks of a data matrix to produce a
plurality of matrix multiplied components; and creating a second
plurality of encoding sub-tasks of the plurality of dispersed
storage error encoding tasks to combine plurality of matrix
multiplied components into a set of encoded data slices of the
plurality of sets of encoded data slices.
7. The method of claim 1, wherein the dispersed storage error
encoding process includes dividing the data object into a plurality
of data segments and dispersed storage error encoding the plurality
of the data segments into a plurality of sets of encoded data
slices in accordance with the error coding dispersal storage
function parameters.
8. The method of claim 1 further comprises: determining a
performance associated with at least some of the plurality of CPUs;
ranking the at least some of the plurality of CPUs based on the
performance; allocating, based on the ranking, first tasks of the
dispersed storage error encoding tasks associated with a read
threshold number of encoded data slices of a set of encoded data
slices of the plurality of sets of encoded data slices to a first
subset of CPUs of the plurality of CPUs; and allocating, based on
the ranking, second tasks of the dispersed storage error encoding
tasks associated with an additional number of encoded data slices
of the set of encoded data slices to a second subset of CPUs of the
plurality of CPUs.
9. A computer readable memory comprises: a first memory section
that stores operational instructions that, when executed by a
computing device of a dispersed storage network (DSN), causes the
computing device to: determine error coding dispersal storage
function parameters, wherein the error coding dispersal storage
function parameters are to be utilized in a dispersed storage error
encoding process of a data object; divide the dispersed storage
error encoding into a plurality of dispersed storage error encoding
tasks; allocate the plurality of dispersed storage error encoding
tasks to a plurality of central processing units (CPUs) available
to the computing device; a second memory section that stores
operational instructions that, when executed by the plurality of
CPUs, causes the plurality of CPUs to: dispersed storage error
encode a plurality of data segments of the data object into the
plurality of sets of encoded data slices in accordance with the
plurality of dispersed storage error encoding tasks; and a third
memory section that stores operational instructions that, when
executed by the computing device, causes the computing device to:
send the plurality of sets of encoded data slices to storage units
of the DSN for storage therein.
10. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to:
determine a number of central processing units available for the
dispersed storage error encoding process of the data object; and
select the plurality of CPUs from the number of central processing
units.
11. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to
divide the dispersed storage error encoding process into the
plurality of dispersed storage error encoding tasks by: creating a
dispersed storage error encoding task of the plurality of dispersed
storage error encoding tasks to be the dividing of the data object
into the plurality of data segments.
12. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to
divide the dispersed storage error encoding process into the
plurality of dispersed storage error encoding tasks by: creating a
dispersed storage error encoding task of the plurality of dispersed
storage error encoding tasks to generate a data matrix for a data
segment of the plurality of data segments.
13. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to
divide the dispersed storage error encoding process into the
plurality of dispersed storage error encoding tasks by: creating a
first dispersed storage error encoding task of the plurality of
dispersed storage error encoding tasks to perform a first matrix
multiplication on a first portion of an encoded matrix and a first
portion of a data matrix to produce one or more encoded data slices
of a set of encoded data slices of the plurality of sets of encoded
data slices; and creating a second dispersed storage error encoding
task of the plurality of dispersed storage error encoding tasks to
perform a second matrix multiplication on a second portion of the
encoded matrix and a second portion of the data matrix to produce
another one or more encoded data slices of the set of encoded data
slices.
14. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to
divide the dispersed storage error encoding process into the
plurality of encoding tasks by: creating a first plurality of
encoding sub-tasks of the plurality of dispersed storage error
encoding tasks to perform a plurality of component level matrix
multiplications on coefficients of an encoding matrix and data
blocks of a data matrix to produce a plurality of matrix multiplied
components; and creating a second plurality of encoding sub-tasks
of the plurality of dispersed storage error encoding tasks to
combine plurality of matrix multiplied components into a set of
encoded data slices of the plurality of sets of encoded data
slices.
15. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to
perform the dispersed storage error encoding process by: dividing
the data object into a plurality of data segments; and dispersed
storage error encoding the plurality of the data segments into a
plurality of sets of encoded data slices in accordance with the
error coding dispersal storage function parameters.
16. The computer readable memory of claim 9, wherein the first
memory section further stores operational instructions that, when
executed by the computing device, causes the computing device to:
determine a performance associated with at least some of the
plurality of CPUs; rank the at least some of the plurality of CPUs
based on the performance; allocate, based on the ranking, first
tasks of the dispersed storage error encoding tasks associated with
a read threshold number of encoded data slices of a set of encoded
data slices of the plurality of sets of encoded data slices to a
first subset of CPUs of the plurality of CPUs; and allocate, based
on the ranking, second tasks of the dispersed storage error
encoding tasks associated with an additional number of encoded data
slices of the set of encoded data slices to a second subset of CPUs
of the plurality of CPUs.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present U.S. Utility patent application claims priority
pursuant to 35 U.S.C. .sctn. 120 as a continuation of U.S. Utility
application Ser. No. 15/362,460 entitled "SELECTABLE PARALLEL
PROCESSING OF DISPERSED STORAGE ERROR ENCODING", filed Nov. 28,
2016, which is a continuation-in-part of U.S. Utility application
Ser. No. 13/270,528, entitled "COMPACTING DISPERSED STORAGE SPACE",
filed Oct. 11, 2011, issued on Feb. 26, 2019 as U.S. Pat. No.
10,216,647, which claims priority pursuant to 35 U.S.C. .sctn.
119(e) to U.S. Provisional Application No. 61/408,980, entitled
"DISPERSED STORAGE NETWORK COMMUNICATION", filed Nov. 1, 2010,
expired, all of which are hereby incorporated herein by reference
in their entirety and made part of the present U.S. Utility patent
application for all purposes.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] Not applicable.
INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT
DISC
[0003] Not applicable.
BACKGROUND OF THE INVENTION
Technical Field of the Invention
[0004] This invention relates generally to computer networks and
more particularly to dispersing error encoded data.
Description of Related Art
[0005] Computing devices are known to communicate data, process
data, and/or store data. Such computing devices range from wireless
smart phones, laptops, tablets, personal computers (PC), work
stations, and video game devices, to data centers that support
millions of web searches, stock trades, or on-line purchases every
day. In general, a computing device includes a central processing
unit (CPU), a memory system, user input/output interfaces,
peripheral device interfaces, and an interconnecting bus
structure.
[0006] As is further known, a computer may effectively extend its
CPU by using "cloud computing" to perform one or more computing
functions (e.g., a service, an application, an algorithm, an
arithmetic logic function, etc.) on behalf of the computer.
Further, for large services, applications, and/or functions, cloud
computing may be performed by multiple cloud computing resources in
a distributed manner to improve the response time for completion of
the service, application, and/or function. For example, Hadoop is
an open source software framework that supports distributed
applications enabling application execution by thousands of
computers.
[0007] In addition to cloud computing, a computer may use "cloud
storage" as part of its memory system. As is known, cloud storage
enables a user, via its computer, to store files, applications,
etc. on an Internet storage system. The Internet storage system may
include a RAID (redundant array of independent disks) system and/or
a dispersed storage system that uses an error correction scheme to
encode data for storage. Improving the writing of data to and the
reading of data from cloud storage is an on-going challenge.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)
[0008] FIG. 1 is a schematic block diagram of an embodiment of a
dispersed or distributed storage network (DSN) in accordance with
the present invention;
[0009] FIG. 2 is a schematic block diagram of an embodiment of a
computing core in accordance with the present invention;
[0010] FIG. 3 is a schematic block diagram of an example of
dispersed storage error encoding of data in accordance with the
present invention;
[0011] FIG. 4 is a schematic block diagram of a generic example of
an error encoding function in accordance with the present
invention;
[0012] FIG. 5 is a schematic block diagram of a specific example of
an error encoding function in accordance with the present
invention;
[0013] FIG. 6 is a schematic block diagram of an example of a slice
name of an encoded data slice (EDS) in accordance with the present
invention;
[0014] FIG. 7 is a schematic block diagram of an example of
dispersed storage error decoding of data in accordance with the
present invention;
[0015] FIG. 8 is a schematic block diagram of a generic example of
an error decoding function in accordance with the present
invention;
[0016] FIGS. 9A-9D are schematic block diagrams of an example of
dividing dispersed storage error encoding of a data segment into
encoding tasks in accordance with the present invention;
[0017] FIG. 10 is a logic diagram of an example of a method of
dividing dispersed storage error encoding of a data segment into
encoding tasks in accordance with the present invention; and
[0018] FIGS. 11A-11B are schematic block diagrams of another
example of dividing dispersed storage error encoding of a data
segment into encoding tasks in accordance with the present
invention;
DETAILED DESCRIPTION OF THE INVENTION
[0019] FIG. 1 is a schematic block diagram of an embodiment of a
dispersed, or distributed, storage network (DSN) 10 that includes a
plurality of computing devices 12-16, a managing unit 18, an
integrity processing unit 20, and a DSN memory 22. The components
of the DSN 10 are coupled to a network 24, which may include one or
more wireless and/or wire lined communication systems; one or more
non-public intranet systems and/or public internet systems; and/or
one or more local area networks (LAN) and/or wide area networks
(WAN).
[0020] The DSN memory 22 includes a plurality of storage units 36
that may be located at geographically different sites (e.g., one in
Chicago, one in Milwaukee, etc.), at a common site, or a
combination thereof. For example, if the DSN memory 22 includes
eight storage units 36, each storage unit is located at a different
site. As another example, if the DSN memory 22 includes eight
storage units 36, all eight storage units are located at the same
site. As yet another example, if the DSN memory 22 includes eight
storage units 36, a first pair of storage units are at a first
common site, a second pair of storage units are at a second common
site, a third pair of storage units are at a third common site, and
a fourth pair of storage units are at a fourth common site. Note
that a DSN memory 22 may include more or less than eight storage
units 36. Further note that each storage unit 36 includes a
computing core (as shown in FIG. 2, or components thereof) and a
plurality of memory devices for storing dispersed error encoded
data.
[0021] Each of the computing devices 12-16, the managing unit 18,
and the integrity processing unit 20 include a computing core 26,
which includes network interfaces 30-33.
[0022] Computing devices 12-16 may each be a portable computing
device and/or a fixed computing device. A portable computing device
may be a social networking device, a gaming device, a cell phone, a
smart phone, a digital assistant, a digital music player, a digital
video player, a laptop computer, a handheld computer, a tablet, a
video game controller, and/or any other portable device that
includes a computing core. A fixed computing device may be a
computer (PC), a computer server, a cable set-top box, a satellite
receiver, a television set, a printer, a fax machine, home
entertainment equipment, a video game console, and/or any type of
home or office computing equipment. Note that each of the managing
unit 18 and the integrity processing unit 20 may be separate
computing devices, may be a common computing device, and/or may be
integrated into one or more of the computing devices 12-16 and/or
into one or more of the storage units 36.
[0023] Each interface 30, 32, and 33 includes software and hardware
to support one or more communication links via the network 24
indirectly and/or directly. For example, interface 30 supports a
communication link (e.g., wired, wireless, direct, via a LAN, via
the network 24, etc.) between computing devices 14 and 16. As
another example, interface 32 supports communication links (e.g., a
wired connection, a wireless connection, a LAN connection, and/or
any other type of connection to/from the network 24) between
computing devices 12 and 16 and the DSN memory 22. As yet another
example, interface 33 supports a communication link for each of the
managing unit 18 and the integrity processing unit 20 to the
network 24.
[0024] Computing devices 12 and 16 include a dispersed storage (DS)
client module 34, which enables the computing device to dispersed
storage error encode and decode data (e.g., data 40) as
subsequently described with reference to one or more of FIGS. 3-8.
In this example embodiment, computing device 16 functions as a
dispersed storage processing agent for computing device 14. In this
role, computing device 16 dispersed storage error encodes and
decodes data on behalf of computing device 14. With the use of
dispersed storage error encoding and decoding, the DSN 10 is
tolerant of a significant number of storage unit failures (the
number of failures is based on parameters of the dispersed storage
error encoding function) without loss of data and without the need
for a redundant or backup copies of the data. Further, the DSN 10
stores data for an indefinite period of time without data loss and
in a secure manner (e.g., the system is very resistant to
unauthorized attempts at accessing the data).
[0025] In operation, the managing unit 18 performs DS management
services. For example, the managing unit 18 establishes distributed
data storage parameters (e.g., vault creation, distributed storage
parameters, security parameters, billing information, user profile
information, etc.) for computing devices 12-14 individually or as
part of a group of user devices. As a specific example, the
managing unit 18 coordinates creation of a vault (e.g., a virtual
memory block associated with a portion of an overall namespace of
the DSN) within the DSN memory 22 for a user device, a group of
devices, or for public access and establishes per vault dispersed
storage (DS) error encoding parameters for a vault. The managing
unit 18 facilitates storage of DS error encoding parameters for
each vault by updating registry information of the DSN 10, where
the registry information may be stored in the DSN memory 22, a
computing device 12-16, the managing unit 18, and/or the integrity
processing unit 20.
[0026] The managing unit 18 creates and stores user profile
information (e.g., an access control list (ACL)) in local memory
and/or within memory of the DSN memory 22. The user profile
information includes authentication information, permissions,
and/or the security parameters. The security parameters may include
encryption/decryption scheme, one or more encryption keys, key
generation scheme, and/or data encoding/decoding scheme.
[0027] The managing unit 18 creates billing information for a
particular user, a user group, a vault access, public vault access,
etc. For instance, the managing unit 18 tracks the number of times
a user accesses a non-public vault and/or public vaults, which can
be used to generate a per-access billing information. In another
instance, the managing unit 18 tracks the amount of data stored
and/or retrieved by a user device and/or a user group, which can be
used to generate a per-data-amount billing information.
[0028] As another example, the managing unit 18 performs network
operations, network administration, and/or network maintenance.
Network operations includes authenticating user data allocation
requests (e.g., read and/or write requests), managing creation of
vaults, establishing authentication credentials for user devices,
adding/deleting components (e.g., user devices, storage units,
and/or computing devices with a DS client module 34) to/from the
DSN 10, and/or establishing authentication credentials for the
storage units 36. Network administration includes monitoring
devices and/or units for failures, maintaining vault information,
determining device and/or unit activation status, determining
device and/or unit loading, and/or determining any other system
level operation that affects the performance level of the DSN 10.
Network maintenance includes facilitating replacing, upgrading,
repairing, and/or expanding a device and/or unit of the DSN 10.
[0029] The integrity processing unit 20 performs rebuilding of
`bad` or missing encoded data slices. At a high level, the
integrity processing unit 20 performs rebuilding by periodically
attempting to retrieve/list encoded data slices, and/or slice names
of the encoded data slices, from the DSN memory 22. For retrieved
encoded slices, they are checked for errors due to data corruption,
outdated version, etc. If a slice includes an error, it is flagged
as a `bad` slice. For encoded data slices that were not received
and/or not listed, they are flagged as missing slices. Bad and/or
missing slices are subsequently rebuilt using other retrieved
encoded data slices that are deemed to be good slices to produce
rebuilt slices. The rebuilt slices are stored in the DSN memory
22.
[0030] FIG. 2 is a schematic block diagram of an embodiment of a
computing core 26 that includes a processing module 50, a memory
controller 52, main memory 54, a video graphics processing unit 55,
an input/output (IO) controller 56, a peripheral component
interconnect (PCI) interface 58, an IO interface module 60, at
least one IO device interface module 62, a read only memory (ROM)
basic input output system (BIOS) 64, and one or more memory
interface modules. The one or more memory interface module(s)
includes one or more of a universal serial bus (USB) interface
module 66, a host bus adapter (HBA) interface module 68, a network
interface module 70, a flash interface module 72, a hard drive
interface module 74, and a DSN interface module 76.
[0031] The DSN interface module 76 functions to mimic a
conventional operating system (OS) file system interface (e.g.,
network file system (NFS), flash file system (FFS), disk file
system (DFS), file transfer protocol (FTP), web-based distributed
authoring and versioning (WebDAV), etc.) and/or a block memory
interface (e.g., small computer system interface (SCSI), internet
small computer system interface (iSCSI), etc.). The DSN interface
module 76 and/or the network interface module 70 may function as
one or more of the interface 30-33 of FIG. 1. Note that the IO
device interface module 62 and/or the memory interface modules
66-76 may be collectively or individually referred to as IO
ports.
[0032] FIG. 3 is a schematic block diagram of an example of
dispersed storage error encoding of data. When a computing device
12 or 16 has data to store it disperse storage error encodes the
data in accordance with a dispersed storage error encoding process
based on dispersed storage error encoding parameters. The dispersed
storage error encoding parameters include an encoding function
(e.g., information dispersal algorithm, Reed-Solomon, Cauchy
Reed-Solomon, systematic encoding, non-systematic encoding, on-line
codes, etc.), a data segmenting protocol (e.g., data segment size,
fixed, variable, etc.), and per data segment encoding values. The
per data segment encoding values include a total, or pillar width,
number (T) of encoded data slices per encoding of a data segment
(i.e., in a set of encoded data slices); a decode threshold number
(D) of encoded data slices of a set of encoded data slices that are
needed to recover the data segment; a read threshold number (R) of
encoded data slices to indicate a number of encoded data slices per
set to be read from storage for decoding of the data segment;
and/or a write threshold number (W) to indicate a number of encoded
data slices per set that must be accurately stored before the
encoded data segment is deemed to have been properly stored. The
dispersed storage error encoding parameters may further include
slicing information (e.g., the number of encoded data slices that
will be created for each data segment) and/or slice security
information (e.g., per encoded data slice encryption, compression,
integrity checksum, etc.).
[0033] In the present example, Cauchy Reed-Solomon has been
selected as the encoding function (a generic example is shown in
FIG. 4 and a specific example is shown in FIG. 5); the data
segmenting protocol is to divide the data object into fixed sized
data segments; and the per data segment encoding values include: a
pillar width of 5, a decode threshold of 3, a read threshold of 4,
and a write threshold of 4. In accordance with the data segmenting
protocol, the computing device 12 or 16 divides the data (e.g., a
file (e.g., text, video, audio, etc.), a data object, or other data
arrangement) into a plurality of fixed sized data segments (e.g., 1
through Y of a fixed size in range of Kilo-bytes to Tera-bytes or
more). The number of data segments created is dependent of the size
of the data and the data segmenting protocol.
[0034] The computing device 12 or 16 then disperse storage error
encodes a data segment using the selected encoding function (e.g.,
Cauchy Reed-Solomon) to produce a set of encoded data slices. FIG.
4 illustrates a generic Cauchy Reed-Solomon encoding function,
which includes an encoding matrix (EM), a data matrix (DM), and a
coded matrix (CM). The size of the encoding matrix (EM) is
dependent on the pillar width number (T) and the decode threshold
number (D) of selected per data segment encoding values. To produce
the data matrix (DM), the data segment is divided into a plurality
of data blocks and the data blocks are arranged into D number of
rows with Z data blocks per row. Note that Z is a function of the
number of data blocks created from the data segment and the decode
threshold number (D). The coded matrix is produced by matrix
multiplying the data matrix by the encoding matrix.
[0035] FIG. 5 illustrates a specific example of Cauchy Reed-Solomon
encoding with a pillar number (T) of five and decode threshold
number of three. In this example, a first data segment is divided
into twelve data blocks (D1-D12). The coded matrix includes five
rows of coded data blocks, where the first row of X11-X14
corresponds to a first encoded data slice (EDS 1_1), the second row
of X21-X24 corresponds to a second encoded data slice (EDS 2_1),
the third row of X31-X34 corresponds to a third encoded data slice
(EDS 3_1), the fourth row of X41-X44 corresponds to a fourth
encoded data slice (EDS 4_1), and the fifth row of X51-X54
corresponds to a fifth encoded data slice (EDS 5_1). Note that the
second number of the EDS designation corresponds to the data
segment number.
[0036] Returning to the discussion of FIG. 3, the computing device
also creates a slice name (SN) for each encoded data slice (EDS) in
the set of encoded data slices. A typical format for a slice name
80 is shown in FIG. 6. As shown, the slice name (SN) 80 includes a
pillar number of the encoded data slice (e.g., one of 1-T), a data
segment number (e.g., one of 1-Y), a vault identifier (ID), a data
object identifier (ID), and may further include revision level
information of the encoded data slices. The slice name functions
as, at least part of, a DSN address for the encoded data slice for
storage and retrieval from the DSN memory 22.
[0037] As a result of encoding, the computing device 12 or 16
produces a plurality of sets of encoded data slices, which are
provided with their respective slice names to the storage units for
storage. As shown, the first set of encoded data slices includes
EDS 1_1 through EDS 5_1 and the first set of slice names includes
SN 1_1 through SN 5_1 and the last set of encoded data slices
includes EDS 1_Y through EDS 5_Y and the last set of slice names
includes SN 1_Y through SN 5_Y.
[0038] FIG. 7 is a schematic block diagram of an example of
dispersed storage error decoding of a data object that was
dispersed storage error encoded and stored in the example of FIG.
4. In this example, the computing device 12 or 16 retrieves from
the storage units at least the decode threshold number of encoded
data slices per data segment. As a specific example, the computing
device retrieves a read threshold number of encoded data
slices.
[0039] To recover a data segment from a decode threshold number of
encoded data slices, the computing device uses a decoding function
as shown in FIG. 8. As shown, the decoding function is essentially
an inverse of the encoding function of FIG. 4. The coded matrix
includes a decode threshold number of rows (e.g., three in this
example) and the decoding matrix in an inversion of the encoding
matrix that includes the corresponding rows of the coded matrix.
For example, if the coded matrix includes rows 1, 2, and 4, the
encoding matrix is reduced to rows 1, 2, and 4, and then inverted
to produce the decoding matrix.
[0040] FIGS. 9A-9D are schematic block diagrams of an example of
dividing dispersed storage error encoding of a data segment into
encoding tasks. FIG. 9A is repeat of FIG. 5 for convenience. FIG.
9B illustrates a unity matrix portion of the encoding matrix [E]
that is matrix multiplied with the data matrix [D] to produce three
rows of the coded matrix [C], which corresponds to the first three
encoded data slices of a set of encoded data slices.
[0041] FIG. 9C illustrates a fourth row of the encoding matrix [E]
that is matrix multiplied with the data matrix [D] to produce a
fourth row of the coded matrix [C], which corresponds to a fourth
encoded data slice of the set of encoded data slices. FIG. 9D
illustrates a fifth row of the encoding matrix [E] that is matrix
multiplied with the data matrix [D] to produce a fifth row of the
coded matrix [C], which corresponds to a fifth encoded data slice
of the set of encoded data slices. Each of the encoding functions
of FIGS. 9B-9D is allocated to a different central processing unit
(CPU) that is available to the computing device. The CPUs include
one or more CPUs in the computing core of the computing device
and/or one or more CPUs in the computing core of one or more other
computing device. Note that one set of CPUs may perform the
encoding of FIGS. 9B-9D for one data segment of the data object and
another set of CPUs may concurrently perform the encoding of FIGS.
9B-9D for another data segment of the data object.
[0042] FIG. 10 is a logic diagram of an example of a method of
dividing dispersed storage error encoding of a data segment into
encoding tasks. The method begins at step 262 where a computing
device receives data for storage. The method continues with step
310 where the computing device determines (e.g., selects) available
central processing units (CPUs) from a plurality of CPUs that are
within the computing device or within one or more other computing
devices. The determination, or selection, may be based on one or
more of a query, a list, a schedule, a test, and a message. The
method continues at step 312 where the computing device determines
error coding dispersal storage function parameters based on one or
more of available CPUs, lookup, a list, and a message. For example,
the computing device determines a read threshold to be just less
than the number of available CPUs.
[0043] The method continues at step 314 where the computing device
determines CPU assignments (e.g., assigns encoding tasks) based on
available CPUs and the error coding dispersal storage function
parameters. The determination may be based on one or more of
available CPUs, the error coding dispersal storage function
parameters, optimizing for lowest estimated time of encoding,
encoding just a slice, encoding just a portion of a slice, a
predetermination, a lookup, and a message. For example, the
processing module assigns faster CPUs to encode a read threshold
number of slices. As another example, the processing module assigns
fast CPUs first to encode slices to be sent to faster dispersed
storage (DS) units. Slice portion tasks are discussed in greater
detail with reference to FIGS. 11A and 11B.
[0044] The assignment of encoding tasks further includes creating
an encoding task for dividing the data object into the plurality of
data segments. The assignment of encoding tasks still further
includes creating an encoding task to generate a data matrix for a
data segment of the plurality of data segments.
[0045] The method continues at step 316 where the computing device
executes the CPU assignments to produce CPU outputs. For example,
CPU 1 encodes a first portion of slice 1, CPU 2 encodes a second
portion of slice 1, and CPU 3 encodes a third portion of slice 1. A
system performance improvement may be realized when the three CPUs
encode the three slice portions substantially in parallel. A CPU
task map illustrating the execution of CPU assignments is discussed
in greater detail with reference to FIG. 11B.
[0046] The method continues at step 318 where the computing device
aggregates CPU outputs to produce encoded data slices. For example,
the computing device aggregates the first portion, the second
portion, and the third portion of slice 1 to produce slice 1. The
method continues at step 320 where the computing device determines
transmission prioritization based on CPU assignments. For example,
the computing device determines to prioritize transmission of slice
1 when the CPU assignments are aligned with producing slice 1
first. As another example, the computing device determines to
prioritize the transmission of a read threshold number of slices to
more quickly enable subsequent retrieval of the data. The method
continues at step 322 where the computing device sends the encoded
data slices in accordance with the transmission prioritization to a
dispersed storage network (DSN) memory for storage therein.
[0047] FIG. 11A is an algorithm diagram illustrating an example of
encoding data. Such encoding may be utilized to dispersed storage
error encode data to produce a set of encoded data slices. The
encoding of each slice of the set includes a plurality of
intermediate steps. For example, a 5 by 3 generator matrix 324 is
multiplied times a 3 by 1 data matrix 326 to produce a 5 by 1
matrix 327 of encoded data slices 1-5. The example corresponds to a
dispersed storage network utilizing a pillar slicing width of five
and a decode threshold of 3. Note that each slice may be calculated
by adding three products of an entry of the generator matrix times
an entry of the data matrix. For example, slice 1 is encoded as
ax+by+cz. A system performance improvement may be realized by
subdividing the execution of the encoding of slices between at
least three CPUs for each slice.
[0048] FIG. 11B is a central processing unit (CPU) task map
illustrating an example of determining CPU assignments. For
example, a CPU load to calculate a slice 1 is divided amongst three
CPUs. In an instance, CPU 1 encodes the "ax" product, CPU 2 encodes
the "by" product, and CPU 3 encodes the "cz" product. Any of the
CPUs may subsequently aggregate the three products to produce slice
1. Note that CPUs 1-3 are also assigned to subsequently encode the
"jx", "ky", "lz", "mx", "ny", and "oz" products. A different CPU
may be assigned to encode a different product of slices 1-3 to
enable the encoding of a threshold number of slices (e.g., three)
as quick as possible. The CPUs are assigned to create and send
slices 4 and 5 once the threshold number of slices (e.g., slices
1-3) are encoded and sent.
[0049] It is noted that terminologies as may be used herein such as
bit stream, stream, signal sequence, etc. (or their equivalents)
have been used interchangeably to describe digital information
whose content corresponds to any of a number of desired types
(e.g., data, video, speech, audio, etc. any of which may generally
be referred to as `data`).
[0050] As may be used herein, the terms "substantially" and
"approximately" provides an industry-accepted tolerance for its
corresponding term and/or relativity between items. Such an
industry-accepted tolerance ranges from less than one percent to
fifty percent and corresponds to, but is not limited to, component
values, integrated circuit process variations, temperature
variations, rise and fall times, and/or thermal noise. Such
relativity between items ranges from a difference of a few percent
to magnitude differences. As may also be used herein, the term(s)
"configured to", "operably coupled to", "coupled to", and/or
"coupling" includes direct coupling between items and/or indirect
coupling between items via an intervening item (e.g., an item
includes, but is not limited to, a component, an element, a
circuit, and/or a module) where, for an example of indirect
coupling, the intervening item does not modify the information of a
signal but may adjust its current level, voltage level, and/or
power level. As may further be used herein, inferred coupling
(i.e., where one element is coupled to another element by
inference) includes direct and indirect coupling between two items
in the same manner as "coupled to". As may even further be used
herein, the term "configured to", "operable to", "coupled to", or
"operably coupled to" indicates that an item includes one or more
of power connections, input(s), output(s), etc., to perform, when
activated, one or more its corresponding functions and may further
include inferred coupling to one or more other items. As may still
further be used herein, the term "associated with", includes direct
and/or indirect coupling of separate items and/or one item being
embedded within another item.
[0051] As may be used herein, the term "compares favorably",
indicates that a comparison between two or more items, signals,
etc., provides a desired relationship. For example, when the
desired relationship is that signal 1 has a greater magnitude than
signal 2, a favorable comparison may be achieved when the magnitude
of signal 1 is greater than that of signal 2 or when the magnitude
of signal 2 is less than that of signal 1. As may be used herein,
the term "compares unfavorably", indicates that a comparison
between two or more items, signals, etc., fails to provide the
desired relationship.
[0052] As may also be used herein, the terms "processing module",
"processing circuit", "processor", and/or "processing unit" may be
a single processing device or a plurality of processing devices.
Such a processing device may be a microprocessor, micro-controller,
digital signal processor, microcomputer, central processing unit,
field programmable gate array, programmable logic device, state
machine, logic circuitry, analog circuitry, digital circuitry,
and/or any device that manipulates signals (analog and/or digital)
based on hard coding of the circuitry and/or operational
instructions. The processing module, module, processing circuit,
and/or processing unit may be, or further include, memory and/or an
integrated memory element, which may be a single memory device, a
plurality of memory devices, and/or embedded circuitry of another
processing module, module, processing circuit, and/or processing
unit. Such a memory device may be a read-only memory, random access
memory, volatile memory, non-volatile memory, static memory,
dynamic memory, flash memory, cache memory, and/or any device that
stores digital information. Note that if the processing module,
module, processing circuit, and/or processing unit includes more
than one processing device, the processing devices may be centrally
located (e.g., directly coupled together via a wired and/or
wireless bus structure) or may be distributedly located (e.g.,
cloud computing via indirect coupling via a local area network
and/or a wide area network). Further note that if the processing
module, module, processing circuit, and/or processing unit
implements one or more of its functions via a state machine, analog
circuitry, digital circuitry, and/or logic circuitry, the memory
and/or memory element storing the corresponding operational
instructions may be embedded within, or external to, the circuitry
comprising the state machine, analog circuitry, digital circuitry,
and/or logic circuitry. Still further note that, the memory element
may store, and the processing module, module, processing circuit,
and/or processing unit executes, hard coded and/or operational
instructions corresponding to at least some of the steps and/or
functions illustrated in one or more of the Figures. Such a memory
device or memory element can be included in an article of
manufacture.
[0053] One or more embodiments have been described above with the
aid of method steps illustrating the performance of specified
functions and relationships thereof. The boundaries and sequence of
these functional building blocks and method steps have been
arbitrarily defined herein for convenience of description.
Alternate boundaries and sequences can be defined so long as the
specified functions and relationships are appropriately performed.
Any such alternate boundaries or sequences are thus within the
scope and spirit of the claims. Further, the boundaries of these
functional building blocks have been arbitrarily defined for
convenience of description. Alternate boundaries could be defined
as long as the certain significant functions are appropriately
performed. Similarly, flow diagram blocks may also have been
arbitrarily defined herein to illustrate certain significant
functionality.
[0054] To the extent used, the flow diagram block boundaries and
sequence could have been defined otherwise and still perform the
certain significant functionality. Such alternate definitions of
both functional building blocks and flow diagram blocks and
sequences are thus within the scope and spirit of the claims. One
of average skill in the art will also recognize that the functional
building blocks, and other illustrative blocks, modules and
components herein, can be implemented as illustrated or by discrete
components, application specific integrated circuits, processors
executing appropriate software and the like or any combination
thereof.
[0055] In addition, a flow diagram may include a "start" and/or
"continue" indication. The "start" and "continue" indications
reflect that the steps presented can optionally be incorporated in
or otherwise used in conjunction with other routines. In this
context, "start" indicates the beginning of the first step
presented and may be preceded by other activities not specifically
shown. Further, the "continue" indication reflects that the steps
presented may be performed multiple times and/or may be succeeded
by other activities not specifically shown. Further, while a flow
diagram indicates a particular ordering of steps, other orderings
are likewise possible provided that the principles of causality are
maintained.
[0056] The one or more embodiments are used herein to illustrate
one or more aspects, one or more features, one or more concepts,
and/or one or more examples. A physical embodiment of an apparatus,
an article of manufacture, a machine, and/or of a process may
include one or more of the aspects, features, concepts, examples,
etc. described with reference to one or more of the embodiments
discussed herein. Further, from figure to figure, the embodiments
may incorporate the same or similarly named functions, steps,
modules, etc. that may use the same or different reference numbers
and, as such, the functions, steps, modules, etc. may be the same
or similar functions, steps, modules, etc. or different ones.
[0057] Unless specifically stated to the contra, signals to, from,
and/or between elements in a figure of any of the figures presented
herein may be analog or digital, continuous time or discrete time,
and single-ended or differential. For instance, if a signal path is
shown as a single-ended path, it also represents a differential
signal path. Similarly, if a signal path is shown as a differential
path, it also represents a single-ended signal path. While one or
more particular architectures are described herein, other
architectures can likewise be implemented that use one or more data
buses not expressly shown, direct connectivity between elements,
and/or indirect coupling between other elements as recognized by
one of average skill in the art.
[0058] The term "module" is used in the description of one or more
of the embodiments. A module implements one or more functions via a
device such as a processor or other processing device or other
hardware that may include or operate in association with a memory
that stores operational instructions. A module may operate
independently and/or in conjunction with software and/or firmware.
As also used herein, a module may contain one or more sub-modules,
each of which may be one or more modules.
[0059] As may further be used herein, a computer readable memory
includes one or more memory elements. A memory element may be a
separate memory device, multiple memory devices, or a set of memory
locations within a memory device. Such a memory device may be a
read-only memory, random access memory, volatile memory,
non-volatile memory, static memory, dynamic memory, flash memory,
cache memory, and/or any device that stores digital information.
The memory device may be in a form a solid state memory, a hard
drive memory, cloud memory, thumb drive, server memory, computing
device memory, and/or other physical medium for storing digital
information.
[0060] While particular combinations of various functions and
features of the one or more embodiments have been expressly
described herein, other combinations of these features and
functions are likewise possible. The present disclosure is not
limited by the particular examples disclosed herein and expressly
incorporates these other combinations.
* * * * *