U.S. patent application number 15/922571 was filed with the patent office on 2019-07-04 for memory cell with asymmetric word line and erase gate for decoupled program erase performance.
This patent application is currently assigned to Microchip Technology Incorporated. The applicant listed for this patent is Microchip Technology Incorporated. Invention is credited to Sonu Daryanani, Mel Hymas, James Walls.
Application Number | 20190207006 15/922571 |
Document ID | / |
Family ID | 67059889 |
Filed Date | 2019-07-04 |
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United States Patent
Application |
20190207006 |
Kind Code |
A1 |
Hymas; Mel ; et al. |
July 4, 2019 |
Memory Cell With Asymmetric Word Line And Erase Gate For Decoupled
Program Erase Performance
Abstract
A memory cell, e.g., a flash memory cell, includes a substrate,
a floating gate formed over the substrate, and a word line and an
erase gate formed over the floating gate. The word line overlaps
the floating gate by a first lateral overlap distance, and the
erase gate overlaps the floating gate by a second lateral overlap
distance that is substantially greater than the first lateral
distance. This configuration allows the program and erase coupling
to the floating gate to be optimized independently, e.g., to
decrease or minimize the program current and/or increase or
maximize the erase current for the cell.
Inventors: |
Hymas; Mel; (Camas, WA)
; Walls; James; (Mesa, AZ) ; Daryanani; Sonu;
(Tempe, AZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Microchip Technology Incorporated |
Chandler |
AZ |
US |
|
|
Assignee: |
Microchip Technology
Incorporated
Chandler
AZ
|
Family ID: |
67059889 |
Appl. No.: |
15/922571 |
Filed: |
March 15, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62612864 |
Jan 2, 2018 |
|
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62613036 |
Jan 2, 2018 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 16/0408 20130101;
G11C 16/08 20130101; H01L 29/7841 20130101; H01L 29/40114 20190801;
H01L 29/42328 20130101; G11C 16/14 20130101; H01L 27/11521
20130101 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 27/11521 20060101 H01L027/11521 |
Claims
1. A method of forming a memory cell, the method comprising:
forming a floating gate over a substrate; forming a word line over
the floating gate such that the word line overlaps the floating
gate by a first lateral distance; and forming an erase gate over
the floating gate such that the erase gate overlaps the floating
gate by a second lateral distance that is at least twice as large
as the first lateral distance.
2. The method of claim 1, wherein the memory cell comprises a flash
memory cell.
3. The method of claim 1, comprises forming a pair of floating
gates of the memory cell, and forming a word line and erase gate
over each floating gate, wherein for each floating gate, the
respective word line overlaps the respective floating gate by a
first respective lateral distance and the respective erase gate
overlaps the respective floating gate by a second respective
lateral distance that is at least twice as large as the first
respective lateral distance.
4. The method of claim 3, wherein the erase gates for the pair of
floating gates are provided by a shared gate.
5. The method of claim 1, wherein the word line and the erase gate
are formed in a common poly layer.
6. The method of claim 1, wherein the floating gate is formed in a
poly1 layer, and the word line and erase gate are formed in a poly2
layer.
7. (canceled)
8. The method of claim 1, wherein the second lateral distance is at
least 5 times as large as the first lateral distance.
9. The method of claim 1, wherein, for a defined voltage level, the
program current for the word line is at least 100 times as the
program current for the erase gate or for a memory cell with
symmetrical word line/erase gate overlap over the floating
gate.
10. The method of claim 1, wherein, for a defined voltage level,
the program current for the word line is at least 1,000 times as
the program current for the erase gate or for a memory cell with
symmetrical word line/erase gate overlap over the floating
gate.
11. A memory cell, comprising: a substrate; a floating gate formed
over the substrate; and a word line and an erase gate formed over
the floating gate; wherein the word line overlaps the floating gate
by a first lateral distance, and the erase gate overlaps the
floating gate by a second lateral distance that is at least twice
as large as the first lateral distance.
12. The memory cell of claim 11, wherein the memory cell comprises
a flash memory cell.
13. The memory cell of claim 11, wherein the memory cell includes:
a pair of floating gates, and a word line and an erase gate over
each floating gate, wherein for each floating gate, the respective
word line overlaps the respective floating gate by a first
respective lateral distance and the respective erase gate overlaps
the respective floating gate by a second respective lateral
distance that is at least twice as large as the first respective
lateral distance.
14. The memory cell of claim 13, wherein the erase gates for the
pair of floating gates are provided by a shared gate.
15. The memory cell of claim 11, wherein the word line and the
erase gate comprises portions of a common poly layer.
16. The memory cell of claim 11, wherein the floating gate
comprises a portion of a poly1 layer, and the word line and erase
gate comprise portions of a poly2 layer.
17. (canceled)
18. The memory cell of claim 11, wherein the second lateral
distance is at least 5 times as large as the first lateral
distance.
19. The memory cell of claim 11, wherein, for a defined voltage
level, the program current for the word line is at least 100 times
as large as the program current for the erase gate or for a memory
cell with symmetrical word line/erase gate overlap over the
floating gate.
20. The memory cell of claim 11, wherein, for a defined voltage
level, the program current for the word line is at least 1,000
times as large as the program current for the erase gate or for a
memory cell with symmetrical word line/erase gate overlap over the
floating gate.
21. A memory cell, comprising: a substrate; a floating gate formed
over the substrate; and a word line and an erase gate formed in a
common poly layer over the floating gate; wherein the word line
overlaps the floating gate by a first lateral distance, and the
erase gate overlaps the floating gate by a second lateral distance
that is at least twice as large as the first lateral distance.
22. The memory cell of claim 21, wherein the floating gate
comprises a portion of a poly1 layer, and the word line and erase
gate comprise portions of a poly2 layer.
23. The memory cell of claim 21, wherein the second lateral
distance is at least five times as large as the first lateral
distance.
24. The memory cell of claim 21, wherein, for a defined voltage
level, the program current for the word line is at least 100 times
as the program current for the erase gate or for a memory cell with
symmetrical word line/erase gate overlap over the floating
gate.
25. A memory cell, comprising: a pair of floating gates formed over
a substrate; a respective word line overlapping each floating gate
by a respective word line lateral overlap distance; and a shared
gate located between and extending over both of the floating gates
such that such that the shared gate overlaps each floating gate by
a respective shared gate lateral overlap distance; wherein for each
floating gate, the respective shared gate lateral overlap distance
is at least twice as large as the respective word line lateral
overlap distance.
26. The memory cell of claim 25, wherein the shared gate defines a
shared erase gate for performing erase functions for each floating
gate.
27. The memory cell of claim 25, wherein the pair of word lines and
the shared gate comprise portions of a common poly layer.
28. The memory cell of claim 25, wherein for each floating gate,
the respective shared gate lateral overlap distance is at least
five times as large as the respective word line lateral overlap
distance.
Description
RELATED PATENT APPLICATION
[0001] This application claims priority to commonly owned United
States Provisional Patent Application Nos. 62/612,864 filed Jan. 2,
2018 and 62/613,036 filed Jan. 2, 2018, which are both hereby
incorporated by reference herein for all purposes.
TECHNICAL FIELD
[0002] The present disclosure relates to memory cells, e.g., flash
memory cells, and more particularly, to a split-gate flash memory
cell or other memory cell having a floating gate with a decoupled
and asymmetric program and erase overlap over the floating
gate.
BACKGROUND
[0003] Certain memory cells, including flash memory cells, include
at least one floating gate that is/are programmed and erased
through one or more program/erase gates, word lines, or other
conductive element(s). Some memory cells use a common program/erase
gate extending over a floating gate to both program and erase the
cell. In some implementations, the floating gate is formed by a
Poly1 layer, while the program/erase gate is formed by a Poly2
layer that partially overlaps the underlying Poly1 floating gate in
the lateral direction.
[0004] FIG. 1 illustrates a partial cross-sectional view of an
example memory cell 10A including a Poly1 floating gate 14 and
overlying "football" oxide 16 formed over a substrate 12, and Poly2
common program/erase gate 18 extending partially over the floating
gate 14. A distance of lateral overlap between the program/erase
gate 18 and underlying floating gate 14, also referred to as the
P1/P2 overlap distance or "FG overlap distance," is indicated in
FIG. 1.
[0005] The FG overlap distance typically affects both the program
and erase characteristics of the cell, including the program and
erase current for the cell. In particular, programming efficiency
(e.g., lower current) is improved by a smaller FG overlap distance,
while erase efficiency (e.g., higher current) is improved by a
larger FG overlap distance. Typically, increasing the difference
between the erase state current (Ir1) and program state current
(Ir0) increases the cell performance/efficiency, and vice
versa.
[0006] Thus, the erase and program efficiency are antagonistic, and
may define a relatively small window for FG overlap distance that
provides and effective or desirable difference between program and
erase state currents (Ir1/Ir0 difference). Further, the Ir1/Ir0
window is reduced with reduced cell size, due to higher program and
erase voltages required in smaller cells, which limits scaling of
certain memory cells.
[0007] In addition, in cells that include multiple floating gates,
e.g., mirrored dual-bitcell flash memory cells, the FG overlap
distance may be asymmetrical between the different floating gates
due to inherent alignment imperfections or tolerances associated
with manufacturing, which may be disadvantageous.
[0008] FIG. 2 illustrates an example of a mirrored memory cell 10B
(e.g., a SuperFlash cell) including two spaced-apart floating gates
14 with a respective program/erase gate 18 formed over each
floating gate 14.
[0009] FIG. 3 illustrates another example mirrored memory cell 10C
(e.g., a SuperFlash cell) including two spaced-apart floating gates
14, a word line 20 formed over each floating gate 14, and a common
erase gate or "coupling gate" 22 formed between and extending over
both floating gates 14, such that for each floating gate 14, the
program and erase couplings to the respective floating gate 14 are
decoupled.
SUMMARY
[0010] Embodiments of the present disclosure provide a memory cell
(e.g., flash memory cell) and method for forming a memory cell
having at least one floating gate, and a word line (or other
program node) and erase gate (or other erase node) associated with
the floating gate, wherein (a) the word line and erase gate are
decoupled from each other and (b) the extent to which the word line
and erase gate overlap the floating gate is asymmetrical, e.g., the
erase gate overlaps the floating gate by a substantially greater
extent then the word line overlaps the floating gate. This
configuration allows the program and erase coupling to the floating
gate to be optimized independently, e.g., to decrease or minimize
the program current and/or increase or maximize the erase current
for the cell.
[0011] One embodiment provides a method of forming a memory cell,
including forming a floating gate over a substrate; forming a word
line over the floating gate such that the word line overlaps the
floating gate by a first lateral distance; and forming an erase
gate over the floating gate (e.g., simultaneous with, or separate
from the forming of the word line) such that the erase gate
overlaps the floating gate by a second lateral distance that is
substantially greater than the first lateral distance.
[0012] In some embodiments, the memory cell comprises a flash
memory cell. For example, the memory cell may comprise any type of
SuperFlash memory cell manufactured by Microchip Technology Inc.,
having a headquarters at 2355 W. Chandler Blvd., Chandler, Ariz.
85224, or a modified version of such memory cells.
[0013] In some embodiments, the method includes forming a pair of
floating gates of the memory cell, and forming a word line and
erase gate over each floating gate, wherein for each floating gate,
the respective word line overlaps the respective floating gate by a
first respective lateral distance and the respective erase gate
overlaps the respective floating gate by a second respective
lateral distance that is substantially greater than the first
respective lateral distance.
[0014] In some embodiments, the erase gates for the pair of
floating gates are provided by a shared gate (control gate). In
some embodiments, the word line and the erase gate are formed in a
common poly layer. For example, in one embodiment, the floating
gate is formed in a Poly1 layer, and the word line and erase gate
are formed in a Poly2 layer.
[0015] In some embodiments, the erase gate-floating gate lateral
overlap distance is at least 1.5 times, at least 2 times, at least
3 times, at least 4 times, at least 5 times, at least 6 times, at
least 7 times, at least 8 times, at least 9 times, or at least 10
times as great as the word line-floating gate lateral overlap
distance. Further, in some embodiments, for a defined voltage
level, the program current for the word line is at least 2 times,
at least 10 times, at least 100 times, at least 1000 times, at
least 5000 times, or at least 10,000 times as large as the program
current for the word line or for a conventional cell with
symmetrical word line/erase gate overlap over the floating
gate.
[0016] Another embodiment provides a memory cell including a
substrate; a floating gate formed over the substrate; and a word
line and an erase gate formed over the floating gate; wherein the
word line overlaps the floating gate by a first lateral distance,
and the erase gate overlaps the floating gate by a second lateral
distance that is substantially greater than the first lateral
distance.
[0017] In some embodiments, the memory cell includes a pair of
floating gates, and a word line and an erase gate over each
floating gate, wherein for each floating gate, the respective word
line overlaps the respective floating gate by a first lateral
distance and the respective erase gate overlaps the respective
floating gate by a second lateral distance that is substantially
greater than the first lateral distance.
[0018] The concepts disclosed herein, e.g., the concepts of
decoupling the program FG overlap from the erase FG overlap, with a
substantial difference between the program (word line) overlap and
erase overlap (i.e., a substantially asymmetric program/erase FG
overlap) to optimize the program and erase coupling independently
(e.g., to maximize or optimize the Ir1/Ir0 difference), may apply
to any suitable memory cell, e.g., certain flash memory cells or
other memory cells including a floating gate. For example, the
concepts disclosed herein may be applied to the type of memory cell
shown in FIG. 3, e.g., by shifting the FG-overlying portions of the
word lines and erase gate laterally to provide a substantially
asymmetrical program/erase FG overlap over each respective floating
gate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Example aspects of the present disclosure are described
below in conjunction with the figures, in which:
[0020] FIG. 1 illustrates a partial cross-sectional view of an
example conventional memory cell including a Poly1 floating gate
and a Poly2 common program/erase gate extending partially over the
floating gate.
[0021] FIG. 2 illustrates an example mirrored memory cell (e.g., a
SuperFlash cell) including two floating gates.
[0022] FIG. 3 illustrates another example mirrored memory cell
(e.g., a SuperFlash cell) including two floating gates, a word line
formed over each floating gate, and a common erase gate formed over
both floating gates, such that for each floating gate, the program
and erase couplings to the floating gate are decoupled.
[0023] FIG. 4 illustrates a cross-section of an example memory cell
formed according to an embodiment of the present invention.
[0024] FIG. 5 illustrates an example method of forming the example
memory cell structure shown in FIG. 4.
[0025] FIG. 6 illustrates a cross-section of an example another
example memory cell formed according to an embodiment of the
present invention.
[0026] FIG. 7 illustrates an example method of forming the example
memory cell structure shown in FIG. 6.
[0027] FIG. 8 illustrates a more detailed example method of forming
the example memory cell shown in FIG. 6.
DETAILED DESCRIPTION
[0028] Embodiments of the present disclosure provide a memory cell
(e.g., flash memory cell) and method for forming a memory cell
having at least one floating gate, and a word line (or other
program node) and erase gate (or other erase node) associated with
the floating gate, wherein (a) the word line and erase gate are
decoupled from each other and (b) the extent to which the word line
and erase gate overlap the floating gate is asymmetrical, e.g., the
erase gate overlaps the floating gate by a substantially greater
extent then the word line overlaps the floating gate. This
configuration allows the program and erase coupling to the floating
gate to be optimized independently, e.g., to decrease or minimize
the program current and/or increase or maximize the erase current
for the cell.
[0029] FIG. 4 illustrates a cross-section of an example memory cell
structure 100 formed according to an embodiment of the present
invention. Memory cell structure 100 includes a floating gate 104
formed over a substrate 102, an oxide region 106 formed over the
floating gate 104, tunnel oxide layer 108 formed over the floating
gate 104/oxide 106 structure, a word line 110 extending over a
first side of the floating gate 104, and an erase gate 112
extending partially over a second side of the floating gate 104. In
some embodiments, the floating gate 104 is formed from in a Poly1
layer, and the word line 110 and erase gate 112 are formed (e.g.,
simultaneously) from a poly2 layer, using known IC manufacturing
techniques.
[0030] As shown, the word line 110 overlaps the floating gate 104
by a lateral distance indicated as "WL/FG overlap," while the erase
gate 112 overlaps the floating gate 104 by a lateral distance
indicated as "EG/FG overlap," which is substantially greater than
the WL/FG overlap, to thereby define a substantial asymmetry
between the program FG overlap and the erase FG overlap, as
discussed above. In some embodiments, the WL/FG overlap is at least
1.5 times, at least 2 times, at least 3 times, at least 4 times, at
least 5 times, at least 6 times, at least 7 times, at least 8
times, at least 9 times, or at least 10 times as great as the WL/FG
overlap.
[0031] FIG. 5 illustrates an example method 150 of forming the
example memory cell structure 100 shown in FIG. 4. At 152, a gate
oxidation is performed or occurs on a top surface of substrate 102.
At 154, a poly1 layer is deposited over the substrate 102. At 156,
a nitride layer is deposited over the poly1 layer 102. At 158, a
floating gate structure is formed from the poly1 layer, e.g., by a
FG lithography and nitride etch process. At 160, a FG poly
oxidation is performed, which may form a football-shaped oxide over
the floating gate structure and define the concave upper surface of
the floating gate structure. At 162, an HDP oxide deposition may be
performed over the football-shaped oxide. At 164, a CMP may be
performed on the HDP oxide to define the flat-topped oxide region
106 shown in FIG. 4. At 166, a floating gate nitride removal
process may be performed. At 168, a poly1 etch may be performed to
define the shape of floating gate 104 shown in FIG. 4, by removing
the portions of poly1 on the lateral side of the illustrated
floating gate 104.
[0032] At 170, a sacrificial spacer layer may be deposited over the
structure. For example, the spacer layer may comprise a nitride
layer having a thickness in the range of 200 .ANG.-600 .ANG., or in
the range of 300 .ANG.-500 .ANG., e.g., a thickness of about 400
.ANG.. At 172, a HVII (High Voltage Ion Implant) source implant may
be performed, to form a source implant region in the substrate 102
that may be self-aligned with the external lateral edge of the
spacer layer. The source implant region may diffuse to define a
source region that extends laterally under the floating gate 104.
The spacer layer may then be removed at 174. A tunnel oxide 108 may
then be formed, e.g., grown, over the structure at 176. At 178, a
poly2 layer may be deposited over the structure. At 180, a poly2
etch may be performed to define the word line 110 and erase gate
112, as shown in FIG. 4.
[0033] FIG. 6 illustrates a portion of another example memory cell
200 formed according to an embodiment of the present invention. In
particular, FIG. 5 shows a flat-top floating gate 204, a flat-top
oxide cap or "stud" region 206 formed over the flat-top floating
gate 204, a word line 210 extending over a first side of the
floating gate 204, and an erase gate 212 extending partially over a
second side of the floating gate 204. The flat-top floating gate
204 and the overlying flat-top oxide cap or "stud" region 206 may
be formed in any suitable manner, for example using the method
shown in FIG. 7 or 8, discussed below.
[0034] FIG. 6 illustrates certain advantages resulting from the
substantially asymmetrical program/erase FG overlap over the
flat-top floating gate 204 and flat-top oxide cap 206. For example,
reducing the WL/FG overlap may allow for a reduction in the
floating gate 204 height/thickness (TFG) and/or doping, which may
decrease unwanted sidewall coupling between the word line (poly2)
210 and floating gate (poly1) 204. As another example, increasing
the EG/FG overlap may allow a reduction of the oxide cap
height/thickness (Toc), which may increase the coupling between the
erase gate (poly2) 212 and floating gate (poly1) 204. Thus, the
flat-top FG cell 200 may allow independent control of the poly1
thickness (TFG) and/or doping, and the oxide cap thickness Toc.
[0035] FIG. 7 illustrates an example method 250 of forming the
example memory cell structure 200 shown in FIG. 6. At 252, a gate
oxidation is performed or occurs on a top surface of substrate 202.
At 254, a poly1 layer is deposited over the substrate 202. At 256,
a nitride layer is deposited over the poly1 layer 202. At 258, a
flat-topped floating gate structure is formed from the poly1 layer,
e.g., by a FG lithography and nitride etch process. At 260, an HDP
oxide deposition may be performed directly on the flat-topped
floating gate structure. Thus, unlike example method 150 (FIG. 5)
to form the cell structure 100 shown in FIG. 4, in this embodiment
the FG poly oxidation step to form a football-shaped oxide over the
floating gate structure (step 160 of method 150 discussed above)
may be omitted. At 262, a CMP may be performed on the HDP oxide to
define the flat-topped oxide region 206 shown in FIG. 4. At 264, a
floating gate nitride removal process may be performed. At 266, a
poly1 etch may be performed to define the shape of floating gate
204 shown in FIG. 4, by removing the portions of poly1 on the
lateral side of the illustrated floating gate 204.
[0036] At 268, a sacrificial spacer layer may be deposited over the
structure. Due to reduced oxide pullback, the required or optimal
thickness of spacer layer may be reduced as compared with the
spacer layer used in the formation of memory cell structure 100
shown in FIG. 4, e.g., at step 170 of method 150 shown in FIG. 5
and discussed above. For example, the spacer layer may comprise a
nitride layer having a thickness in the range of 100 .ANG.-400
.ANG., or in the range of 150 .ANG.-300 .ANG., e.g., a thickness of
about 200 .ANG.. At 270, a HVII (High Voltage Ion Implant) source
implant may be performed, to form a source implant region in the
substrate 202 that may be self-aligned with the external lateral
edge of the spacer layer. The source implant region may diffuse to
define a source region that extends laterally under the floating
gate 204. The spacer layer may be removed at 272. A tunnel oxide
208 may then be formed, e.g., grown, over the structure at 274. At
276, a poly2 layer may be deposited over the structure. At 278, a
poly2 etch may be performed to define the word line 210 and erase
gate 212, as shown in FIG. 4.
[0037] FIG. 8 illustrates another example method 300 of forming the
example memory cell structure 200 shown in FIG. 6. At 302, a gate
clean oxidation is performed on a top surface of substrate 202. At
304, a FG poly (poly1) layer is deposited over the substrate 202.
At 306, a FG poly implant is performed. At 308, a FG nitride clean
and deposition is performed. At 310, a FG photoresist is formed. At
312, a FG nitride etch is performed. At 314, a cell Vt (voltage
threshold) implant is performed. At 316, a resist strip is
performed. At 318, a wet clean is performed. At 320, a FG poly
oxide clean is performed.
[0038] At 322, an HDP oxide deposition is performed over the
floating gate structure, with a selected oxide thickness, e.g., in
the range of 1000 .ANG.-2500 .ANG., or in the range of 1300
.ANG.-2000 .ANG., or in the range of 1500 .ANG.-1800 .ANG., e.g., a
thickness of about 1650 .ANG.. At 324, a FG oxide CMP is performed,
e.g., to a depth that leaves approximately 1200 .ANG. of the
nitride layer. At 326, a FG nitride removal may be performed, e.g.,
a plasma etch to remove the 1200A nitride thickness. At 328, a FG
top up implant may be performed. At 330, a wet clean is performed.
At 332, a POP (poly oxide poly) photoresist is formed. At 334, a
FG/POP etch and in-situ ash process is performed. At 336, a resist
strip is performed. At 338, a sacrificial FG nitride spacer is
deposited over the structure. At 340, a HVII (High Voltage Ion
Implant) photoresist is formed. At 342, an HVII source implant is
performed. At 344, a resist strip is performed. At 346, the FG
nitride spacer is removed. At 348, a tunnel oxide 108 may be
formed, e.g., grown, over the structure. At 350, a poly2 layer is
deposited over the structure. At 352, a poly2 etch may be performed
to define the word line and erase gate.
[0039] The present invention has been described in terms of one or
more preferred embodiments, and it should be appreciated that many
equivalents, alternatives, variations, and modifications, aside
from those expressly stated (e.g., methods of manufacturing,
product by process, and so forth), are possible and within the
scope of the invention.
* * * * *