U.S. patent application number 16/223497 was filed with the patent office on 2019-06-27 for image sensing device and image sensing system.
The applicant listed for this patent is CANON KABUSHIKI KAISHA. Invention is credited to Hisashi Takado.
Application Number | 20190199978 16/223497 |
Document ID | / |
Family ID | 66950934 |
Filed Date | 2019-06-27 |
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United States Patent
Application |
20190199978 |
Kind Code |
A1 |
Takado; Hisashi |
June 27, 2019 |
IMAGE SENSING DEVICE AND IMAGE SENSING SYSTEM
Abstract
An image sensing device includes a plurality of pixels and a
receiver configured to receive, from an outside, a trigger signal
that gives a first timing and a second timing. Each of the
plurality of pixels includes a photoelectric converter, a first
charge holding portion configured to hold charges generated by the
photoelectric converter, and a second charge holding portion
configured to hold charges generated by the photoelectric
converter. In each of the plurality of pixels, the charges whose
accumulation is started in the photoelectric converter in
accordance with the first timing are held by the first charge
holding portion, and the charges whose accumulation is started in
the photoelectric converter in accordance with the second timing
are held by the second charge holding portion.
Inventors: |
Takado; Hisashi;
(Kawasaki-shi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
CANON KABUSHIKI KAISHA |
Tokyo |
|
JP |
|
|
Family ID: |
66950934 |
Appl. No.: |
16/223497 |
Filed: |
December 18, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H04N 5/3532 20130101;
H04N 5/37452 20130101; H04N 5/2257 20130101; H04N 5/3765 20130101;
H04N 5/23227 20180801; H04N 7/188 20130101; H04N 5/3741
20130101 |
International
Class: |
H04N 7/18 20060101
H04N007/18; H04N 5/374 20060101 H04N005/374; H04N 5/378 20060101
H04N005/378; H04N 5/353 20060101 H04N005/353 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 22, 2017 |
JP |
2017-246399 |
Claims
1. An image sensing device comprising: a plurality of pixels; and a
receiver configured to receive, from an outside, a trigger signal
that gives a first timing and a second timing, wherein each of the
plurality of pixels includes a photoelectric converter, a first
charge holding portion configured to hold charges generated by the
photoelectric converter, and a second charge holding portion
configured to hold charges generated by the photoelectric
converter, and in each of the plurality of pixels, the charges
whose accumulation is started in the photoelectric converter in
accordance with the first timing are held by the first charge
holding portion, and the charges whose accumulation is started in
the photoelectric converter in accordance with the second timing
are held by the second charge holding portion.
2. The device according to claim 1, wherein each of the plurality
of pixels includes a first transfer portion configured to transfer
the charges in the photoelectric converter to the first charge
holding portion, a second transfer portion configured to transfer
the charges held by the first charge holding portion to the second
charge holding portion, a pixel output portion, and a third
transfer portion configured to transfer the charges held by the
second charge holding portion to the pixel output portion.
3. The device according to claim 2, wherein after a signal
corresponding to the charges held by the second charge holding
portion is read out, the charges held by the first charge holding
portion are transferred to the second charge holding portion by the
second transfer portion, and a signal corresponding to the charges
transferred to the second charge holding portion is read out.
4. The device according to claim 1, wherein each of the plurality
of pixels includes a first transfer portion configured to transfer
the charges in the photoelectric converter to the first charge
holding portion, a second transfer portion configured to transfer
the charges in the photoelectric converter to the second charge
holding portion, a pixel output portion, a third transfer portion
configured to transfer the charges held by the first charge holding
portion to the pixel output portion, and a fourth transfer portion
configured to transfer the charges held by the second charge
holding portion to the pixel output portion.
5. The device according to claim 4, wherein in a case in which the
second timing is given by the trigger signal before a signal
corresponding to the charges held by the first charge holding
portion is read out, the accumulation of the charges is started in
the photoelectric converter in accordance with the second
timing.
6. The device according to claim 1, wherein the receiver includes a
first terminal configured to receive, from the outside, a first
trigger signal that gives the first timing, and a second terminal
configured to receive, from the outside, a second trigger signal
that gives the second timing.
7. The device according to claim 5, wherein the receiver includes a
first terminal configured to receive, from the outside, a first
trigger signal that gives the first timing, and a second terminal
configured to receive, from the outside, a second trigger signal
that gives the second timing.
8. The device according to claim 1, wherein the trigger signal
gives the first timing at one of a leading edge and a trailing edge
and gives the second timing at the other of the leading edge and
the trailing edge.
9. The device according to claim 5, wherein the trigger signal
gives the first timing at one of a leading edge and a trailing edge
and gives the second timing at the other of the leading edge and
the trailing edge.
10. The device according to claim 1, further comprising a
synchronization signal terminal configured to receive a
synchronization signal from the outside, wherein a signal
corresponding to the charges held by the first charge holding
portion and a signal corresponding to the charges held by the
second charge holding portion are read out in accordance with the
synchronization signal.
11. The device according to claim 1, wherein each of the plurality
of pixels performs a global electronic shutter operation.
12. The device according to claim 1, wherein each of the plurality
of pixels performs a rolling shutter operation.
13. The device according to claim 1, wherein the trigger signals
are complementary signals.
14. An image sensing system comprising: a detector configured to
detect an occurrence of an event and generate a detection signal;
and an image sensing device of claim 1, wherein the image sensing
device receives the detection signal as the trigger signal by the
receiver.
15. The system according to claim 14, wherein the occurrence of the
event is approach of an object.
16. A moving apparatus comprising: a detector configured to detect
an event and generate a detection signal; an image sensing device
of claim 1; an obtaining unit configured to obtain distance
information up to a target object from a parallax image based on a
signal output from each pixel of the image sensing device; and a
controller configured to control the target object based on the
distance information, wherein the image sensing device receives the
detection signal as the trigger signal by the receiver.
17. The apparatus according to claim 16, wherein an occurrence of
the event is approach of an object.
Description
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The present invention relates to an image sensing device and
an image sensing system.
Description of the Related Art
[0002] In recent years, image sensing devices including a plurality
of memories in a pixel have been proposed for the purpose of
attaining high image quality and/or multiple functions.
US-2013-0135486 describes an image sensing device in which each
pixel includes a plurality of accumulation nodes to expand the
dynamic range. More specifically, each pixel described in
US-2013-0135486 includes a photodiode, a first accumulation node, a
second accumulation node, a first transfer gate, and a second
transfer gate. The first transfer gate transfers charges
accumulated in the photodiode during a time TA to the first
accumulation node, and the second transfer gate transfers charges
accumulated in the photodiode during a time TB to the second
accumulation node. In one exposure, a cycle including TA and TB is
repeated as times TA, TB, TA, TB . . . .
[0003] The image sensing device described in US-2013-0135486 starts
image sensing at timings different from each other and is therefore
advantageous in, for example, sensing an object that moves at a
high speed at timings different from each other. In the image
sensing device described in US-2013-0135486, however, arbitrary
timings different from each other cannot be given from the outside
as the timing of the start of image sensing. Hence, the image
sensing device described in US-2013-0135486 cannot start image
sensing of an object that moves at a high speed or an object that
can arbitrarily appear at each of arbitrary timings that do not
synchronize with each other. Examples of the object that moves at a
high speed and the object that can arbitrarily appear are an
automobile that moves on a road and an article that moves on a
conveyor.
SUMMARY OF THE INVENTION
[0004] The present invention provides a technique advantageous in
starting image sensing of an object that moves at a high speed or
an object that can arbitrarily appear at each of arbitrary timings
that do not synchronize with each other.
[0005] One of aspects of the present invention provides an image
sensing device comprises a plurality of pixels, and a receiver
configured to receive, from an outside, a trigger signal that gives
a first timing and a second timing, wherein each of the plurality
of pixels includes a photoelectric converter, a first charge
holding portion configured to hold charges generated by the
photoelectric converter, and a second charge holding portion
configured to hold charges generated by the photoelectric
converter, and in each of the plurality of pixels, the charges
whose accumulation is started in the photoelectric converter in
accordance with the first timing are held by the first charge
holding portion, and the charges whose accumulation is started in
the photoelectric converter in accordance with the second timing
are held by the second charge holding portion.
[0006] Further features of the present invention will become
apparent from the following description of exemplary embodiments
with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a block diagram showing the schematic arrangement
of an image sensing device according to the first embodiment;
[0008] FIG. 2 is a circuit diagram showing an equivalent circuit of
the pixels of the image sensing device according to the first
embodiment;
[0009] FIG. 3 is a timing chart conceptually showing the operation
of the image sensing device according to the first embodiment;
[0010] FIGS. 4A and 4B are timing charts showing the operation of
the image sensing device according to the first embodiment;
[0011] FIG. 5 is a circuit diagram showing an equivalent circuit of
the pixels of an image sensing device according to the second
embodiment;
[0012] FIG. 6 is a timing chart conceptually showing the operation
of the image sensing device according to the second embodiment;
[0013] FIGS. 7A to 7C are timing charts showing the operation of
the image sensing device according to the second embodiment;
[0014] FIG. 8 is a block diagram showing the schematic arrangement
of an image sensing device according to the third embodiment;
[0015] FIG. 9 is a timing chart conceptually showing the operation
of the image sensing device according to the third embodiment;
[0016] FIG. 10 is a timing chart showing the operation of the image
sensing device according to the third embodiment;
[0017] FIG. 11 is a block diagram showing the schematic arrangement
of an image sensing device according to the fourth embodiment;
[0018] FIG. 12 is a timing chart conceptually showing the operation
of the image sensing device according to the fourth embodiment;
[0019] FIG. 13 is a timing chart showing an operation of the image
sensing device according to the fourth embodiment;
[0020] FIG. 14 is a timing chart showing another operation of the
image sensing device according to the fourth embodiment;
[0021] FIG. 15 is a timing chart conceptually showing the operation
of an image sensing device according to the fifth embodiment;
[0022] FIGS. 16A and 16B are timing charts showing the operation of
the image sensing device according to the fifth embodiment;
[0023] FIG. 17 is a timing chart conceptually showing the operation
of an image sensing device according to the sixth embodiment;
[0024] FIG. 18 is a block diagram showing the arrangement of an
image sensing system according to an embodiment of the present
invention; and
[0025] FIGS. 19A and 19B are views showing the arrangement of a
moving apparatus according to an embodiment of the present
invention.
DESCRIPTION OF THE EMBODIMENTS
[0026] The present invention will now be described with reference
to the accompanying drawings by way of exemplary embodiments. In
this specification and the accompanying drawings, a signal line and
a signal output to the signal line will sometimes be denoted by the
same reference numerals or names.
[0027] An image sensing device according to the first embodiment of
the present invention will be described with reference to FIGS. 1,
2, 3, 4A, and 4B. FIG. 1 shows the schematic arrangement of an
image sensing device ISD according to the first embodiment. The
image sensing device ISD can include a pixel array 100, a vertical
scanning circuit 101, a column amplifier circuit 102, a horizontal
scanning circuit 103, an output circuit 104, a control circuit 105,
and a receiver IP. The receiver IP receives, from the outside,
trigger signals that give a first timing and a second timing that
do not synchronize with each other. The receiver IP can include,
for example, a first external trigger terminal (first terminal) 106
and a second external trigger terminal (second terminal) 107. The
first external trigger terminal 106 can receive, from the outside,
a first external trigger signal (first trigger signal) that gives
the first timing. The second external trigger terminal 107 can
receive, from the outside, a second external trigger signal (second
trigger signal) that gives the second timing. The pixel array 100
includes a plurality of pixels 20 arranged to form a plurality of
rows and a plurality of columns. The vertical scanning circuit 101
is a row selection circuit that selects (the pixels 20 of) a read
target row of the plurality of rows of the pixel array 100. The
vertical scanning circuit 101 drives (the pixels 20 of) the
plurality of rows of the pixel array 100. The vertical scanning
circuit 101 can include, for example, a logic circuit such as a
shift register or an address decoder.
[0028] Each of the plurality of rows of the pixel array 100 is
provided with a vertical output line 10, and signals from the
pixels 20 can be output to the vertical output lines 10. The column
amplifier circuit 102 includes a plurality of amplifiers
corresponding to the plurality of vertical output lines 10,
respectively, and amplifies a plurality of signals to be output to
the plurality of vertical output lines 10. The column amplifier
circuit 102 can be configured to perform, for example, correlated
double sampling processing based on signals at the time of reset of
the pixels 20 and signals by the photoelectric conversion of the
pixels 20. The horizontal scanning circuit 103 can include, for
example, a plurality of switches connected to the plurality of
amplifiers of the column amplifier circuit 102, respectively, and a
selection circuit configured to generate a plurality of control
signals to control the plurality of switches, respectively. The
output circuit 104 is formed by, for example, a buffer amplifier, a
differential amplifier, and the like, and outputs a signal from the
column amplifier circuit 102 to a signal processing unit outside
the image sensing device ISD. The column amplifier circuit 102 or
the output circuit 104 may be provided with an A/D converter, and a
digital image signal may be output from the image sensing device
ISD.
[0029] The control circuit 105 can control the vertical scanning
circuit 101, the column amplifier circuit 102, the horizontal
scanning circuit 103, and the output circuit 104. In addition, the
control circuit 105 can control the plurality of pixels 20 of the
pixel array 100 via the control of the vertical scanning circuit
101. More specifically, the control circuit 105 controls the
plurality of pixels 20 of the pixel array 100 via the control of
the vertical scanning circuit 101 in accordance with the first
external trigger signal and the second external trigger signal
supplied from the outside via the first external trigger terminal
106 and the second external trigger terminal 107.
[0030] FIG. 2 shows the arrangement of a part of the pixel array
100 of the image sensing device ISD. More specifically, FIG. 2
shows 2 rows.times.2 columns=4 pixels 20 in the pixel array 100.
Each of the plurality of pixels 20 can include a photoelectric
converter 1, a first charge holding portion 2, a second charge
holding portion 3, a floating diffusion (third charge holding
portion) 4, a first transfer transistor (first transfer portion) 5,
and a second transfer transistor (second transfer portion) 6.
Additionally, each of the plurality of pixels 20 can include a
third transfer transistor (third transfer portion) 7, a selection
transistor 9, a reset transistor 11, an amplification transistor
12, and an overflow transistor 14.
[0031] The photoelectric converter 1 is arranged in a semiconductor
substrate, photoelectrically converts incident light, and
accumulates charges generated by the photoelectric conversion. When
a first transfer signal line pGS1 connected to the gate of the
first transfer transistor 5 is driven to active level, the first
transfer transistor 5 is turned on and transfers the charges in the
photoelectric converter 1 to the first charge holding portion 2.
The first transfer transistor 5 can be configured to transfer all
the charges in the photoelectric converter 1 to the first charge
holding portion 2. The first charge holding portion 2 temporarily
holds the charges transferred by the first transfer transistor 5.
The first charge holding portion 2 can be configured to, for
example, have a region that is arranged in the semiconductor
substrate in which the photoelectric converter 1 is arranged and
changes to a depletion region, and hold the charges in the
region.
[0032] When a second transfer signal line pGS2 connected to the
gate of the second transfer transistor 6 is driven to active level,
the second transfer transistor 6 is turned on and transfers the
charges held by the first charge holding portion 2 to the second
charge holding portion 3. The second transfer transistor 6 can be
configured to transfer all the charges held by the first charge
holding portion 2 to the second charge holding portion 3. The
second charge holding portion 3 temporarily holds the charges
transferred by the second transfer transistor 6. The second charge
holding portion 3 can be configured to, for example, have a region
that is arranged in the semiconductor substrate in which the
photoelectric converter 1 and the first charge holding portion 2
are arranged and changes to a depletion region, and hold the
charges in the region.
[0033] When a third transfer signal line pTX connected to the gate
of the third transfer transistor 7 is driven to active level, the
third transfer transistor 7 is turned on and transfers the charges
held by the second charge holding portion 3 to the floating
diffusion (third charge holding portion) 4. The third transfer
transistor 7 can be configured to transfer all the charges held by
the second charge holding portion 3 to the floating diffusion 4.
The floating diffusion 4 can be configured to, for example, have a
region that is arranged in the semiconductor substrate in which the
photoelectric converter 1, the first charge holding portion 2, and
the second charge holding portion 3 are arranged and changes to a
depletion region, and hold the charges in the region.
[0034] The amplification transistor 12 can form, for example, a
source follower circuit together with a current source (not shown)
connected to the vertical output line 10 and output a signal
corresponding to the voltage of the floating diffusion 4 to the
vertical output line 10 via the selection transistor 9. The
amplification transistor 12 is a pixel output portion that outputs
a signal corresponding to the voltage of the floating diffusion 4.
When a reset signal line pRES connected to the gate of the reset
transistor 11 is driven to active level, the reset transistor 11 is
turned on and can reset the voltage of the floating diffusion 4 to
a voltage corresponding to the voltage of a power supply line 13.
When a discharge signal line pOFD connected to the gate of the
overflow transistor 14 is driven to active level, the overflow
transistor 14 is turned on and can discharge the charges
accumulated in the photoelectric converter 1 to the power supply
line 13.
[0035] A common control signal is supplied from the vertical
scanning circuit 101 to the pixels 20 of the same row. More
specifically, control signal lines pGS1(m), pGS2(m), and pTX(m) are
connected to the gates of the first transfer transistors 5, the
second transfer transistors 6, and the third transfer transistors 7
of the pixels 20 of the mth row, respectively. In addition, control
signal lines pSEL(m), pRES(m), and pOFD(m) are connected to the
gates of the selection transistors 9, the reset transistors 11, and
the overflow transistors 14 of the pixels 20 of the mth row,
respectively. In this example, these transistors are turned on when
the voltages of the control signal lines are at high level (active
level) and off when the voltages are at low level (inactive level).
pGS1(m) can also be called a first transfer signal line, pGS2(m)
can also be called a second transfer signal line, pTX(m) can also
be called a third transfer signal line, pSEL(m) can also be called
a selection signal line, pRES(m) can also be called a reset signal
line, and pOFD(m) can also be called a discharge signal line.
[0036] A driving method of the image sensing device ISD according
to the first embodiment will be described next with reference to
FIG. 3. FIG. 3 conceptually shows the driving method of the image
sensing device ISD according to the first embodiment. Referring to
FIG. 3, the arrow from the photoelectric converter to the first
charge holding portion means transfer of charges in a global
electronic shutter operation. In FIG. 3, operations concerning the
nth frame are indicated by solid lines, and operations concerning
the (n+1)th frame and the (n-1)th frame are indicated by broken
lines. The driving method of the image sensing device ISD is the
same in the nth frame and the (n+1)th frame. Hence, in this
specification, a description will be made while placing focus
mainly on the operation of the nth frame.
[0037] At time T0, the control circuit 105 detects the trailing
edge of the first external trigger signal (pulse signal) supplied
to the first external trigger terminal 106, accordingly generates a
first trigger pulse, and causes the photoelectric converter 1 to
start accumulating charges with reference to the first trigger
pulse. At time T1, the control circuit 105 causes the photoelectric
converter 1 to transfer charges PD1(n) accumulated in it during the
period from time T0 to time T1 to the first charge holding portion
2 via the first transfer transistor 5 and causes the first charge
holding portion 2 to hold the charges. This transfer is performed
at once in all the pixels 20 of the pixel array 100. In FIG. 3, the
charges held by the first charge holding portion 2 are represented
by MEM1(n). When the transfer ends at time T1, the control circuit
105 causes the photoelectric converter 1 to discharge the charges
to the power supply line 13 via the overflow transistor 14.
[0038] At time T2, the control circuit 105 detects the trailing
edge of the second external trigger signal (pulse signal) supplied
to the second external trigger terminal 107, accordingly generates
a second trigger pulse, and causes the photoelectric converter 1 to
start accumulating charges with reference to the second trigger
pulse. At time T3, the control circuit 105 causes the first charge
holding portion 2 to transfer the charges (the charges MEM1(n)
whose accumulation is started in accordance with the first trigger
pulse and which are then transferred to the first charge holding
portion 2) held by the first charge holding portion 2 to the second
charge holding portion 3 via the second transfer transistor 6.
After that, the control circuit 105 causes the photoelectric
converter 1 to transfer charges PD2(n) accumulated in it during the
period from time T2 to time T3 to the first charge holding portion
2 via the first transfer transistor 5 and causes the first charge
holding portion 2 to hold the charges. This transfer is performed
at once in all the pixels 20 of the pixel array 100.
[0039] The control circuit 105 controls a read operation such that
a signal corresponding to the charges MEM1(n) whose accumulation is
started in accordance with the first trigger pulse is
row-sequentially read out from the second charge holding portion 3
during the period from the transfer end time of time T3 to time T4.
The read operation is performed by controlling the vertical
scanning circuit 101, the column amplifier circuit 102, the
horizontal scanning circuit 103, and the output circuit 104 by the
control circuit 105.
[0040] At time T4, the control circuit 105 causes the first charge
holding portion 2 to transfer the charges (charges MEM2(n) whose
accumulation is started in accordance with the second trigger pulse
and which are then transferred to the first charge holding portion
2) held by the first charge holding portion 2 to the second charge
holding portion 3 via the second transfer transistor 6. This
transfer is performed at once in all the pixels 20 of the pixel
array 100.
[0041] The control circuit 105 controls the read operation such
that the charges MEM2(n) whose accumulation is started in
accordance with the second trigger pulse are row-sequentially read
out from the second charge holding portion 3 during the period from
the transfer end time of time T4 to time T5. The read operation is
performed by controlling the vertical scanning circuit 101, the
column amplifier circuit 102, the horizontal scanning circuit 103,
and the output circuit 104 by the control circuit 105.
[0042] The driving method of the image sensing device ISD according
to the first embodiment will be described next in more detail with
reference to FIGS. 4A and 4B. Note that in the following
explanation of timing charts, a control signal used to control the
pixels 20 of the mth row will be described with (m) added to the
end of the name of the control signal. When making a description
without particularly distinction between rows, a description will
be made without adding a character to the end of the control signal
name.
[0043] As shown in FIG. 4A, at time T0, the control circuit 105
detects the trailing edge of a first external trigger signal
EXTTRG1 supplied to the first external trigger terminal 106, and
accordingly generates a first trigger pulse pTRG1. According to the
leading edge of the first trigger pulse pTRG1, the voltage of the
discharge signal line pOFD transitions from high level to low
level, and the overflow transistor 14 is turned off. Accordingly,
the photoelectric converter 1 starts accumulating charges
corresponding to incident light. Based on a charge accumulation
time defined by a parameter value set in the register (not shown)
of the image sensing device ISD, the control circuit 105 controls
pulse driving of the first transfer signal line pGS1 such that the
voltage of the first transfer signal line pGS1 transitions from
high level to low level at time T1. Accordingly, at time T1, the
first transfer transistor 5 is turned off, and the charge transfer
from the photoelectric converter 1 to the first charge holding
portion 2 ends.
[0044] At time T2, the control circuit 105 detects the trailing
edge of a second external trigger signal EXTTRG2 supplied to the
second external trigger terminal, and accordingly generates a
second trigger pulse pTRG2. According to the leading edge of the
second trigger pulse pTRG2, the voltage of the discharge signal
line pOFD transitions from high level to low level, and the
overflow transistor 14 is turned off. Accordingly, the
photoelectric converter 1 starts (resumes) accumulating charges
corresponding to incident light. Based on a charge accumulation
time defined by a parameter value set in the register (not shown)
of the image sensing device ISD, the control circuit 105 controls
pulse driving of the first transfer signal line pGS1 such that the
voltage of the first transfer signal line pGS1 transitions from
high level to low level at time T3. Accordingly, at time T3, the
first transfer transistor 5 is turned off, and the charge transfer
from the photoelectric converter 1 to the first charge holding
portion 2 ends.
[0045] In addition, at time T41 before time T3, the control circuit
105 controls pulse driving of the second transfer signal line pGS2
such that the voltage of the second transfer signal line pGS2
transitions from high level to low level. Accordingly, after the
charge transfer from the first charge holding portion 2 to the
second charge holding portion 3 is started, at time T41, the second
transfer transistor 6 is turned off, and the transfer from the
first charge holding portion 2 to the second charge holding portion
3 ends.
[0046] During the period from time T3 to time T4, the control
circuit 105 controls the read operation of the signal corresponding
to the charges transferred to the second charge holding portion 3
and held by the second charge holding portion 3. This read
operation is performed for the pixels 20 of all rows of the pixel
array 100. The read operation will be described later with
reference to FIG. 4B.
[0047] At time T4, the control circuit 105 controls pulse driving
of the second transfer signal line pGS2 such that the voltage of
the second transfer signal line pGS2 transitions from high level to
low level. Accordingly, after the charge transfer from the first
charge holding portion 2 to the second charge holding portion 3 is
started, at time T4, the second transfer transistor 6 is turned
off, and the transfer from the first charge holding portion 2 to
the second charge holding portion 3 ends.
[0048] During the period from time T4 to time T5, the control
circuit 105 controls the read operation of the signal corresponding
to the charges transferred to the second charge holding portion 3
and held by the second charge holding portion 3. This read
operation is performed for the pixels 20 of all rows of the pixel
array 100.
[0049] FIG. 4B shows the read operation from the pixels 20 of the
mth row and the (m+1)th row. At time T42, the control circuit 105
makes the voltage of the selection signal line pSEL(m) transition
from low level to high level via the vertical scanning circuit 101.
The pixels 20 of the mth row are thus selected. Halfway through the
period from time T42 to time T43, the control circuit 105 makes the
voltage of the reset signal line pRES(m) transition to high level
and turns on the reset transistor 11 by the control via the
vertical scanning circuit 101. At time T43, the control circuit 105
makes the voltage of the reset signal line pRES(m) transition to
low level and turns off the reset transistor 11 by the control via
the vertical scanning circuit 101. With this operation, the charges
existing in the floating diffusion 4 are discharged to the power
supply line 13. The voltage (noise signal) of the floating
diffusion 4 is amplified by the source follower operation and
output to the vertical output line 10.
[0050] During the period from time T43 to time T44, the control
circuit 105 causes the column amplifier circuit 102 to read out the
noise signal (N-read). After that, the control circuit 105 makes
the voltage of the third transfer signal line pTX1(m) transition to
high level and turns on the third transfer transistor 7 by control
via the vertical scanning circuit 101. The charges MEM1(n) of the
nth frame are thus transferred from the second charge holding
portion 3 that holds the charges of the pixels 20 of the mth row to
the floating diffusion 4. The voltage (optical signal) of the
floating diffusion 4 is amplified by the source follower operation
and output to the vertical output line 10. At time T44, the control
circuit 105 turns off the voltage of the third transfer signal line
pTX1(m) by control via the vertical scanning circuit 101.
[0051] During the period from time T44 to time T45, the control
circuit 105 causes the column amplifier circuit 102 to read out the
optical signal corresponding to the charges MEM1(n) (S-read). At
time T45, the control circuit 105 makes the voltage of the
selection signal line pSEL(m) transition to low level by control
via the vertical scanning circuit 101, thereby ending selection of
the mth row. In addition, at time T45, the control circuit 105
makes the voltage of a selection signal line pSEL(m+1) transition
to high level, thereby starting selection of the (m+1)th row.
[0052] In the first embodiment, detection of an object is executed
by an external device different from the image sensing device ISD,
and a detection signal representing the detection of the object can
be supplied from the external device to the first and second
external trigger terminals of the image sensing device ISD. The
timing at which the object enters the image sensing range of the
image sensing device ISD and the start of image sensing by the
pixels 20 of the image sensing device ISD (the start of charge
accumulation) can thus be synchronized with each other. In
addition, two external trigger terminals are provided in the image
sensing device ISD to allow the image sensing device ISD to
independently receive two external trigger signals, thereby
controlling the interval of the charge accumulation start timings
asynchronously with the period of the read operation. In addition,
one charge holding portion is caused to hold charges accumulated in
correspondence with the first trigger pulse, and the other charge
holding portion is caused to hold charges accumulated in
correspondence with the second trigger pulse. This enables
continuous image sensing even in a case in which the interval of
image sensing is shorter than the interval of the read
operation.
[0053] Additionally, in this embodiment, since the charge transfer
from the photoelectric converter to the charge holding portion is
performed at once in all the pixels, all the pixels have the same
charge accumulation period, and the effect of a global electronic
shutter without any distortion of the object can be obtained.
However, the operation may be changed to a rolling shutter
operation.
[0054] In the above-described example, the trigger pulse is
generated by detecting the trailing edge of the external trigger
signal. However, the trigger pulse is generated by detecting the
leading edge of the external trigger signal.
[0055] An image sensing device according to the second embodiment
of the present invention will be described with reference to FIGS.
5, 6, and 7A to 7C. Matters that are not mentioned as the second
embodiment can comply with the first embodiment. An image sensing
device ISD according to the second embodiment is different from
that of the first embodiment in that a first charge holding portion
2 and a second charge holding portion 3 are connected in
parallel.
[0056] Each of a plurality of pixels 20 can include a photoelectric
converter 1, the first charge holding portion 2, the second charge
holding portion 3, a floating diffusion (third charge holding
portion) 4, a first transfer transistor (first transfer portion) 5,
and a second transfer transistor (second transfer portion) 6.
Additionally, each of the plurality of pixels 20 includes a third
transfer transistor (third transfer portion) 7, a fourth transfer
transistor (fourth transfer portion) 8, a selection transistor 9, a
reset transistor 11, an amplification transistor 12, and an
overflow transistor 14.
[0057] The photoelectric converter 1 is arranged in a semiconductor
substrate, photoelectrically converts incident light, and
accumulates charges generated by the photoelectric conversion. When
a first transfer signal line pGS1 connected to the gate of the
first transfer transistor 5 is driven to active level, the first
transfer transistor 5 is turned on and transfers the charges in the
photoelectric converter 1 to the first charge holding portion 2.
The first transfer transistor 5 can be configured to transfer all
the charges in the photoelectric converter 1 to the first charge
holding portion 2. The first charge holding portion 2 temporarily
holds the charges transferred by the first transfer transistor 5.
The first charge holding portion 2 can be configured to, for
example, have a region that is arranged in the semiconductor
substrate in which the photoelectric converter 1 is arranged and
changes to a depletion region, and hold the charges in the
region.
[0058] When a second transfer signal line pGS2 connected to the
gate of the second transfer transistor 6 is driven to active level,
the second transfer transistor 6 is turned on and transfers the
charges in the photoelectric converter 1 to the second charge
holding portion 3. That is, when the second transfer signal line
pGS2 connected to the gate of the second transfer transistor 6 is
driven to active level, the second transfer transistor 6 is turned
on and transfers the charges in the photoelectric converter 1 to
the second charge holding portion 3 without an intervention of the
first charge holding portion 2. The second transfer transistor 6
can be configured to transfer all the charges in the photoelectric
converter 1 to the second charge holding portion 3. The second
charge holding portion 3 temporarily holds the charges transferred
by the second transfer transistor 6. The second charge holding
portion 3 can be configured to, for example, have a region that is
arranged in the semiconductor substrate in which the photoelectric
converter 1 and the first charge holding portion 2 are arranged and
changes to a depletion region, and hold the charges in the
region.
[0059] When a third transfer signal line pTX1 connected to the gate
of the third transfer transistor 7 is driven to active level, the
third transfer transistor 7 is turned on and transfers the charges
held by the first charge holding portion 2 to the floating
diffusion (third charge holding portion) 4. The third transfer
transistor 7 can be configured to transfer all the charges held by
the first charge holding portion 2 to the floating diffusion 4. The
floating diffusion 4 can be configured to, for example, have a
region that is arranged in the semiconductor substrate in which the
photoelectric converter 1, the first charge holding portion 2, and
the second charge holding portion 3 are arranged and changes to a
depletion region, and hold the charges in the region.
[0060] When a fourth transfer signal line pTX2 connected to the
gate of the fourth transfer transistor 8 is driven to active level,
the fourth transfer transistor 8 is turned on and transfers the
charges held by the second charge holding portion 3 to the floating
diffusion (third charge holding portion) 4. The fourth transfer
transistor 8 can be configured to transfer all the charges held by
the second charge holding portion 3 to the floating diffusion
4.
[0061] The amplification transistor 12 forms a source follower
circuit together with a current source (not shown) connected to a
vertical output line 10 and outputs a signal corresponding to the
voltage of the floating diffusion 4 to the vertical output line 10
via the selection transistor 9. When a reset signal line pRES
connected to the gate of the reset transistor 11 is driven to
active level, the reset transistor 11 is turned on and resets the
voltage of the floating diffusion 4 to a voltage corresponding to
the voltage of a power supply line 13. When a discharge signal line
pOFD connected to the gate of the overflow transistor 14 is driven
to active level, the overflow transistor 14 is turned on and
discharges the charges accumulated in the photoelectric converter 1
to the power supply line 13.
[0062] A common control signal is supplied from a vertical scanning
circuit 101 to the pixels 20 of the same row. More specifically,
control signal lines pGS1(m), pGS2(m), pTX1(m), and pTX2(m) are
connected to the gates of the first transfer transistors 5, the
second transfer transistors 6, the third transfer transistors 7,
and the fourth transfer transistors 8 of the pixels 20 of the mth
row, respectively. More specifically, control signal lines pSEL(m),
pRES(m), and pOFD(m) are connected to the gates of the selection
transistors 9, the reset transistors 11, and the overflow
transistors 14 of the pixels 20 of the mth row, respectively. In
this example, these transistors are turned on when the voltages of
the control signal lines are at high level (active level) and off
when the voltages are at low level (inactive level). pGS1(m) is
also called a first transfer signal line, pGS2(m) is also called a
second transfer signal line, pTX1(m) is also called a third
transfer signal line, pTX2(m) is also called a fourth transfer
signal line, pSEL(m) is also called a selection signal line,
pRES(m) is also called a reset signal line, and pOFD(m) is also
called a discharge signal line.
[0063] A driving method of the image sensing device ISD according
to the second embodiment will be described next with reference to
FIG. 6. FIG. 6 conceptually shows the driving method of the image
sensing device ISD according to the second embodiment. Referring to
FIG. 6, the arrow from the photoelectric converter to the first and
second charge holding portions means transfer of charges in a
global electronic shutter operation. In FIG. 6, operations
concerning the nth frame are indicated by solid lines, and
operations concerning the (n+1)th frame and the (n-1)th frame are
indicated by broken lines. The driving method of the image sensing
device ISD is the same in the nth frame and the (n+1)th frame.
Hence, in this specification, a description will be made while
placing focus mainly on the operation of the nth frame.
[0064] The image sensing device ISD according to the second
embodiment is different from the image sensing device ISD according
to the first embodiment in that the charge accumulation period
according to the second external trigger signal supplied to a
second external trigger terminal 107 and at least part of the read
operation period of the signal corresponding to the charges held by
the first charge holding portion can overlap.
[0065] At time T0, a control circuit 105 detects the trailing edge
of a first external trigger signal supplied to a first external
trigger terminal 106, accordingly generates a first trigger pulse,
and causes the photoelectric converter 1 to start accumulating
charges with reference to the first trigger pulse. At time T1, the
control circuit 105 causes the photoelectric converter 1 to
transfer charges PD1(n) accumulated in it during the period from
time T0 to time T1 to the first charge holding portion 2 via the
first transfer transistor 5 and causes the first charge holding
portion 2 to hold the charges. This transfer is performed at once
in all the pixels 20 of a pixel array 100. In FIG. 6, the charges
held by the first charge holding portion 2 are represented by
MEM1(n). When the transfer ends at time T1, the control circuit 105
causes the photoelectric converter 1 to discharge the charges to
the power supply line 13 via the overflow transistor 14. The
control circuit 105 controls the read operation such that the
charges MEM1(n) whose accumulation is started in accordance with
the first trigger pulse are row-sequentially read out from the
first charge holding portion 2 during the period from the transfer
end time of time T1 to time T4. The read operation is performed by
controlling the vertical scanning circuit 101, a column amplifier
circuit 102, a horizontal scanning circuit 103, and an output
circuit 104 by the control circuit 105.
[0066] At time T2, the control circuit 105 detects the trailing
edge of the second external trigger signal (pulse signal) supplied
to the second external trigger terminal 107, accordingly generates
a second trigger pulse, and causes the photoelectric converter 1 to
start accumulating charges with reference to the second trigger
pulse. At time T3, the control circuit 105 causes the photoelectric
converter 1 to transfer charges PD2(n) accumulated in it during the
period from time T2 to time T3 to the second charge holding portion
3 via the second transfer transistor 6 and causes the second charge
holding portion 3 to hold the charges. This transfer is performed
at once in all the pixels 20 of the pixel array 100. In FIG. 6, the
charges held by the second charge holding portion 3 are represented
by MEM2(n). When the transfer ends at time T3, the control circuit
105 causes the photoelectric converter 1 to discharge the charges
to the power supply line 13 via the overflow transistor 14.
[0067] At time T3, the read operation of the signal corresponding
to the charges MEM1(n) and the charge accumulation according to the
second external trigger signal supplied to the second external
trigger terminal 107 are performed in parallel. This is implemented
by connecting the first charge holding portion 2 and the second
charge holding portion 3 in parallel.
[0068] At time T4, the read operation of the signal corresponding
to the charges MEM1(n) ends, and the read operation of the signal
corresponding to the charges MEM2(n) starts next. During the period
from time T4 to time T7, the read operation of the signal
corresponding to the charges MEM2(n) is performed.
[0069] At time T5, the second external trigger signal supplied to
the second external trigger terminal 107 changes to low level.
However, since the read operation of the signal corresponding to
the charges MEM2(n) is executed at time T5, the control circuit 105
does not cause the image sensing device ISD to resume accumulation
of charges. On the other hand, at time T6 after the end of the read
operation of the signal corresponding to the charges MEM1(n), the
control circuit 105 detects the trailing edge of the second
external trigger signal supplied to the first external trigger
terminal. According to this detection, the control circuit 105
generates a first trigger pulse and causes the photoelectric
converter 1 to start accumulating charges with reference to the
first trigger pulse.
[0070] At time T8, the control circuit 105 causes the photoelectric
converter 1 to transfer charges PD1(n+1) accumulated in it during
the period from time T0 to time T1 to the first charge holding
portion 2 via the first transfer transistor 5 and causes the first
charge holding portion 2 to hold the charges. This transfer is
performed at once in all the pixels 20 of the pixel array 100. In
FIG. 6, the charges newly held by the first charge holding portion
2 are represented by MEM1(n+1). When the transfer ends at time T8,
the control circuit 105 causes the photoelectric converter 1 to
discharge the charges to the power supply line 13 via the overflow
transistor 14. In addition, after the end of the transfer at time
T8, the control circuit 105 controls the read operation such that
the charges MEM1(n+1) are row-sequentially read out from the first
charge holding portion 2. The read operation is performed by
controlling the vertical scanning circuit 101, the column amplifier
circuit 102, the horizontal scanning circuit 103, and the output
circuit 104 by the control circuit 105.
[0071] The driving method of the image sensing device ISD according
to the second embodiment will be described next in more detail with
reference to FIGS. 7A to 7C. As shown in FIG. 7A, at time T0, the
control circuit 105 detects the trailing edge of a first external
trigger signal EXTTRG1 supplied to the first external trigger
terminal 106, and accordingly generates a first trigger pulse
pTRG1. According to the leading edge of the first trigger pulse
pTRG1, the voltage of the discharge signal line pOFD transitions
from high level to low level, and the overflow transistor 14 is
turned off. Accordingly, the photoelectric converter 1 starts
accumulating charges corresponding to incident light. Based on a
charge accumulation time defined by a parameter value set in the
register (not shown) of the image sensing device ISD, the control
circuit 105 controls pulse driving of the first transfer signal
line pGS1 such that the voltage of the first transfer signal line
pGS1 transitions from high level to low level at time T1.
Accordingly, at time T1, the first transfer transistor 5 is turned
off, and the charge transfer from the photoelectric converter 1 to
the first charge holding portion 2 ends.
[0072] During the period from time T1 to time T4, the control
circuit 105 controls the read operation of the signal corresponding
to the charges transferred to the first charge holding portion 2
and held by the first charge holding portion 2. This read operation
is performed for the pixels 20 of all rows of the pixel array 100.
The read operation will be described later with reference to FIG.
7B.
[0073] At time T2, the control circuit 105 detects the trailing
edge of a second external trigger signal EXTTRG2 supplied to the
second external trigger terminal, and accordingly generates a
second trigger pulse pTRG2. According to the leading edge of the
second trigger pulse pTRG2, the voltage of the discharge signal
line pOFD transitions from high level to low level, and the
overflow transistor 14 is turned off. Accordingly, the
photoelectric converter 1 starts (resumes) accumulating charges
corresponding to incident light. Based on a charge accumulation
time defined by a parameter value set in the register (not shown)
of the image sensing device ISD, the control circuit 105 controls
pulse driving of the second transfer signal line pGS2 such that the
voltage of the second transfer signal line pGS2 transitions from
high level to low level at time T3. Accordingly, at time T3, the
second transfer transistor 6 is turned off, and the charge transfer
from the photoelectric converter 1 to the second charge holding
portion 3 ends.
[0074] At time T4, the read operation of the signal corresponding
to the charges MEM1(n) ends for all rows. During the period from
time T4 to time T7, the control circuit 105 controls the read
operation of the signal corresponding to the charges transferred to
the second charge holding portion 3 and held by the second charge
holding portion 3. This read operation is performed for the pixels
20 of all rows of the pixel array 100. The read operation will be
described later with reference to FIG. 7C.
[0075] At time T5, the second external trigger signal supplied to
the second external trigger terminal (EXTTRG2) changes to low
level. However, since the read operation of the signal
corresponding to the charges MEM2(n) is executed at time T5, the
control circuit 105 does not generate the second trigger pulse.
This prevents the charges from being transferred from the
photoelectric converter 1 to the second charge holding portion 3
during the period of the read operation from the second charge
holding portion 3. For the first external trigger signal supplied
to the first external trigger terminal (EXTTRG1) as well, during
the read operation from the first charge holding portion 2, the
control circuit 105 does not generate the first trigger pulse even
when the first external trigger terminal changes to low level.
[0076] Here, the control circuit 105 can be configured to neglect
the external trigger signal that can cause charge transfer to a
charge holding portion during the period of the read operation from
the charge holding portion. However, more exactly, the conflict
between the period of the read operation from the charge holding
portion and charge transfer to the charge holding portion is caused
by transferring charges to the charge holding portion before the
end of the read operation from the charge holding portion. Hence,
the control circuit 105 may be configured to, for example, specify
the end time of the charge accumulation period based on the charge
accumulation time defined by a parameter value set in the register
(not shown) and not to generate the trigger pulse in a case in
which the end time is within the period of the read operation.
[0077] At time T6, the control circuit 105 detects the trailing
edge of the first external trigger signal EXTTRG1 supplied to the
first external trigger terminal 106, and accordingly generates the
first trigger pulse pTRG1. According to the leading edge of the
first trigger pulse pTRG1, the voltage of the discharge signal line
pOFD transitions from high level to low level, and the overflow
transistor 14 is turned off. Accordingly, the photoelectric
converter 1 starts accumulating charges corresponding to incident
light. Based on a charge accumulation time defined by a parameter
value set in the register (not shown) of the image sensing device
ISD, the control circuit 105 controls pulse driving of the first
transfer signal line pGS1 such that the voltage of the first
transfer signal line pGS1 transitions from high level to low level
at time T8. Accordingly, at time T8, the first transfer transistor
5 is turned off, and the charge transfer from the photoelectric
converter 1 to the first charge holding portion 2 ends.
[0078] FIG. 7B shows the read operation (Read1 in FIG. 7A) from the
first charge holding portions 2 of the pixels 20 of the mth row and
the (m+1)th row. At time T70, the control circuit 105 makes the
voltage of the selection signal line pSEL(m) transition from low
level to high level via the vertical scanning circuit 101. The
pixels 20 of the mth row are thus selected. Halfway through the
period from time T70 to time T71, the control circuit 105 makes the
voltage of the reset signal line pRES(m) transition to high level
and turns on the reset transistor 11 by the control via the
vertical scanning circuit 101. At time T71, the control circuit 105
makes the voltage of the reset signal line pRES(m) transition to
low level and turns off the reset transistor 11 by the control via
the vertical scanning circuit 101. With this operation, the charges
existing in the floating diffusion 4 are discharged to the power
supply line 13. The voltage (noise) signal of the floating
diffusion 4 is amplified by the source follower operation and
output to the vertical output line 10.
[0079] During the period from time T71 to time T72, the control
circuit 105 causes the column amplifier circuit 102 to read out the
noise signal (N-read). After that, the control circuit 105 makes
the voltage of the third transfer signal line pTX1(m) transition to
high level and turns on the third transfer transistor 7 by control
via the vertical scanning circuit 101. The charges MEM1(n) (the
charges accumulated in accordance with the first trigger pulse) of
the nth frame are thus transferred from the first charge holding
portion 2 that holds the charges of the pixels 20 of the mth row to
the floating diffusion 4. The voltage (optical signal) of the
floating diffusion 4 is amplified by the source follower operation
and output to the vertical output line 10. At time T72, the control
circuit 105 turns off the voltage of the third transfer signal line
pTX1(m) by control via the vertical scanning circuit 101.
[0080] During the period from time T72 to time T73, the control
circuit 105 causes the column amplifier circuit 102 to read out the
optical signal corresponding to the charges MEM1(n) (S-read). At
time T73, the control circuit 105 makes the voltage of the
selection signal line pSEL(m) transition to low level by control
via the vertical scanning circuit 101, thereby ending selection of
the mth row. In addition, at time T73, the control circuit 105
makes the voltage of a selection signal line pSEL(m+1) transition
to high level, thereby starting selection of the (m+1)th row.
[0081] FIG. 7C shows the read operation (Read2 in FIG. 7A) from the
first charge holding portions 2 of the pixels 20 of the mth row and
the (m+1)th row. At time T77, the control circuit 105 makes the
voltage of the selection signal line pSEL(m) transition from low
level to high level via the vertical scanning circuit 101. The
pixels 20 of the mth row are thus selected. Halfway through the
period from time T77 to time T78, the control circuit 105 makes the
voltage of the reset signal line pRES(m) transition to high level
and turns on the reset transistor 11 by the control via the
vertical scanning circuit 101. At time T78, the control circuit 105
makes the voltage of the reset signal line pRES(m) transition to
low level and turns off the reset transistor 11 by the control via
the vertical scanning circuit 101. With this operation, the charges
existing in the floating diffusion 4 are discharged to the power
supply line 13. The voltage (noise) signal of the floating
diffusion 4 is amplified by the source follower operation and
output to the vertical output line 10.
[0082] During the period from time T78 to time T79, the control
circuit 105 causes the column amplifier circuit 102 to read out the
noise signal (N-read). After that, the control circuit 105 makes
the voltage of the fourth transfer signal line pTX2(m) transition
to high level and turns on the fourth transfer transistor 8 by
control via the vertical scanning circuit 101. The charges MEM1(n)
(the charges accumulated in accordance with the second trigger
pulse) of the nth frame are thus transferred from the second charge
holding portion 3 that holds the charges of the pixels 20 of the
mth row to the floating diffusion 4. The voltage (optical signal)
of the floating diffusion 4 is amplified by the source follower
operation and output to the vertical output line 10. At time T79,
the control circuit 105 turns off the voltage of the fourth
transfer signal line pTX2(m) by control via the vertical scanning
circuit 101.
[0083] During the period from time T79 to time T710, the control
circuit 105 causes the column amplifier circuit 102 to read out the
optical signal corresponding to the charges MEM1(n) (S-read). At
time T710, the control circuit 105 makes the voltage of the
selection signal line pSEL(m) transition to low level by control
via the vertical scanning circuit 101, thereby ending selection of
the mth row. In addition, at time T710, the control circuit 105
makes the voltage of a selection signal line pSEL(m+1) transition
to high level, thereby starting selection of the (m+1)th row.
[0084] According to the second embodiment, the read operation of
the signal corresponding to the charges accumulated in accordance
with the first external trigger signal and accumulation of the
charges according to the second external trigger signal are
performed in parallel. Hence, the second embodiment is advantageous
for shortening the interval between image sensing and image
sensing. In other words, the second embodiment is advantageous for
an application purpose in which the external trigger signals are
more frequency supplied.
[0085] An image sensing device according to the third embodiment of
the present invention will be described with reference to FIGS. 8,
9, and 10. The third embodiment is a modification of the second
embodiment, and matters that are not mentioned as the third
embodiment can comply with the second embodiment. However, matters
described in the third embodiment may be applied to the image
sensing device ISD according to the first embodiment. FIG. 8 shows
the schematic arrangement of an image sensing device ISD according
to the third embodiment. As shown in FIG. 8, the image sensing
device ISD according to the third embodiment additionally includes
a synchronization signal terminal 108 configured to receive a
vertical synchronization signal from an external device. In the
third embodiment, signals from pixels 20 of a pixel array 100 are
output in accordance with the vertical synchronization signal.
[0086] A driving method of the image sensing device ISD according
to the third embodiment will be described with reference to FIG. 9.
FIG. 9 conceptually shows the driving method of the image sensing
device ISD according to the third embodiment. At time T0, a control
circuit 105 detects the trailing edge of a first external trigger
signal supplied to a first external trigger terminal 106,
accordingly generates a first trigger pulse, and causes a
photoelectric converter 1 to start accumulating charges with
reference to the first trigger pulse. At time T1, the control
circuit 105 detects the leading edge of the first external trigger
signal supplied to the first external trigger terminal 106.
According to the detection of the leading edge, the control circuit
105 causes the photoelectric converter 1 to transfer charges PD1(n)
accumulated in it during the period from time T0 to time T1 to a
first charge holding portion 2 via a first transfer transistor 5
and causes the first charge holding portion 2 to hold the charges.
This transfer is performed at once in all the pixels 20 of the
pixel array 100. When the transfer ends at time T1, the control
circuit 105 causes the photoelectric converter 1 to discharge the
charges to a power supply line 13 via an overflow transistor
14.
[0087] At time T2, the control circuit 105 detects the trailing
edge of a second external trigger signal supplied to a second
external trigger terminal 107, accordingly generates a second
trigger pulse, and causes the photoelectric converter 1 to start
accumulating charges with reference to the second trigger pulse. At
time T3, the control circuit 105 detects the leading edge of the
second external trigger signal supplied to the second external
trigger terminal 107. According to the detection of the leading
edge, the control circuit 105 causes the photoelectric converter 1
to transfer charges PD2(n) accumulated in it during the period from
time T2 to time T3 to a second charge holding portion 3 via a
second transfer transistor 6 and causes the second charge holding
portion 3 to hold the charges. This transfer is performed at once
in all the pixels 20 of the pixel array 100. In FIG. 9, when the
transfer ends at time T3, the control circuit 105 causes the
photoelectric converter 1 to discharge the charges to the power
supply line 13 via the overflow transistor 14.
[0088] At time T4, the control circuit 105 detects the trailing
edge of the first external trigger signal supplied to the first
external trigger terminal 106, accordingly generates the first
trigger pulse, and causes the photoelectric converter 1 to start
accumulating charges with reference to the first trigger pulse. At
time T5, the control circuit 105 detects the leading edge of the
first external trigger signal supplied to the first external
trigger terminal 106. According to the detection of the leading
edge, the control circuit 105 causes the photoelectric converter 1
to transfer charges PD3(n) accumulated in it during the period from
time T4 to time T5 to the first charge holding portion 2 via the
first transfer transistor 5 and causes the first charge holding
portion 2 to hold the charges. This transfer is performed at once
in all the pixels 20 of the pixel array 100. In the first charge
holding portion 2, the already held charges PD1(n) and the charges
PD3(n) newly transferred by the first transfer transistor 5 are
added. When the transfer ends at time T5, the control circuit 105
causes the photoelectric converter 1 to discharge the charges to
the power supply line 13 via the overflow transistor 14.
[0089] At time T6, the control circuit 105 detects the trailing
edge of the second external trigger signal supplied to the second
external trigger terminal 107, accordingly generates the second
trigger pulse, and causes the photoelectric converter 1 to start
accumulating charges with reference to the second trigger pulse. At
time T7, the control circuit 105 detects the leading edge of the
second external trigger signal supplied to the second external
trigger terminal 107. According to the detection of the leading
edge, the control circuit 105 causes the photoelectric converter 1
to transfer charges PD4(n) accumulated in it during the period from
time T6 to time T7 to the second charge holding portion 3 via the
second transfer transistor 6 and causes the second charge holding
portion 3 to hold the charges. This transfer is performed at once
in all the pixels 20 of the pixel array 100. In the second charge
holding portion 3, the already held charges PD2(n) and the charges
PD4(n) newly transferred by the second transfer transistor 6 are
added. When the transfer ends at time T7, the control circuit 105
causes the photoelectric converter 1 to discharge the charges to
the power supply line 13 via the overflow transistor 14.
[0090] The control circuit 105 detects the trailing edge of the
vertical synchronization signal at time T8, and accordingly causes
the device to perform the read operation during the period from
time T8 to time T9. In this read operation, charges MEM1(n) held by
the first charge holding portion 2 are row-sequentially read out
from the first charge holding portion 2. The control circuit 105
detects the trailing edge of the vertical synchronization signal at
time T10, and accordingly causes the device to perform the read
operation during the period from time T10 to time T11. In this read
operation, charges MEM2(n) held by the second charge holding
portion 3 are row-sequentially read out from the second charge
holding portion 3. The read operation is performed by controlling a
vertical scanning circuit 101, a column amplifier circuit 102, a
horizontal scanning circuit 103, and an output circuit 104 by the
control circuit 105.
[0091] The driving method of the image sensing device ISD according
to the third embodiment will be described next in more detail with
reference to FIG. 10. As shown in FIG. 10, at time T0, the control
circuit 105 detects the trailing edge of a first external trigger
signal EXTTRG1 supplied to the first external trigger terminal 106,
and accordingly generates a first trigger pulse pTRG1. According to
the first trigger pulse pTRG1, at time T80, the voltage of a
discharge signal line pOFD transitions from high level to low
level, and the overflow transistor 14 is turned off. Accordingly,
the photoelectric converter 1 starts accumulating charges
corresponding to incident light.
[0092] At time T1, the control circuit 105 detects the leading edge
of the first external trigger signal EXTTRG1 supplied to the first
external trigger terminal 106 and accordingly pulse-drives a first
transfer signal line pGS1. The pulse-driven first transfer signal
line pGS1 transitions from high level to low level at time T81.
Accordingly, at time T81, the first transfer transistor 5 is turned
off, and the charge transfer from the photoelectric converter 1 to
the first charge holding portion 2 ends. The first charge
accumulation period is the period from time T80 to time T81.
[0093] At time T2, the control circuit 105 detects the trailing
edge of a second external trigger signal EXTTRG2 supplied to the
second external trigger terminal 107, and accordingly generates a
second trigger pulse pTRG2. According to the second trigger pulse
pTRG2, at time T82, the voltage of the discharge signal line pOFD
transitions from high level to low level, and the overflow
transistor 14 is turned off. Accordingly, the photoelectric
converter 1 starts accumulating charges corresponding to incident
light.
[0094] At time T3, the control circuit 105 detects the leading edge
of the second external trigger signal EXTTRG2 supplied to the
second external trigger terminal 107 and accordingly pulse-drives a
second transfer signal line pGS2. The pulse-driven second transfer
signal line pGS2 transitions from high level to low level at time
T83. Accordingly, at time T83, the first transfer transistor 5 is
turned off, and the charge transfer from the photoelectric
converter 1 to the second charge holding portion 3 ends. The second
charge accumulation period is the period from time T82 to time
T83.
[0095] At time T4, the control circuit 105 detects the trailing
edge of the first external trigger signal EXTTRG1 supplied to the
first external trigger terminal 106, and accordingly generates the
first trigger pulse pTRG1. According to the first trigger pulse
pTRG1, at time T84, the voltage of the discharge signal line pOFD
transitions from high level to low level, and the overflow
transistor 14 is turned off. Accordingly, the photoelectric
converter 1 starts accumulating charges corresponding to incident
light.
[0096] At time T5, the control circuit 105 detects the leading edge
of the first external trigger signal EXTTRG1 supplied to the first
external trigger terminal 106 and accordingly pulse-drives the
first transfer signal line pGS1. The pulse-driven first transfer
signal line pGS1 transitions from high level to low level at time
T85. Accordingly, at time T85, the first transfer transistor 5 is
turned off, and the charge transfer from the photoelectric
converter 1 to the first charge holding portion 2 ends. The third
charge accumulation period is the period from time T84 to time
T85.
[0097] At time T6, the control circuit 105 detects the trailing
edge of the second external trigger signal EXTTRG2 supplied to the
second external trigger terminal 107, and accordingly generates the
second trigger pulse pTRG2. According to the second trigger pulse
pTRG2, at time T86, the voltage of the discharge signal line pOFD
transitions from high level to low level, and the overflow
transistor 14 is turned off. Accordingly, the photoelectric
converter 1 starts accumulating charges corresponding to incident
light.
[0098] At time T7, the control circuit 105 detects the leading edge
of the second external trigger signal EXTTRG2 supplied to the
second external trigger terminal 107 and accordingly pulse-drives
the second transfer signal line pGS2. The pulse-driven second
transfer signal line pGS2 transitions from high level to low level
at time T87. Accordingly, at time T87, the first transfer
transistor 5 is turned off, and the charge transfer from the
photoelectric converter 1 to the second charge holding portion 3
ends. The fourth charge accumulation period is the period from time
T86 to time T87.
[0099] The control circuit 105 detects the trailing edge of the
vertical synchronization signal at time T8, and accordingly
controls the read operation such that the charges MEM1(n) held by
the first charge holding portion 2 are row-sequentially read out
from the first charge holding portion 2.
[0100] According to the third embodiment, even in a case in which
the external trigger signals are given at a time interval shorter
than that of the read operation of one frame (the period of the
vertical synchronization signal) defined by the vertical
synchronization signal, image sensing according to this can be
performed. In addition, when the timing of charge accumulation when
performing the charge transfer from the photoelectric converter 1
to the first charge holding portion 2 or the second charge holding
portion 3 a plurality of times is controlled by the external
trigger signals, the degree of freedom in control of multiple
exposure can be increased. Furthermore, as for the timing of charge
transfer to the charge holding portion, the charge transfer is
alternately performed for the first charge holding portion, the
second charge holding portion, the first charge holding portion, .
. . . This can reduce the influence of overlap of an object, which
is caused by multiple exposure. In addition, when the start of the
read operation is controlled by the signal (vertical
synchronization signal) from the external device, the degree of
freedom of the timing of the read operation can be improved.
[0101] An image sensing device according to the fourth embodiment
of the present invention will be described with reference to FIGS.
11, 12, 13, and 14. The fourth embodiment is a modification of the
second embodiment, and matters that are not mentioned as the fourth
embodiment can comply with the second embodiment. However, matters
described in the fourth embodiment may be applied to the image
sensing device ISD according to the first or third embodiment. FIG.
11 shows the schematic arrangement of an image sensing device ISD
according to the fourth embodiment. As shown in FIG. 11, in the
image sensing device ISD according to the fourth embodiment, the
two external trigger terminals are multiplexed into one external
trigger terminal.
[0102] A driving method of the image sensing device ISD according
to the fourth embodiment will be described next with reference to
FIG. 12. FIG. 12 conceptually shows the driving method of the image
sensing device ISD according to the fourth embodiment. Referring to
FIG. 12, the arrow from the photoelectric converter to the first
charge holding portion means transfer of charges in a global
electronic shutter operation. In FIG. 12, operations concerning the
nth frame are indicated by solid lines, and operations concerning
the (n+1)th frame and the (n-1)th frame are indicated by broken
lines.
[0103] At time T0, a control circuit 105 detects the trailing edge
of an external trigger signal supplied to an external trigger
terminal 106, accordingly generates a first trigger pulse, and
causes a photoelectric converter 1 to start accumulating charges
with reference to the first trigger pulse. At time T1, the control
circuit 105 causes the photoelectric converter 1 to transfer
charges PD1(n) accumulated in it during the period from time T0 to
time T1 to a first charge holding portion 2 via a first transfer
transistor 5 and causes the first charge holding portion 2 to hold
the charges. This transfer is performed at once in all pixels 20 of
a pixel array 100. In FIG. 12, the charges held by the first charge
holding portion 2 are represented by MEM1(n). When the transfer
ends at time T1, the control circuit 105 causes the photoelectric
converter 1 to discharge the charges to a power supply line 13 via
an overflow transistor 14.
[0104] The control circuit 105 controls the read operation such
that a signal corresponding to the charges MEM1(n) whose
accumulation is started in accordance with the first trigger pulse
is row-sequentially read out from the first charge holding portion
2 during the period from the transfer end time of time T1 to time
T4. At time T2, the control circuit 105 detects the leading edge of
the external trigger signal (pulse signal) supplied to the external
trigger terminal 106, accordingly generates a second trigger pulse,
and causes the photoelectric converter 1 to start accumulating
charges with reference to the second trigger pulse. At time T3, the
control circuit 105 causes the photoelectric converter 1 to
transfer charges PD2(n) accumulated in it during the period from
time T2 to time T3 to a second charge holding portion 3 via a
second transfer transistor 6 and causes the second charge holding
portion 3 to hold the charges. This transfer is performed at once
in all the pixels 20 of the pixel array 100. In FIG. 12, the
charges held by the second charge holding portion 3 are represented
by MEM2(n).
[0105] At time T4, the read operation of the signal corresponding
to the charges MEM1(n) held by the first charge holding portion 2
ends, and the read operation of the signal corresponding to the
charges MEM2(n) held by the second charge holding portion 3 starts
next.
[0106] The driving method of the image sensing device ISD according
to the fourth embodiment will be described next in more detail with
reference to FIG. 13. As shown in FIG. 13, at time T0, the control
circuit 105 detects the trailing edge of an external trigger signal
EXTTRG1 supplied to the external trigger terminal 106, and
accordingly generates a first trigger pulse pTRG1. According to the
leading edge of the first trigger pulse pTRG1, the voltage of a
discharge signal line pOFD transitions from high level to low
level, and an overflow transistor 14 is turned off. Accordingly,
the photoelectric converter 1 starts accumulating charges
corresponding to incident light. Based on a charge accumulation
time defined by a parameter value set in the register (not shown)
of the image sensing device ISD, the control circuit 105 controls
pulse driving of the first transfer signal line pGS1 such that the
voltage of a first transfer signal line pGS1 transitions from high
level to low level at time T1. Accordingly, at time T1, the first
transfer transistor 5 is turned off, and the charge transfer from
the photoelectric converter 1 to the first charge holding portion 2
ends.
[0107] The control circuit 105 controls the read operation such
that a signal corresponding to the charges MEM1(n) whose
accumulation is started in accordance with the first trigger pulse
is row-sequentially read out from the first charge holding portion
2 during the period from the transfer end time of time T1 to time
T4.
[0108] At time T2, the control circuit 105 detects the leading edge
of the external trigger signal EXTTRG1 supplied to the external
trigger terminal 106, and accordingly generates a second trigger
pulse pTRG2. According to the leading edge of the second trigger
pulse pTRG2, the voltage of the discharge signal line pOFD
transitions from high level to low level, and the overflow
transistor 14 is turned off. Accordingly, the photoelectric
converter 1 starts accumulating charges corresponding to incident
light. Based on a charge accumulation time defined by a parameter
value set in the register (not shown) of the image sensing device
ISD, the control circuit 105 controls pulse driving of the second
transfer signal line pGS2 such that the voltage of a second
transfer signal line pGS2 transitions from high level to low level
at time T3. Accordingly, at time T3, the second transfer transistor
6 is turned off, and the charge transfer from the photoelectric
converter 1 to the second charge holding portion 3 ends.
[0109] At time T4, the read operation of the signal corresponding
to the charges MEM1(n) held by the first charge holding portion 2
ends, and the read operation of the signal corresponding to the
charges MEM2(n) held by the second charge holding portion 3 starts
next.
[0110] In the above-described example, the control circuit 105
generates the first trigger pulse using the trailing edge of the
external trigger signal supplied to the external trigger terminal
106 as the first timing, and generates the second trigger pulse
using the leading edge of the external trigger signal as the second
timing. However, the control circuit 105 generates the first
trigger pulse using the leading edge of the external trigger signal
supplied to the external trigger terminal 106 as the first timing,
and generates the second trigger pulse using the trailing edge of
the external trigger signal as the second timing. That is, the
external trigger signal supplied to the external trigger terminal
106 gives the first timing at one of the leading edge and the
trailing edge and gives the second timing at the other of the
leading edge and the trailing edge.
[0111] In addition, FIG. 14 conceptually shows the driving method
of the image sensing device ISD that is another modification of the
fourth embodiment. Referring to FIG. 14, the arrow from the
photoelectric converter to the first charge holding portion means
transfer of charges in a global electronic shutter operation. In
FIG. 14, operations concerning the nth frame are indicated by solid
lines, and operations concerning the (n+1)th frame and the (n-1)th
frame are indicated by broken lines.
[0112] At time T0, the control circuit 105 detects the trailing
edge of the external trigger signal supplied to the external
trigger terminal 106, and generates the first trigger pulse in
accordance with the trailing edge and a trigger identification
signal (not shown) in the image sensing device. Then, the control
circuit 105 causes the photoelectric converter 1 to start
accumulating charges with reference to the first trigger pulse. At
time T1, the control circuit 105 causes the photoelectric converter
1 to transfer charges PD1(n) accumulated in it during the period
from time T0 to time T1 to the first charge holding portion 2 via
the first transfer transistor 5 and causes the first charge holding
portion 2 to hold the charges. This transfer is performed at once
in all the pixels 20 of the pixel array 100. In FIG. 14, the
charges held by the first charge holding portion 2 are represented
by MEM1(n). At time T1, the control circuit 105 detects the leading
edge of the external trigger signal supplied to the external
trigger terminal 106. According to the detection of the leading
edge, the control circuit 105 causes the photoelectric converter 1
to transfer the charges PD1(n) accumulated in it during the period
from time T0 to time T1 to the first charge holding portion 2 via
the first transfer transistor 5 and causes the first charge holding
portion 2 to hold the charges. This transfer is performed at once
in all the pixels 20 of the pixel array 100. When the transfer ends
at time T1, the control circuit 105 causes the photoelectric
converter 1 to discharge the charges to the power supply line 13
via the overflow transistor 14. In addition, at time T1, the
trigger identification signal in the image sensing device is
inverted to generate the second trigger pulse at the next trailing
edge.
[0113] The control circuit 105 controls the read operation such
that the charges MEM1(n) whose accumulation is started in
accordance with the first trigger pulse are row-sequentially read
out from the first charge holding portion 2 during the period from
the transfer end time of time T1 to time T4. The read operation is
performed by controlling a vertical scanning circuit 101, a column
amplifier circuit 102, a horizontal scanning circuit 103, and an
output circuit 104 by the control circuit 105.
[0114] At time T2, the control circuit 105 detects the trailing
edge of the external trigger signal supplied to the external
trigger terminal 106, and generates the second trigger pulse in
accordance with the trailing edge and the trigger identification
signal in the image sensing device. Then, the control circuit 105
causes the photoelectric converter 1 to start accumulating charges
with reference to the second trigger pulse. At time T3, the control
circuit 105 detects the leading edge of the external trigger signal
supplied to the external trigger terminal 106. According to the
detection of the leading edge, the control circuit 105 causes the
photoelectric converter 1 to transfer the charges PD2(n)
accumulated in it during the period from time T2 to time T3 to the
second charge holding portion 3 via the second transfer transistor
6 and causes the second charge holding portion 3 to hold the
charges. This transfer is performed at once in all the pixels 20 of
the pixel array 100. In FIG. 14, when the transfer ends at time T3,
the control circuit 105 causes the photoelectric converter 1 to
discharge the charges to the power supply line 13 via the overflow
transistor 14. In addition, at time T1, the trigger identification
signal in the image sensing device is inverted to generate the
first trigger pulse at the next trailing edge.
[0115] At time T4, the read operation of the signal corresponding
to the charges MEM1(n) ends, and the read operation of the signal
corresponding to the charges MEM2(n) starts next. During the period
from time T4 to time T7, the read operation of the signal
corresponding to the charges MEM2(n) is performed.
[0116] At time T5, the control circuit 105 detects the trailing
edge of the external trigger signal supplied to the external
trigger terminal 106, and generates the first trigger pulse in
accordance with the trailing edge and the trigger identification
signal in the image sensing device. Then, the control circuit 105
causes the photoelectric converter 1 to start accumulating charges
with reference to the first trigger pulse. At time T6, the control
circuit 105 detects the leading edge of the external trigger signal
supplied to the external trigger terminal 106. According to the
detection of the leading edge, the control circuit 105 causes the
photoelectric converter 1 to transfer the charges PD1(n+1)
accumulated in it during the period from time T5 to time T6 to the
first charge holding portion 2 via the first transfer transistor 5
and causes the first charge holding portion 2 to hold the charges.
This transfer is performed at once in all the pixels 20 of the
pixel array 100. When the transfer ends at time T5, the control
circuit 105 causes the photoelectric converter 1 to discharge the
charges to the power supply line 13 via the overflow transistor
14.
[0117] According to the fourth embodiment, it is possible to
decrease the number of external trigger terminals. In addition, an
effect of avoiding the influence of signal delay on two signal
lines corresponding to two external trigger terminals, unlike other
embodiments, is provided.
[0118] An image sensing device according to the fifth embodiment of
the present invention will be described with reference to FIGS. 15,
16A, and 16B. The fifth embodiment is a modification of the fourth
embodiment, and matters that are not mentioned as the fifth
embodiment can comply with the fourth embodiment. However, matters
described in the fifth embodiment may be applied to the image
sensing devices 1 according to the first to third embodiments. An
image sensing device ISD according to the fifth embodiment is
different from the image sensing device ISD according to the fourth
embodiment in that the electronic shutter operation is a rolling
shutter operation, and multiple exposure is performed.
[0119] At time T0, a control circuit 105 detects the trailing edge
of an external trigger signal supplied to an external trigger
terminal 106, accordingly generates a first trigger pulse, and
causes a photoelectric converter 1 of each pixel 20 of the first
row to start accumulating charges with reference to the first
trigger pulse. From then on, the control circuit 105
row-sequentially causes the photoelectric converter 1 of each pixel
20 of the second and subsequent rows to start accumulating charges.
Here, the accumulation of charges in the photoelectric converter 1
is started by turning off an overflow transistor 14.
[0120] At time T1, the control circuit 105 detects the leading edge
of the external trigger signal supplied to the external trigger
terminal 106, and accordingly generates a second trigger pulse.
Then, according to the second trigger pulse, the control circuit
105 causes the photoelectric converter 1 of each pixel 20 of the
first row to transfer signal charges PD1(n) accumulated in it
during the period from time T0 to time T1 to a first charge holding
portion 2 via a first transfer transistor 5 and causes the first
charge holding portion 2 to hold the charges. After that, the
charges are row-sequentially transferred to the first charge
holding portion 2. In FIG. 15, the charges held by the first charge
holding portion 2 are represented by MEM1(n). When the charge
transfer from the photoelectric converter 1 to the first charge
holding portion 2 in each pixel 20 of the first row ends, that is,
when charge accumulation during the first charge accumulation
period ends at time T1, charge accumulation in the second charge
accumulation period starts.
[0121] At time T2, the control circuit 105 detects the trailing
edge of the external trigger signal supplied to the external
trigger terminal 106, and accordingly generates the first trigger
pulse. Then, according to the first trigger pulse, the control
circuit 105 causes the photoelectric converter 1 to transfer
charges PD2(n) accumulated in it during the period from time T1 to
time T3 to a second charge holding portion 3. When the transfer
ends, charge accumulation in the third charge accumulation period
starts.
[0122] At time T3, the control circuit 105 detects the leading edge
of the external trigger signal supplied to the external trigger
terminal 106, and accordingly generates the second trigger pulse.
Then, according to the second trigger pulse, the control circuit
105 causes the photoelectric converter 1 of each pixel 20 of the
first row to transfer signal charges PD3(n) accumulated in it
during the period from time T3 to time T4 to the first charge
holding portion 2 via the first transfer transistor 5 and causes
the first charge holding portion 2 to hold the charges. After that,
the charges are row-sequentially transferred to the first charge
holding portion 2. When the transfer ends, charge accumulation in
the fourth charge accumulation period starts.
[0123] At time T4, the control circuit 105 detects the trailing
edge of a vertical synchronization signal, and accordingly starts
the read operation of a signal from each pixel 20 of the first row
and row-sequentially performs the read operation.
[0124] The driving method of the image sensing device ISD according
to the fifth embodiment will be described next in more detail with
reference to FIGS. 16A and 16B. As shown in FIG. 16A, at time T0,
the control circuit 105 detects the trailing edge of an external
trigger signal EXTTRG1 supplied to the external trigger terminal
106, and accordingly generates a first trigger pulse pTRG1.
According to the first trigger pulse pTRG1, the voltage of a
discharge signal line pOFD(1) for the pixels 20 of the first row
transitions from high level to low level, and the overflow
transistor 14 of each pixel 20 of the first row is turned off.
Accordingly, the photoelectric converter 1 of each pixel 20 of the
first row starts accumulating charges corresponding to incident
light.
[0125] At time T1, the control circuit 105 detects the leading edge
of the external trigger signal EXTTRG1 supplied to the external
trigger terminal 106, and accordingly generates a second trigger
pulse pTRG2. According to the second trigger pulse pTRG2, the
control circuit 105 generates a pulse in a first transfer signal
pGS1(1) for the pixels 20 of the first row. Accordingly, when the
first transfer signal pGS1(1) is at high level, the charges are
transferred from the photoelectric converter 1 to the first charge
holding portion 2 in each pixel 20 of the first row.
[0126] At time T2, the control circuit 105 detects the trailing
edge of the external trigger signal EXTTRG1 supplied to the
external trigger terminal 106, and accordingly generates the first
trigger pulse pTRG1. According to the first trigger pulse pTRG1,
the control circuit 105 generates a pulse in a second transfer
signal pGS2(1) for the pixels 20 of the first row. Accordingly,
when the second transfer signal pGS2(1) is at high level, the
charges are transferred from the photoelectric converter 1 to the
second charge holding portion 3 in each pixel 20 of the first
row.
[0127] At time T3, the control circuit 105 detects the leading edge
of the external trigger signal EXTTRG1 supplied to the external
trigger terminal 106, and accordingly generates the second trigger
pulse pTRG2. According to the second trigger pulse pTRG2, the
control circuit 105 generates a pulse in the first transfer signal
pGS1(1) for the pixels 20 of the first row. Accordingly, when the
first transfer signal pGS1(1) is at high level, the charges are
transferred from the photoelectric converter 1 to the first charge
holding portion 2 in each pixel 20 of the first row.
[0128] At time T4, the control circuit 105 detects the trailing
edge of the vertical synchronization signal, and accordingly starts
the read operation of the signal from each pixel 20 of the first
row and row-sequentially performs the read operation. This
operation is shown in FIG. 16B.
[0129] FIG. 16B shows the read operation (Read in FIG. 16A) from
the first charge holding portions 2 of the pixels 20 of the mth row
and the (m+1)th row. At time T90, the control circuit 105 makes the
voltage of a selection signal line pSEL(m) transition from low
level to high level via a vertical scanning circuit 101. The pixels
20 of the mth row are thus selected. Halfway through the period
from time T90 to time T91, the control circuit 105 makes the
voltage of a reset signal line pRES(m) transition to high level and
turns on a reset transistor 11 by the control via the vertical
scanning circuit 101. At time T91, the control circuit 105 makes
the voltage of the reset signal line pRES(m) transition to low
level and turns off the reset transistor 11 by the control via the
vertical scanning circuit 101. With this operation, the charges
existing in a floating diffusion 4 are discharged to a power supply
line 13. The voltage (noise) signal of the floating diffusion 4 is
amplified by the source follower operation and output to a vertical
output line 10.
[0130] During the period from time T91 to time T92, the control
circuit 105 causes a column amplifier circuit 102 to read out the
noise signal (N-read). After that, the control circuit 105 makes
the voltage of a third transfer signal line pTX1(m) transition to
high level and turns on a third transfer transistor 7 by control
via the vertical scanning circuit 101. The charges MEM1(m) (the
charges accumulated in accordance with the first trigger pulse) are
thus transferred from the first charge holding portion 2 that holds
the charges of the pixels 20 of the mth row to the floating
diffusion 4. The voltage (optical signal) of the floating diffusion
4 is amplified by the source follower operation and output to the
vertical output line 10. At time T92, the control circuit 105 turns
off the voltage of the third transfer signal line pTX1(m) by
control via the vertical scanning circuit 101.
[0131] During the period from time T92 to time T93, the control
circuit 105 causes the column amplifier circuit 102 to read out the
optical signal corresponding to the charges MEM1(m) (S1-read), and
after that, makes the voltage of the reset signal line pRES(m)
transition to high level by the control via the vertical scanning
circuit 101. The reset transistor 11 is thus turned on. At time
T93, the control circuit 105 makes the voltage of the reset signal
line pRES(m) transition to low level and turns off the reset
transistor 11 by the control via the vertical scanning circuit 101.
With this operation, the charges existing in the floating diffusion
4 are discharged to the power supply line 13. The voltage (noise)
signal of the floating diffusion 4 is amplified by the source
follower operation and output to the vertical output line 10.
[0132] During the period from time T94 to time T95, the control
circuit 105 causes the column amplifier circuit 102 to read out the
noise signal (N-read). After that, the control circuit 105 makes
the voltage of a fourth transfer signal line pTX2(m) transition to
high level and turns on a fourth transfer transistor 8 by control
via the vertical scanning circuit 101. The charges MEM2(m) (the
charges accumulated in accordance with the first trigger pulse) are
thus transferred from the second charge holding portion 3 that
holds the charges of the pixels 20 of the mth row to the floating
diffusion 4. The voltage (optical signal) of the floating diffusion
4 is amplified by the source follower operation and output to the
vertical output line 10. At time T94, the control circuit 105 turns
off the voltage of the fourth transfer signal line pTX2(m) by
control via the vertical scanning circuit 101.
[0133] During the period from time T94 to time T95, the control
circuit 105 causes the column amplifier circuit 102 to read out the
optical signal corresponding to the charges MEM2(m) (S2-read).
After that, the control circuit 105 makes the voltage of the reset
signal line pRES(m) transition to high level by control via the
vertical scanning circuit 101. The reset transistor 11 is thus
turned on.
[0134] At time T95, the control circuit 105 makes the voltage of
the selection signal line pSEL(m) transition to low level by
control via the vertical scanning circuit 101, thereby ending
selection of the mth row. In addition, the control circuit 105
makes the voltage of the selection signal line pSEL(m+1) transition
to high level, thereby starting selection of the (m+1)th row.
[0135] According to the fifth embodiment, in a state in which an
object continuously moves asynchronously with the vertical
synchronization signal, even if the image sensing interval is
shorter than a time interval shorter than that of the read
operation of one frame (the period of the vertical synchronization
signal) defined by the vertical synchronization signal, continuous
image sensing can be performed. In addition, an image for which the
charge accumulation time is short and an image for which the charge
accumulation time is long can be obtained. Furthermore, an object
such as a moving apparatus can be recorded in one image a plurality
of times by multiple exposure.
[0136] An image sensing device according to the sixth embodiment of
the present invention will be described with reference to FIG. 17.
The sixth embodiment is a modification of the second embodiment,
and matters that are not mentioned as the sixth embodiment can
comply with the second embodiment. However, matters described in
the sixth embodiment may be applied to the image sensing devices
ISD according to the first and third to fifth embodiments. In the
sixth embodiment, a first external trigger signal supplied to a
first external trigger terminal 106 and a second external trigger
signal supplied to a second external trigger terminal 107 are
complementary signals.
[0137] In the sixth embodiment, at time T0, a control circuit 105
detects the trailing edge of the first external trigger signal
supplied to the first external trigger terminal 106 and the leading
edge of the second external trigger signal supplied to the second
external trigger terminal 107 and generates a first trigger pulse.
Then, the control circuit 105 causes a photoelectric converter 1 to
start accumulating charges with reference to the first trigger
pulse. At time T1, the control circuit 105 causes the photoelectric
converter 1 to transfer charges PD1(n) accumulated in it during the
period from time T0 to time T1 to a first charge holding portion 2
and causes the first charge holding portion 2 to hold the charges.
This transfer is performed at once in all pixels 20 of a pixel
array 100. In FIGS. 16A and 16B, the charges held by the first
charge holding portion 2 are represented by MEM1(n). When the
transfer ends at time T1, the control circuit 105 causes the
photoelectric converter 1 to discharge the charges to a power
supply line 13 via an overflow transistor 14.
[0138] After the charge transfer at time T1 ends, the control
circuit 105 controls a read operation such that a signal
corresponding to the charges MEM1(n) whose accumulation is started
in accordance with the first trigger pulse is row-sequentially read
out from the first charge holding portion 2. The read operation is
performed by controlling a vertical scanning circuit 101, a column
amplifier circuit 102, a horizontal scanning circuit 103, and an
output circuit 104 by the control circuit 105.
[0139] At time T2, the control circuit 105 detects both the leading
edge of the first external trigger signal supplied to the first
external trigger terminal 106 and the trailing edge of the second
external trigger signal supplied to the second external trigger
terminal 107 and generates a second trigger pulse. Then, the
control circuit 105 causes the photoelectric converter 1 to start
accumulating charges with reference to the second trigger pulse. At
time T3, the control circuit 105 causes the photoelectric converter
1 to transfer charges PD2(n) accumulated in it during the period
from time T2 to time T3 to a second charge holding portion 3 and
causes the second charge holding portion 3 to hold the charges.
This transfer is performed at once in all the pixels 20 of the
pixel array 100.
[0140] At time T4, the read operation of the signal corresponding
to the charges MEM1(n) ends, and the read operation of the signal
corresponding to charges MEM2(n) starts next.
[0141] According to the sixth embodiment, when the complementary
signals are used as the external trigger signals, noise resistance
can be improved.
[0142] FIG. 18 shows the arrangement of an image sensing system 200
according to an embodiment of the present invention. The image
sensing system 200 can include a detector D1 and a camera CAM.
Alternatively, the image sensing system 200 can include the
detector D1 and the image sensing device ISD. The detector D1
detects an object and generates, as the first external trigger
signal EXTTRG1 and the second external trigger signal EXTTRG2
described above, detection signals TR1 and TR2 representing that
the object is detected. Alternatively, the detector D1 may be
configured to detect an object and generate, as an external trigger
signal EXTTRG described above, a detection signal TR representing
that the object is detected. The detector D1 can include, for
example, a sensor such as a loop coil, a magnetic sensor, a
photoelectric converter sensor, or an ultrasonic sensor configured
to detect an object such as an automobile. Alternatively, the
detector D1 can include a sensor such as a photointerrupter
configured to detect an object on a conveyor. The detector D1 can
be configured to, for example, generate the first detection signal
TR1 (first external trigger signal EXTTRG1) upon detecting one
object and generate the second detection signal TR2 (second
external trigger signal EXTTRG2) upon detecting one more object.
Alternatively, the detector D1 can be configured to invert the
logic level of the detection signal TR (external trigger signal
EXTTRG) upon detecting one object and further invert the logic
level of the detection signal TR (external trigger signal EXTTRG)
upon detecting one more object.
[0143] The camera CAM can be any device having an image sensing
function. The camera CAM can include constituent elements shown in
FIG. 18 in addition to the image sensing device ISD. The camera CAM
can include a lens C02 that forms an optical image of an object on
the imaging plane of the image sensing device ISD. In addition, the
camera CAM can include a stop C04 configured to change the amount
of light passing through the lens C02, and a barrier C06 configured
to protect the lens C02. The image sensing device ISD converts the
optical image formed by the lens C02 into image data.
[0144] The camera CAM can also include a signal processing unit C08
that processes an output signal output from the image sensing
device ISD. The signal processing unit C08 can perform, for
example, correction, processing, compression, and the like of the
image data. The camera CAM can include a memory C10 configured to
temporarily store image data, and an external interface (external
I/F) C12 configured to communicate with an external computer or the
like. The camera CAM can also include a recording medium C14 such
as a semiconductor memory used to record image data, and a medium
controller C16 configured to record image data in the recording
medium C14 and read out image data from the recording medium C14.
The recording medium C14 may stationarily be provided in the camera
CAM or may be detachable. The camera CAM can include a main
controller C18 that controls the constituent elements of the camera
CAM. The first detection signal TR1 and the second detection signal
TR2 serving as the first external trigger signal EXTTRG1 and the
second external trigger signal EXTTRG2 can be supplied from the
detector D1 to the image sensing device ISD. The image sensing
device ISD can perform image sensing in accordance with the first
detection signal TR1 and the second detection signal TR2.
[0145] An example of the image sensing system is a monitoring
camera. In the monitoring camera used for an application purpose of
security, monitoring, or the like, the detector D1 detects the
occurrence of an event (an approach or occurrence of an object of
interest (a person, an animal, an object, a moving apparatus, an
abnormal phenomenon, or the like)). As the result of the detection,
the external trigger signals TR1 and TR2 are output to the image
sensing device ISD. Another example of the image sensing system is
an industrial camera. An application purpose of the industrial
camera is monitoring of products conveyed through a production
line. In this industrial camera, the detector D1 detects the
occurrence of an event (an approach of a product, an occurrence of
an abnormal phenomenon, or the like). As the result of the
detection, the external trigger signals TR1 and TR2 are output to
the image sensing device ISD.
[0146] As described above, when the plurality of external trigger
signals are used, the interval between image sensing and image
sensing can be shortened as compared to a case in which one
external trigger signal is used. This makes it possible to quickly
sense each of the occurrences of a plurality of events such as a
plurality of moving apparatuses that move at a high speed, a
plurality of products, and a continuous occurrence of a plurality
of abnormal phenomena.
[0147] An image sensing system and a moving apparatus according to
the seventh embodiment will be described with reference to FIGS.
19A and 19B. FIGS. 19A and 19B are views showing examples of the
arrangements of the image sensing system and the moving apparatus
according to this embodiment.
[0148] FIG. 19A shows an example of an image sensing system 400
concerning an onboard camera. The image sensing system 400 includes
an image sensing device 410. The image sensing device 410 is one of
the image sensing devices described in the above embodiments. The
image sensing system 400 includes an image processing unit 412 that
performs image processing for a plurality of image data obtained by
the image sensing device 410, and a parallax obtaining unit 414
that obtains a parallax (the phase difference of a parallax image)
from the plurality of image data obtained by the image sensing
device 410. The image sensing system 400 includes a distance
obtaining unit 416 that obtains the distance to a target object
based on the obtained parallax, and a collision determination unit
418 that determines based on the obtained distance whether there is
a collision possibility. Here, the parallax obtaining unit 414 and
the distance obtaining unit 416 are examples of a distance
information obtaining unit that obtains the distance information to
a target object. That is, the distance information is information
about a parallax, a defocus amount, a distance to a target object,
or the like. The collision determination unit 418 may determine the
collision possibility using one of these pieces of distance
information. The distance information obtaining unit may be
implemented by specially designed hardware or may be implemented by
a software module. Alternatively, the distance information
obtaining unit may be implemented by an FPGA (Field Programmable
Gate Array), an ASIC (Application Specific Integrated Circuit), or
the like or may be implemented by a combination thereof.
[0149] The image sensing system 400 is connected to a vehicle
information obtaining device 420 and can obtain vehicle information
such as a vehicle speed, a yaw rate, a steering angle, and the
like. The image sensing system 400 is also connected to a control
ECU 430 that is a control device configured to output a control
signal to generate a braking force to the vehicle based on the
determination result of the collision determination unit 418. That
is, the control ECU 430 is an example of a moving apparatus
controller that controls a moving apparatus based on distance
information. In addition, the image sensing system 400 is also
connected to a warning device 440 that generates a warning to the
driver based on the determination result of the collision
determination unit 418. For example, if the collision possibility
is high as the determination result of the collision determination
unit 418, the control ECU 430 performs vehicle control to avoid a
collision or reduce damage by, for example, applying the brake,
returning the accelerator, or suppressing the engine output. The
warning device 440 warns the user by, for example, generating a
warning sound or the like, displaying warning information on the
screen of a car navigation system or the like, or giving a
vibration to a seat belt or steering wheel.
[0150] In this embodiment, the image sensing system 400 senses the
periphery, for example, the front or rear of the vehicle. FIG. 19B
shows the image sensing system 400 in a case in which the front of
the vehicle (image sensing range 450) is sensed. The vehicle
information obtaining device 420 sends an instruction to operate
the image sensing system 400 and execute image sensing. When one of
the image sensing devices of the above-described embodiments is
used as the image sensing device 410, the image sensing system 400
according to this embodiment can improve the accuracy of distance
measurement.
[0151] In addition, as an output unit that outputs an external
trigger signal to the image sensing device 410, one or some of the
parallax obtaining unit 414, the distance obtaining unit 416, the
collision determination unit 418, and the vehicle information
obtaining device 420 can be used. For example, in a case in which
the front of a moving apparatus is sensed, the external trigger
signal may be output to the image sensing device 410 when one or
some of the parallax obtaining unit 414, the distance obtaining
unit 416, the collision determination unit 418, and the vehicle
information obtaining device 420 detect the approach of a person or
another moving apparatus.
[0152] An example in which control is performed not to cause a
collision against another vehicle has been described above.
However, the image sensing system can also be applied to control
for automated driving following another vehicle or automated
driving without deviation from a lane. The image sensing system can
be applied not only to a vehicle such as a self-vehicle but also
to, for example, a moving apparatus such as a ship, an airplane, or
an industrial robot. In addition, the image sensing system can also
be applied not only to a moving apparatus but also to a device that
widely uses object recognition, such as Intelligent Transport
Systems (ITS).
Modified Embodiments
[0153] In addition to the above-described embodiments, various
modifications can be made for the present invention.
[0154] For example, an example in which some components of an
embodiment are added to another embodiment and an example in which
the components are replaced with some components of another
embodiment are also included in the embodiments of the present
invention.
[0155] In addition, the circuit arrangement of the pixel 12 or the
column read circuit 30 is not limited to that shown in FIG. 2 and
can appropriately be changed. For example, each pixel 12 may
include a plurality of photoelectric converters PD.
[0156] Furthermore, in the above-described embodiments, an RGBW 12
array has been described as a color filter array. However, the
color filters need not always have the RGBW 12 array. For example,
color filters having an RGBW array in which the ratio of W pixels
is different, for example, an RGBW 8 array may be used.
Alternatively, color filters having have a CMYW array including C
pixels with cyan CFs, M pixels with magenta CFs, Y pixels with
yellow CFs, and W pixels may be used.
[0157] In addition, the image sensing system shown in each of the
third and fourth embodiments exemplifies an image sensing system to
which the image sensing device according to the present invention
can be applied. The image sensing system to which the image sensing
device according to the present invention can be applied is not
limited to the arrangement shown in FIGS. 18, 19A, and 19B.
OTHER EMBODIMENTS
[0158] Embodiment(s) of the present invention can also be realized
by a computer of a system or apparatus that reads out and executes
computer executable instructions (e.g., one or more programs)
recorded on a storage medium (which may also be referred to more
fully as a `non-transitory computer-readable storage medium`) to
perform the functions of one or more of the above-described
embodiment(s) and/or that includes one or more circuits (e.g.,
application specific integrated circuit (ASIC)) for performing the
functions of one or more of the above-described embodiment(s), and
by a method performed by the computer of the system or apparatus
by, for example, reading out and executing the computer executable
instructions from the storage medium to perform the functions of
one or more of the above-described embodiment(s) and/or controlling
the one or more circuits to perform the functions of one or more of
the above-described embodiment(s). The computer may comprise one or
more processors (e.g., central processing unit (CPU), micro
processing unit (MPU)) and may include a network of separate
computers or separate processors to read out and execute the
computer executable instructions. The computer executable
instructions may be provided to the computer, for example, from a
network or the storage medium. The storage medium may include, for
example, one or more of a hard disk, a random-access memory (RAM),
a read only memory (ROM), a storage of distributed computing
systems, an optical disk (such as a compact disc (CD), digital
versatile disc (DVD), or Blu-ray Disc (BD).TM.), a flash memory
device, a memory card, and the like.
[0159] While the present invention has been described with
reference to exemplary embodiments, it is to be understood that the
invention is not limited to the disclosed exemplary embodiments.
The scope of the following claims is to be accorded the broadest
interpretation so as to encompass all such modifications and
equivalent structures and functions.
[0160] This application claims the benefit of Japanese Patent
Application No. 2017-246399, filed Dec. 22, 2017, which is hereby
incorporated by reference herein in its entirety.
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