U.S. patent application number 15/836363 was filed with the patent office on 2019-06-13 for single pin test interface for pin limited systems.
The applicant listed for this patent is Silicon Laboratories Inc.. Invention is credited to Stefan N. Mastovich, Krishna Pentakota, Huanhui Zhan.
Application Number | 20190178937 15/836363 |
Document ID | / |
Family ID | 66696657 |
Filed Date | 2019-06-13 |
United States Patent
Application |
20190178937 |
Kind Code |
A1 |
Zhan; Huanhui ; et
al. |
June 13, 2019 |
SINGLE PIN TEST INTERFACE FOR PIN LIMITED SYSTEMS
Abstract
An integrated circuit includes a supply terminal to receive a
supply voltage and a test terminal that operates in an input mode
and an output mode. A test interface of the integrated circuit
operates in a normal mode requiring a serial write to the test
terminal to access test locations in the integrated circuit. The
test interface also operates in an automatic mode in which
addresses for test locations are auto incremented by toggling the
supply voltage from a high voltage level to a low voltage level and
back to the high voltage level. In an input mode, with the supply
voltage at the low voltage level, the test pin receives
configuration and address information. In output mode, with the
supply voltage at the high voltage level, the test pin supplies
test information corresponding to the address information
received.
Inventors: |
Zhan; Huanhui; (Austin,
TX) ; Pentakota; Krishna; (Austin, TX) ;
Mastovich; Stefan N.; (Round Rock, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Silicon Laboratories Inc. |
Austin |
TX |
US |
|
|
Family ID: |
66696657 |
Appl. No.: |
15/836363 |
Filed: |
December 8, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G01R 31/31713 20130101;
G01R 31/3172 20130101; G01R 31/31702 20130101; G01R 31/31722
20130101; G01R 31/316 20130101 |
International
Class: |
G01R 31/317 20060101
G01R031/317; G01R 31/316 20060101 G01R031/316 |
Claims
1. A method comprising: configuring an integrated circuit into an
automatic mode using a first terminal of the integrated circuit;
sending first address information to the first terminal with a
supply voltage at a first voltage level, the first address
information identifying a first test location in the integrated
circuit; supplying first test information corresponding to the
first test location over the first terminal with the supply voltage
at a second voltage level; toggling the supply voltage by changing
the supply voltage from the second voltage level to the first
voltage level and back to the second voltage level; modifying the
first address information responsive to the toggling to generate
modified address information identifying a second test location in
the integrated circuit; and supplying second test information
corresponding to the second test location from the first terminal
with the supply voltage at second voltage level.
2. The method as recited in claim 1 further comprising: generating
a clock signal from the toggling of the supply voltage; and
modifying the first address information responsive to the clock
signal.
3. The method as recited in claim 1, wherein the modifying of the
first address information comprises incrementing or decrementing
the first address information.
4. The method as recited in claim 1, wherein the first voltage
level is lower than the second voltage level.
5. The method as recited in claim 1, wherein only a first portion
of first address information is changeable responsive to the
toggling.
6. The method as recited in claim 1, further comprising: writing
second address information while remaining in the automatic mode;
and modifying the second address information responsive to further
toggling of the supply voltage while in the automatic mode.
7. The method as recited in claim 1, further comprising:
configuring the first terminal as an input terminal responsive to
the supply voltage being at the first voltage level and as an
output terminal responsive to the supply voltage being at the
second voltage level.
8. An integrated circuit comprising: a first terminal; a second
terminal to receive a supply voltage; a storage location to store
first address information identifying a first test location in the
integrated circuit, the first address information received over the
first terminal; wherein the first terminal is coupled to supply
first test information from the first test location responsive to
the first address information identifying the first test location
and the supply voltage being at a first voltage level; a clock
generation circuit to supply a clock signal responsive to toggling
of the supply voltage from the first voltage level to a second
voltage level that is below the first voltage level and back to the
first voltage level; a circuit to modify the first address
information responsive to the clock signal to generate second
address information identifying a second test location; and wherein
the first terminal is coupled to supply second test information
from the second test location responsive to the second address
information and the supply voltage being at the first voltage
level.
9. The integrated circuit as recited in claim 8 further comprising:
a decoder circuit to assert an automatic mode of operation signal
responsive to receiving mode control information from the first
terminal; a threshold voltage detector circuit to detect when the
supply voltage is above a threshold voltage level thereby
indicating the first voltage level and to detect when the supply
voltage is below the threshold voltage level thereby indicating the
second voltage level; and wherein the clock generation circuit is
configured to assert a rising edge of the clock signal responsive
to the automatic mode of operation signal being asserted and
responsive to the threshold voltage detector circuit detecting the
supply voltage has transitioned from the first voltage level to the
second voltage level.
10. The integrated circuit as recited in claim 8, wherein the
circuit to modify increments or decrements the first address
information responsive to the clock signal.
11. The integrated circuit as recited in claim 8, wherein only a
first portion of the first address information is configured to
change responsive to the toggling.
12. The integrated circuit as recited in claim 8 wherein the first
terminal is configured to be in an input mode responsive to the
supply voltage being at the second voltage level and to be in an
output mode responsive to the supply voltage being at the first
voltage level.
13. The integrated circuit as recited in claim 8 further
comprising: a decoder circuit to assert an automatic mode of
operation signal responsive to receiving first mode information
from the first terminal and to de-assert the automatic mode of
operation signal responsive to receiving second mode address
information from the first terminal.
14. A method comprising: configuring an integrated circuit into an
automatic mode for test operation; supplying first test information
over a terminal of the integrated circuit, the first test
information corresponding to a first test location identified by
address information stored in the integrated circuit; modifying the
address information responsive to toggling of a supply voltage from
a first voltage level above a threshold voltage level to a second
voltage level below the threshold voltage level and back to the
first voltage level, to thereby generate modified address
information; and supplying second test information corresponding to
a second test location identified by the modified address
information over the terminal of the integrated circuit.
15. The method as recited in claim 14 comprising: modifying the
address information by incrementing the address information.
16. The method as recited in claim 14 comprising: configuring the
integrated circuit to operate in the automatic mode responsive to
mode information received over the terminal of the integrated
circuit with the supply voltage at the second voltage level.
17. The method as recited in claim 16 supplying the first test
information over the terminal with the supply voltage at the first
voltage level and supplying the second test information over the
terminal with the supply voltage at the first voltage level.
18. The method as recited in claim 17 further comprising
configuring the terminal to be in an input mode responsive to the
supply voltage being at the first voltage level and to be in an
output mode responsive to the supply voltage being at the second
voltage level.
19. The method as recited in claim 14 comprising: modifying the
modified address information responsive to further toggling of the
supply voltage and supplying further modified address information;
and supplying third test information corresponding to a third test
location identified by the further modified address information,
the third test information being supplied with the supply voltage
at the first voltage level.
20. The method as recited in claim 14 comprising: receiving the
address information over the terminal with the supply voltage at
the second voltage level.
Description
BACKGROUND
Field of the Disclosure
[0001] The disclosure herein relates to test interfaces and ways to
reduce test time in certain test environments.
Description of the Related Art
[0002] For a pin limited or cost limited chip package, a one pin
test interface is preferred. However, providing only one pin (also
referred to herein as terminal) requires that the one pin be used
for both test input and test output making the control needed to
switch transmit directions complicated. That is, during testing,
the direction of the serial communication channel changes from
input to output and vice versa in order to send test control
information to the integrated circuit and receive test results from
the integrated circuit. Switching direction on the serial
communication channel can take significant time, especially during
production test, making testing take longer and driving up the
cost.
[0003] Accordingly, it would be desirable to provide testing
improvements that can help reduce testing time.
SUMMARY OF EMBODIMENTS OF THE INVENTION
[0004] Accordingly, in one embodiment, a method includes
configuring an integrated circuit into an automatic mode using a
first terminal, e.g., a test terminal, of the integrated circuit.
The method includes sending first address information to the first
terminal with a supply voltage at a first voltage level, the
address information identifying a first test location in the
integrated circuit. First test information corresponding to the
first test location is supplied over the first terminal with the
supply voltage at a second voltage level. The supply voltage is
toggled by changing the supply voltage from the second voltage
level to the first voltage level and back to the second voltage
level. The first address information is modified responsive to the
toggling to generate modified address information identifying a
second test location in the integrated circuit. Second test
information corresponding to the second test location is supplied
from the first terminal with the supply voltage at the second
voltage level.
[0005] In another embodiment an integrated circuit includes a first
terminal and includes a second terminal to receive a supply
voltage. A storage location stores first address information
received over the first terminal identifying a first test location
in the integrated circuit. The first terminal, e.g., a test
terminal, supplies first test information from the first test
location responsive to the first address information identifying
the first test location and the supply voltage being at a first
voltage level. A clock generation circuit supplies a clock signal
responsive to toggling of the supply voltage from the first voltage
level to a second voltage level that is below the first voltage
level and back to the first voltage level. A circuit modifies,
e.g., increments, the first address information responsive to the
clock signal to generate second address information identifying a
second test location and the first terminal is coupled to supply
second test information from the second test location responsive to
the second address and to the supply voltage being at the first
voltage level.
[0006] In another embodiment a method includes configuring an
integrated circuit into an automatic mode for test operation. First
test information corresponding to a first test location identified
by address information stored in the integrated circuit is supplied
over a terminal of the integrated circuit. The address information
is modified responsive to toggling of the supply voltage from a
first voltage level above a threshold voltage level to a second
voltage level below the threshold voltage level and back to the
first voltage level, to thereby generate modified address
information. Second test information corresponding to a second test
location identified by the modified address information is supplied
over the terminal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The present invention may be better understood, and its
numerous objects, features, and advantages made apparent to those
skilled in the art by referencing the accompanying drawings.
[0008] FIG. 1 illustrates a test interface of an integrated circuit
according to an embodiment.
[0009] FIG. 2 is a timing diagram illustrating operation of the
test interface in normal mode.
[0010] FIG. 3 is a timing diagram illustrating operation of the
test interface in automatic mode.
[0011] FIG. 4 illustrates an example of an embodiment of mode
decode logic.
[0012] FIG. 5 illustrates a high level functional block diagram of
an auto increment and latch block according to an embodiment.
[0013] FIG. 6 illustrates a high level functional block diagram of
another embodiment of an auto increment and latch block.
[0014] The use of the same reference symbols in different drawings
indicates similar or identical items.
DETAILED DESCRIPTION
[0015] Referring to FIG. 1, a test interface 100 of an integrated
circuit utilizes a single test terminal 101 to receive and transmit
test related information. In a test environment the integrated
circuit may be packaged and the term "terminal" refers to a pin or
other electrical connection on the package. The term terminal can
also refer to the part of the die that couples to a package pin in
a die or wafer test environment. In addition to the test terminal
101, the illustrated embodiment utilizes the supply voltage
terminal 103 to receive the voltage supply (VDD) and to convey a
digital signal to the test interface of the integrated circuit.
That allows additional test functionality to be gained without
having to physically provide another terminal.
[0016] The test terminal 101 receives information to, e.g.,
establish a normal mode or automatic mode of operation, which are
described further herein, and to supply address information that
identifies a location in the integrated circuit that is a test
location. The test terminal may also be used to receive data to
configure the integrated circuit or the test interface of the
integrated circuit. The test location identified by the address
information may relate to digital or analog data. For example, the
address information may specify a register to be read from or
written to in order configure the integrated circuit. The address
information may specify an analog location to be "probed." In
either case, the test terminal 101 receives the test information
related to the test location.
[0017] Referring to FIG. 2, a timing diagram illustrates one aspect
of operation of the test interface 100. The voltage supply VDD can
take on a high voltage value (VDDH) and a low voltage value (VDDL).
VDDL needs to be at a voltage level sufficient to operate the test
interface block 100, but in at least some embodiments does not need
to operate those portions the integrated circuit that are unrelated
with test configuration. In addition, VDD can take on a zero
voltage value when power is off. FIG. 2 shows that at 201 the
voltage supply is VDDL and at 203, the voltage supply is at VDDH.
By way of example, VDDL may be 1.8 V and VDDH may be 2.5 V.
Different integrated circuits can have different voltage ranges
that are sufficient to operate the integrated circuit. Referring to
FIGS. 1 and 2, with the supply voltage at VDDL, the VDD threshold
detector 105 detects the VDDL voltage level and sets the VDDOK
signal 106 to be a logic low. Inverter 108 supplies the VDDOKB
signal 110 with the opposite polarity. With VDD at VDDL, the test
terminal 101 functions as an input terminal. With VDD at the VDDH
level, AND gate 107 blocks any input from the terminal since the
VDDOKB signal 110 is a logic low. With VDD at the VDDH level the
VDDOK signal enables the test signal output buffer 109, which
drives the test terminal 101 with test information from the
integrated circuit. As described above, that may be analog or
digital data.
[0018] During the time period 201 with VDD at VDDL, the test
terminal 101 receives mode configuration information. Prior to
receiving the configuration information, in certain embodiments the
test interface receives an unlock command, e.g., a unique string of
data bits to unlock the test interface. After unlocking the test
interface, the information received by the test terminal 101
includes a mode field that specifies the mode of operation. The
mode field can be a single bit or multiple bits if more than two
modes of operation are possible for the test interface. In the
operation illustrated in FIG. 2, the mode field specified a normal
mode of operation. In addition to configuring the test interface in
normal mode in 207, the test interface receives address information
that specifies the test location in the integrated circuit to be
"probed" and supplied as test information on test terminal 101. For
example, the address information may include 16 bits with 8 (or
fewer) bits being block select bits specifying a block, e.g., block
111 within the integrated circuit and 8 bits (or fewer) specifying
a node to be probed within that block. In addition, the address
information may be divided into address bits and data bits for
writing data to a particular location in the integrated circuit. As
stated earlier, the location being probed may be an analog signal
or digital data.
[0019] In the timing diagram of FIG. 2, assume the address
information received by the test terminal with VDD at VDDL during
201 was address "W". When VDD switches to VDDH during 203, the test
signal output buffer 109 drives the test information from test
location W in the block under test on signal line 119 to test
terminal 101 operating in output mode. The test information may be,
e.g., a voltage from one of multiple selectable nodes within block
111. Application Ser. No. 15/609,996, entitled TEST INTERFACE WITH
ACCESS ACROSS ISOLATION BARRIER, filed May 31, 2017, which is
incorporated herein by reference, describes how analog and digital
test locations (probe points) may be selected. FIG. 2 shows the
address bits, supplied as block select bits 115 and data select
bits 117 from the test interface 100 to identify the desired test
location.
[0020] In order to probe another test location ("Y") in normal
mode, the external test interface (not shown) has to reduce the
supply voltage to VDDL at 211 and serially write address
information that identifies Y at 215. Address Y may, e.g., identify
a test location in block 112. Turning the bus around from receive
to transmit and then back to receive takes time at the external
test interface supplying the address information and receiving the
test information. In addition, writing the additional address
information Y also takes time. After the serial write at 215 and
after VDD goes to VDDH at 212, the test terminal 101 supplies the
test information from test location Y at 217. In a debug or
verification test environment, the delay to obtain test information
from the next probe point may be acceptable. However, in a
production test environment, the longer the test time for an
integrated circuit, the lower the throughput and the higher the
cost.
[0021] Accordingly, in addition to the normal mode illustrated in
FIG. 2, embodiments described herein also support an automatic mode
in which the address information is automatically changed (e.g.,
incremented or decremented) by toggling the supply voltage VDD from
VDDH to VDDL to VDDH. FIG. 3 illustrates operation in automatic
mode. Starting at 301 with VDD at VDDL, the test terminal 101 is in
input mode and receives configuration information during 307 to
configure the test interface to automatic mode. The configuration
information may be, e.g., the two most significant bits (MSBs) of
the address. In an embodiment, the two MSBs being set to 11
indicates automatic mode and the remaining values 00, 01, 11
indicate normal mode. Of course, many other approaches can be used
to encode the configuration information. Once in automatic mode,
the test terminal receives address information. That address
information may be included with the configuration information or
may be sent in a separate serial transaction with VDD at VDDL. Note
that with VDD at VDDL, the test interface supplies block and data
select bits with a value of 0 (D'0). Responsive to VDD switching to
VDDH, the test output signal buffer 109 drives test information for
test location W to the test terminal at 309 as indicated by PROBE W
in FIG. 3.
[0022] Instead of having to perform another serial write, the
automatic mode allows the address information to be modified (e.g.,
incremented or decremented) by toggling VDD. While driving the test
information from test location W, VDD was at VDDH at 303. Toggling
VDD to VDDL at 305 and then to VDDH at 306 causes the address
information to change to (W+1) at 316 resulting in the test output
signal buffer 109 driving test information for test location (W+1)
to the test terminal at 317. Thus, the VDD signal acts as a clock
signal. The test terminal direction never has to be turned around
from output mode to input mode and back. The test equipment
receiving the test information also can remain in a receive mode
without having to initiate another serial write. The serial
operation shown at 215 in FIG. 2 can be omitted. By continuing to
toggle the supply voltage, the test interface can sweep through
test locations by incrementing (or decrementing) the current
address information. In this mode, all tests locations can be swept
by toggling VDD between VDDL and VDDH.
[0023] Referring back to FIG. 1, the high level blocks used to
cause operation in automatic mode are described in more detail. A
logic block 131 decodes a received serial string and unlocks the
test interface when the correct serial string is received. In
addition, in an embodiment, the logic block 131 also recovers the
clock from the data and provides both data and clock to test mode
and configuration block 133 along with an unlock signal 134
indicating the test interface has been unlocked. In an embodiment,
the serial interface operates using pulse width modulation to
encode the digital data but many other serial communication
protocols are well known in the art and can be used in embodiments
to supply the configuration and address information described
herein. The test mode configuration block 133 decodes received
information to determine whether to operate in normal mode or
automatic mode. The test mode configuration block also receives
address information from block 131 and supplies the address
information to the auto increment and latch block 143 described
further herein.
[0024] Referring to FIG. 4, the mode decoder logic in block 133 in
an embodiment includes AND gate 401 and inverter 403, assuming two
bits of the address information determine the mode and a binary
"11" sets automatic mode. Of course, additional decoding may be
required for other aspects of the address information received.
[0025] Once automatic mode is enabled, the test mode configuration
block 133 supplies an asserted enable automatic mode signal 135 to
AND gate 137. When VDD toggles, VDDOK starts at a logic high in
311, goes to 0 in 315 and goes back high in 317. VDD threshold
detector 105 supplies AND gate 137 with VDDOK 106. When VDDOK rises
back to a logic high, that causes a rising edge on the clock signal
138 that causes an arithmetic circuit to increment (or decrement)
the address information.
[0026] FIG. 5 illustrates a high level functional block diagram of
auto increment and latch block 143. Block 143 includes a latch or
register 501 that stores address information 502 received from the
test mode configuration block 133 when a load signal (not shown) is
asserted and supplies address information 504 to the integrated
circuit, e.g., as block select 115 and data select 117. The auto
increment and latch block 143 also includes an adder circuit 505
that is loaded from latch 501 when latch 501 is loaded. In
automatic mode, the adder circuit increments (or decrements) by one
(or other predetermined amount). For ease of discussion assume
adder 505 is a one bit incrementer. After incrementing, the
incremented value is loaded into latch 501 and is supplied from
latch 501 as address 504 to select the next test location to probe,
e.g., in the form of block select and data select lines. Note that
the latch and increment functionality may be combined.
[0027] In an exemplary embodiment, the block select portion of the
address information is 8 bits and the data select portion is also 8
bits. However, in an embodiment, only a portion of the block select
portion and the data select portion are auto incremented. Referring
to FIG. 6, latch 601 receives address information 602 and supplies
address information 604 to select a test location. Three bits [2:0]
of block select and three bits [2:0] of data select are subject to
auto increment in automatic mode. Bits [7:3] of block select and
bits [7:3] of data select are unaffected by automatic mode and can
only be changed to a non-zero value using a serial write. During
auto increment mode the data select bits [2:0] will increment from
0 (000) to 7 (111). On the next increment clock, data select bits
[2:0] in adder 605 roll over to zero and block selects bits [2:0]
in adder 605 increment by one. In other words, the LSBs of block
select and data select act like a contiguous field even though
there are additional bits in the block select and data select bits
in latch 601 not subject to auto incrementing. While incrementing
has been described other embodiments may start the address
information at a particular value specified by a serial write and
decrement the address information.
[0028] While toggling the supply voltage, the increment block can
advance through the addresses. However, it may be desirable to
change all or part of the address information in automatic mode.
For example, it may be desirable to change the high order bits of
block select and/or data select. Thus, referring back to FIG. 3,
when VDD is brought down to VDDL at 305, the time period spent in
305 can be extended and a serial write similar to 215 can be
performed to change the address information that is being
incremented. Once the serial transfer completes and VDD is brought
high to VDDH, an auto-increment occurs before the next test
information is provided. For example, if the serial write writes
address information R, the probe returns test location (R+1) due to
the automatic mode increment.
[0029] The auto increment and latch block can utilize any increment
or decrement value useful for the embodiment. In other embodiments
a different sort of arithmetic circuit may be used to modify the
address information. While the address information has been
described in one embodiment as containing block select and data
select information, in other embodiments the address information is
not broken down in block select and data select.
[0030] Thus, various aspects have been described relating to
improved test access to an integrated circuit particularly useful
during production testing. The description of the invention set
forth herein is illustrative, and is not intended to limit the
scope of the invention as set forth in the following claims. Other
variations and modifications of the embodiments disclosed herein,
may be made based on the description set forth herein, without
departing from the scope of the invention as set forth in the
following claims.
* * * * *