U.S. patent application number 15/749107 was filed with the patent office on 2019-05-23 for ffs type tft array substrate and the manufacturing method thereof.
The applicant listed for this patent is Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.. Invention is credited to Meng Chen, Hui Xia, Zhichao Zhou.
Application Number | 20190157301 15/749107 |
Document ID | / |
Family ID | 66532545 |
Filed Date | 2019-05-23 |
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United States Patent
Application |
20190157301 |
Kind Code |
A1 |
Zhou; Zhichao ; et
al. |
May 23, 2019 |
FFS TYPE TFT ARRAY SUBSTRATE AND THE MANUFACTURING METHOD
THEREOF
Abstract
The present invention provides an FFS type TFT array substrate
and a manufacturing method thereof. The manufacturing method for an
FFS type TFT array substrate of the present invention comprises
that a gate electrode, a scanning line, a common electrode, and a
common electrode line are formed in one photomask process.
Comparing with the conventional art, the present invention
simplifies the manufacturing process, with fewer photomasks, and a
shorter processing time, therefore, the production cost is low. The
fabrication process of the FFS type TFT array substrate of the
present invention is simple, has low production cost and excellent
electrical performance.
Inventors: |
Zhou; Zhichao; (Shenzhen
City, CN) ; Xia; Hui; (Shenzhen City, CN) ;
Chen; Meng; (Shenzhen City, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Shenzhen China Star Optoelectronics Semiconductor Display
Technology Co., Ltd. |
Shenzhen City, GD |
|
CN |
|
|
Family ID: |
66532545 |
Appl. No.: |
15/749107 |
Filed: |
December 20, 2017 |
PCT Filed: |
December 20, 2017 |
PCT NO: |
PCT/CN2017/117346 |
371 Date: |
January 30, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G02F 2201/121 20130101;
G02F 1/134363 20130101; G02F 2201/123 20130101; H01L 27/127
20130101; H01L 27/1288 20130101; H01L 27/1248 20130101; H01L 27/124
20130101; H01L 27/1237 20130101; G02F 1/134309 20130101; H01L
29/41733 20130101; G02F 2001/134372 20130101; H01L 27/1259
20130101; G02F 2001/136231 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12; G02F 1/1343 20060101 G02F001/1343 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 22, 2017 |
CN |
201711177283.7 |
Claims
1. A manufacturing method for a fringe field switching (FFS) type
thin film transistor (TFT) array substrate, comprising: providing a
base substrate, and forming a gate electrode, a scanning line, a
common electrode and a common electrode line on the base substrate
by using a first photomask process; wherein the gate electrode is
connected with the scanning line, and the common electrode is
connected with the common electrode line; depositing a gate
insulating layer on the gate electrode, the scanning line, the
common electrode, the common electrode line and the base substrate,
and depositing a semiconductor layer on the gate insulating layer,
patterning the semiconductor layer by using a second photomask
process, so as to obtain an active layer corresponding onto the
gate electrode; disposing a source/drain metal layer on the active
layer and the gate insulating layer, and patterning the
source/drain metal layer by using a third photomask process, so as
to obtain a source electrode, a drain electrode, and a data line;
wherein, the source electrode and the drain electrode are
respectively in contact with the active layer; the data line is
connected with the source electrode; forming a passivation layer on
the source electrode, the drain electrode, the data line, the
active layer, and the gate insulating layer, patterning the
passivation layer by using a fourth photomask process, so as to
obtain a first through hole located on the passivation layer, the
first through hole corresponding onto the drain electrode;
depositing a second transparent conductive layer on the passivation
layer, and patterning the second transparent conductive layer by
using a fifth photomask process, so as to obtain a pixel electrode
on the passivation layer; wherein the pixel electrode is connected
with the drain electrode via the first through hole located on the
passivation layer; or forming a passivation layer on the source
electrode, the drain electrode, the data line, the active layer,
and the gate insulating layer, and forming a planer layer on the
passivation layer, patterning the passivation layer and the planer
layer by using a fourth photomask process, so as to obtain a second
through hole located on the passivation layer and the planer layer,
the second through hole corresponding onto the drain electrode;
depositing a second transparent conductive layer on the planer
layer, and patterning the second transparent conductive layer by
using a fifth photomask process, so as to obtain a pixel electrode
on the planer layer; wherein the pixel electrode is connected with
the drain electrode via the second through hole located on the
passivation layer and the planer layer; wherein the gate electrode
and the scanning line have a dual-layer structure comprising a
layer of a first material and a second layer of a second material
disposed on a top of the layer of the first material layer, and
common electrode and the common electrode line have a single-layer
structure comprising a layer of the first material.
2. The manufacturing method for a FFS type TFT array substrate
according to claim 1, wherein in the step of forming a gate
electrode, a scanning line, a common electrode and a common
electrode line on the base substrate by using a first photomask
process further comprises: depositing a first transparent
conductive layer on the base substrate, patterning the first
transparent conductive layer by using the first photomask process,
so as to obtain a predetermined pattern of the gate electrode and a
predetermined pattern of the scanning line, the common electrode,
and the common electrode line; plating a first metal layer on the
predetermined pattern of the gate electrode and the predetermined
pattern of the scanning line, so as to obtain the gate electrode
and the scanning line; wherein a conductivity of the first metal
layer is greater than a conductivity of the first transparent
conductive layer.
3. The manufacturing method for a FFS type TFT array substrate
according to claim 2, wherein the first transparent conductive
layer is selected from the group consisting of transparent
conductive metal oxide; and the first metal layer is selected from
the group consisting of copper.
4. The manufacturing method for a FFS type TFT array substrate
according to claim 2, wherein a process of plating a first metal
layer on the predetermined pattern of the gate electrode and the
predetermined pattern of the scanning line is an electroplating
process.
5. The manufacturing method for a FFS type TFT array substrate
according to claim 1, wherein the passivation layer is selected
from the group consisting of silicon oxide and silicon nitride, and
the planer layer is selected from the group consisting of an
organic photoresist material.
6. The manufacturing method for a FFS type TFT array substrate
according to claim 1, wherein after forming the passivation layer
on the source electrode, the drain electrode, the data line, the
active layer, and the gate insulating layer, the fourth photomask
process comprises processes of coating photoresist, exposure,
development, dry etching and photoresist stripping; after forming
the passivation layer on the source electrode, the drain electrode,
the data line, the active layer, and the gate insulating layer, and
after forming the planer layer on the passivation layer, the fourth
photomask process comprises processes of exposure, development, and
dry etching.
7. A fringe field switching (FFS) type thin film transistor (TFT)
array substrate, comprising: a base substrate; a gate electrode, a
scanning line, a common electrode, and a common electrode line
being disposed on the base substrate; wherein the gate electrode is
connected with the scanning line, and the common electrode is
connected with the common electrode line; a gate insulating layer
being disposed on the gate electrode, the scanning line, the common
electrode, the common electrode line and the base substrate; an
active layer being disposed on the gate insulating layer and
corresponding onto the gate electrode; a source electrode and a
drain electrode being disposed on the active layer and the gate
insulating layer, and a data line being disposed on the gate
insulating layer; wherein, the source electrode and the drain
electrode are respectively in contact with the active layer; the
data line is connected with the source electrode; a passivation
layer being disposed on the source electrode, the drain electrode,
the data line, the active layer, and the gate insulating layer; a
first through hole being disposed on the passivation layer and
corresponding onto the drain electrode; a pixel electrode being
disposed on the passivation layer; wherein the pixel electrode is
connected with the drain electrode via the first through hole
located on the passivation layer; or a passivation layer being
disposed on the source electrode, the drain electrode, the data
line, the active layer, and the gate insulating layer, and a planer
layer being disposed on the passivation layer, a second through
hole being disposed on the passivation layer and the planer layer
and corresponding onto the drain electrode; a pixel electrode being
disposed on the planer layer; wherein the pixel electrode is
connected with the drain electrode via the second through hole
located on the passivation layer and the planer layer; wherein the
gate electrode and the scanning line have a dual-layer structure
comprising a layer of a first material and a second layer of a
second material disposed on a top of the layer of the first
material layer, and common electrode and the common electrode line
have a single-layer structure comprising a layer of the first
material.
8. The FFS type TFT array substrate according to claim 7, wherein
the common electrode and the common electrode line comprise a first
transparent conductive layer disposed on the base substrate, the
gate electrode and the scanning line comprise the first transparent
conductive layer and a first metal layer disposed on the first
transparent conductive layer; wherein a conductivity of the first
metal layer is greater than a conductivity of the first transparent
conductive layer.
9. The FFS type TFT array substrate according to claim 8, wherein
the first transparent conductive layer is selected from the group
consisting of transparent conductive metal oxide; and the first
metal layer is selected from the group consisting of copper.
10. The FFS type TFT array substrate according to claim 7, wherein
the passivation layer is selected from the group consisting of
silicon oxide and silicon nitride, and the planer layer is selected
from the group consisting of an organic photoresist material.
11. A manufacturing method for a fringe field switching (FFS) type
thin film transistor (TFT) array substrate, comprising: providing a
base substrate, and forming a gate electrode, a scanning line, a
common electrode and a common electrode line on the base substrate
by using a first photomask process; wherein the gate electrode is
connected with the scanning line, and the common electrode is
connected with the common electrode line; depositing a gate
insulating layer on the gate electrode, the scanning line, the
common electrode, the common electrode line and the base substrate,
and depositing a semiconductor layer on the gate insulating layer,
patterning the semiconductor layer by using a second photomask
process, so as to obtain an active layer corresponding onto the
gate electrode; disposing a source/drain metal layer on the active
layer and the gate insulating layer, and patterning the
source/drain metal layer by using a third photomask process, so as
to obtain a source electrode, a drain electrode, and a data line;
wherein, the source electrode and the drain electrode are
respectively in contact with the active layer; the data line is
connected with the source electrode; forming a passivation layer on
the source electrode, the drain electrode, the data line, the
active layer, and the gate insulating layer, patterning the
passivation layer by using a fourth photomask process, so as to
obtain a first through hole located on the passivation layer, the
first through hole being corresponding onto the drain electrode;
depositing a second transparent conductive layer on the passivation
layer, and patterning the second transparent conductive layer by
using a fifth photomask process, so as to obtain a pixel electrode
on the passivation layer; wherein the pixel electrode is connected
with the drain electrode via the first through hole located on the
passivation layer; or forming a passivation layer on the source
electrode, the drain electrode, the data line, the active layer,
and the gate insulating layer, and forming a planer layer on the
passivation layer, patterning the passivation layer and the planer
layer by using a fourth photomask process, so as to obtain a second
through hole located on the passivation layer and the planer layer,
the second through hole being corresponding onto the drain
electrode; depositing a second transparent conductive layer on the
planer layer, and patterning the second transparent conductive
layer by using a fifth photomask process, so as to obtain a pixel
electrode on the planer layer; wherein the pixel electrode is
connected with the drain electrode via the second through hole
located on the passivation layer and the planer layer; wherein in
the step of forming a gate electrode, a scanning line, a common
electrode and a common electrode line on the base substrate by
using a first photomask process further comprises: depositing a
first transparent conductive layer on the base substrate,
patterning the first transparent conductive layer by using the
first photomask process, so as to obtain a predetermined pattern of
the gate electrode and a predetermined pattern of the scanning
line, the common electrode, and the common electrode line; plating
a first metal layer on the predetermined pattern of the gate
electrode and the predetermined pattern of the scanning line, so as
to obtain the gate electrode and the scanning line; wherein a
conductivity of the first metal layer is greater than a
conductivity of the first transparent conductive layer; wherein the
first transparent conductive layer is selected from the group
consisting of transparent conductive metal oxide; and the first
metal layer is selected from the group consisting of copper;
wherein a process of plating a first metal layer on the
predetermined pattern of the gate electrode and the predetermined
pattern of the scanning line is an electroplating process; wherein
the passivation layer is selected from the group consisting of
silicon oxide and silicon nitride, and the planer layer is selected
from the group consisting of an organic photoresist material; and
wherein the gate electrode and the scanning line have a dual-layer
structure comprising a layer of a first material and a second layer
of a second material disposed on a top of the layer of the first
material layer, and common electrode and the common electrode line
have a single-layer structure comprising a layer of the first
material, the layer of the first material comprising the first
transparent conductive layer, the layer of the second material
comprising the first metal layer.
12. The manufacturing method for a FFS type TFT array substrate
according to claim 11, wherein after forming the passivation layer
on the source electrode, the drain electrode, the data line, the
active layer, and the gate insulating layer, the fourth photomask
process comprises processes of coating photoresist, exposure,
development, dry etching and photoresist stripping; after forming
the passivation layer on the source electrode, the drain electrode,
the data line, the active layer, and the gate insulating layer, and
after forming the planer layer on the passivation layer, the fourth
photomask process comprises processes of exposure, development, and
dry etching.
Description
BACKGROUND OF THE INVENTION
Field of Invention
[0001] The present invention relates to the field of display
technology, and more particularly to a fringe field switching (FFS)
thin film transistor (TFT) array substrate and a manufacturing
thereof.
Description of Prior Art
[0002] Liquid crystal displays (LCDs) such as flat panel display
devices are widely used in mobile phones, televisions, personal
digital assistants, digital cameras, notebooks, desktop, other
consumer electronics products and etc. for high quality, power
saving, thin body and wide application range. The LCDs has become
the mainstream in display device.
[0003] Most of the liquid crystal display (LCD) devices on the
market are backlight type LCDs, which comprise a LCD panel and a
backlight module. In general, the LCD panel is composed of a color
filter (CF) substrate, a thin film transistor (TFT) substrate, a
liquid crystal (LC) sandwiched between the CF substrate and the TFT
substrate, and a sealant frame sealant.
[0004] TFT-LCDs can be classified into a vertical electric field
type and a horizontal electric field type, according to the
direction of the electric field driving the LC. A vertical electric
field TFT-LCD needs to form pixel electrodes on the TFT array
substrate and form common electrodes on the CF substrate; and a
horizontal electric field TFT-LCD needs to form pixel electrodes
and common electrodes on the TFT array substrate at the same time.
The vertical electric field type TFT-LCDs comprise a twist nematic
(TN) TFT-LCD; the horizontal electric field TFT-LCDs comprise a
Fringe Field Switching (FFS) type TFT-LCD and an in-plane switching
(IPS) type TFT-LCD. The horizontal electric field TFT-LCDs,
especially, the FFS TFT-LCDs are widely used in the field of LCDs,
for its high transmittance, wide viewing angle, fast response and
low power consumption, and etc. However, presently, the
manufacturing method for the FFS type TFT array substrate usually
uses 6 photomask processes. Due to the high fabrication cost of the
photomask and the long process time of the 6 photomask processes,
the current fabrication cost of the FFS type TFT array substrate is
relatively high.
SUMMARY OF THE INVENTION
[0005] An object of the present invention is to provide a method
for fabricating an FFS type TFT array substrate, which uses less
photomask processes and low production cost.
[0006] An object of the present invention is to further provide an
FFS type TFT array substrate with a simple fabrication process, low
production cost and excellent electrical performance.
[0007] In order to achieve the object, the present invention
provides a manufacturing method for an FFS type TFT array
substrate, which comprises:
[0008] A base substrate is provided. A gate electrode, a scanning
line, a common electrode and a common electrode line are formed on
the base substrate by using a first photomask process. The gate
electrode is connected with the scanning line. The common electrode
is connected with the common electrode line.
[0009] A gate insulating layer is deposited on the gate electrode,
the scanning line, the common electrode, the common electrode line
and the base substrate. A semiconductor layer is deposited on the
gate insulating layer. The semiconductor layer is patterned by
using a second photomask process, so as to obtain an active layer
corresponding onto the gate electrode.
[0010] A source/drain metal layer is deposited on the active layer
and the gate insulating layer. The source/drain metal layer is
patterned by using a third photomask process, so as to obtain a
source electrode, a drain electrode, and a data line. The source
electrode and the drain electrode are respectively in contact with
the active layer. The data line is connected with the source
electrode.
[0011] A passivation layer is formed on the source electrode, the
drain electrode, the data line, the active layer, and the gate
insulating layer. The passivation layer is patterned by using a
fourth photomask process, so as to obtain a first through hole
located on the passivation layer. The first through hole is
disposed corresponding onto the drain electrode. A second
transparent conductive layer is deposited on the passivation layer,
and the second transparent conductive layer is patterned by using a
fifth photomask process, so as to obtain a pixel electrode on the
passivation layer. The pixel electrode is connected with the drain
electrode via the first through hole located on the passivation
layer.
[0012] Or, a passivation layer is formed on the source electrode,
the drain electrode, the data line, the active layer, and the gate
insulating layer. A planer layer is formed on the passivation
layer. The passivation layer and the planer layer are patterned by
using a fourth photomask process, so as to obtain a second through
hole located on the passivation layer and the planer layer. The
second through hole is disposed corresponding onto the drain
electrode. A second transparent conductive layer is deposited on
the planer layer. The second transparent conductive layer is
patterned by using a fifth photomask process, so as to obtain a
pixel electrode on the planer layer. The pixel electrode is
connected with the drain electrode via the second through hole
located on the passivation layer and the planer layer.
[0013] In the step of forming a gate electrode, a scanning line, a
common electrode and a common electrode line on the base substrate
by using a first photomask process further comprises:
[0014] A first transparent conductive layer is deposited on the
base substrate. The first transparent conductive layer is patterned
by using the first photomask process, so as to obtain a
predetermined pattern of the gate electrode and a predetermined
pattern of the scanning line, the common electrode, and the common
electrode line.
[0015] A first metal layer is plated on the predetermined pattern
of the gate electrode and the predetermined pattern of the scanning
line, so as to obtain the gate electrode and the scanning line. A
conductivity of the first metal layer is greater than a
conductivity of the first transparent conductive layer.
[0016] The first transparent conductive layer is selected from the
group consisting of transparent conductive metal oxide. The first
metal layer is selected from the group consisting of copper.
[0017] A process of plating a first metal layer on the
predetermined pattern of the gate electrode and the predetermined
pattern of the scanning line is an electroplating process.
[0018] The passivation layer is selected from the group consisting
of silicon oxide and silicon nitride. The planer layer is selected
from the group consisting of an organic photoresist material.
[0019] After the passivation layer is formed on the source
electrode, the drain electrode, the data line, the active layer,
and the gate insulating layer, the fourth photomask process
comprises processes of coating photoresist, exposure, development,
dry etching and photoresist stripping.
[0020] After the passivation layer is formed on the source
electrode, the drain electrode, the data line, the active layer,
and the gate insulating layer, and the planer layer is formed on
the passivation layer, the fourth photomask process comprises
processes of exposure, development, and dry etching.
[0021] The present invention further provides an FFS TFT array
substrate, which comprises:
[0022] A base substrate.
[0023] A gate electrode, a scanning line, a common electrode, and a
common electrode line are disposed on the base substrate. The gate
electrode is connected with the scanning line. The common electrode
is connected with the common electrode line.
[0024] A gate insulating layer is disposed on the gate electrode,
the scanning line, the common electrode, the common electrode line
and the base substrate.
[0025] An active layer is disposed on the gate insulating layer and
corresponding onto the gate electrode.
[0026] A source electrode and a drain electrode are disposed on the
active layer and the gate insulating layer. A data line is disposed
on the gate insulating layer. The source electrode and the drain
electrode are respectively in contact with the active layer. The
data line is connected with the source electrode.
[0027] A passivation layer is disposed on the source electrode, the
drain electrode, the data line, the active layer, and the gate
insulating layer. A first through hole is disposed on the
passivation layer and corresponding onto the drain electrode. A
pixel electrode is disposed on the passivation layer. The pixel
electrode is connected with the drain electrode via the first
through hole located on the passivation layer.
[0028] Or, a passivation layer is disposed on the source electrode,
the drain electrode, the data line, the active layer, and the gate
insulating layer. A planer layer is disposed on the passivation
layer. A second through hole is disposed on the passivation layer
and the planer layer and corresponding disposed onto the drain
electrode. A pixel electrode is disposed on the planer layer. The
pixel electrode is connected with the drain electrode via the
second through hole located on the passivation layer and the planer
layer.
[0029] The common electrode and the common electrode line comprise
a first transparent conductive layer disposed on the base
substrate. The gate electrode and the scanning line comprise the
first transparent conductive layer and a first metal layer disposed
on the first transparent conductive layer. A conductivity of the
first metal layer is greater than a conductivity of the first
transparent conductive layer.
[0030] The first transparent conductive layer is selected from the
group consisting of transparent conductive metal oxide. The first
metal layer is selected from the group consisting of copper.
[0031] The passivation layer is selected from the group consisting
of silicon oxide and silicon nitride. The planer layer is selected
from the group consisting of an organic photoresist material.
[0032] The present invention further provides another manufacturing
method for an FFS type TFT array substrate, which comprises:
[0033] A base substrate is provided. A gate electrode, a scanning
line, a common electrode and a common electrode line are formed on
the base substrate by using a first photomask process. The gate is
connected with the scanning line. The common electrode is connected
with the common electrode line.
[0034] A gate insulating layer is deposited on the gate, the
scanning line, the common electrode, the common electrode line and
the base substrate. A semiconductor layer is deposited on the gate
insulating layer. The semiconductor layer is patterned by using a
second photomask process, so as to obtain an active layer
corresponding onto the gate electrode.
[0035] A source/drain metal layer is deposited on the active layer
and the gate insulating layer. The source/drain metal layer is
patterned by using a third photomask process, so as to obtain a
source electrode, a drain electrode, and a data line. The source
electrode and the drain electrode are respectively in contact with
the active layer. The data line is connected with the source
electrode.
[0036] A passivation layer is formed on the source electrode, the
drain electrode, the data line, the active layer, and the gate
insulating layer. The passivation layer is patterned by using a
fourth photomask process, so as to obtain a first through hole
located on the passivation layer. The first through hole is
disposed corresponding onto the drain electrode. A second
transparent conductive layer is deposited on the passivation layer,
and the second transparent conductive layer is patterned by using a
fifth photomask process, so as to obtain a pixel electrode on the
passivation layer. The pixel electrode is connected with the drain
electrode via the first through hole located on the passivation
layer.
[0037] Or, a passivation layer is formed on the source electrode,
the drain electrode, the data line, the active layer, and the gate
insulating layer. A planer layer is formed on the passivation
layer. The passivation layer and the planer layer are patterned by
using a fourth photomask process, so as to obtain a second through
hole located on the passivation layer and the planer layer. The
second through hole is disposed corresponding onto the drain
electrode. A second transparent conductive layer is deposited on
the planer layer. The second transparent conductive layer is
patterned by using a fifth photomask process, so as to obtain a
pixel electrode on the planer layer. The pixel electrode is
connected with the drain electrode via the second through hole
located on the passivation layer and the planer layer.
[0038] Wherein in the step of forming a gate electrode, a scanning
line, a common electrode and a common electrode line on the base
substrate by using a first photomask process further comprises:
[0039] A first transparent conductive layer is deposited on the
base substrate. The first transparent conductive layer is patterned
by using the first photomask process, so as to obtain a
predetermined pattern of the gate electrode and a predetermined
pattern of the scanning line, the common electrode, and the common
electrode line.
[0040] A first metal layer is plated on the predetermined pattern
of the gate electrode and the predetermined pattern of the scanning
line, so as to obtain the gate electrode and the scanning line. A
conductivity of the first metal layer is greater than a
conductivity of the first transparent conductive layer.
[0041] Wherein the first transparent conductive layer is selected
from the group consisting of transparent conductive metal oxide.
The first metal layer is selected from the group consisting of
copper.
[0042] Wherein a process of plating a first metal layer on the
predetermined pattern of the gate electrode and the predetermined
pattern of the scanning line is an electroplating process.
[0043] The passivation layer is selected from the group consisting
of silicon oxide and silicon nitride. The planer layer is selected
from the group consisting of an organic photoresist material.
[0044] The beneficial effects of the present invention are: The
manufacturing method for an FFS type TFT array substrate of the
present invention comprises that a gate electrode, a scanning line,
a common electrode, and a common electrode line are formed in one
photomask process. Comparing with the conventional art, the present
invention simplifies the manufacturing process, with fewer
photomasks, and a shorter processing time, therefore, the
production cost is low. The fabrication process of the FFS type TFT
array substrate of the invention is simple, has low production cost
and excellent electrical performance.
[0045] For further understanding of the features and technical
contents of the present invention, reference should be made to the
following detailed description and accompanying drawings of the
present invention. However, the drawings are for reference only and
are not intended to limit the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0046] The technical solutions of the present invention and other
beneficial effects will be apparent from the following detailed
description of specific embodiments of the present invention with
reference to the accompanying drawings.
[0047] In drawings:
[0048] FIG. 1 is a flowchart of a manufacturing method for an FFS
type TFT array substrate according to the present invention.
[0049] FIG. 2 is a schematic top view of a step S11 of the
manufacturing method for an FFS type TFT array substrate according
to the present invention.
[0050] FIG. 3 is a schematic cross-sectional view of FIG. 2.
[0051] FIG. 4 is a schematic top view of a step S12 of the
manufacturing method for an FFS type TFT array substrate according
to the present invention.
[0052] FIG. 5 is a schematic cross-sectional view of FIG. 4.
[0053] FIG. 6 is a schematic top view of a step S2 of the
manufacturing method for an FFS type TFT array substrate according
to the present invention.
[0054] FIG. 7 is a schematic cross-sectional view of FIG. 6.
[0055] FIG. 8 is a schematic top view of a step S3 of the
manufacturing method for an FFS type TFT array substrate according
to the present invention.
[0056] FIG. 9 is a schematic cross-sectional view of FIG. 8.
[0057] FIG. 10 is a schematic top view of a step S4 of the
manufacturing method for an FFS type TFT array substrate according
to the present invention.
[0058] FIGS. 11a and 11b are schematic cross-sectional views of
FIG. 10.
[0059] FIG. 12 is a schematic top view of a step S5 of the
manufacturing method for an FFS type TFT array substrate according
to the present invention.
[0060] FIGS. 13a and 13b are schematic cross-sectional views of
FIG. 12.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0061] To further illustrate the technical solutions adopted by the
present invention and the effects thereof, the following describes
the preferred embodiments of the present invention and the
accompanying drawings in detail.
[0062] Please refer to FIG. 1, the present invention provides a
manufacturing method for an FFS type TFT array substrate, which
comprises below steps:
[0063] S1, as shown in FIGS. 2-5. A base substrate 10 is provided.
A gate electrode 21, a scanning line 22, a common electrode 23 and
a common electrode line 24 are formed on the base substrate 10 by
using a first photomask process. The gate electrode 21 is connected
with the scanning line 22. The common electrode 23 is connected
with the common electrode line 24.
[0064] Specifically, the step of forming a gate electrode 21, a
scanning line 22, a common electrode 23 and a common electrode line
24 on the base substrate 10 by using a first photomask process
further comprises:
[0065] S11, as shown in FIGS. 2-3. A first transparent conductive
layer 11 is deposited on the base substrate 10. The first
transparent conductive layer 11 is patterned by using the first
photomask process, so as to obtain a predetermined pattern of the
gate electrode 15 and a predetermined pattern of the scanning line
16, the common electrode 23, and the common electrode line 24.
[0066] S12, as shown in FIGS. 4-5. A first metal layer 12 is plated
on the predetermined pattern of the gate electrode 15 and the
predetermined pattern of the scanning line 16, so as to obtain the
gate electrode 21 and the scanning line 22. A conductivity of the
first metal layer 12 is greater than a conductivity of the first
transparent conductive layer 11.
[0067] Specifically, the first transparent conductive layer 11 is
selected from a group consisting of a transparent conductive metal
oxide such as indium tin oxide (ITO), and the first transparent
conductive layer 11 is deposited by PVD.
[0068] Specifically, the first metal layer 12 is selected from the
group consisting of copper.
[0069] Because the common electrode 23 and the common electrode
line 24 do not need to have low resistance, the electrical
performance requirement can be satisfied only by the first
transparent conductive layer 11. Because the gate electrode 21 and
the scanning line 22 need to have low resistance, the transparent
conductive layer 11 is plated with the first metal layer 12 (it's
better to be Copper) to have a better conductivity to prepare the
gate electrode 21 and the scanning line 22, and the resistance
value thereof can be reduced to meet the corresponding electrical
performance requirements.
[0070] Specifically, a process of plating a first metal layer 12 on
the predetermined pattern of the gate electrode 15 and the
predetermined pattern of the scanning line 16 is an electroplating
process. In the electroplating process, the predetermined pattern
of the gate electrode 15 and the predetermined pattern of the
scanning line 16 are electrically connected, however, the common
electrode 23 and the common electrode line 24 are electrically
disconnected, so that the first metal layer 12 can be only plated
on the predetermined pattern of the gate electrode 15 and the
predetermined pattern of the scanning line 16, instead of being
plated on the common electrode 23 and the common electrode line
24.
[0071] Specifically, with plating the first metal layer 12 on the
predetermined pattern of the gate electrode 15 and the
predetermined pattern of the scanning line 16, the present
invention can improve the conductivity performance of the gate
electrode 21 and the scanning line 22.
[0072] Specifically, the base substrate 10 is a glass
substrate.
[0073] Specifically, the first photomask process comprises
processes of coating photoresist, exposure, development, dry
etching and photoresist stripping.
[0074] S2, as shown in FIGS. 6-7. A gate insulating layer 30 is
deposited on the gate electrode 21, the scanning line 22, the
common electrode 23, the common electrode line 24 and the base
substrate 10. A semiconductor layer 35 is deposited on the gate
insulating layer 30. The semiconductor layer 35 is patterned by
using a second photomask process, so as to obtain an active layer
40 corresponding onto the gate electrode 21.
[0075] Specifically, the gate insulating layer 30 is selected from
the group consisting of silicon oxide (SiOx) and silicon nitride
(SiNx).
[0076] Specifically, the semiconductor layer 35 is selected from
the group consisting of amorphous silicon, polycrystalline silicon,
and metal oxide.
[0077] Specifically, the gate insulating layer 30 and the
semiconductor layer 35 are both deposited by chemical vapor
deposition (CVD).
[0078] Specifically, the second photomask process comprises
processes of coating photoresist, exposure, development, dry
etching and photoresist stripping.
[0079] S3, as shown in FIGS. 8-9. A source/drain metal layer 45 is
deposited on the active layer 40 and the gate insulating layer 30.
The source/drain metal layer 45 is patterned by using a third
photomask process, so as to obtain a source electrode 51, a drain
electrode 52, and a data line 53. The source electrode 51 and the
drain electrode 52 are respectively in contact with the active
layer 40. The data line 53 is connected with the source electrode
51.
[0080] Specifically, the source/drain metal layer 45 is deposited
by physical vapor deposition (PVD).
[0081] Specifically, the third photomask process comprises
processes of coating photoresist, exposure, development, dry
etching and photoresist stripping.
[0082] S4, as shown in FIGS. 10 and 11a. A passivation layer 60 is
formed on the source electrode 51, the drain electrode 52, the data
line 53, the active layer 40, and the gate insulating layer 30. The
passivation layer 60 is patterned by using a fourth photomask
process, so as to obtain a first through hole 61 located on the
passivation layer 60. The first through hole 61 is disposed
corresponding onto the drain electrode 52.
[0083] Or, as shown in FIGS. 10 and 11b. A passivation layer 60 is
formed on the source electrode 51, the drain electrode 52, the data
line 53, the active layer 40, and the gate insulating layer 30. A
planer layer 70 is formed on the passivation layer 60. The
passivation layer 60 and the planer layer 70 are patterned by using
a fourth photomask process, so as to obtain a second through hole
72 located on the passivation layer 60 and the planer layer 70. The
second through hole 72 is disposed corresponding onto the drain
electrode 52.
[0084] Specifically, the passivation layer 60 is selected from the
group consisting of silicon oxide (SiOx) and silicon nitride
(SiNx). The passivation layer 60 is formed by CVD.
[0085] Specifically, the planer layer 70 is selected from the group
consisting of an organic photoresist material. The planer layer 70
is formed by coating process.
[0086] Specifically, in S4, as shown in FIGS. 10 and 11a. After the
passivation layer 60 is formed on the source electrode 51, the
drain electrode 52, the data line 53, the active layer 40, and the
gate insulating layer 30, the fourth photomask process comprises
processes of coating photoresist, exposure, development, dry
etching and photoresist stripping.
[0087] As shown in FIGS. 10 and 11b. After the passivation layer 60
is formed on the source electrode 51, the drain electrode 52, the
data line 53, the active layer 40, and the gate insulating layer
30, and the planer layer 70 is formed on the passivation layer 60,
the fourth photomask process comprises processes of exposure,
development, and dry etching.
[0088] Specifically, by introducing the planer layer 70 on the
passivation layer 60, the planarity of the pixel electrode 80, to
be fabricated next, can be improved and the stability of the LCD
panel can be further improved.
[0089] S5, as shown in FIGS. 12 and 13a. A second transparent
conductive layer 75 is deposited on the passivation layer 60, and
the second transparent conductive layer 75 is patterned by using a
fifth photomask process, so as to obtain a pixel electrode 80 on
the passivation layer 60. The pixel electrode 80 is connected with
the drain electrode 52 via the first through hole 61 located on the
passivation layer 60.
[0090] Or, as shown in FIGS. 12 and 13b. A second transparent
conductive layer 75 is deposited on the planer layer 70. The second
transparent conductive layer 75 is patterned by using a fifth
photomask process, so as to obtain a pixel electrode 80 on the
planer layer 70. The pixel electrode 80 is connected with the drain
electrode 52 via the second through hole 72 located on the
passivation layer 60 and the planer layer 70.
[0091] Specifically, the second transparent conductive layer 75 is
selected from a group consisting of a transparent conductive metal
oxide such as indium tin oxide (ITO), and the second transparent
conductive layer 75 is deposited by PVD.
[0092] Specifically, the fifth photomask process comprises
processes of coating photoresist, exposure, development, dry
etching and photoresist stripping.
[0093] The manufacturing method for an FFS type TFT array substrate
of the present invention comprises that a gate electrode 21, a
scanning line 22, a common electrode 23, and a common electrode
line 24 are formed in one photomask process. Comparing with the
conventional art, the present invention simplifies the
manufacturing process, with fewer photomasks, and a shorter
processing time, therefore, the production cost is low.
[0094] Please refer to FIGS. 12, 13a, and 13b. Based on the above
manufacturing method for an FFS type TFT array substrate, the
present invention further provides an FFS TFT array substrate,
which comprises:
[0095] A base substrate 10.
[0096] A gate electrode 21, a scanning line 22, a common electrode
23, and a common electrode line 24 are disposed on the base
substrate 10. The gate electrode 21 is connected with the scanning
line 22. The common electrode 23 is connected with the common
electrode line 24.
[0097] A gate insulating layer 30 is disposed on the gate electrode
21, the scanning line 22, the common electrode 23, the common
electrode line 24 and the base substrate 10.
[0098] An active layer 40 is disposed on the gate insulating layer
30 and corresponding onto the gate electrode 21.
[0099] A source electrode 51 and a drain electrode 52 are disposed
on the active layer 40 and the gate insulating layer 30. A data
line 53 is disposed on the gate insulating layer 30. The source
electrode 51 and the drain electrode 52 are respectively in contact
with the active layer 40. The data line 53 is connected with the
source electrode 51.
[0100] A passivation layer 60 is disposed on the source electrode
51, the drain electrode 52, the data line 53, the active layer 40,
and the gate insulating layer 30. A first through hole 61 is
disposed on the passivation layer 60 and corresponding onto the
drain electrode 52. A pixel electrode 80 is disposed on the
passivation layer 60. The pixel electrode 80 is connected with the
drain electrode 52 via the first through hole 61 located on the
passivation layer 60.
[0101] Or, a passivation layer 60 is disposed on the source
electrode 51, the drain electrode 52, the data line 53, the active
layer 40, and the gate insulating layer 30. A planer layer 70 is
disposed on the passivation layer 60. A second through hole 72 is
disposed on the passivation layer 60 and the planer layer 70 and
corresponding onto the drain electrode 52. A pixel electrode 80 is
disposed on the planer layer 70. The pixel electrode 80 is
connected with the drain electrode 52 via the second through hole
72 located on the passivation layer 60 and the planer layer 70.
[0102] Specifically, the common electrode 23 and the common
electrode line 24 comprise a first transparent conductive layer 11
disposed on the base substrate 10. The gate electrode 21 and the
scanning line 22 comprise the first transparent conductive layer 11
and a first metal layer 12 disposed on the first transparent
conductive layer 11. A conductivity of the first metal layer 12 is
greater than a conductivity of the first transparent conductive
layer 11.
[0103] Specifically, the first transparent conductive layer 11 is
selected from a group consisting of a transparent conductive metal
oxide such as ITO.
[0104] Specifically, the first metal layer 12 is selected from the
group consisting of copper.
[0105] Specifically, the base substrate 10 is a glass
substrate.
[0106] Specifically, the gate insulating layer 30 is selected from
the group consisting of silicon oxide (SiOx) and silicon nitride
(SiNx).
[0107] Specifically, the active layer 40 is selected from the group
consisting of amorphous silicon, polycrystalline silicon, and metal
oxide.
[0108] Specifically, the passivation layer 60 is selected from the
group consisting of silicon oxide (SiOx) and silicon nitride
(SiNx). The planer layer 70 is selected from the group consisting
of an organic photoresist material.
[0109] Specifically, the pixel electrode 80 is selected from a
group consisting of a transparent conductive metal oxide such as
ITO.
[0110] The fabrication process of the FFS type TFT array substrate
of the present invention has a simple fabrication process, low
production cost and excellent electrical performance.
[0111] As mentioned above, the manufacturing method for an FFS type
TFT array substrate of the present invention comprises that a gate
electrode, a scanning line, a common electrode, and a common
electrode line are formed in one photomask process. Comparing with
the conventional art, the present invention simplifies the
manufacturing process, with fewer photomasks, and a shorter
processing time, therefore, the production cost is low. The
fabrication process of the FFS type TFT array substrate of the
invention is simple, has low production cost and excellent
electrical performance.
[0112] As mentioned above, those of ordinary skill in the art,
without departing from the spirit and scope of the present
invention, can make various kinds of modifications and variations
to the present invention. Therefore, all such modifications and
variations are intended to be included in the protection scope of
the appended claims of the present invention.
* * * * *