U.S. patent application number 16/234711 was filed with the patent office on 2019-05-09 for epitaxial growth of defect-free, wafer-scale single-layer graphene on thin films of cobalt.
The applicant listed for this patent is GlobalWafers Co., Ltd. Invention is credited to Sanjay Behura, Vikas Berry, Phong Nguyen, Michael R. Seacrist.
Application Number | 20190139762 16/234711 |
Document ID | / |
Family ID | 57184788 |
Filed Date | 2019-05-09 |
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United States Patent
Application |
20190139762 |
Kind Code |
A1 |
Berry; Vikas ; et
al. |
May 9, 2019 |
EPITAXIAL GROWTH OF DEFECT-FREE, WAFER-SCALE SINGLE-LAYER GRAPHENE
ON THIN FILMS OF COBALT
Abstract
A method for depositing a layer of graphene directly on the
surface of a substrate, such as a semiconductor substrate is
provided. Due to the strong adhesion of graphene and cobalt to a
semiconductor substrate, the layer of graphene is epitaxially
deposited.
Inventors: |
Berry; Vikas; (Chicago,
IL) ; Behura; Sanjay; (Chicago, IL) ; Nguyen;
Phong; (Witchita, KS) ; Seacrist; Michael R.;
(Lake St. Louis, MO) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GlobalWafers Co., Ltd |
|
|
|
|
|
Family ID: |
57184788 |
Appl. No.: |
16/234711 |
Filed: |
December 28, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15764370 |
Mar 29, 2018 |
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PCT/US2016/054202 |
Sep 28, 2016 |
|
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16234711 |
|
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62235800 |
Oct 1, 2015 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/02527 20130101;
H01L 21/02502 20130101; H01L 21/02658 20130101; H01L 21/02381
20130101; H01L 21/02392 20130101; H01L 21/02395 20130101; H01L
21/02491 20130101; C30B 29/02 20130101; H01L 21/0262 20130101; C30B
25/183 20130101; H01L 21/02488 20130101; C01B 32/184 20170801; C30B
25/18 20130101; H01L 21/02378 20130101; H01L 21/0242 20130101; H01L
29/1606 20130101; H01L 21/02389 20130101 |
International
Class: |
H01L 21/02 20060101
H01L021/02; C30B 25/18 20060101 C30B025/18; C30B 29/02 20060101
C30B029/02; H01L 29/16 20060101 H01L029/16; C01B 32/184 20170101
C01B032/184 |
Claims
1. A multilayer structure comprising: a silicon wafer, the silicon
wafer comprising a front wafer surface, a back wafer surface, and a
circumferential wafer edge joining the front wafer surface and the
back wafer surface; a dielectric layer in contact with the front
wafer surface of the silicon wafer; a layer comprising single
crystalline cobalt in contact with the dielectric layer, the layer
comprising single crystalline cobalt comprising a front cobalt
layer surface, a back cobalt layer surface, and a bulk cobalt layer
region between the front cobalt layer surface and the back cobalt
layer surface, wherein the back layer cobalt surface is in contact
with the dielectric layer; and a graphene layer in contact with the
front cobalt layer surface of the layer comprising single
crystalline cobalt.
2. The multilayer structure of claim 1 wherein the silicon wafer
comprises a dopant selected from the group consisting of boron (p
type), gallium (p type), phosphorus (n type), antimony (n type),
and arsenic (n type), and any combination thereof.
3. The multilayer structure of claim 1 wherein the silicon wafer
comprises boron (p type) dopant.
4. The multilayer structure of claim 1 wherein the silicon wafer
comprises phosphorus (n type) dopant.
5. The multilayer structure of claim 1 wherein the silicon wafer
comprises arsenic (n type) dopant.
6. The multilayer structure of claim 1 wherein the dielectric layer
is selected from the group consisting of a silicon dioxide layer, a
silicon nitride layer, a silicon oxynitride layer, and any
combination thereof.
7. The multilayer structure of claim 1 wherein the dielectric layer
is a multilayer comprising at least two of a silicon dioxide layer,
a silicon nitride layer, and a silicon oxynitride layer.
8. The multilayer structure of claim 1 wherein the dielectric layer
is between about 10 nanometers and about 1000 nanometers thick.
9. The multilayer structure of claim 1 wherein the dielectric layer
is between about 50 nanometers and about 300 nanometers thick.
10. The multilayer structure of claim 1 wherein the layer
comprising single crystalline cobalt is between about 50 nanometers
and about 20 micrometers thick.
11. The multilayer structure of claim 1 wherein the layer
comprising single crystalline cobalt is between about 50 nanometers
and about 10 micrometers thick.
12. The multilayer structure of claim 1 wherein the layer
comprising single crystalline cobalt is between about 50 nanometers
and about 1 micrometer thick.
13. The multilayer structure of claim 1 wherein the graphene layer
has a single mono-atomic thickness.
14. The multilayer structure of claim 1 wherein the graphene layer
has a quality factor of at least about 4.
15. The multilayer structure of claim 1 wherein the graphene layer
has a quality factor of at least about 7.
16. The multilayer structure of claim 1 wherein the graphene layer
has a quality factor of at least about 7.5.
Description
CROSS REFERENCE TO RELATED APPLICATION(S)
[0001] This application is a divisional application of U.S.
application Ser. No. 15/764,370, filed Mar. 29, 2018, the
disclosure of which is incorporated by reference as set forth in
its entirety. U.S. application Ser. No. 15/764,370 is a National
Stage application of International Application No.
PCT/US2016/054202, filed on Sep. 28, 2016, the disclosure of which
is incorporated by reference as set forth in its entirety.
International Application No. PCT/US2016/054202 claims priority to
U.S. Provisional Application Ser. No. 62/235,800 filed Oct. 1,
2015, the disclosure of which is incorporated by reference as set
forth in its entirety.
FIELD OF THE INVENTION
[0002] The field of the invention relates generally to a method for
producing atomically thick sheets of graphene on a substrate, such
as a semiconductor substrate, and more specifically to a method for
producing layers of atomically thick sheets of graphene on a cobalt
layer, which is in contact with the semiconductor substrate.
BACKGROUND OF THE INVENTION
[0003] A single atom thick, graphene is the youngest allotrope of
carbon and in the last decade it has become one of the most
researched material in the scientific community because of its
excellent optical, mechanical, and electrical properties. Graphene
is the hexagonal arrangement of carbon atoms forming a one-atom
thick planar sheet of sp.sup.2 hybridized (double bonded) carbon
atoms arranged in a honeycomb lattice. Graphene is a promising
electronic material. It has the potential to significantly impact
the semiconductor industry due to its superior electrical, thermal,
mechanical, and optical properties while at the same time offering
compatibility with existing semiconductor processing techniques.
Graphene has shown extraordinary applications, including single
molecule detection, ultrafast FETs, hydrogen visualization-template
for TEM, and tunable spintronic devices. Furthermore, it exhibits
high thermal conductivity (25.times. silicon), high mechanical
strength (strongest nanomaterial), high optical transparency (80%),
carrier controlled interband/optical-transition, and flexible
structure. Electronically, graphene is a semi-metal with zero
band-gap owing to the conduction band touching the valence band at
two points (K and K') in the Brillouin zone. Graphene's high
density of .pi.-electrons from the sp.sup.2 carbon atoms and
carrier-confinement in an open crystallographic structure imparts
it with the highest mobility measured to date.
[0004] In order to realize these benefits in volume manufacturing,
paths to integrating graphene on large diameter semiconductor,
e.g., silicon, substrates are necessary. Current processes require
graphene to be transferred from a metal base to the desired
substrate. This transfer process of an atomically-thick sheet is
challenging and leads to low yield and a significant density of
folds and tears.
[0005] Since the successful isolation, identification, and
characterization of graphene by A. Geim and K. Novoselov in 2004,
the most common method for producing flakes of graphene has been by
tape exfoliation from graphite and transfer to an oxidized silicon
wafer. The transfer process for graphene from a metal (a) is not
feasible for large scale synthesis due to inconsistent coverage,
(b) leaves transfer polymer residue on graphene (PMMA, PDMS,
thermal-adhesive-tape) increasing carrier-scattering, and (c)
produces folds, wrinkles, and tears. Therefore, transfer of
graphene is not feasible for industrial processing. Clearly, the
scotch-tape method is not scalable for semiconductor industry. As a
result of these deficiencies, this method produces small,
irregularly shaped flakes of graphene and is not suitable for
scaling to large diameter integration with silicon. See A. K. Geim
and K. S. Novovselov, "The Rise of Graphene" Nature Materials 6
(2007) 183-191.
[0006] Research into producing wafer level graphene and large area
sheets of graphene has produced the development of two main
options.
[0007] First, W. deHeer's group at Georgia Institute of Technology
has demonstrated the formation of graphene layers on SiC wafer by
silicon sublimation and out-diffusion at very high temperature. The
disadvantage of this technique is the high cost of SiC wafers, the
smaller diameter SiC wafers, and the absence of integration scale
possible on silicon wafers. Some groups are working on depositing
SiC on Silicon and attempting to form graphene on the deposited SiC
layer. See P. First, W. deHeer et al, "Epitaxial Graphenes on
Silicon Carbide" MRS Bulletin 35, 296-305 (2010).
[0008] Groups in Korea and the University of Texas system have
demonstrated graphene formation on metal foils such as Cu and Ni.
See S. Bae et al, "Roll-to Roll Production of 30 inch Graphene
Films for Transparent Electrodes" Nature Nanotechnology 5, 574-578
(2010) and X. Li et al, ECS Transactions, "Synthesis,
Characterization, and Properties of Large-Area Graphene Films" 19
(5), 41-52 (2005). Using a carbon source such as methane mixed with
hydrogen at temperatures in the 700-1000.degree. C. range in a CVD
chamber at pressure such as 500 millitorr, carbon is absorbed into
the metal film and upon cooling segregates or precipitates to the
surface of the metal foil forming single or multi-layer graphene
depending on the process conditions and the metal foil. The
graphene layer then has to be transferred to oxidized silicon. The
transfer process generally uses a material like PMMA on graphene
followed by dissolution of the metal foil, then graphene is
interfaced to the silicon dioxide layer, and finally the PMMA is
removed leaving graphene on SiO.sub.2 on Silicon. Although the
graphene formation on metal foils enables large sheets of graphene
to be produced, the process for transferring large area graphene
sheets to large diameter silicon substrates for electronic device
fabrication is challenging. Issues such as film stress, chemical
residues, bonding defects, and wrinkles in the graphene film are
likely to be significant challenges for a manufacturable
process.
BRIEF DESCRIPTION OF THE INVENTION
[0009] Briefly, the present invention is directed to a method of
forming a multilayer structure, the method comprising: epitaxially
depositing a graphene layer on a layer comprising cobalt, wherein
the layer comprising cobalt is in contact with a dielectric layer,
and further wherein the dielectric layer is in contact with a front
wafer surface of a semiconductor wafer.
[0010] The present invention is further directed to a multilayer
structure comprising: a semiconductor wafer, the semiconductor
wafer comprising a front wafer surface, a back wafer surface, and a
circumferential wafer edge joining the front wafer surface and the
back wafer surface; a dielectric layer in contact with the front
wafer surface of the semiconductor wafer; a layer comprising cobalt
in contact with the dielectric layer, the layer comprising cobalt
comprising a front layer surface, a back layer surface, and a bulk
layer region between the front layer surface and the back layer
surface, wherein the back layer surface is in contact with the
dielectric layer; and a graphene layer in contact with the front
layer surface of the layer comprising cobalt.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1A through 1D depict the process flow according to an
embodiment of the present invention.
[0012] FIGS. 2A through 2D are X-ray diffraction spectra of
deposited cobalt layers. FIG. 2A is the spectra after E-beam
evaporation. FIG. 2B is the spectra after heating to 1000.degree.
C. FIG. 2C is the spectra after heating to 1000.degree. C. and
annealing for 10 min. FIG. 2D is the spectra after graphene
growth.
[0013] FIG. 3 is Raman spectroscopic analysis of single-layer
graphene on Co surfaces. The spectrum shows graphene's
characteristic G and 2D-bands with ratio of 7.5 with no D-band.
DETAILED DESCRIPTION OF THE EMBODIMENT(S) OF THE INVENTION
[0014] The present invention is directed to a method for forming
graphene directly on a substrate, e.g., a semiconductor substrate,
such as a semiconductor wafer, which optionally comprises a
dielectric layer. By direct, it is meant that the graphene is
formed on the substrate without layer transfer. According to some
embodiments of the method of the present invention, a layer
comprising cobalt is deposited on the front surface of a
semiconductor substrate, such as a semiconductor wafer, which
optionally comprises a dielectric layer. Thereafter, a layer of
graphene is formed on the layer comprising cobalt. The present
invention is therefore additionally directed to a multilayer
article comprising a semiconductor substrate, a layer comprising
cobalt, and a layer of graphene. Advantageously, the method of the
present invention enables coating at least a portion of a large
diameter semiconductor wafer, e.g., a silicon wafer coated with
silicon dioxide, with at least a layer of graphene.
[0015] This invention relies on the high-quality, defect-free,
single-layer graphene with maximum coverage on thin films of cobalt
(Co) on SiO.sub.2/Si substrate via high temperature, and
low-pressure chemical vapor deposition of a carbon-containing gas
on the cobalt surface. The graphene formation on Co is
precipitation-based due to high carbon solubility (0.9 wt %) in Co
at high temperature (1320.degree. C.). Since the grain size of Co
is increased, during the high temperature growth, surface
nucleation of graphene is dominant and the graphene is able to grow
in large single crystal (several micrometers). Furthermore, since
the cooling stage is fast, the precipitation of carbon radical
forms single-layer on the surface of the Cobalt. Due to the strong
adhesion of graphene and cobalt, the growth is preferably
epitaxial.
I. Substrates for Layer Deposition
[0016] According to the method of the present invention, the
graphene layer or layers is/are formed directly on a semiconductor
substrate, i.e., without a layer transfer step. With reference now
to FIG. 1A, a semiconductor substrate 10 may comprise two major,
generally parallel surfaces, one of which is a front surface of the
substrate and the other of which is a back surface of the
substrate. A circumferential edge joins the front and back
surfaces, and a central plane lies between the front and back
surfaces. The substrate 10 comprises a bulk region between the
front and back surfaces. Prior to any operation as described
herein, the front surface and the back surface of the substrate 10
may be substantially identical. A surface is referred to as a
"front surface" or a "back surface" merely for convenience and
generally to distinguish the surface upon which the operations of
method of the present invention are performed. In some embodiments
of the present invention, the operations of the invention are
performed on the front surface of the semiconductor substrate 10.
In some embodiments of the present invention, the operations of the
present invention are performed on both the front surface and the
back surface of the semiconductor substrate 10.
[0017] In some embodiments, the semiconductor substrate 10
comprises a semiconductor wafer. In some embodiments, the
semiconductor material may be selected from the group consisting of
silicon, silicon carbide, sapphire, aluminum nitride, silicon
germanium, gallium arsenide, gallium nitride, indium phosphide,
indium gallium arsenide, germanium, and combinations thereof. In
some preferred embodiments, the semiconductor wafer comprises a
material selected from among silicon, silicon carbide, silicon
germanium, gallium arsenide, gallium nitride, indium phosphide,
indium gallium arsenide, and germanium. The semiconductor wafer may
comprise combinations of such materials, e.g., in a multilayer
structure. In general, the semiconductor wafer has a diameter of at
least about 20 mm, more typically between about 20 mm and about 500
mm. In some embodiments, the diameter is at least about 20 mm, at
least about 45 mm, at least about 90 mm, at least about 100 mm, at
least about 150 mm, at least about 200 mm, at least about 250 mm,
at least about 300 mm, at least about 350 mm, or even at least
about 450 mm. The semiconductor wafer may have a thickness between
about 100 micrometers and about 5000 micrometers, such as between
about 100 micrometers and about 1500 micrometers, suitably within
the range of about 500 micrometers to about 1000 micrometers.
[0018] In particularly preferred embodiments, the semiconductor
wafer comprises a wafer sliced from a single crystal silicon wafer
which has been sliced from a single crystal ingot grown in
accordance with conventional Czochralski crystal growing methods.
Such methods, as well as standard silicon slicing, lapping,
etching, and polishing techniques are disclosed, for example, in F.
Shimura, Semiconductor Silicon Crystal Technology, Academic Press,
1989, and Silicon Chemical Etching, (J. Grabmaier ed.)
Springer-Verlag, N.Y., 1982 (incorporated herein by reference). In
some preferred embodiments, the semiconductor silicon substrate is
a polished silicon wafer grown by the CZ method. The silicon
substrate may have any crystal orientation, e.g., (100), (110), and
(111).
[0019] Silicon wafer resistivity is not critical to forming a
graphene layer on the substrate. However, resistivity may vary
depending upon end use requirements. In view thereof, the wafer may
be heavily doped, may be semi-insulating, or may have a doping
profile somewhere between. The resistivity may therefore vary from
milliohm or less to megaohm or more. In some embodiments, the
single crystal semiconductor wafer comprises a p-type or an n-type
dopant. Suitable dopants include boron (p type), gallium (p type),
phosphorus (n type), antimony (n type), and arsenic (n type). The
dopant concentration is selected based on the desired resistivity
of the wafer. In some embodiments, the wafer types may have
resistivity so that they can be characterized as any of N++ type,
N+ type, N type, N- type, and N-- type. Typical N+ resistivity
ranges are as low as 10 milliohm-cm for Sb doping, N++ as low as 2
milliohm-cm for As doping, and N+++ as low as 1 milliohm-cm for P
doping. Specification ranges are usually 2-3.times. for max/min due
to segregation in crystal growth. In some embodiments, the wafer
types may have resistivity so that they can be characterized as any
of P++ type, P+ type, P type, P- type, and P-- type. Typical P+
resistivity range is as low as 10 milliohm-cm and P++ as low as 5
milliohm-cm. Specification ranges are usually 1.5-2.times. for
max/min due to segregation in crystal growth. The resistivity of
the wafer may therefore vary from about 0.1 milliohm-cm to about 10
kiloohm-cm. In some embodiments, the resistivity may range from
about 0.1 milliohm-cm to about 1 kiloohm-cm, such as from 0.1
milliohm-cm to about 100 ohm-cm, such as from 0.1 milliohm-cm to
about 10 ohm-cm, or from about 0.1 milliohm-cm to about 1 ohm-cm.
Substrate are also available in lightly doped form, such as nominal
values of 1 ohm-cm or 10 ohm-cm or 100 ohm-cm, in both N-type
(Phos) and P-type (Boron). Choice of substrate resistivity depends
on application (example if substrate is used as backgate then lower
resistivity is preferred) but should not impact growth of the
graphene layer.
[0020] With reference now to FIG. 1B, in some embodiments of the
method of the present invention, one or more of the major surfaces
of the semiconductor substrate 10 may be modified with a dielectric
layer 20. The dielectric layer may comprise silicon dioxide,
silicon nitride, silicon oxynitride, or a combination of silicon
dioxide and silicon nitride layers. In some preferred embodiments,
the semiconductor substrate 10 comprises a silicon wafer, the front
surface layer of which is oxidized. In preferred embodiments, the
front surface layer, i.e., the layer upon which the metal film is
deposited, is oxidized. In preferred embodiments wherein the
semiconductor substrate 10 comprises a silicon wafer, the front
surface of the silicon wafer is preferably oxidized such that the
front surface layer of the silicon wafer comprises a silicon
dioxide (SiO.sub.2) dielectric layer 20 having a thickness between
about 10 nm and about 1000 nm, between about 30 nm and about 1000
nm, between about 50 nm and about 500 nm, preferably between about
50 nm and about 300 nm, such as between about 90 nm and about 300
nanometers thick, or between about 90 nm and about 200 nanometers
thick. Deposition of the dielectric layer may be accomplished by
means known in the art, such as thermal oxidation (in which some
portion of the deposited semiconductor material film will be
consumed) and/or CVD oxide and/or nitride deposition. In some
embodiments, the wafer may be thermally oxidized (in which some
portion of the deposited semiconductor material film will be
consumed) or the film may be grown by CVD oxide and/or nitride
deposition. In some embodiments, the wafer may be thermally
oxidized in a furnace such as an ASM A400. The front surface of the
silicon wafer may be thermally oxidized via wet or dry oxidation,
as is known in the art. Oxidation generally occurs at temperatures
between about 800.degree. C. and about 1200.degree. C. using water
vapor and/or oxygen. The oxidizing ambient atmosphere can be a
mixture of inert gas, such as Ar or N.sub.2, and O.sub.2. The
oxygen content may vary from 1 to 10 percent, or higher. In some
embodiments, the oxidizing ambient atmosphere may be up to 100% (a
"dry oxidation"). In some embodiments, the ambient atmosphere may
comprise a mixture of inert gas, such as Ar or N.sub.2, and
oxidizing gases, such as O.sub.2 and water vapor (a "wet
oxidation"). In an exemplary embodiment, semiconductor wafers may
be loaded into a vertical furnace, such as an A400. The temperature
is ramped to the oxidizing temperature with a mixture of N.sub.2
and O.sub.2. After the desired oxide thickness has been obtained,
the O.sub.2 is turned off and the furnace temperature is reduced
and wafers are unloaded from the furnace.
[0021] In some embodiments, the semiconductor substrate 10 may
comprise a dielectric layer 20 comprising silicon nitride. In some
embodiments, the semiconductor substrate 10 comprises a silicon
wafer, the front surface layer of which is oxidized as described
above, which is followed by deposition of a silicon nitride layer.
A silicon nitride layer may be deposited on the silicon oxide layer
since silicon nitride advantageously forms a barrier layer to
reduce diffusion of metal atoms, e.g., nickel, into the silicon
oxide layer. In some embodiments, the silicon nitride layer may
range in thickness between about 10 nm and about 1000 nm, between
about 30 nm and about 1000 nm, or from about 50 nanometers to about
1000 nanometers. In some embodiments, the silicon nitride layer may
range in thickness from about 50 nanometers to about 500
nanometers. In some embodiments, the silicon nitride layer may
range in thickness from about 70 nanometers to about 250
nanometers. The thickness of the silicon nitride layer is
determined in view of the trade-off between device performance,
such that thinner layers are preferred, and an effective barrier to
prevent in-diffusion of impurities into the semiconductor
substrate, such that thicker layers are preferred. Silicon nitride
may be deposited on the surface of the silicon oxide layer by
contacting the substrate with an atmosphere of nitrogen at elevated
temperature. For example, the semiconductor may be exposed to
nitrogen gas or ammonia at temperatures ranging from about
700.degree. C. to about 1300.degree. C. In some embodiments,
silicon nitride is formed by chemical vapor deposition at about
800.degree. C. In order to incorporate nitrogen and oxygen to
deposit silicon oxynitride, the atmosphere may comprise a
combination of oxygen and nitrogen, and the temperature may be
increased to a temperature between 1100.degree. C. and 1400.degree.
C. An alternative nitrogen source is ammonia.
[0022] In some embodiments, the semiconductor substrate 10
comprising the dielectric layer 20 is cleaned prior to deposition
of the layer comprising cobalt, for example to remove organic
matter or other impurities. A suitable cleaning solution is the
piranha solution, which comprises H.sub.2SO.sub.4 (concentrated)
and H.sub.2O.sub.2 (30% solution), typically in a 3:1 ratio, but
other ratios, such as 4:1 or 7:1 are suitable. Cleaning duration is
suitably between about 15 minutes and about 2 hours.
II. Deposition of Layer comprising Cobalt
[0023] With reference to FIG. 1C, according to the method of the
present invention, the major surface of the semiconductor substrate
10, e.g., a silicon wafer comprising a dielectric layer 20, e.g., a
silicon oxide layer and optionally a silicon nitride layer and/or a
silicon oxynitride layer, is coated with a layer comprising cobalt
30. In some embodiments, the layer comprising cobalt 30 may be
deposited over the entire major surface of the semiconductor
substrate 10 comprising a dielectric layer 20. In some embodiments,
the layer comprising cobalt 30 may be deposited over a portion of
the semiconductor substrate 10 comprising a dielectric layer 20,
such as at least about 10% of the total area of the major surface,
or at least about 25% of the total area, or at least about 50% of
the total area, or at least about 75% of the total area. In some
embodiments, the layer comprising cobalt 30 may be deposited over
the entire major surface of the semiconductor substrate 10
comprising a dielectric layer 20 and thereafter metal may be
removed selectively, using conventional lithography techniques, to
thereby leave a desired pattern of metal deposition on the major
surface of the substrate. In some embodiments, the front surface
layer of the semiconductor substrate 10 comprising a dielectric
layer 20 is coated with a layer comprising cobalt 30. The front
surface layer may be completely coated with cobalt, partially
coated with cobalt, or coated with a cobalt pattern by lithography.
In some embodiments, the semiconductor substrate 10 comprises a
semiconductor wafer having a dielectric layer 20 thereon. In some
embodiments, the semiconductor substrate 10 comprises a silicon
wafer having a silicon dioxide front surface layer, and the layer
comprising cobalt 30 is deposited onto the silicon dioxide front
surface layer. The silicon dioxide layer may be completely coated
with cobalt, partially coated with cobalt, or coated with a cobalt
pattern by lithography. In some embodiments, the semiconductor
substrate 10 comprises a silicon wafer having a silicon dioxide
layer and a silicon nitride front surface layer, and the layer
comprising cobalt 30 is deposited onto the silicon nitride front
surface layer. The silicon nitride layer may be completely coated
with cobalt, partially coated with cobalt, or coated with a cobalt
pattern by lithography. For the sake of convenience, the surfaces
of the layer comprising cobalt 30 may be referred to as a "front
cobalt layer surface" and "a back cobalt layer surface." Herein,
the back cobalt layer surface is in contact with the dielectric
layer 20. The graphene layer is deposited on the front cobalt layer
surface. A bulk metal region is between the front and back cobalt
layer surfaces.
[0024] The layer comprising cobalt 30 may be deposited by
techniques known in the art, including sputtering, evaporation,
electron-beam evaporation, ion beam evaporation, chemical vapor
deposition, electrolytic plating, and metal foil bonding. In some
embodiments, the layer comprising cobalt 30 is deposited by
sputtering or evaporation using, e.g., a Sputtering and Metal
evaporation Unit. In some embodiments, a cobalt layer may be
deposited via electron-beam evaporation technique in a clean room
environment, using, for example, a Varian Electron Beam Evaporator.
Electrolytic metal plating may occur according to the methods
described by Supriya, L.; Claus, R. O. Solution-Based Assembly of
Conductive Gold Film on Flexible Polymer Substrates: Langmuir 2004,
20, 8870-8876. In some embodiments, the layer comprising cobalt 30
may be deposited by chemical vapor deposition at relatively low
temperatures, such as between about 100.degree. C. and about
300.degree. C., such as about 200.degree. C. Preferably, the layer
comprising cobalt 30 is between about 50 nanometers and about 20
micrometers thick, such as between about 50 nanometers and about 10
micrometers thick, such as between about 50 nanometers and about
1000 nanometers (1 micrometer), such as between about 100
nanometers and about 500 nanometers, such as between about 100
nanometers and about 400 nanometers, such as about 300 nanometers
or about 500 nanometers.
[0025] The use of cobalt for the deposition of a graphene layers is
advantageous since, unlike copper (with carbon solubility of 0.01
wt % at 1084.degree. C.), the graphene formation in Co is
precipitation-based. This is due to the high carbon solubility (0.9
wt %) in Co at high temperature (1320.degree. C.). Accordingly, the
carbon prefers to precipitate near the grain boundaries during
cooling. It has been observed that high temperature growth enhances
the rapid precipitation and surface nucleation so that graphene
nuclei try to attach to each other preferentially in the same
orientation resulting epitaxial growth of large coverage
single-layer graphene.
[0026] After deposition of the metal film, the multilayer structure
may be cleaned. The multilayer structure comprises the
semiconductor substrate 10, dielectric layer 20 (e.g., silicon
dioxide, which may additionally comprise a silicon nitride layer),
and a layer comprising cobalt 30. In some preferred embodiments,
the multilayer structure may be cleaned by heating the structure in
a vacuum furnace in a reducing atmosphere. A chemical vapor
deposition system may be used where only baking under high vacuum
is performed. In preferred embodiments, the reducing atmosphere
comprises hydrogen gas or other reducing gas. An inert carrier gas
may be used, such as argon or helium. In preferred embodiments, the
temperature during exposure to the reducing atmosphere is
preferably between about 800.degree. C. and about 1200.degree. C.,
such as about 1000.degree. C. The pressure is preferably
sub-atmospheric, such as less than about 100 Pa (less than about 1
Torr), preferably less than about 1 Pa (less than about 0.01 Torr),
even more preferably less than about 0.1 Pa (less than about 0.001
Torr), and even more preferably less than about 0.01 Pa (less than
about 0.0001 Torr). The cleaning anneal may adjust the grain size
of the metal film, e.g., increase the grain size at elevated
temperatures.
[0027] After heat treatment, the multilayer substrate (FIG. 1C) is
analyzed by X-ray diffraction to confirm crystallographic
orientations. The X-ray diffraction analysis reveals a single
crystalline Co film on SiO.sub.2/Si substrate, which enables the
formation of very-high quality graphene. Annealing the multilayer
structure after deposition of the layer comprising cobalt promotes
epitaxial growth, as confirmed by analyzing the Co surface before
and after annealing via X-ray diffraction (XRD). See FIGS. 2A
through 2D. That is, before anneal, the XRD pattern for room
temperature (RT) evaporated Co reveals three diffraction peaks. See
FIG. 2A. The strong peak at 44.degree. corresponds to either
hexagonal closed packed (hcp) Co(0002) or face centered cubic (fcc)
Co(111). See Ago et al., ACS Nano, 4, 7407 (2010). The XRD pattern
for non-annealed cobalt also reveals another two weak peaks are
also observed at 42.degree. (Co(200)) and 47.degree. (hcp Co(101)).
See J. Mater. Chem., 2009, 19, 7371-7378. These results confirm the
polycrystalline nature of the evaporated Co surface prior to
anneal. The layer comprising cobalt that has been subjected to
anneal reveals a different XRD pattern. For example, the Co(0002)
or Co(111) peak at 44.degree. for CVD annealed Co (1000.degree. C.
for 10 min) become stronger and narrower at it full width. See
FIGS. 2B and 2C. Additionally, anneal causes the weak peaks at
42.degree. and 47.degree. to disappear, which implies improvement
in the crystallinity of the annealed cobalt layer. A weak peak at
52.degree. appears, which may be due to Co(200). The XRD pattern of
Co surface after graphene formation shows the Co(0002) or Co(111)
peak with little less strength because of formation of the graphene
layer. See FIG. 2D.
III. Deposition of Graphene Layer
[0028] According to some embodiments of the method of the present
invention and with reference to FIG. 1C, the multilayer structure
comprising the semiconductor substrate 10, a dielectric layer 20,
and a layer comprising cobalt 30 may be exposed to a
carbon-containing gas to thereby nucleate atomic carbon on the
front cobalt layer surface of the layer comprising cobalt 30 and
between crystalline cobalt grains.
[0029] In some embodiments, the structure is placed in an
appropriate chamber, such as a CVD system, and brought to a vacuum,
such as a pressure of around 0.1 Pa (about 1 mTorr). Thereafter,
the structure is brought to the appropriate anneal temperature in a
reducing atmosphere. The temperature for anneal in a reducing
atmosphere is generally between about 500.degree. C. and about
1100.degree. C., such as between about 700.degree. C. and about
1000.degree. C. The reducing atmosphere may comprise hydrogen. The
atmosphere is preferably a reducing atmosphere, which may comprise
between about 1% and about 99% hydrogen, such as between about 70%
and about 99% hydrogen, preferably about 95% hydrogen, balance
inert gas.
[0030] In some embodiments, a carbon-containing gas flow may be
added to the reducing gas flow. The carbon-containing gas may be
selected from among volatile hydrocarbons, for example, methane,
ethane, ethylene, acetylene, propane, propylene, propyne, butane,
isobutane, butylenes, butynes, and the like. The carbon-containing
gas, e.g., methane, is a source of carbon that may precipitate into
graphene according to the process of the present invention. The
atmosphere may be a reducing atmosphere, further comprising a
reducing gas, such as hydrogen. In some embodiments, the gas may
comprise methane gas and hydrogen gas in a ratio from about 1:1 to
about 200:1, such as between about 1:1 and about 100:1, such as
about 144:15. The minimum temperature during carbon absorption
and/or adsorption is generally at least about 500.degree. C. The
maximum temperature during carbon absorption and/or adsorption is
generally no more than about 1100.degree. C. In general, the
temperature is preferably between about 700.degree. C. and about
1000.degree. C. In general, the pressure inside the reaction
chamber during hydrogen gas/methane flow is between about 10 Pa
(about 0.1 Torr) and about 1500 Pa (about 100 Torr), such as
between about 50 P (about 0.4 Torr) and about 150 Pa (about 1
Torr).
[0031] Optionally, after the flow of gases is stopped, the
structure may be held at the absorption temperature in order to
promote equilibrium of nucleation and adsorption between the
crystalline cobalt grains. The duration of equilibration after the
flow of carbon-containing gas is stopped may range from about 5
seconds to about 3600 seconds, such as about 600 seconds to about
1800 seconds. In some embodiments, the duration of carbon
in-diffusion is very short, such as about 10 seconds.
[0032] Thereafter, the multilayer structure is rapidly cooled, such
as at a rate of at least about 10.degree. C./min, at least about
50.degree. C./min, at least about 100.degree. C./min. In general,
the pressure inside the reaction chamber during cooling is between
about 10 Pa (about 0.1 Torr) and about 1500 Pa (about 100 Torr),
such as between about 50 P (about 0.4 Torr) and about 150 Pa (about
1 Torr). The atmosphere is preferably a reducing atmosphere, which
may comprise between about 1% and about 99% hydrogen, such as
between about 70% and about 99% hydrogen, preferably about 95%
hydrogen, balance inert gas. High temperature growth and rapid
cooling enhance the precipitation and surface nucleation fast so
that graphene nuclei tries to attach each other preferentially in
the same orientation resulting epitaxial growth of large coverage,
high quality single-layer graphene. See FIG. 1D, depicting a
multilayer structure comprising the semiconductor substrate 10, a
dielectric layer 20, a layer comprising cobalt 30, and the
single-layer graphene 40.
IV. Graphene Layer Quality Testing
[0033] The deposited and cooled graphene layer 40 in contact with
the layer comprising cobalt 30 may be analyzed by Raman
spectroscopy to determine the quality of the deposited layer. Raman
spectroscopy is a commanding technique to ascertain the number of
graphene layers and defects. Raman spectroscopy and 2D mapping to
determine the quality of the deposited graphene may be performed
with a 532 nm excitation laser. The quality of the deposited
graphene may be determined by reference to several bands in the
resultant Raman spectrum. See FIG. 3. These bands include: (i) the
D band (.about.1,350 cm.sup.-1) attributing to the breathing mode
of sp.sup.2 carbons activated by presence of defects, (ii) the G
band (.about.1,580 cm.sup.-1) representing the E.sub.2g mode of the
C--C stretching vibration in the graphitic lattice at the
.gamma.-point, and (iii) the 2D band (.about.2,690 cm.sup.-1) due
to the second order two-phonon process in graphene. Additionally,
in the representative sample surface (the D-band map), it is also
noticed that the intensity ratio i.e. I.sub.D/I.sub.G are
negligibly small and near the background level for most of the
graphene area, indicating low defect contents and an absence of
crystal grain boundaries, which also indicates the formation of
single grain graphene. The G-band map and 2D-band map clearly show
the presence of single-layer graphene in the whole sample surface.
The quality of a single-layer graphene may be determined by the
ratio of the intensities of Raman 2D to G-band peaks
(I.sub.2D/I.sub.G.gtoreq.2). This ratio of the intensities of Raman
2D to G-band peaks may be referred to herein as a "quality factor."
High quality graphene exhibits a Raman 2D to G-band peak ratio
(I.sub.2D/I.sub.G) or quality factor ratio of at least about 4,
such as at least about 7, at least about 7.5, at least about 8, or
even at least about 10. Additionally, in high quality graphene, no
defect induced D-band is observed. In comparison, I.sub.2D/I.sub.G
for high-quality exfoliated graphene is about 3-4.
[0034] The graphene may be further quality tested by transferring
to transmission electron microscopy grids for analysis of the
selected area electron diffraction (SAED) patterns. The SAED
patterns confirm the hexagonal nature of graphene indicating the
d-spacing of 2.15 .ANG..
[0035] The following non-limiting examples are provided to further
illustrate the present invention.
Example 1. Cobalt Deposition on Silicon Wafer Substrate
[0036] Suitable silicon wafer substrates include:
[0037] 1. A silicon wafer (n++ type) comprising a SiO.sub.2
dielectric having a thickness of 90 nm,
[0038] 2. A silicon wafer (n++ type) comprising a SiO.sub.2
dielectric having a thickness of 300 nm,
[0039] 3. A silicon wafer (p+ type) comprising a SiO.sub.2
dielectric having a thickness of 90 nm, and
[0040] 4. A silicon wafer (p+ type) comprising a SiO.sub.2
dielectric having a thickness of 300 nm,
[0041] The bulk silicon substrates were obtained from SunEdison
Semiconductor, Ltd. (St. Peters, Mo.). The substrates may be
provided with thermal silicon oxide layer, or they may be provided
without a thermal oxide layer.
[0042] The silicon wafers were cleaned using Piranha solution
(H.sub.2SO.sub.4:H.sub.2O.sub.2=3:1) as necessary for durations
between 15 minutes and 2 h. After cleaning and rinsing, a thin film
of cobalt having a thickness between about 100 nanometers and about
300 nanometers were deposited on the silicon oxide layers of each
wafer. The cobalt layer was deposited via electron-beam evaporation
technique in a clean room environment. The instrument used was a
Varian Electron Beam Evaporator. The source of cobalt, i.e., the
cobalt target, was cobalt pellets having 99.99% purity and
approximate dimensions of 1/4'' diameter.times.1/4'' length. The
metal evaporation parameters in the reaction chamber were:
Pressure: 10.sup.-7 Torr; Voltage: 10 KV; Current: 45 mA; Tooling
factor: 140%; Z-Ratio: 0.343; Density: 8.9 kg/m.sup.3; Thickness of
the deposited cobalt: 100 nm and 300 nm.
Example 2. Quality Testing of Cobalt Layer
[0043] The crystallinity of the cobalt layer is determined both
before anneal and after anneal. Crystallinity of the cobalt layer
was measured by X-ray diffraction and analysis of the XRD peaks.
The multilayer structure (Co/SiO.sub.2/Si) prepared according to
Example 1 is heat-treated and subsequently analyzed via X-ray
diffraction (XRD) to confirm crystallographic orientations. See
FIGS. 2A through 2D, which are X-ray diffraction spectra of
deposited cobalt layers. FIG. 2A is the spectra after E-beam
evaporation according to the parameters set forth in Example 1.
FIG. 2B is the spectra after heating to 1000.degree. C. FIG. 2C is
the spectra after heating to 1000.degree. C. and annealing for 10
min. FIG. 2D is the spectra after graphene growth. The X-ray
diffraction analysis reveals a single crystalline Co film on
SiO.sub.2/Si substrate, which enables the formation of very-high
quality graphene.
[0044] The XRD pattern for room temperature (RT) evaporated Co is
performed in which three diffraction peaks were observed. See FIG.
2A. The strong peak at 44.degree. corresponds to either hexagonal
closed packed (hcp) Co(0002) or face centered cubic (fcc) Co(111)
and another two weak peaks are also observed at 42.degree. (CoO
(200)) and 47.degree. (hcp Co(101)). These peaks confirm the
polycrystalline nature of evaporated Co surface.
[0045] The structure is subjected to anneal at 1000.degree. C. for
10 min. See FIG. 2B (at temperature and before anneal) and FIG. 2C
(after anneal at 1000.degree. C. for 10 minutes). The Co(0002) and
Co(111) peak at 44.degree. in the annealed cobalt layer become
stronger and narrower at it full width. The weak peaks at
42.degree. and 47.degree. disappear. The change in XRD peaks
confirms improvement in the crystallinity of Co. A weak peak at
52.degree. appears, which may be due to Co(200).
Example 3. Growth of Graphene on the Prepared Substrate Via
Chemical Vapor Deposition (CVD)
[0046] A CVD system was designed where the substrate (1.times.1
inches) was placed in a split tube furnace with a fused quartz tube
(outside diameter of 1 inch). The precursor gases included methane
(CH.sub.4) and hydrogen (H.sub.2). Initially, the chamber is
allowed to achieve a base pressure of 1 mTorr. Substrates prepared
according to Example 1 were directly placed in the center of quartz
tube's heating zone and heated to 1000.degree. C. in a hydrogen
atmosphere at a flow rate of 100 standard cubic centimeters per
minute (SCCM) to restrict further oxidation. Right after the
temperature reaches 1000.degree. C., the substrates were annealed
for 5-10 minutes at the same temperature at a pressure of 500 mTorr
in a hydrogen atmosphere at a flow rate of 15 standard cubic
centimeters per minute (SCCM). To nucleate carbon on the cobalt
surface and between cobalt grains, the gas composition was changed
to CH.sub.4:H.sub.2 at a vol:vol ratio of 144:15. The pressure
during methane:hydrogen flow was 1 Torr for 10 minutes. This was
followed by cooling at a rate of about 100.degree. C./min. See FIG.
2D for the XRD spectra of the structure after deposition of
graphene.
Example 4. Quality Testing of Epitaxially Deposited Graphene on
Cobalt
[0047] The quality of the epitaxially deposited graphene on cobalt
was tested by Raman spectroscopy and 2D mapping with a 532 nm
excitation laser. See FIG. 3, which is Raman spectroscopic analysis
of single-layer graphene on Co surfaces. The spectrum shows
graphene's characteristic G and 2D-bands with ratio of 7.5 with no
D-band. The Raman spectrum of the epitaxial graphene exhibited: (i)
a negligible D band (.about.1,350 cm.sup.-1) attributing to the
breathing mode of sp.sup.2 carbons activated by presence of
defects, (ii) a strong and sharp G band (.about.1,580 cm.sup.-)
representing the E.sub.2g mode of the C--C stretching vibration in
the graphitic lattice at the .gamma.-point, and (iii) a strong and
sharp 2D band (.about.2,690 cm.sup.-1) due to the second order
two-phonon process in graphene. In the representative sample
surface (the D-band map), it is also noticed that the intensity
ratio, i.e. I.sub.D/I.sub.G are negligibly small and near the
background level for most of the graphene area, indicating low
defect contents and an absence of crystal grain boundaries, which
also claims the formation of single grain graphene. The G-band map
and 2D-band map clearly show the presence of single-layer graphene
in the whole sample surface. The quality of a single-layer graphene
may be determined by the ratio of the intensities of Raman 2D to
G-band peaks (I.sub.2D/I.sub.G.gtoreq.2). A superior Raman 2D to
G-band peak ratio (I.sub.2D/I.sub.G)>7.5 and no defect induced
D-band is observed. In comparison, I.sub.2D/I.sub.G for
high-quality exfoliated graphene is about 3-4.
[0048] The graphene is further transferred to transmission electron
microscopy grids for analysis of the selected area electron
diffraction (SAED) patterns. The SAED pattern confirm the hexagonal
nature of graphene indicating the d-spacing of 2.15 .ANG..
[0049] This written description uses examples to disclose the
invention, including the best mode, and also to enable any person
skilled in the art to practice the invention, including making and
using any devices or systems and performing any incorporated
methods. The patentable scope of the invention is defined by the
claims, and may include other examples that occur to those skilled
in the art. Such other examples are intended to be within the scope
of the claims if they have structural elements that do not differ
from the literal language of the claims, or if they include
equivalent structural elements with insubstantial differences from
the literal languages of the claims.
* * * * *