U.S. patent application number 15/789158 was filed with the patent office on 2019-04-25 for mtj structures, stt mram structures, and methods for fabricating integrated circuits including the same.
The applicant listed for this patent is Globalfoundries Singapore Pte. Ltd.. Invention is credited to Jingsheng Chen, Shaohai Chen, Francis YongWee Poh, Danny PakChum Shum.
Application Number | 20190122799 15/789158 |
Document ID | / |
Family ID | 66171184 |
Filed Date | 2019-04-25 |
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United States Patent
Application |
20190122799 |
Kind Code |
A1 |
Shum; Danny PakChum ; et
al. |
April 25, 2019 |
MTJ STRUCTURES, STT MRAM STRUCTURES, AND METHODS FOR FABRICATING
INTEGRATED CIRCUITS INCLUDING THE SAME
Abstract
Magnetic tunnel junction (MTJ) structures, spin transfer torque
magnetic random access memory (STT MRAM) structures, and methods
for fabricating integrated circuits including such structures are
provided. In an embodiment, an MTJ structure includes a cobalt iron
carbon (CoFeC) fixed reference layer. Further, the MTJ structure
includes a cobalt iron carbon (CoFeC) free storage layer. Also, the
MTJ structure includes a tunnel barrier layer between the fixed
reference layer and the free storage layer.
Inventors: |
Shum; Danny PakChum;
(Singapore, SG) ; Poh; Francis YongWee;
(Singapore, SG) ; Chen; Jingsheng; (Singapore,
SG) ; Chen; Shaohai; (Singapore, SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Globalfoundries Singapore Pte. Ltd. |
Singapore |
|
SG |
|
|
Family ID: |
66171184 |
Appl. No.: |
15/789158 |
Filed: |
October 20, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01F 10/3254 20130101;
G11C 11/161 20130101; H01L 43/02 20130101; H01F 10/16 20130101;
H01F 10/329 20130101; H01L 43/10 20130101; H01L 27/228 20130101;
H01L 43/12 20130101; H01F 10/3286 20130101; H01L 43/08
20130101 |
International
Class: |
H01F 10/32 20060101
H01F010/32; H01L 43/08 20060101 H01L043/08; H01L 43/02 20060101
H01L043/02; H01L 43/10 20060101 H01L043/10; H01L 43/12 20060101
H01L043/12; G11C 11/16 20060101 G11C011/16 |
Claims
1. A magnetic tunnel junction (MTJ) structure comprising: a cobalt
iron carbon (CoFeC) reference layer; a cobalt iron carbon (CoFeC)
storage layer; and a tunnel barrier layer between the reference
layer and the storage layer.
2. The MTJ structure of claim 1 wherein the tunnel barrier layer is
a magnesium oxide (MgO) tunnel barrier layer.
3. The MTJ structure of claim 1 wherein the reference layer
directly contacts the tunnel barrier layer, and wherein the storage
layer directly contacts the tunnel barrier layer.
4. (canceled)
5. (canceled)
6. (canceled)
7. The MTJ structure of claim 1 wherein the storage layer includes
a first storage sublayer, a second storage sublayer, and a
non-magnetic insertion layer between the first storage sublayer and
the second storage sublayer.
8. The MTJ structure of claim 1 wherein the tunnel barrier layer
between the fixed layer and the storage layer is a first tunnel
barrier layer, and wherein the MTJ structure further comprises a
second tunnel barrier layer over the storage layer.
9. The MTJ structure of claim 1 further comprising a non-magnetic
underlayer that is non-reactive to iron.
10. The MTJ structure of claim 9 wherein the non-magnetic
underlayer comprises platinum or tantalum.
11. The MTJ structure of claim 1 wherein the MTJ structure is
substantially free of boron.
12. A spin transfer torque magnetic random access memory (STT MRAM)
structure comprising: a bottom electrode; a carbon doped reference
layer over the bottom electrode; a tunnel barrier layer over the
carbon doped reference layer; a carbon doped storage layer over the
tunnel barrier layer, wherein the carbon doped reference layer, the
tunnel barrier layer, and the carbon doped storage layer form a
magnetic tunnel junction (MTJ) element; and a top electrode over
the MTJ element.
13. The STT MRAM structure of claim 12 wherein the carbon doped
reference layer and the carbon doped storage layer are carbon doped
cobalt iron (CoFeC) layers.
14. The STT MRAM structure of claim 12 wherein the tunnel barrier
layer is a magnesium oxide (MgO) tunnel barrier layer.
15. The STT MRAM structure of claim 12 wherein the tunnel barrier
layer is a first tunnel barrier layer, and wherein the STT MRAM
structure further comprises a second tunnel barrier layer between
the carbon doped storage layer and the top electrode.
16. The STT MRAM structure of claim 12 further comprising a hard
layer between the bottom electrode and the carbon doped reference
layer.
17. The STT MRAM structure of claim 16 further comprising a
non-magnetic underlayer between the hard layer and the carbon doped
reference layer.
18. (canceled)
19. (canceled)
20. (canceled)
21. A magnetic tunnel junction (MTJ) structure comprising: a
ferromagnetic reference layer excluding cobalt iron boron (CoFeB)
and including cobalt iron carbon (CoFeC); a ferromagnetic storage
layer excluding cobalt iron boron (CoFeB) and including cobalt iron
carbon (CoFeC); and a tunnel barrier layer between the reference
layer and the storage layer.
22. The MTJ structure of claim 21 wherein the tunnel barrier layer
is a magnesium oxide (MgO) tunnel barrier layer.
23. The MTJ structure of claim 21 wherein the reference layer
directly contacts the tunnel barrier layer, and wherein the storage
layer directly contacts the tunnel barrier layer.
24. The MTJ structure of claim 21 wherein the storage layer
includes a first storage sublayer consisting of cobalt iron carbon
(CoFeC), a second storage sublayer consisting of cobalt iron carbon
(CoFeC), and a non-magnetic insertion layer between the first
storage sublayer and the second storage sublayer.
25. The MTJ structure of claim 21 wherein the storage layer
includes a first storage sublayer consisting of cobalt iron carbon
(CoFeC), a second storage sublayer consisting of cobalt iron carbon
(CoFeC), and a non-magnetic insertion layer disposed between the
first storage sublayer and the second storage sublayer and
consisting of tantalum (Ta), platinum (Pt), molybdenum (Mo),
tungsten (W), chromium (Cr), or palladium (Pd).
Description
TECHNICAL FIELD
[0001] The technical field generally relates to integrated
circuits, and more particularly relates to integrated circuits with
magnetic tunnel junction (MTJ) structures, such as spin transfer
torque magnetic random access memory (STT-MRAM) structures.
BACKGROUND
[0002] A magnetic memory cell or device stores information by
changing electrical resistance of a magnetic tunnel junction (MTJ)
element. The MTJ element typically includes a thin insulating
tunnel barrier layer sandwiched between a magnetically fixed layer
and a magnetically free layer, forming a magnetic tunnel junction.
Magnetic orientations of the fixed and free layers may be in a
vertical direction, forming a perpendicular MTJ (or pMTJ) element.
The pMTJ element could be either in a bottom pinned pMTJ element or
a top pinned pMTJ element. The bottom pinned pMTJ element is formed
by having the magnetically fixed layer disposed below the
magnetically free layer while the top pinned pMTJ element is formed
by having the fixed layer disposed above the free layer.
[0003] Spin transfer torque (STT) or spin transfer switching, uses
spin-aligned ("polarized") electrons to directly torque the MTJ
layers. Specifically, when electrons flowing into a layer have to
change spin direction, a torque is developed and is transferred to
the nearby layer.
[0004] In order to obtain strong perpendicular magnetic anisotropy
(PMA), conventional methods have used boron doped cobalt iron
(CoFeB) material for the fixed and free layers and a thin oxide
tunnel barrier layer. Typically, the boron doped cobalt iron
material is annealed at a low temperature to induce strong
perpendicular magnetic anisotropy. However, boron may diffuse from
the boron doped cobalt iron material and form boron oxide,
particularly during post-anneal processing. This may decrease the
tunneling magnetoresistance (TMR) ratio and reduce perpendicular
magnetic anisotropy, which is reliant on iron-oxygen bonding. Thus,
conventional techniques undesirably lead to reduced thermal budget
and reduced thermal endurance of the pMTJ stack.
[0005] In view of the foregoing, it is desirable to provide MTJ
structures, and memory structures including MTJ elements, with
improved perpendicular magnetic anisotropy (PMA), enhanced thermal
endurance and thermal budget, as well as higher tunneling
magnetoresistance (TMR) signal. Furthermore, it is also desirable
to provide a method for fabricating such memory structures that is
cost effective and compatible with logic processing. Also, it is
desirable to provide integrated circuits and methods for
fabricating integrated circuits including such structures.
Furthermore, other desirable features and characteristics will
become apparent from the subsequent detailed description and the
appended claims, taken in conjunction with the accompanying
drawings and this background.
BRIEF SUMMARY
[0006] Magnetic tunnel junction (MTJ) structures, spin transfer
torque magnetic random access memory (STT MRAM) structures, and
methods for fabricating integrated circuits including such
structures are provided. In an exemplary embodiment, an MTJ
structure includes a cobalt iron carbon (CoFeC) fixed reference
layer. Further, the MTJ structure includes a cobalt iron carbon
(CoFeC) free storage layer. Also, the MTJ structure includes a
tunnel barrier layer between the fixed reference layer and the free
storage layer.
[0007] In another exemplary embodiment, a spin transfer torque
magnetic random access memory (STT MRAM) structure is provided. The
STT MRAM structure includes a bottom electrode and a carbon doped
fixed reference layer over the bottom electrode. Further, the STT
MRAM structure includes a tunnel barrier layer over the fixed
reference layer and a carbon doped free storage layer over the
tunnel barrier layer. The carbon doped fixed reference layer, the
tunnel barrier layer, and the carbon doped free storage layer form
a magnetic tunnel junction (MTJ) element. The STT MRAM structure
also includes a top electrode over the MTJ element.
[0008] In yet another exemplary embodiment, a method for
fabricating an integrated circuit is provided. The method includes
forming a bottom electrode and forming a first ferromagnetic layer
over the bottom electrode. The first ferromagnetic layer includes
carbon doped cobalt iron (CoFeC). The method also includes forming
a tunnel barrier layer over the first ferromagnetic layer. The
tunnel barrier layer includes magnesium oxide (MgO). Further, the
method includes forming a second ferromagnetic layer over the
tunnel barrier layer. The second ferromagnetic layer includes
carbon doped cobalt iron (CoFeC). The method also includes forming
a top electrode over the second ferromagnetic layer.
[0009] This summary is provided to introduce a selection of
concepts in a simplified form that are further described below in
the detailed description. This summary is not intended to identify
key features or essential features of the claimed subject matter,
nor is it intended to be used as an aid in determining the scope of
the claimed subject matter.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The various embodiments will hereinafter be described in
conjunction with the following drawing figures, wherein like
numerals denote like elements, and wherein:
[0011] FIG. 1 illustrates simplified diagrams of parallel state and
anti-parallel state of a bottom fixed perpendicular MTJ element of
a magnetic memory cell.
[0012] FIG. 2 is a schematic diagram of an embodiment of a magnetic
memory cell.
[0013] FIG. 3 illustrates shows an exemplary array of magnetic
memory cells.
[0014] FIG. 4 is a cross-sectional view of an exemplary embodiment
of a memory cell.
[0015] FIGS. 5 and 6 are cross-sectional views of exemplary
embodiments of a storage unit of magnetic memory cell.
[0016] FIGS. 7 and 8 are cross-sectional views of exemplary
embodiments of the MTJ structures of FIGS. 5 and 6.
[0017] FIGS. 9-20 are cross-sectional views illustrating a process
for forming a memory cell in accordance with an embodiment
herein.
DETAILED DESCRIPTION
[0018] The following detailed description is merely exemplary in
nature and is not intended to limit the magnetic tunnel junction
(MTJ) structures, spin transfer torque magnetic random access
memory (STT MRAM) structures, integrated circuits including such
structures, or methods for fabricating such integrated circuits.
Furthermore, there is no intention to be bound by any expressed or
implied theory presented in the preceding technical field,
background or brief summary, or in the following detailed
description.
[0019] For the sake of brevity, conventional techniques related to
conventional device fabrication may not be described in detail
herein. Moreover, the various tasks and processes described herein
may be incorporated into a more comprehensive procedure or process
having additional functionality not described in detail herein. In
particular, various techniques in semiconductor fabrication
processes are well-known and so, in the interest of brevity, many
conventional techniques will only be mentioned briefly herein or
will be omitted entirely without providing the well-known process
details. Further, it is noted that integrated circuits include a
varying number of components and that single components shown in
the illustrations may be representative of multiple components.
[0020] The drawings are semi-diagrammatic and not to scale and,
particularly, some of the dimensions are for the clarity of
presentation and are shown exaggerated in the drawings. Similarly,
although the views in the drawings for ease of description
generally show similar orientations, this depiction in the drawings
is arbitrary. Generally, the integrated circuit can be operated in
any orientation. As used herein, it will be understood that when a
first element or layer is referred to as being "over" or "under" a
second element or layer, the first element or layer may be directly
on the second element or layer, or intervening elements or layers
may be present. When a first element or layer is referred to as
being "on" a second element or layer, the first element or layer is
directly on and in contact with the second element or layer.
Further, spatially relative terms, such as "upper", "over",
"lower", "under" and the like, may be used herein for ease of
description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. It
will be understood that the spatially relative terms are intended
to encompass different orientations of the device in use or
operation in addition to the orientation depicted in the figures.
For example, if the device in the figures is turned over, elements
described as being "under" other elements or features would then be
oriented "above" the other elements or features. Thus, the
exemplary term "under" can encompass either an orientation of above
or below. The device may be otherwise oriented (rotated 90 degrees
or at other orientations) and the spatially relative descriptors
used herein may likewise be interpreted accordingly. As used
herein, a "material layer" is a layer that includes at least 60 wt.
% of the identified material. For example, a magnesium oxide layer
is a layer that is at least 60 wt. % magnesium oxide. Likewise, a
layer that is a "material" includes at least 60 wt. % of the
identified material. For example, a layer that is magnesium oxide
is a layer that is at least 60 wt. % magnesium oxide. In certain
embodiments, a "material layer" is a layer that includes at least
90 wt. % of the identified material and layer that is a "material"
includes at least 90 wt. % of the identified material.
[0021] Embodiments of the present disclosure generally relate to
magnetic tunnel junction (MTJ) structures used in magnetoresistive
memory cells such as spin transfer torque magnetoresistive random
access memory (STT-MRAM) devices. An exemplary MTJ structure
includes a fixed reference layer, i.e., magnetically fixed, and a
free storage layer, i.e., magnetically free, that are formed from
carbon doped cobalt iron (CoFeC) alloys. Further, the exemplary MTJ
structures include a magnesium oxide (MgO) tunnel barrier layer
between the CoFeC layers. Other suitable types of memory cells may
also be useful and may be incorporated into standalone memory
devices including, but not limited to, USB Enterprise SSD or other
types of portable storage units, or integrated circuits (ICs), such
as microcontrollers or system on chips (SoCs). The devices or
integrated circuits may be incorporated into or used with, for
example, consumer electronic products, internet of things (IoT), or
relate to other types of devices.
[0022] The crystal structures of CoFeC and MgO provide coherent
tunneling and higher tunneling magnetoresistance (TMR). Carbon has
a smaller atomic number than boron, which is used in conventional
ferromagnetic layers. Thus, with the use of carbon rather than
boron, there is less spin orbital interaction. In other words,
carbon provides for less spin flipping of transport electrons.
Further, the carbon doped cobalt iron layer is naturally amorphous,
i.e., iron-cobalt alloys can form an amorphous state, which can
promote the formation of the MgO tunnel barrier layer with the
desired crystallinity during annealing.
[0023] Also, carbon is a relatively light element and is relatively
easy to diffuse away from CoFe. In comparison with boron oxide,
carbon-oxide formed at the CoFe and MgO interface is volatile.
Thus, there is less C--O bonding at the interface between the CoFeC
layers and the MgO tunnel barrier layer, preventing degradation of
the crystalline structure of MgO and CoFe. Because embodiments
herein may avoid use of boron in the MTJ structure, a tantalum
underlayer, typically needed to absorb boron that may diffuse from
layers within the MTJ structure, may not be needed and a new
nonmagnetic (NM) underlayer that is less reactive to iron may be
used and may improve the magnetic properties of the MTJ structure.
For example, tantalum has a large reaction potential with iron,
causing diffusion of iron into tantalum. As described herein, the
layer that is less reactive with iron exhibits no diffusion of iron
into the layer during processing.
[0024] FIG. 1 shows a simplified cross-sectional view of an
embodiment of a bottom pinned perpendicular MTJ (pMTJ) unit 110 of
a magnetic memory cell in a programmed state 111 and in a
programmed state 112. The MTJ unit 110 includes a pMTJ element or
stack 120 disposed between a bottom electrode 131 and a top
electrode 132. The bottom electrode 131 is proximate to the
substrate (not shown) on which the memory cell is formed while the
top electrode 132 is distal from the substrate.
[0025] The exemplary pMTJ stack 120 includes a magnetically fixed
(pinned) layer or polarizer layer 126, a tunnel barrier layer 127,
and a magnetically free layer or storage layer 128. In the
illustrated embodiment, the magnetically fixed layer 126 is
disposed below the magnetically free layer 128, forming a bottom
pinned pMTJ stack 120. The magnetic orientation of fixed layer 126
is fixed in a first perpendicular direction. The term perpendicular
direction refers to the direction that is perpendicular to the
surface of a substrate or perpendicular to the plane of the layers
of the pMTJ stack 120. As shown, the first perpendicular direction
is in an upward direction away from the substrate. Providing the
first perpendicular direction in a downward direction towards the
substrate may also be useful in alternative embodiments. The
magnetic orientation of free layer 128 may be programmed to be in a
first or same direction as fixed layer 126 or in a second or
opposite direction as fixed layer 126.
[0026] For example, as shown by programmed state 111, the magnetic
direction of free layer 128 is programmed to be in the second or
anti-parallel direction to fixed layer 126. The corresponding MTJ
electrical resistance between free layer 128 and fixed layer 126 in
anti-parallel arrangement is denoted as R.sub.AP. In programmed
state 112, the magnetization of free layer 128 is programmed to be
in the first or parallel direction to fixed layer 126. The
corresponding MTJ electrical resistance between free layer 128 and
fixed layer 126 in parallel arrangement is denoted as R. The
resistance R.sub.AP is higher than the resistance R.
[0027] FIG. 2 is a schematic diagram of an embodiment of an
exemplary memory structure 200. The memory structure 200 is a
non-volatile memory cell, for example, a magnetoresistive memory
cell, such as a spin transfer torque-magnetoresistive random access
memory (STT-MRAM) cell. Other suitable types of memory structures
may also be useful. As shown, the memory structure 200 includes a
magnetic storage unit 210 and a cell selector unit 240. The
magnetic storage unit 210 is coupled to the cell selector unit 240
at a first cell node 239 of the memory cell 200. The exemplary
magnetic storage unit 210 includes a pMTJ element 220. The pMTJ
element 220 may be similar to that described in FIG. 1. Other
suitable types of MTJ elements may also be useful.
[0028] The exemplary pMTJ element 220 includes a first electrode
231 and a second electrode 232. The first electrode 231, for
example, may be a bottom electrode while the second electrode 232
may be a top electrode. Other configurations of electrodes may also
be useful. In one embodiment, the top electrode 232 is electrically
connected to a bit line (BL) and the bottom electrode 231 is
electrically connected to the first cell node 239.
[0029] In FIG. 2, the exemplary cell selector unit 240 is a select
transistor for selecting the memory cell 200. In one embodiment,
the cell selector unit 240 is a metal oxide semiconductor (MOS)
transistor, such as an n-type MOS transistor, and includes a gate
or control terminal 244, a first source/drain (S/D) terminal 245,
and a second source/drain (S/D) terminal 246. The first S/D
terminal 245 may be referred to as the drain and the second S/D
terminal 246 may be referred to as the source. Exemplary S/D
terminals 245 and 246 are heavily doped with first polarity type
dopants, defining the first type transistor. For example, in the
case of an n-type transistor, the S/D terminals 245 and 246 are
n-type heavily doped regions and may have a dopant concentration of
about 1E20/cm.sup.3 or greater. Other types of transistors or
selectors, for example finFET devices may also be useful, provided
such devices are CMOS compatible.
[0030] In an embodiment, the first S/D terminal 245 of the cell
selector unit 240 and first electrode 231 of the magnetic storage
unit 210 are commonly coupled at the first cell node 239, i.e., the
drain terminal 245 of the cell selector unit 240 is coupled to the
bottom electrode 231 of the magnetic storage unit 210. In such
embodiment, the second or source terminal 246 of the cell selector
unit 240 is coupled to a source line (SL) while the gate terminal
244 is coupled to a wordline WL.
[0031] FIG. 3 shows a schematic diagram of an embodiment of a
memory array with localized source 300 that includes a plurality of
interconnected memory cells 200. The memory cells 200 may be
similar to those described in FIG. 2. For example, the memory cells
200 may be MRAM cells, such as STT-MRAM cells. Common elements may
not be described or described in detail. Other suitable types of
memory cells may also be useful.
[0032] As shown, the memory array 300 includes four memory cells
200 arranged in a 2x2 array, i.e., the memory array 300 is arranged
to form two rows and two columns of memory cells 200. Memory cells
200 of a row are interconnected by a wordline (WL1 or WL2) while
memory cells 200 of a column are interconnected by a bitline (BL1
or BL2). The second S/D or source terminal of each memory cell 200
(as identified in FIG. 2) is coupled to a common source line (SL1
or SL2) SL. As shown, the source lines extend in the row or
wordline direction. Other suitable cell configurations may also be
useful, such as an array with dedicated BL/SL per column with SL in
parallel to BL direction. Although the memory array 300 is
illustrated as a 2x2 array, it is understood that arrays of other
sizes may also be useful.
[0033] FIG. 4 shows a cross-sectional view of an exemplary
embodiment of a memory cell 400 of a device. The cross-sectional
view is taken along a second or bitline direction of the device.
The memory cell 400 may be a NVM cell, for example a
magnetoresistive NVM cell, such as a STT-MRAM cell. The memory cell
400 may be similar to that described in FIG. 2. Common elements may
not be described or described in detail.
[0034] As shown, the memory cell 400 is disposed on a substrate
405. An exemplary substrate 405 is a semiconductor substrate, such
as a bulk silicon substrate. For example, the substrate 405 may be
a lightly doped p-type substrate. Providing an intrinsic or other
types of doped substrates, such as silicon-germanium (SiGe),
germanium (Ge), gallium-arsenic (GaAs) or any other suitable
semiconductor materials, may also be useful. In some embodiments,
the substrate may be a crystalline-on-insulator (COI) substrate. A
COI substrate includes a surface crystalline layer separated from a
crystalline bulk by an insulator layer. The insulator layer, for
example, may be formed of a dielectric insulating material. The
insulator layer, for example, is formed from silicon oxide, which
provides a buried oxide (BOX) layer. Other types of dielectric
insulating materials may also be useful. The COI substrate, for
example, is a fully depleted silicon-on-insulator (FDSOI)
substrate. For example, the thin surface and bulk crystalline
layers are single crystalline silicon. Other types of COI
substrates may also be useful. It is understood that the surface
and bulk layers need not be formed of the same material.
[0035] In an exemplary embodiment of FIG. 4, the memory cell 400 is
disposed in a cell region of the substrate 405 that may be part of
an array region. An exemplary array region may include a plurality
of cell regions. The substrate 405 may include other types of
device regions (not shown), such as high voltage (HV) device
regions as well as logic regions, including low voltage (LV) and
intermediate voltage (IV) device regions. Other types of regions
may also be provided.
[0036] As shown, isolation regions 480 are formed in substrate 405.
Exemplary isolation regions 480 serve to isolate different device
regions in substrate 405. As shown, a cell region for a memory cell
400 is isolated by isolation regions 480. Isolation regions 480 may
be provided to isolate columns of memory cells 400. Isolation
regions 480 may be shallow trench isolation (STI) regions. Other
configurations of isolation regions may also be useful.
[0037] In FIG. 4, the memory cell 400 includes a cell selector unit
440 and a storage unit 410. The cell selector unit 440 is formed in
the cell region. The cell selector unit 440 includes a select
transistor for selecting the memory cell 400. In one embodiment,
the select transistor is a metal oxide semiconductor (MOS)
transistor. The transistor, as shown, includes first and second
source/drain (S/D) regions 445 and 446 formed in the substrate 405
and a gate 444 disposed on the substrate 405 between the S/D
regions 445 and 446. The first S/D region 445 may be referred to as
a drain region and the second S/D region 446 may be referred to as
a source region. An exemplary gate 444 may be a gate conductor
extending along a first or wordline direction. Such a gate
conductor may form a common gate for a row of memory cells 400.
[0038] As shown, a dielectric layer 490 lies over the transistors
and other components on the substrate 405. The dielectric layer may
be silicon oxide. Dielectric layer 490 may serve as a premetal
dielectric layer or first contact layer. Dielectric layer 490 may
be referred to as CA level.
[0039] Interconnects connect various components of the integrated
circuit to perform desired functions. Exemplary interconnects
include contacts 493 and conductive or metal lines 495 that are
formed through the ILD layer 490 to be coupled to a metal level
494. The conductors and contacts may be formed of a metal, such as
copper, copper alloy, aluminum, tungsten or a combination thereof.
Other suitable types of metal, alloys or conductive materials may
also be useful. In some cases, the conductors and contacts may be
formed of the same material. In some cases, the conductors and
contacts may have different materials.
[0040] In FIG. 4, a dielectric layer covers the CA level dielectric
layer and may serve as a first metal level M1 of the first ILD
layer 490. The upper dielectric layer, for example, is a silicon
oxide layer. Other types of dielectric layers, such as low k (LK),
ultra lowk (ULK) or a combination of dielectric materials, may also
be useful. Conductive lines 495 are formed in the M1 level
dielectric layer. The first metal level M1 and CA may be referred
to as within lower ILD level 490. Upper ILD layers or levels may
include ILD level 2 to ILD level x. For example, in the case where
x=5 (5 levels), the upper levels include ILD levels from 2 to 5,
which include via levels V1 to V4 and metal levels M2 to M5. The
number of ILD layers may depend on, for example, design
requirements or the logic process involved. The upper ILD layers
may be formed of silicon oxide.
[0041] The uppermost ILD level (e.g., M5) may have different design
rules, such as critical dimension (CD), than the lower ILD levels.
For example, Mx may have a larger CD than metal levels M1 to Mx-1
below. For example, the uppermost metal level may have a CD that is
two times or multiple integer times the CD of the metal levels
below. Other configurations of the ILD levels may also be
useful.
[0042] A dielectric liner (not shown) may be disposed between ILD
levels and on the substrate 405 and may serve as an etch stop
layer. The dielectric liner may be formed of a low k dielectric
material, such as nBLOK. Other types of dielectric materials, such
as silicon nitride (SiN), for the dielectric liner may also be
useful.
[0043] As shown, S/D contacts 493 are disposed in the CA level. The
S/D contacts 493 are coupled to the first and second S/D regions
445 and 446 of the select transistor. Other S/D contacts to other
S/D regions of transistors may also be provided. The CA level may
include a gate contact (not shown) coupled to the gate 444 of the
select transistor. The gate contact may be disposed in another
cross-section of the device. The contacts may be tungsten contacts.
Other types of contacts may also be useful. Other S/D and gate
contacts for other transistors may also be provided.
[0044] As described, conductive lines 495 are provided in Ml.
Conductive lines 495 are coupled to the S/D contacts 493. In one
embodiment, a source line is coupled to the second S/D region 446
of the select transistor. The first S/D contact may be coupled to
contact pad or island in Ml. The contact pads provide connections
to upper ILD levels. The conductive lines or contact pads may be
formed of copper or copper alloy. Other types of conductive
material may also be useful.
[0045] Exemplary upper ILD levels may include contacts in the via
level and contact pads/metal lines in the metal level. The contacts
and contact pads provide connection from M5 to the first S/D region
445 of the select transistor. A pad level (not shown) may be
disposed over the uppermost ILD level for providing external
electrical interconnections to the components. A dielectric liner
may be disposed between the uppermost metal level and pad level.
The dielectric liner, for example, serves as an etch stop layer
during via etch process and may also serve as a diffusion barrier
layer for, for example, copper (Cu) layer.
[0046] As shown in FIG. 4, the storage unit 410 of the memory cell
400 is disposed in a storage dielectric layer 450. The storage
dielectric layer 450 may be a via level of an ILD level. As shown,
the storage dielectric layer 450 is a dedicated V1 of M2 with a
dedicated V1 mask. Providing the storage dielectric layer 450 at
other via levels may also be useful. In other embodiments, the
storage dielectric layer 450 is a common CMOS dielectric layer and
part of an interconnect level with common CMOS V1. Other
configurations of storage dielectric layer 450 may also be useful.
The storage unit 410 includes a storage element disposed between
bottom and top electrodes, forming a pMTJ element. The storage unit
410, in one embodiment, is a bottom pinned pMTJ storage element,
such as that described in FIG. 1 and FIGS. 5-6, as will be
described later. Common elements may not be described or described
in detail.
[0047] In one embodiment, the bottom electrode of the storage unit
410 is coupled to a drain of the select transistor. For example,
the bottom electrode is coupled to a contact pad in the M1 level
and a via contact in the CA level. Other configurations of coupling
the bottom electrode may also be useful. The top electrode is
coupled to a bitline BL. For example, the top electrode is coupled
to the bitline disposed in M2 with tight CD. In other
configurations, the bitline may be disposed in Mx+1, where x+1 with
wider CD of M1/M2 (typically 233 ) and taller Vx that serve as the
storage layer. The bitline extends along a bitline direction. The
source of the select transistor is coupled to the source line. The
source line, for example, may be in the first or wordline direction
for a localized source array. Providing a source line in the second
or bitline direction may also be useful. For example, a via contact
in CA is provided to couple the source region to source line SL in
M1 for tighter metal pitch design. Providing source line SL in
other levels may also be useful.
[0048] The gate of cell selector is coupled to a wordline WL. The
wordline, for example, extends along a wordline direction. The
bitline and wordline directions are perpendicular to each other. As
shown, wordline WL is disposed in M3 for tighter metal pitch
design. Wordline WL may be coupled to the gate by contact pads in
M2 and M1 and via contacts in V2 and V1 (not shown). Other
configurations of coupling the wordline WL to the gate may also be
useful. For example, the wordline WL may be disposed in other metal
levels.
[0049] In general, lines that are parallel in a first direction may
be formed in the same metal level while lines that are in a second
direction perpendicular to the first may be formed in a different
metal level. For example, WLs and BLs are formed in different metal
levels and are perpendicular to one another.
[0050] As described, the cell dielectric 450 is disposed in V1 in
between M1 and M2. It is understood that providing other
configurations of cell dielectric layers may be also useful.
[0051] FIG. 5 shows a cross-sectional view of an embodiment of a
magnetic storage unit 510 for use as the storage unit 410 of the
memory cell 400 of FIG. 4. In one embodiment, the magnetic storage
unit 510 includes an MTJ structure 520 as a bottom pinned pMTJ
stack 520 disposed between a bottom electrode 531 and top electrode
532. The exemplary pMTJ stack 520 includes a fixed layer 526, a
free layer 528, and a tunnel barrier layer 527 separating the fixed
layer 526 from the free layer 528. As shown, the fixed layer 526 is
disposed below the free layer 528, forming the bottom pinned pMTJ
stack 520. A capping layer 580 is disposed over the free layer 528.
The fixed layer 526, tunnel barrier layer 527 and the free layer
528 form the pMTJ stack 520.
[0052] The bottom and top electrodes 531 and 532 may be formed of a
conductive material. In one embodiment, the bottom and top
electrodes 531 and 532 may be formed of tantalum (Ta), titanium
(Ti), tantalum nitride (TaN), titanium nitride (TiN), copper (Cu),
tungsten (W) or a combination of such electrode materials.
Furthermore, it is understood that the bottom and top electrodes
531 and 532 need not be of the same material. A thickness of the
bottom and top electrodes 531 and 532 may be from about 1 to about
50 nm.
[0053] The various layers of the pMTJ stack 520 will be described
upward from the bottom electrode 531. As shown, fixed layer 526 is
located on the bottom electrode 531. An exemplary fixed layer 526
is a fixed layer stack that includes a base layer 560, a hard layer
570, and a reference layer 568. In the illustrated embodiment, a
spacer layer 578 is provided between the hard layer 570 and the
reference layer 568. However, spacer layer 578 may be optional such
that the reference layer 568 is located directly on the hard layer
570.
[0054] The base layer 560 promotes orientation of the hard layer
570 in a desired crystal structure or orientation to increase
perpendicular magnetic anisotropy (PMA). In an embodiment, the base
layer 560 promotes FCC crystal structure of the hard layer 570
along (111) orientation. In an embodiment, the base layer 560
promotes face-centered cubic (FCC) crystal structure of the hard
layer 570 along the (111) orientation. Other embodiments may
promote body-centered cubic (BCC) crystal structure of the hard
layer 570 along the (110) orientation or hexagonal close packed
(HCP) crystal structure of the hard layer 570 along the (002)
orientation.
[0055] In one embodiment, the base layer 560 includes an optional
wetting layer 562 and a seed layer 564. If used, the wetting layer
562 promotes adhesion between the bottom electrode 531 and the seed
layer 564. An exemplary wetting layer 562 has a BCC (110), FCC
(111) or HCP (002) orientation. Further, an exemplary wetting layer
562 enhances a BCC (110), FCC (111) or HCP (002) structure of the
seed layer 564. In one embodiment, the wetting layer 562 is a
magnesium (Mg) layer, a hafnium (Hf) layer, a tantalum (Ta) layer,
a titanium (Ti) layer, a platinum manganese (PtMn) layer, a
ruthenium (Ru) layer, a platinum (Pt) layer or a combination
thereof. An exemplary wetting layer has a thickness of from more
than about 0 to about 50 A, such as from about 1 to about 20 A. The
thickness of the wetting layer 562 may be about 10 A. Other
thicknesses may also be useful. The wetting layer 562 may be formed
by PVD.
[0056] If used, the wetting layer 562 may include multiple layers.
The multiple layers include magnesium and other material layers
that together promote the desired crystal structure along the
desired orientation. For example, the multiple layers may include
layers having an FCC structure along (111) orientation, layers
having a BCC structure along (110) orientation and layers having a
HCP structure along the (002) orientation. Exemplary layers having
an FCC (111) structure include magnesium (Mg), exemplary layers
having a BCC (110) include molybdenum (Mo), chromium (Cr), tungsten
(W), niobium (Nb) and vanadium (V) layers, and exemplary layers
having a HCP (002) wetting layer 562 may include hafnium (Hf) and
ruthenium (Ru) layers. Other suitable types of FCC (111), BCC (110)
and HCP (002) layers may also be used as the wetting layer 562 as
long as these layers promote FCC crystal structure of the hard
layer 570 along (111) orientation.
[0057] In certain embodiments, the wetting layer 562 has a smooth
surface with a roughness of less than about 4 A root mean squared
(RMS). For example, the wetting layer 562 may have a roughness of
less than about 1 A RMS. The smoothness of the wetting layer 562
enhances the smoothness of the seed layer 564 formed thereon.
[0058] In FIG. 5, the seed layer 564 is illustrated as being formed
on the wetting layer 562. As noted above, the wetting layer 562 may
not be present in certain embodiments such that the seed layer 564
is formed on the bottom electrode 531. An exemplary seed layer 564
is nickel chromium (NiCr), chromium (Cr), chromium ruthenium
(CrRu), or nickel chromium ruthenium (NiCrRu) material or material
based. In an embodiment, the seed layer 564 includes multiple
bilayers, forming a multi-bilayered seed stack or superlattice
formation.
[0059] Further, an exemplary seed layer 564 has a thickness of less
than about 100 A. For example, the seed layer 564 may have a
thickness of from about 5 A to about 100 A, such as from about 5 A
to about 60 A, such as about 50 A. A thinner seed layer 564 may
reduce total interface or surface roughness of the fixed layer 526.
In certain embodiments, seed layer 564 has a smooth surface with a
roughness of less than about 4 A root mean squared (RMS). For
example, the seed layer 564 may have a roughness of less than about
1 A RMS. The reduced interface roughness may improve thermal
endurance. The structure may withstand processing at about
400.degree. C. for at least 30 minutes. This enables compatibility
with complementary metal oxide semiconductor (CMOS) processes. The
exemplary seed layer 564 has a desired texture to produce strong
PMA. An exemplary seed layer 564 has a BCC (110), FCC (111) or HCP
(002) orientation. In one embodiment, the texture of a
multi-bilayered seed layer 564 has a FCC structure along the (111)
orientation.
[0060] In FIG. 5, hard layer 570 is formed over the base layer 560.
For example, the hard layer 570 is formed on the seed layer 564 of
the base layer 560. The hard layer 570, in one embodiment, is a
composite hard layer 570 with multiple layers to form a hard layer
stack. In one embodiment, the hard layer 570 includes first and
second antiparallel (AP) layers 572 and 576 separated by a coupling
or spacer layer 574, such as a synthetic antiferromagnetic (SAF)
layer.
[0061] In one embodiment, the antiparallel layers 572 and 576 are
configured with a FCC structure along the (111) orientation.
Formation of layers in the (111) orientation, as discussed, is
facilitated by the base layer 560. The first and second
antiparallel layers 572 and 576 have magnetization directions that
are antiparallel. For example, antiparallel layer 572 has a first
perpendicular magnetization direction that is the opposite of the
second perpendicular magnetization direction of antiparallel layer
576. For example, the perpendicular magnetization of antiparallel
layer 572 is down while the perpendicular magnetization direction
of antiparallel layer 576 is up.
[0062] Each or either antiparallel layer 572 or 576 may include
multiple antiparallel bilayers, forming an antiparallel bilayered
stack or layer. An exemplary bilayer of an antiparallel layer 572
or 576 may include cobalt/platinum (Co/Pt) or cobalt/nickel (Co/Ni)
layers. A bilayer of an antiparallel layer 572 or 576 may be
cobalt/nickel (Co/Ni). Other types of antiparallel layers 572 or
576, such as cobalt-iron/nickel (CoFe/Ni), cobalt-iron-boron/nickel
(CoFeB/Ni), cobalt-iron/platinum (CoFe/Pt)n or
cobalt-iron-boron/platinum (CoFeB/Pt)m, may also be useful. Layers
in an antiparallel layer 572 or 576 may be provided in any
sequence. In one embodiment, the nickel layer is the uppermost
layer of the antiparallel layer 572 or 576. For example, depending
on the configuration, the uppermost layer may be a bilayer with
nickel as the top layer, or may be a single layer of nickel. In an
embodiment, antiparallel layer 572 or 576 can be a single magnetic
layer or a composite layer of cobalt/platinum/cobalt (Co/Pt/Co),
cobalt/nickel/cobalt (Co/Ni/Co), cobalt-iron/platinum/cobalt-iron
(CoFe/Pt/CoFe), cobalt-iron/nickel/cobalt-iron (CoFe/Ni/CoFe),
cobalt-iron-boron/platinum/cobalt-iron-boron (CoFeB/Pt/CoFeB), or
cobalt-iron-boron/nickel/cobalt-iron-boron (CoFeB/Ni/CoFeB).
[0063] In an embodiment, the coupling or spacer layer 574 serves to
promote Ruderman-Kittle-Kasuya-Yosida (RKKY) coupling. An exemplary
coupling layer 574 is a ruthenium (Ru) layer. Providing other types
of coupling layers may also be useful. The various layers of the
hard layer 570 may be formed by PVD.
[0064] In the embodiment of FIG. 5, a spacer layer 578 is provided
between antiparallel layer 576 and reference layer 568. An
exemplary spacer layer 578 serves as a texture breaking layer. The
spacer layer 578 facilitates a different texture for the reference
layer 568. For example, the spacer layer 578 enables the reference
layer 568 to have a different texture from that of the hard layer
570. For example, the spacer layer 578 enables the reference layer
568 to be amorphous when deposited. In one embodiment, the spacer
layer 578 may be a tantalum (Ta) layer or a platinum (Pt) layer.
The thickness of the spacer layer 578 should be thin to maintain
magnetic coupling between antiparallel layer 576 and reference
layer 568. The spacer layer 578, for example, may be from about 1
to about 6 A thick.
[0065] The reference layer 568, in one embodiment, is a magnetic
layer. An exemplary reference layer 568 is a carbon doped
cobalt-iron (CoFeC) layer. The reference layer 568 may be a single
layer or a composite layer. Other suitable types of magnetic
reference layers 568 may also be useful. In one embodiment, the
reference layer 568 is deposited by, for example, PVD. In an
exemplary embodiment, reference layer 568 is deposited as an
amorphous layer. Depositing the reference layer 568 as an amorphous
layer enhances TMR when the amorphous layer is subsequently
recrystallized during an anneal process performed on the MTJ stack.
The reference layer 568 should be sufficiently thick without
sacrificing the perpendicular magnetic anisotropy (PMA). The
thickness of an exemplary reference layer 568 may be from about 5
to about 20 A thick. Forming the reference layer 568 using other
techniques or processes as well as other thicknesses may also be
useful. In an exemplary embodiment, a CoFeC sputter target is
utilized in a physical vapor deposition (PVD) process to form the
CoFeC layer.
[0066] The tunnel barrier layer 527 that is disposed over the hard
layer 570 may be a magnesium oxide (MgO) layer. Other suitable
types of barrier layers 527 may also be useful. The tunnel barrier
layer 527 may be formed by an RF PVD process with a MgO sputter
target, or by a DC PVD process with a Mg sputter target and natural
oxidation on Mg to form MgO . The thickness of the tunnel barrier
layer 527 may be from about 1 to about 20 A. An exemplary tunnel
barrier layer 527 has a thickness of from about 8 to about 12 A.
Other forming techniques or thicknesses for the tunnel barrier
layer 527 may also be useful.
[0067] As shown in FIG. 5, the free or storage layer 528 is
disposed over the tunnel barrier layer 527. The exemplary storage
layer 528 is a magnetic layer. In one embodiment, the storage layer
528 is a carbon doped cobalt-iron (CoFeC) layer. The storage layer
528 may be a single layer or a composite layer. The thickness of
the storage layer 528 may be from about 10 to about 20 A to
maintain PMA. An exemplary composite storage layer 528 may include
a magnetic/non-magnetic/magnetic stack. The magnetic layer may be
cobalt-iron-carbon (CoFeC) while the non-magnetic layer may be
tantalum (Ta), platinum (Pt), molybdenum (Mo), tungsten (W),
chromium (Cr), or palladium (Pd). The non-magnetic layer is thin,
such as from about from about 1 to about 20 A to avoid magnetic
decoupling of the magnetic layer of the composite storage layer
528. The storage layer 528 may be formed by, for example, PVD.
Other techniques for forming the storage layer 528 or thicknesses
may also be useful.
[0068] A capping layer 580 is provided over the storage layer 528.
The capping layer 580, for example, serves to minimize the top
electrode diffusion through the tunnel barrier layer 527 or
magnetic layers. An exemplary capping layer 580 is a ruthenium (Ru)
layer or a tantalum (Ta) layer. Providing a composite capping layer
580 may also be useful. For example, the capping layer 580 may
include ruthenium and tantalum layers. In one embodiment, the
capping layer 580 may include a ruthenium/cobalt-iron/tantalum
(Ru/CoFe/Ta) or a ruthenium/cobalt-iron-boron/tantalum
(Ru/CoFeB/Ta) composite layer. In the case of the composite capping
layer 580, the ruthenium layer may be about 10 A thick, the CoFeB
or CoFe layer may be about 15 A thick, and the Ta layer may be
about 50 A thick. Other configurations of capping layers 580 may
also be useful. The capping layer 580 may be formed by, for
example, PVD.
[0069] FIG. 6 shows a cross-sectional view of another embodiment of
a magnetic storage unit 510 of a magnetic memory cell. In the
embodiment of FIG. 6, the magnetic storage unit 510 again includes
a bottom pinned pMTJ stack as an MTJ structure 520 disposed between
bottom and top electrodes 531 and 532. The pMTJ stack 520 is
similar to that described in FIG. 5 and common elements are not
described in detail.
[0070] In contrast to the magnetic storage unit 510 of FIG. 5, the
magnetic storage unit 510 of FIG. 6 includes a first tunnel barrier
layer 527 and a second tunnel barrier layer 529. This configuration
produces a dual tunnel barrier pMTJ stack 520. In one embodiment,
the free layer 528 is disposed between the tunnel barrier layers
527 and 529. The tunnel barrier layers 527 and 529, for example,
may be magnesium oxide (MgO) layers. Other suitable types of tunnel
barrier layers may also be useful. It is also understood that the
tunnel barrier layers 527 and 529 thickness and/or method of
formation need not be the same. The other layers of the pMTJ stack
520 may be the same or similar to those described above in relation
to FIG. 5.
[0071] In one embodiment, the first tunnel barrier layer 527 has
resistance area (RA) of about 9 Ohms/um.sup.2 while the second
tunnel barrier layer 529 has a RA of about 5 Ohms/um.sup.2. The
second tunnel barrier layer 529 enhances anisotropy of the storage
layer 528, increasing thermal stability. Additionally, the second
tunnel barrier layer 529 reduces the damping effect of the storage
layer 528, reducing switching current.
[0072] FIG. 7 illustrates another embodiment of the MTJ structure
520 of FIGS. 5 and 6. In FIG. 7, the MTJ structure 520 again
includes a reference layer 568, a tunnel barrier layer 527, and a
storage layer 528. In FIG. 7, however, the MTJ structure 520
further includes a non-magnetic insertion layer 591 and a
non-magnetic insertion layer 592. As shown, the non-magnetic
insertion layer 591 is formed below the reference layer 568 and the
non-magnetic insertion layer 592 is formed over the storage layer
528. In certain embodiments, a second tunnel barrier layer 529 may
be located over the non-magnetic insertion layer 592. An exemplary
non-magnetic insertion layer 591 and 592 is a tantalum (Ta) or a
platinum (Pt) layer and is independently a CoFeX layer, wherein X
is selected from aluminum, carbon or boron for high spin
polarization due to PMA of MgO/CoFeX, where PMA comes from the
coupling effect of Fe--O atoms at the interface.
[0073] FIG. 8 illustrates an embodiment of the MTJ structure 520
that includes first and second tunnel barrier layers 527 and 529
and non-magnetic insertion layers 591 and 592 as in FIG. 7. In such
an embodiment, the storage layer 528 is a multilayer, split into
5281/5282 and a non-magnetic layer 593 is inserted between the
storage layers 5281 and 5282. Each of exemplary non-magnetic layers
591, 592 and 593 is a tantalum (Ta) layer or a platinum (Pt) layer.
Further, a capping layer 598 is provided between the tunnel barrier
layer 529 and the top electrode (not shown).
[0074] FIGS. 9-20 show cross-sectional views of an embodiment of a
process 600 for forming a device including a memory cell, such as a
magnetic random access memory (MRAM) cell. An exemplary memory cell
is the same or similar to that described in relation to FIG. 2 and
includes an MTJ stack as described in FIGS. 5-8. Common elements
may not be described or described in detail.
[0075] The cross-sectional views of FIGS. 9-20 are along the bit
line direction. Although the cross-sectional views show one memory
cell, it is understood that the device may include a plurality of
memory cells, such as cells forming a memory array. In one
embodiment, the process of forming the memory cell is highly
compatible with CMOS logic process. For example, the cells can be
formed simultaneously with CMOS logic devices (not shown) on the
same substrate.
[0076] Referring to FIG. 9, a substrate 605 is provided. An
exemplary substrate 605 is a semiconductor substrate, such as
substrate 405 as described above in relation to FIG. 4. Substrate
605 is processed to define a cell region in which a memory cell is
formed. The cell region may be part of an array region that
includes a plurality of cell regions. Substrate 605 may include
other types of device regions, such as logic regions or other types
of regions.
[0077] Isolation regions 680 are formed in substrate 605. In one
embodiment, isolation regions 680 are shallow trench isolation
(STI) regions. Other types of isolation regions may also be useful.
Isolation regions 680 are provided to isolate device regions from
other regions and may also isolate contact regions within a cell
region. Isolation regions 680 may be formed by, for example,
etching trenches in the substrate 605 and filling them with a
dielectric material, such as silicon oxide. A planarization
process, such as chemical mechanical polish (CMP), may be performed
to remove excess dielectric material.
[0078] As shown in FIG. 9, a doped well or device well 608 is
formed in substrate 605. In an exemplary embodiment, well 608 is
formed after isolation regions 680 are formed. In one embodiment,
the well 608 serves as a well for select transistors of a selector
unit. An exemplary well 608 is a second polarity type doped well,
i.e., the opposite polarity type of the transistor of the cell
selector unit. In an embodiment, device well 608 is a p-type well
for a n-type cell select transistor, such as a metal oxide
semiconductor field effect transistor (MOSFET). Device well 608 may
serve as a body of the select transistor.
[0079] In an embodiment, an implant mask may be employed to implant
dopants to form doped well 608. The implant mask, for example, is a
patterned photoresist layer. The implant mask exposes regions of
substrate 605 where the second polarity wells are formed. Device
well 608 may be lightly or intermediately doped with second
polarity type dopants. For example, device well 608 may have a
dopant concentration of about 1E15 to 1E19/cm.sup.3. Other dopant
concentrations may also be useful. An exemplary well 608 may be a
common device well for a memory array.
[0080] The process may include forming other wells for other device
regions. In the case where the wells are different polarity type of
dopant concentration, they may be formed using separate processes,
such as separate mask and implants. For example, first polarity
typed doped wells, wells of different dopant concentrations as well
as other wells may be formed using separate mask and implant
processes.
[0081] As shown in FIG. 10, gate layers are formed on substrate
605. Exemplary gate layers include a gate dielectric layer 642 and
a gate electrode layer 643. An exemplary gate dielectric layer 642
is silicon oxide and may be formed by thermal oxidation. An
exemplary gate electrode layer 642 is polysilicon and may be formed
by chemical vapor deposition (CVD). Other suitable types of gate
layers, including high k dielectric and metal gate electrode
layers, or other suitable techniques for forming gate layers may
also be useful.
[0082] Referring to FIG. 11, gate layers 642 and 643 are patterned
to form a gate 644 of the select transistor of the select unit.
Patterning the gate layers may be achieved using conventional mask
and etch techniques. Patterning the gate layers forms gate 644 of
the select transistor. An exemplary gate 644 is a gate conductor
extending along a first or word line direction and serves as a
common gate for a row of memory cells.
[0083] Referring to FIG. 12, an implant is performed to form first
and second S/D regions 645 and 646 adjacent gate 644. In an
exemplary embodiment, first polarity type dopants are implanted to
form first polarity type S/D regions 645 and 646. In one
embodiment, the implant forms heavily doped first polarity type S/D
regions 645 and 646 in substrate 605 adjacent gate 644. S/D regions
645 and 646, for example, include a dopant concentration of about
5E19 to 1E21/cm.sup.3. Other dopant concentrations may also be
useful. The implant process to form S/D regions 645 and 646 may be
performed together while forming first polarity type S/D regions in
other device regions (not shown) on the same substrate as well as
first polarity type contact regions.
[0084] An extension implant and halo region implant may be
performed to form extension regions (not shown) and halo regions
(not shown) of S/D regions 645 and 646. The extension and halo
implants may be performed prior to forming the S/D regions 645 and
646. After forming the extension regions, sidewall spacers (not
shown) may be formed on sidewalls of the gate 644 followed by
forming the S/D regions 645 and 646.
[0085] Separate implants for second polarity type S/D and extension
regions may be performed. The second polarity type implants form
S/D and extension regions for second polarity type transistors in
other device regions as well as second polarity type contact
regions.
[0086] Referring to FIG. 13, a dielectric layer 690.sub.1 is formed
over the substrate 605, and covers gate 644 and S/D regions 645 and
646 of the transistor. An exemplary dielectric layer 690.sub.1
serves as a dielectric layer of an ILD layer. For example,
dielectric layer 690.sub.1 serves as a PMD or CA level of an ILD
layer. An exemplary dielectric layer 690.sub.1 is silicon oxide,
though other types of dielectric layers may also be useful.
Dielectric layer 690.sub.1 may be formed by CVD. Other techniques
for forming the dielectric layer 690.sub.1 may also be useful. A
planarizing process, such as CMP, may be performed to produce a
planar surface. Other types of planarizing processes may also be
useful.
[0087] In an exemplary embodiment, contacts 693 are formed in the
dielectric layer 690.sub.1 as shown in FIG. 14. Exemplary contacts
693 connect to contact regions, such as S/D regions 645 and 646 and
gate (not shown). Forming contacts 693 may include forming contact
vias in dielectric layer 690.sub.1 to expose the contact regions.
Forming the contact vias may be achieved using mask and etch
techniques. After the vias are formed, a conductive material is
deposited to fill the vias. The conductive material, for example,
may be tungsten (W). Other types of conductive materials may also
be useful. A planarization process, such as CMP, is performed to
remove excess conductive material, leaving contact plugs in the
contact vias.
[0088] In FIG. 15, a dielectric layer 690.sub.2 is formed over the
substrate 605, covering the lower dielectric layer 690.sub.1. An
exemplary dielectric layer 690.sub.2 serves as a metal level of an
ILD layer. In an embodiment, dielectric layer 690.sub.2 serves as
M1 level of the ILD layer. An exemplary dielectric layer 690.sub.2
is silicon oxide, though other types of dielectric layers may also
be useful. Dielectric layer 690.sub.2 may be formed by CVD. Other
techniques for forming the dielectric layer 690.sub.2 may also be
useful. Because the underlying surface is already planar, a
planarizing process may not be needed. However, it is understood
that a planarization process, such as CMP, may be performed if
desired to produce a planar surface.
[0089] In FIG. 16, conductive or metal lines 695 are formed in the
dielectric layer 690.sub.2. Conductive lines 695 may be formed by
damascene technique by etching upper dielectric layer 690.sub.2 to
form trenches and filing the trenches with a conductive layer. For
example, a copper or copper alloy layer may be formed to fill the
openings. The conductive material may be formed by, for example,
plating, such as electro or electroless plating. Other types of
conductive layers or forming techniques may also be useful. In one
embodiment, a source line SL is formed to connect to the source
region 646 of the transistor while other interconnects, such as
interconnect pad 697 formed in M1 is coupled to drain region 645.
The source line may extend along the wordline direction. Providing
the source line in the bitline direction may also be useful. The
interconnect pad may serve as a storage pad. Other conductive lines
and pads may also be formed.
[0090] As shown in FIG. 17, the process continues to form a storage
unit of the memory cell. In one embodiment, the process forms
various layers 612 of a storage unit with a pMTJ stack. The various
layers 612 are formed on dielectric layer 690.sub.2. The layers 612
may include layers as described in FIG. 5-8. The layers 612 may be
formed by PVD or other suitable deposition techniques. The
deposition technique may depend on the type of layer.
[0091] The layers 612 are patterned to form a storage unit 610 with
a pMTJ element, as shown in FIG. 18. Patterning the layers 612 may
be achieved using an anisotropic etch, such as RIE, with a
patterned mask layer. Other techniques for forming the MTJ element
may also be useful.
[0092] The process may further include performing an anneal process
at a temperature of at least 400.degree. C. for at least 30 minutes
to crystallize the layers 612, including the MTJ ferromagnetic
layers and tunnel barrier layers. Due to the use of the carbon
doped cobalt iron layer described above, and by avoiding use of
boron in the MTJ layers, the anneal process may be performed at
higher temperatures and/or for a longer duration than conventional
processing. For example, the anneal process may be performed at
420.degree. C. for longer than 30 minutes to improve crystallinity.
Another major benefit for carbon doped MTJ materials is improved
tolerance for longer BEOL process temperature that typical run at a
temperature of 400.degree. C. for over an hour and may include
CVD-based ILD dielectric materials and alloy forming step.
[0093] Referring to FIG. 19, a storage dielectric layer 690.sub.3
is formed over and covers MTJ storage unit 610. An exemplary
storage dielectric layer 690.sub.3 is silicon oxide. Storage
dielectric layer 690.sub.3 may be formed by, for example, CVD.
Other types of storage dielectric layers or forming techniques may
also be useful. A planarization process, such as CMP, is performed
to remove excess dielectric material to form a planar surface. As
shown, storage dielectric layer 690.sub.3 is disposed above the
surface of storage unit 610. An exemplary storage dielectric layer
690.sub.3 includes V1 and M1/M2 levels.
[0094] In FIG. 20, a conductive or metal line is formed in the
dielectric layer in M2. For example, a bitline BL is formed in M2
of the dielectric layer, coupling to storage unit 610. Other
conductive lines may also be formed. The conductive lines in M2 may
be formed using a dual damascene technique.
[0095] Additional processes may be performed to complete forming
the device. For example, the processes may include forming
additional ILD, pad, and passivation levels, pad opening, dicing,
assembly and testing. Other types of processes may also be
performed.
[0096] As described, the storage unit is formed in V1 and BL is
formed in M2. Forming the storage unit and BL in other ILD levels,
such as in an upper ILD level, may also be useful. In the case
where the storage unit is provided in an upper ILD level, contact
and interconnect pads may be formed in the intermediate ILD levels
to connect to the storage unit. The contact and interconnect pads
may be formed using dual damascene techniques.
[0097] In addition, a metal wordline may be provided in a metal
layer above the gate. The metal wordline, for example, may be
coupled to the gate of the select transistor. The metal wordline
may be provided in M1 or other metal levels. For example, the metal
wordline may be parallel with the SL. Also, as described, the
various components are disposed in specific via or metal levels. It
is understood that other configurations of the memory cell may also
be useful. For example, the components may be disposed in other
metal or via levels.
[0098] The embodiments as described result in various advantages.
In the embodiments as described, a base layer having the seed layer
and wetting layer enhances the FCC structure along the (111)
orientation of the fixed layer, thereby improving PMA of the fixed
layer. Furthermore, the seed layer as described in this disclosure
includes a reduced thickness without sacrificing PMA of the fixed
layer. A thinner seed layer reduces total interface or surface
roughness of the fixed layer. The reduced interface roughness
improves thermal endurance of the pMTJ stack, for example at about
400.degree. C. As a result, a pMTJ stack with improved thermal
budget and PMA can be achieved. The seed layer with reduced
thickness could also lead to a minimized pMTJ stack. As described,
a surface smoother, such as a surfactant layer, is provided between
the wetting and seed layers. This enhances the smoothness of the
seed layer and leads to improved thermal endurance. Moreover, the
process as described is highly compatible with logic processing or
technology. This avoids investment of new tools and does not
require creating new low temperature modules or processing,
providing a cost effective solution.
[0099] The present disclosure may be embodied in other specific
forms without departing from the spirit or essential
characteristics thereof. The foregoing embodiments, therefore, are
to be considered in all respects illustrative rather than limiting.
The scope of the subject matter is thus indicated by the appended
claims, rather than by the foregoing description, and all changes
that come within the meaning and range of equivalency of the claims
are intended to be embraced therein.
[0100] While at least one exemplary embodiment has been presented
in the foregoing detailed description, it should be appreciated
that a vast number of variations exist. It should also be
appreciated that the exemplary embodiment or exemplary embodiments
are only examples, and are not intended to limit the scope,
applicability, or configuration as claimed in any way. Rather, the
foregoing detailed description will provide those skilled in the
art with a convenient road map for implementing the exemplary
embodiment or exemplary embodiments. It should be understood that
various changes can be made in the function and arrangement of
elements without departing from the scope herein as set forth in
the appended claims and the legal equivalents thereof.
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