U.S. patent application number 15/783057 was filed with the patent office on 2019-04-18 for voltage sensor-less position detection in an active front end.
This patent application is currently assigned to Deere & Company. The applicant listed for this patent is Deere & Company. Invention is credited to Jason DICKHERBER, Tianjun FU, Chris J. TREMEL, Kent WANNER, Long WU.
Application Number | 20190115820 15/783057 |
Document ID | / |
Family ID | 66096621 |
Filed Date | 2019-04-18 |
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United States Patent
Application |
20190115820 |
Kind Code |
A1 |
FU; Tianjun ; et
al. |
April 18, 2019 |
VOLTAGE SENSOR-LESS POSITION DETECTION IN AN ACTIVE FRONT END
Abstract
A controller may include a memory having computer-readable
instructions stored therein; and a processor configured to execute
the computer-readable instructions to generate Pulse Width
Modulation (PWM) signals to control power switches of an Active
Front End (AFE) inverter based on at least a synthesized grid
voltage vector angle at a terminal of an alternating current (AC)
grid without using physical voltage sensors at the terminal of the
AC grid, and control the AFE inverter to supply power to a load
based on the PWM signals.
Inventors: |
FU; Tianjun; (Fargo, ND)
; WU; Long; (Fargo, ND) ; WANNER; Kent;
(Moline, IL) ; DICKHERBER; Jason; (Moline, IL)
; TREMEL; Chris J.; (West Fargo, ND) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Deere & Company |
Moline |
IL |
US |
|
|
Assignee: |
Deere & Company
Moline
IL
|
Family ID: |
66096621 |
Appl. No.: |
15/783057 |
Filed: |
October 13, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H02M 7/5395 20130101;
H02M 1/08 20130101; H02M 1/4216 20130101; H02M 7/53871
20130101 |
International
Class: |
H02M 1/08 20060101
H02M001/08; H02M 7/5387 20060101 H02M007/5387; H02M 7/5395 20060101
H02M007/5395 |
Claims
1. A controller comprising: a memory having computer-readable
instructions stored therein; and a processor configured to execute
the computer-readable instructions to, estimate a synthesized grid
voltage vector angle at a terminal of an alternating current (AC)
grid without using physical voltage sensors at the terminal of the
AC grid by, estimating a terminal voltage of an Active Front End
(AFE) inverter when the AFE inverter is enabled, the terminal
voltage of the AFE inverter being a voltage of a terminal of the
AFE inverter, estimating a first AFE inverter terminal voltage
vector angle when the AFE inverter is disabled, the first AFE
inverter terminal voltage vector angle being an angle associated
with the voltage vector of the terminal of the AFE inverter at an
initial time, determining a second AFE inverter terminal voltage
vector angle when the AFE inverter is enabled, the second AFE
inverter terminal voltage vector angle being an angle associated
with the voltage vector of the terminal of the AFE inverter at a
second time subsequent to the initial time, and estimating the
synthesized grid voltage vector angle based on the second AFE
inverter terminal voltage vector angle, the synthesized grid
voltage vector angle being an angle associated with a voltage
vector at the terminal of the AC grid; generate Pulse Width
Modulation (PWM) signals to control power switches of the AFE
inverter based on at least (i) the synthesized grid voltage vector
angle at the terminal of the AC grid and (ii) a AC grid terminal
reference power factor the AC grid terminal reference power factor
representing a desired phase shift between the voltage vector and a
current vector at the terminal of the AC grid; and control the AFE
inverter to supply power to a load based on the PWM signals.
2. (canceled)
3. The controller of claim 1, wherein the processor is configured
to generate the PWM signals by, converting measured current from a
measured 3-phase current in a stationary reference frame to a
measured direct-quadrature (dq)-axis current in a dq rotating
reference frame, generating a q-axis current reference based on the
AC grid terminal reference power factor, generating a d-axis
current reference based on an actual DC bus voltage and a reference
DC bus voltage, the actual DC bus voltage being connected to the
load, the d-axis current reference and the q-axis current reference
forming a dq-axis current reference, generating dq-axis reference
voltages based on the measured dq-axis current in the dq rotating
reference frame and the dq-axis current reference, and generating
3-phase gate driving signals for the AFE inverter by converting the
dq-axis reference voltages based on the synthesized grid voltage
vector angle, the 3-phase gate driving signals being the PWM
signals.
4. The controller of claim 1, wherein the processor is configured
to generate the PWM signals such that the AFE inverter maintains an
actual DC bus voltage connected to the load.
5. (canceled)
6. The controller of claim 1, wherein, if the inverter is enabled,
the processor is configured to estimate the terminal voltage of the
AFE inverter by, estimating 3-phase line-to-neutral voltages of the
terminal of the AFE inverter based on status signals associated
with power switches of the AFE inverter and corresponding voltage
drops across the power switches.
7. The controller of claim 6, wherein the processor is configured
to estimate the 3-phase line-to-neutral voltages by, examining
collector-emitter voltages associated with each of the power
switches of the AFE inverter.
8. The controller of claim 1, wherein, if the inverter is disabled,
the processor is configured to estimate the first AFE inverter
terminal voltage vector angle by, detecting zero-crossing instants
when the voltage of the terminal of the AFE inverter crosses zero,
calculating a AFE inverter terminal voltage vector angular
frequency based on the zero-crossing instants, the AFE inverter
terminal voltage vector angular frequency being an angular
frequency in rad/sec of the voltage of the terminal of the AFE
inverter, and calculating the first AFE inverter terminal voltage
vector angle based on the AFE inverter terminal voltage vector
angular frequency and a position of an AFE inverter terminal
voltage vector corresponding to a most recent one of the
zero-crossing instants.
9. The controller of claim 1, wherein the processor is configured
to estimate the second AFE inverter terminal voltage vector angle
by, initializing a phase locking loop (PLL) using the first AFE
inverter terminal voltage vector angle when the inverter is
disabled, and running the phase locking loop (PLL) using 3-phase
line-to-neutral voltages of the terminal of the AFE inverter when
the inverter is enabled.
10. The controller of claim 9, wherein the processor is configured
to estimate the second AFE inverter terminal voltage vector angle
by running the PLL to align the second AFE inverter terminal
voltage vector angle with a d-axis of a dq rotating reference
frame.
11. The controller of claim 10, wherein, when the AFE inverter is
enabled, the processor is configured to estimate the second AFE
inverter terminal voltage vector angle by running the PLL to
continually, calculate a position error between the second AFE
inverter terminal voltage vector angle and the d-axis, calculate an
angular frequency of the second AFE inverter terminal voltage
vector angle by using a PI controller to regulate the position
error, and calculate the second AFE inverter terminal voltage
vector angle by integrating the angular frequency.
12. The controller of claim 1, wherein the processor is configured
to estimate the AC grid voltage vector angle by compensating for an
actual phase shift due to a voltage drop across a filter between
the terminal of the AFE inverter and the terminal of the AC
grid.
13. The controller of claim 12, wherein the filter is one of a LCL
line filter and a LR line filter.
14. The controller of claim 3, wherein the processor is configured
to convert the measured current from the measured 3-phase current
to the measured dq-axis current based on the synthesized grid
voltage vector angle.
15. The controller of claim 3, wherein the processor is configured
to generate the d-axis current reference by, comparing the actual
dc bus voltage and the reference DC bus voltage, and generating the
d-axis current reference using a PI controller.
16. The controller of claim 3, wherein the processor is configured
to generate the q-axis current reference based on the AC grid
terminal reference power factor and the d-axis current
reference.
17. The controller of claim 3, wherein the processor is configured
to generate the dq-axis reference voltages by, generating a
comparison signal based on a result of comparing the d-axis current
reference and the q-axis current reference with a d-axis value of
the measured dq-axis current and a q-axis value of the measured
dq-axis current, respectively, and generating dq-axis reference
voltages based on the comparison signal.
18. The controller of claim 3, wherein the processor is configured
to, refine the synthesized grid voltage vector angle by
compensating for a time delay associated with digital processing to
generate a refined synthesized grid voltage vector angle, and
generate the 3-phase gate driving signals for the AFE inverter
based on the dq-axis reference voltages and the refined synthesized
grid voltage vector angle, wherein the 3-phase gate driving signals
are transmitted to the AFE inverter to switch a plurality of half
bridges included in the power switches of the AFE inverter.
19. A method of generating Pulse Width Modulation (PWM) signals for
power switches of an Active Front End (AFE) inverter, the method
comprising: estimating a synthesized grid voltage vector angle at a
terminal of an alternating current (AC) grid without using physical
voltage sensors at the terminal of the AC grid by, estimating a
terminal voltage of the AFE inverter when the AFE inverter is
enabled, the terminal voltage of the AFE inverter being a voltage
of a terminal of the AFE inverter, estimating a first AFE inverter
terminal voltage vector angle when the AFE inverter is disabled,
the first AFE inverter terminal voltage vector angle being an angle
associated with the voltage vector of the terminal of the AFE
inverter at an initial time, determining a second AFE inverter
terminal voltage vector angle when the AFE inverter is enabled, the
second AFE inverter terminal voltage vector angle being an angle
associated with the voltage vector of the terminal of the AFE
inverter at a second time subsequent to the initial time, and
estimating the synthesized grid voltage vector angle based on the
second AFE inverter terminal voltage vector angle, the synthesized
grid voltage vector angle being an angle associated with a voltage
vector at the terminal of the AC grid generating the PWM signals to
control the power switches of the AFE inverter based on at least
(i) the synthesized grid voltage vector angle at the terminal of
the AC grid and (ii) a AC grid terminal reference power factor, the
AC grid terminal reference power factor representing a desired
phase shift between the voltage vector and a current vector at the
terminal of the AC grid; and controlling the AFE inverter to supply
power to a load based on the PWM signals.
20. (canceled)
21. The method of claim 19, wherein the generating the PWM signals
comprises: converting measured current from a measured 3-phase
current in a stationary reference frame to a measured
direct-quadrature (dq)-axis current in a dq rotating reference
frame; generating a q-axis current reference based on the AC grid
terminal reference power factor; generating a d-axis current
reference based on an actual DC bus voltage and a reference DC bus
voltage, the actual DC bus voltage being connected to the load, the
d-axis current reference and the q-axis current reference forming a
dq-axis current reference; generating dq-axis reference voltages
based on the measured dq-axis current in the dq rotating reference
frame and the dq-axis current reference; and generating 3-phase
gate driving signals for the AFE inverter by converting the dq-axis
reference voltages based on the synthesized grid voltage vector
angle, the 3-phase gate driving signals being the PWM signals.
22. The method of claim 19, wherein the generating the PWM signals
generates the PWM signals such that the AFE inverter maintains an
actual DC bus voltage connected to the load.
23. A controller comprising: a memory having computer-readable
instructions stored therein; and a processor configured to execute
the computer-readable instructions to, estimate a synthesized grid
voltage vector angle at a terminal of an alternating current (AC)
grid without using physical voltage sensors at the terminal of the
AC grid; generate Pulse Width Modulation (PWM) signals to control
power switches of an Active Front End (AFE) inverter based on at
least (i) the synthesized grid voltage vector angle at the terminal
of the AC grid and (ii) a AC grid terminal reference power factor
without using physical voltage sensors at the terminal of the AC
grid, the AC grid terminal reference power factor representing a
desired phase shift between a voltage vector and a current vector
at the terminal of the AC grid, wherein the controller is
configured to generate the PWM signals by, converting measured
current from a measured 3-phase current in a stationary reference
frame to a measured direct-quadrature (dq)-axis current in a dq
rotating reference frame, generating a q-axis current reference
based on the AC grid terminal reference power factor, generating a
d-axis current reference based on an actual DC bus voltage and a
reference DC bus voltage, the actual DC bus voltage being connected
to a load, the d-axis current reference and the q-axis current
reference forming a dq-axis current reference, generating dq-axis
reference voltages based on the measured dq-axis current in the dq
rotating reference frame and the dq-axis current reference, and
generating 3-phase gate driving signals for the AFE inverter by
converting the dq-axis reference voltages based on the synthesized
grid voltage vector angle, the 3-phase gate driving signals being
the PWM signals; and control the AFE inverter to supply power to
the load based on the PWM signals.
Description
BACKGROUND
1. Field
[0001] Example embodiments relate generally to an apparatus
configured to detect: an angle of a grid voltage vector at a
terminal of an alternating current (AC) grid, a system and/or a
method of performing same.
2. Related Art
[0002] In an Active Front End (AFE) control system, a phase locked
loop (PLL) based control method is often used to detect an angle of
a grid voltage vector at a terminal of an alternating current (AC)
based on grid line-to-line voltage information. Conventionally, in
order to detect the angle of the grid voltage vector of the AC
grid, the grid line-to-line voltage information may need to be
sensed first using external voltage sensors attached to terminals
of the AC grid.
SUMMARY
[0003] Some example embodiments relate to a controller and/or a
method of generating Pulse Width Modulation (PWM) signals for power
switches of an Active Front End (AFE) inverter.
[0004] In some example embodiments, the controller may include a
memory having computer-readable instructions stored therein; and a
processor configured to execute the computer-readable instructions
to, generate Pulse Width Modulation (PWM) signals to control power
switches of an Active Front End (AFE) inverter based on at least a
synthesized grid voltage vector angle at a terminal of an
alternating current (AC) grid without using physical voltage
sensors at: the terminal of the AC grid, and control the AFE
inverter to supply power to a load based on the PWM signals.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] At least some example embodiments will become more fully
understood from the detailed description provided below and the
accompanying drawings, wherein like elements are represented by
like reference numerals, which are given by way of illustration
only and thus are not of example embodiments and wherein:
[0006] FIG. 1 is a block diagram of a system for controlling a load
according to some example embodiments;
[0007] FIG. 2 illustrates a method of controlling a system based on
voltage sensorless position detecting according to some example
embodiments;
[0008] FIG. 3 illustrates a method of operating a controller to
perform a voltage sensorless position detecting in a system
according to some example embodiments;
[0009] FIG. 4 illustrates a voltage sensorless position detecting
module according to some example embodiments,
[0010] FIG. 5 illustrates a method of operating a voltage
sensorless position detecting module according to some example
embodiments;
[0011] FIG. 6 illustrates a method of estimating the inverter
terminal voltage according to some example embodiments;
[0012] FIG. 7 illustrates a block diagram of an inverter terminal
voltage vector angle detecting module included in a voltage
sensorless position detecting module according to some example
embodiments;
[0013] FIG. 8 illustrates a method of estimating the inverter
terminal voltage vector angle according to some example
embodiments;
[0014] FIG. 9 illustrates a method of estimating the grid voltage
vector angle according to some example embodiments;
[0015] FIG. 10 illustrates a method of generating an initial
terminal voltage vector angle according to some example
embodiments;
[0016] FIGS. 11A to 11C are vector diagrams illustrating current
and voltage vectors in a direct-quadrature (dq) rotating reference
frame according to some example embodiments; and
[0017] FIG. 12 is a circuit diagram illustrating an AFE inverter
connected to a load according to some example embodiments.
DETAILED DESCRIPTION
[0018] Some example embodiments will now be described more fully
with reference to the accompanying drawings in which some example
embodiments are illustrated.
[0019] Accordingly, while example embodiments are capable of
various modifications and alternative forms, embodiments thereof
are shown by way of example in the drawings and will herein be
described in detail. It should be understood, however, that there
is no intent to limit example embodiments to the particular forms
disclosed, but on the contrary, example embodiments are to cover
all modifications, equivalents, and alternatives falling within the
scope of the claims. Like numbers refer to like elements throughout
the description of the figures.
[0020] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are only
used to distinguish one element from another. For example, a first
element could be termed a second element, and, similarly, a second
element could be termed a first element, without departing from the
scope of example embodiments. As used herein, the term "and/or"
includes any and all combinations of one or more of the associated
listed items.
[0021] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements present. Other words
used to describe the relationship between elements should be
interpreted in a like fashion (e.g., "between" versus "directly
between," "adjacent" versus "directly adjacent," etc.).
[0022] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
example embodiments. As used herein, the singular forms "a," "an"
and "the" are intended to include the plural forms as well, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises," "comprising," "includes"
and/or "including," when used herein, specify the presence of
stated features, integers, steps, operations, elements and/or
components, but do not preclude the presence or addition of one or
more other features, integers, steps, operations, elements,
components and/or groups thereof.
[0023] It should also be noted that in some alternative
implementations, the functions/acts noted may occur out of the
order noted in the figures. For example, two figures shown in
succession may in fact be executed substantially concurrently or
may sometimes be executed in the reverse order, depending upon the
functionality/acts involved.
[0024] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which example
embodiments belong. It will be further understood that terms, e.g.,
those defined in commonly used dictionaries, should be interpreted
as having a meaning that is consistent with their meaning in the
context of the relevant art and will not be interpreted in an
idealized or overly formal sense unless expressly so defined
herein.
[0025] Portions of example embodiments and corresponding detailed
description are presented in terms of software, or algorithms and
symbolic representations of operation on data bits within a
computer memory. These descriptions and representations are the
ones by which those of ordinary skill in the art effectively convey
the substance of their work to others of ordinary skill in the art.
An algorithm, as the term is used here, and as it is used
generally, is conceived to be a self-consistent sequence of steps
leading to a result. The steps are those requiring physical
manipulations of physical quantities. Usually, though not
necessarily, these quantities take the form of optical, electrical,
or magnetic signals capable of being stored, transferred, combined,
compared, and otherwise manipulated. It has proven convenient at
times, principally for reasons of common usage, to refer to these
signals as bits, values, elements, symbols, characters, terms,
numbers, or the like.
[0026] In the following description, illustrative embodiments will
be described with reference to acts and symbolic representations of
operations (e.g., in the form of flowcharts) that may be
implemented as program modules or functional processes including
routines, programs, objects, components, data structures, etc.,
that perform particular tasks or implement particular abstract data
types and may be implemented using existing hardware. Such existing
hardware may include one or more Central Processing Units (CPUs),
digital signal processors (DSPs),
application-specific-integrated-circuits, field programmable gate
arrays (FPGAs) computers or the like.
[0027] It should be borne in mind, however, that all of these and
similar terms are to be associated with the appropriate physical
quantities and are merely convenient labels applied to these
quantities. Unless specifically stated otherwise, or as is apparent
from the discussion, terms such as "processing" or "computing" or
"calculating" or "determining" or "displaying" or the like, refer
to the action and processes of a computer system, or similar
electronic computing device, that manipulates and transforms data
represented as physical, electronic quantities within the computer
system's registers and memories into other data similarly
represented as physical quantities within the computer system
memories or registers or other such information storage,
transmission or display devices.
[0028] In this application, including the definitions below, the
term `module` or the term `controller` may be replaced with the
term `circuit.` The term `module` may refer to, be part of, or
include processor hardware (shared, dedicated, or group) that
executes code and memory hardware (shared, dedicated, or group)
that stores the code executed by the processor hardware.
[0029] The module may include one or more interface circuits. In
some examples, the interface circuits may include wired or wireless
interfaces that are connected to a local area network (LAN), the
Internet, a wide area network (WAN), or combinations thereof. The
functionality of any given module of the present disclosure may be
distributed among multiple modules that are connected via interface
circuits. For example, multiple modules may allow load balancing.
In a further example, a server (also known as remote, or cloud)
module may accomplish some functionality on behalf of a client
module.
[0030] Further, at least one embodiment of the invention relates to
a non-transitory computer-readable storage medium comprising
electronically readable control information stored thereon,
configured in such that when the storage medium is used in a
controller of a magnetic resonance device, at least one embodiment
of the method is carried out.
[0031] Even further, any of the aforementioned methods may be
embodied in the form of a program. The program may be stored on a
non-transitory computer readable medium and is adapted to perform
any one of the aforementioned methods when run on a computer device
(a device including a processor). Thus, the non-transitory,
tangible computer readable medium, is adapted to store information
and is adapted to interact with a data processing facility or
computer device to execute the program of any of the above
mentioned embodiments and/or to perform the method of any of the
above mentioned embodiments.
[0032] The computer readable medium or storage medium may be a
built-in medium installed inside a computer device main body or a
removable medium arranged so that it can be separated from the
computer device main body. The term computer-readable medium, as
used herein, does not encompass transitory electrical or
electromagnetic signals propagating through a medium (such as on a
carrier wave); the term computer-readable medium is therefore
considered tangible and non-transitory. Non-limiting examples of
the non-transitory computer-readable medium include, but are not
limited to, rewriteable non-volatile memory devices (including, for
example flash memory devices, erasable programmable read-only
memory devices, or a mask read-only memory devices); volatile
memory devices (including, for example static random access memory
devices or a dynamic random access memory devices); magnetic
storage media (including, for example an analog or digital magnetic
tape or a hard disk drive); and optical storage media (including,
for example a CD, a DVD, or a Blu-ray Disc). Examples of the media
with a built-in rewriteable non-volatile memory, include but are
not limited to memory cards; and media with a built-in ROM,
including but not limited to ROM cassettes; etc. Furthermore,
various information regarding stored images, for example, property
information, may be stored in any other form, or it may be provided
in other ways.
[0033] The term code, as used above, may include software,
firmware, and/or microcode, and may refer to programs, routines,
functions, classes, data structures, and/or objects. Shared
processor hardware encompasses a single microprocessor that
executes some or all code from multiple modules. Group processor
hardware encompasses a microprocessor that, in combination with
additional microprocessors, executes some or all code from one or
more modules. References to multiple microprocessors encompass
multiple microprocessors on discrete dies, multiple microprocessors
on a single die, multiple cores of a single microprocessor,
multiple threads of a single microprocessor, or a combination of
the above.
[0034] Shared memory hardware encompasses a single memory device
that stores some or all code from multiple modules. Group memory
hardware encompasses a memory device that, in combination with
other memory devices, stores sonic or all code from one or more
modules.
[0035] The term memory hardware is a subset of the term
computer-readable medium. The term computer-readable medium, as
used herein, does not encompass transitory electrical or
electromagnetic signals propagating through a medium (such as on a
carrier wave); the term computer-readable medium is therefore
considered tangible and non-transitory. Non-limiting examples of
the non-transitory computer-readable medium include, but are not
limited to, rewriteable non-volatile memory devices (including, for
example flash memory devices, erasable programmable read-only
memory devices, or a mask read-only memory devices); volatile
memory devices (including, for example static random access memory
devices or a dynamic random access memory devices); magnetic
storage media (including, for example an analog or digital magnetic
tape or a hard disk drive); and optical storage media (including,
for example a CD, a DVD, or a Blu-ray Disc). Examples of the media
with a built-in rewriteable non-volatile memory, include but are
not limited to memory cards; and media with a built-in ROM,
including but not limited to ROM cassettes; etc. Furthermore,
various information regarding stored images, for example, property
information, may be stored in any other form, or it may be provided
in other ways.
[0036] The transmission medium may be twisted wire pairs, coaxial
cable, optical fiber, or some other suitable transmission medium
known to the art.
[0037] The example embodiments may have different forms and/or be
combined, and should not be construed as being limited to the
descriptions set forth herein.
[0038] In one or more example embodiments, a data processing system
may estimate the grid input line-to-line voltage information
directly from the AFE inverter terminals during an inverter
self-sensing mode by estimating the inverter terminal voltage
(e.g., voltage drops across the inverter switches and diodes) based
on inverter gate drive signals, and subsequently estimating the
angle of the composite voltage vector, which is constructed from
the three-phase inverter terminal voltages, using the PLL based
position detection method.
[0039] To precisely control the AFE system power factor at a grid
input voltage terminal, the data processing system may compensate
for a voltage drop across the impedance between the grid input
voltage terminal and the AFE inverter terminals by converting the
estimated inverter voltage vector angle from the inverter terminal
voltages to the grid voltage vector angle corresponding to the
voltage at the grid input terminals.
[0040] FIG. 1 is a block diagram of a system for controlling a load
according to some example embodiments, and FIG. 2 illustrates a
method of controlling the system according to some example
embodiments.
[0041] Referring to FIGS. 1 and 2, a system 1000 may include a data
processing system 100, such as a controller, an alternating current
(AC) transformer 200 and an inductor resistor (LR) line filter 300
connected to an alternating current (AC) power grid 400, an active
front end (AFE) inverter 500, and an. AFE load 800. In some example
embodiments, the AFE load 800 may include an inverter 600, and a
load 700, such as an interior permanent magnet (IPM) motor.
[0042] The data processing system 100 may be, but not limited to, a
processor, Central Processing Unit (CPU), a controller, an
arithmetic logic unit (ALU), a digital signal processor, a
microcomputer, a field programmable gate array (FPGA), an
Application Specific Integrated Circuit (ASIC), a System-on-Chip
(SoC), a programmable logic unit, a microprocessor, or any other
device capable of performing operations in a defined manner. In an
example embodiment, the data processing system 100 may include a
processor and a memory to support storing, processing and execution
of software instructions of one or more software modules.
[0043] As discussed below, the data processing system 100 may
control the AFE inverter 500 based on signals received from the AFE
inverter 500.
[0044] In some example embodiments, the processor of the data
processing system 100 may generate Pulse Width Modulation (PWM)
signals to control power switches of an Active Front End (AFE)
inverter based on at least a synthesized grid voltage vector angle
at a terminal of an alternating current (AC) grid without using
physical voltage sensors at the terminal of the AC grid, and
control the AFE inverter to supply power to a load based on the PWM
signals.
[0045] In some example embodiments, the processor may generate the
PWM signals by, estimating the synthesized grid voltage vector
angle at the terminal of the AC grid without using the physical
voltage sensors.
[0046] In some example embodiments, the processor is configured to
generate the PWM signals by, converting measured current from a
measured. 3-phase current in a stationary reference frame to a
measured direct-quadrature (dq)-axis current in a dq rotating
reference frame, generating a q-axis current reference based on a
AC grid terminal reference power factor, generating a d-axis
current reference based on an actual DC bus voltage and a reference
DC bus voltage, the actual DC bus voltage being connected to a
load, the d-axis current reference and the q-axis current reference
forming a dq-axis current reference, generating dq-axis reference
voltages based on the measured dq-axis current in the dq rotating
reference frame and the dq-axis current reference, and generating
3-phase gate driving signals for the AFE inverter by converting the
dq-axis reference voltages based on the synthesized grid voltage
vector angle, the 3-phase gate driving signals being the PWM
signals.
[0047] In some example embodiments, the processor is configured to
generate the PWM signals such that the AFE inverter maintains an
actual DC bus voltage connected to the :load.
[0048] In some example embodiments, the processor is configured to
estimate the synthesized grid voltage vector angle by, estimating a
terminal voltage of the AFE inverter when the inverter is enabled,
the terminal voltage of the AFE inverter being a voltage of a
terminal of the AFE inverter, estimating a first AFE inverter
terminal voltage vector angle when the AFE inverter is disabled,
the first AFE inverter terminal voltage vector angle being an angle
associated with a voltage vector of the terminal of the AFE
inverter at an initial time, determining a second AFE inverter
terminal voltage vector angle when the AFE inverter is enabled, the
second AFE inverter terminal voltage vector angle being an angle
associated with a voltage vector of the terminal of the AFE
inverter at a second time subsequent to the initial time, and
estimating the synthesized grid voltage vector angle based on the
second AFE inverter terminal voltage vector angle, the synthesized
grid voltage vector angle being an angle associated with a voltage
vector of the terminal of the AC grid.
[0049] In some example embodiments, if the inverter is enabled, the
processor is configured to estimate the terminal voltage of the AFE
inverter by, estimating 3-phase line-to-neutral voltages of the
terminal of the AFE inverter based on status signals associated
with power switches of the AFE inverter and corresponding voltage
drops across the power switches.
[0050] In some example embodiments, the processor is configured to
estimate the 3-phase line-to-neutral voltages by, examining
collector-emitter voltages associated with each of the power
switches of the AFE inverter.
[0051] In some example embodiments, if the inverter is disabled,
the processor is configured to estimate the first AFE inverter
terminal voltage vector angle by, detecting zero-crossing instants
when the voltage of the terminal of the AFE inverter crosses zero,
calculating a AFE inverter terminal voltage vector angular
frequency based on the zero-crossing instants, the AFE inverter
terminal voltage vector angular frequency being an angular
frequency in rad/sec of the voltage of the terminal of the AFE
inverter, and calculating the first AFE inverter terminal voltage
vector angle based on the AFE inverter terminal voltage vector
angular frequency and a position of an AFE inverter terminal
voltage vector corresponding to a most recent one of the
zero-crossing instants.
[0052] In some example embodiments, the processor is configured to
estimate the second AFE inverter terminal voltage vector angle by,
initializing a phase locking loop (PLL) using the first AFE
inverter terminal voltage vector angle when the inverter is
disabled, and running the phase locking loop (PLL) using 3-phase
line-to-neutral voltages of the terminal of the AFE inverter when
the inverter is enabled.
[0053] In some example embodiments, the processor is configured to
estimate the second AFE inverter terminal voltage vector angle by
running the PLL to align the second AFE inverter terminal voltage
vector angle with a d-axis of a dq rotating reference frame.
[0054] In some example embodiments, when the AFE inverter is
enabled, the processor is configured to estimate the second AFT;
inverter terminal voltage vector angle by running the PLL to
continually, calculate a position error between the second AFE
inverter terminal voltage vector angle and the d-axis, calculate an
angular frequency of the second AFE inverter terminal voltage
vector angle by using a PI controller to regulate the position
error, and calculate the second AFE inverter terminal voltage
vector angle by integrating the angular frequency.
[0055] In some example embodiments, the processor is configured to
estimate the AC grid voltage vector angle by compensating for a
phase shift due to a voltage drop across a filter between the
terminal of the AFE inverter and the terminal of the AC grid.
[0056] In some example embodiments, the filter is one of a LCL line
filter and a LR line filter.
[0057] In some example embodiments, the processor is configured to
convert the measured current from the measured 3-phase current to
the measured dq-axis current based on the synthesized grid voltage
vector angle.
[0058] In some example embodiments, the processor is configured to
generate the d-axis current reference by, comparing the actual dc
bus voltage and the reference DC bus voltage, and generating the
d-axis current reference using a PI controller.
[0059] In some example embodiments, the processor is configured to
generate the q-axis current reference based on the AC grid terminal
reference power factor and the d-axis current reference.
[0060] In some example embodiments, the processor is configured to
generate the dq-axis reference voltages by, generating a comparison
signal based on a result of comparing the d-axis current reference
and the q-axis current reference with a d-axis value of the
measured dq-axis current and a q-axis value of the measured dq-axis
current, respectively, and generating dq-axis reference voltages
based on the comparison signal.
[0061] In some example embodiments, the processor is configured to,
refine the synthesized grid voltage vector angle by compensating
for a time delay associated with digital processing to generate a
refined synthesized grid voltage vector angle; and generate the
3-phase gate driving signals for the AFE inverter based on the
dq-axis reference voltages and the refined synthesized grid voltage
vector angle, wherein the 3-phase gate driving signals are
transmitted to the AFE inverter to switch a plurality of half
bridges included in the power switches of the AFE inverter.
[0062] The data processing system 100 may include a voltage
sensorless position detecting module 110, an abc/dq Transformation
Module 120, a PI controller 130, a reactive power control module
140, a current regulation controller 150, and a PWM generation
module 160. The voltage sensorless position detecting module 110 is
shown in greater detail in FIG. 4.
[0063] As discussed below, the data processing system 100 may
estimate a grid voltage vector angle .theta..sub.g without using
physical voltage sensors attached to terminals of the AC grid 400,
generate Pulse Width Modulation (PWM) signals to control power
switches of the AFE inverter 500 based on the estimated grid
voltage vector angle .theta..sub.g, and operate the load 800 based
on the PWM signals.
[0064] Referring to FIG. 2, in operation S100, the AC grid 400 may
supply or consume AC power to maintain a stable DC bus voltage
V.sub.dc at a DC bus. The DC bus electrically connects the AFE
inverter 500 and the load inverter 600. The DC bus may be modeled
as a capacitor that consumes the electrical power from the AC grid
400 and supplies the electrical power to the load 800. For example,
the AC grid 400 may supply power to the AFE inverter 500 when the
DC bus voltage V.sub.dc is less than the reference DC bus voltage
V.sub.dc due to the load 700 drawing more power from the DC bus
than the AFE inverter 500 can supply. The AC grid 400 also may
consume the AC power when the DC bus voltage V.sub.dc is greater
than the reference DC bus voltage V.sub.dc due to the load 700,
which is running as a generator, supplying more power to the DC
bus.
[0065] In operation S200, the three-phase AC transformer 200 may
convert between high and low three-phase AC voltage.
[0066] In operation S300, the LR line filter 300 may filter out the
current: harmonics on lines. For example, the LR line filter 300
may be a pre-designed LR filter. The LR line filter 300 may be
embodied as long cables connected between the AFE inverter 500 and
the three-phase AC transformer 200, the length of which is
determined based on the current harmonics on the lines.
[0067] In other example embodiments, the system 1000 may include a
inductor-capacitor-inductor style filter or LCL filter (not shown)
between the AFE inverter 500 and the three-phase AC transformer 200
rather than the LR filter 300, such that the data processing system
100 is configured to compensate for a phase shift due to a voltage
drop across the LCL filter (not shown).
[0068] In operation S400, the data processing system 100 may
estimate the grid voltage vector angle .theta..sub.g, generate the
Pulse Width Modulation (PWM) signals to control power switches of
the AFE inverter 500 based on the estimated grid voltage vector
angle .theta..sub.g. Operation S400 is discussed in greater detail
below with reference to the sub-operations illustrated in FIG.
4.
[0069] For example, the voltage sensorless position detecting
module 110 may estimate the grid voltage vector angle .theta..sub.g
defined as the d-axis orientation of the rotating dq-axis frame
without using physical voltage sensors attached to the AC grid
terminals 400. Thereafter, the data processing system 100 may
generate the Pulse Width Modulation (PWM) signals to control the
power switches of the AFE inverter 500 based on the estimated grid
voltage vector angle .theta..sub.g.
[0070] Details on the operation of the data processing system 100
including the estimation of the grid voltage vector angle
.theta..sub.g by the voltage sensorless position detecting module
110, and the generation of the PWM signals based thereon will be
discussed below with reference to FIGS. 3 to 11.
[0071] In operation S500, the AFE inverter 500 may supply/consume
power to/from the AC grid 400 to regulate the DC bus voltage. For
example, the AFE inverter 500 may consume power from the AC grid
400 when the DC bus voltage is less than the reference DC bus
voltage V*.sub.dc. Alternatively, the AFE inverter 500 may supply
power back to the AC grid 400 when the DC bus voltage is greater
than the reference DC bus voltage V*.sub.dc.
[0072] The AFE inverter 500 may include power electronics, such as
switching semiconductors to generate, modify and/or control the PWM
signals or other alternating current signals (e.g., pulse, square
wave, sinusoidal, or other waveforms) applied to the DC bus to
operate the load 800.
[0073] In operation S600, the inverter 600 may supply/consume
electric power to/from the load 700. For example, the inverter 600
may supply the electric power to the load 700. In this case, the
inverter 600 draws power from the DC bus. Alternatively, the
inverter 600 may also consume mechanical power from the load 700,
when the load 700 is running as a generator. In this case, the
inverter 600 supplies electric power to the DC bus.
[0074] The inverter 600 may include power electronics, such as
switching semiconductors to generate, modify and control
pulse-width modulated signals or other alternating current signals
(e.g., pulse, square wave, sinusoidal, or other waveforms) applied
to the load 700. A separate PWM generation module provides inputs
to a driver stage within the inverter 600. An output stage of the
inverter 600 provides the pulse-width modulated voltage waveform or
other voltage signal to control the load 700. In an example
embodiment, the inverter 600 is powered by the direct current (dc)
voltage bus voltage V.sub.dc.
[0075] In operation S700, the load 700 may consume power from the
inverter 600. In this case, the inverter 600 consumes power from
the DC bus. Alternatively, the load 700 may also supply power to
the inverter 600 and the inverter 600 may supply the power back to
the DC bus, when the load 700 runs as a generator.
[0076] FIG. 3 illustrates a method of operating a controller to
perform a voltage sensorless position detecting in a system
according to some example embodiments.
[0077] Referring to FIGS. 1 to 3, in operation S400 illustrated in
FIG. 2, the data processing system 100 may estimate the grid
voltage vector angle .theta..sub.g, and generate the Pulse Width
Modulation (PWM) signals to control the power switches of the AFE
inverter 500 based on the estimated grid voltage vector angle
.theta..sub.g by performing operations S110 to S160, discussed
below.
[0078] In operation S110, the voltage sensorless position detecting
module 110 may receive the power switch status information from the
AFE inverter 500 when inverter switching is enabled, receive the
detected phase voltage zero-crossing signals from the AFE inverter
500 when the inverter switching is disabled, and estimate the grid
voltage vector angle .theta..sub.g defined as the d-axis
orientation of the rotating dq-axis based thereon without using
physical voltage sensors attached to the AC grid terminals 400.
Therefore, the bulky and costly external voltage sensors can be
removed from the AFE control system. Operation S110 will be
discussed in more detail below with reference to FIGS. 4 to 11.
[0079] In operation S120, the abc/dq Transformation Module 120 may
receive the 3-phase grid currents I.sub.c, I.sub.b, I.sub.a and
perform the Clarke/Park transformation (abc-to-dq) based on the
estimated grid voltage vector angle .theta..sub.g to convert the
3-phase grid currents into the q-axis current I.sub.q and the
d-axis current I.sub.d in the dq rotating reference frame.
[0080] The dq axis current may refer to the direct axis current and
the quadrature axis current in the dq rotating reference frame as
applicable in the context of vector-controlled alternating current
machines, such as the load 700.
[0081] The abc/dq Transformation Module 120 may apply a Clarke
transformation and a Park transformation or other conversion
equations (e.g., certain conversion equations that are suitable and
are known to those of ordinary skill in the art) to convert the
measured three-phase representations of current: into two-phase
representations of current based on the current data I.sub.a,
I.sub.b, and I.sub.c and the estimated grid voltage vector angle
.theta..sub.g.
[0082] In operation S130, the PI controller 130 may receive a
difference between the measured DC bus voltage V.sub.dc and a
reference DC bus voltage V*.sub.dc, and may generate the d-axis
reference current I*.sub.d based on the difference between the
detected DC bus voltage V.sub.dc and the reference DC bus voltage
V*.sub.dc. The PI controller is a closed loop proportional-integral
controller used for the measured DC bus voltage V.sub.dc to track
the reference DC bus voltage V*.sub.dc.
[0083] In operation S140, the reactive power control module 140 may
generate the q-axis reference current I*.sub.q based on a reference
power factor PF* received from a high-level system control unit
(not shown). The reference power factor PF* may be empirically
determined for the system 1000 based on users' system control
requirements. The q-axis reference current I*.sub.q is generated to
assure the system 1000 is satisfying the requirement on the
reference power factor PF* with the determined d-axis reference
current I*.sub.d from the operation S140.
[0084] In operation S150, the current regulation controller 150 may
utilize the d-axis reference current I*.sub.d and the q-axis
reference current I*.sub.q as reference currents to generate the dq
axis reference voltage V*.sub.d and V*.sub.q. For example, the
current regulation controller 150 may receive the difference
between I.sub.q and I*.sub.q, and the difference between I.sub.d
and I*.sub.d, and may generate dq axis reference voltage V*.sub.d
and V*.sub.q therefrom. The current: regulation controller 150 may
include two closed loop PI controllers along with a dq-axis
cross-coupling decoupling module to track the d-axis current
I.sub.d and the q-axis current I.sub.q to their respective
references I.sub.d* and I.sub.q*. The outputs from the d-axis
current regulator and q-axis current regulator are the d-axis
reference voltage V*.sub.d and q-axis reference voltage
V*.sub.q.
[0085] In operation S160, the PWM generation module 160, may
receive the dq axis reference voltage V*.sub.d and V*.sub.q in the
dq rotating reference frame from the current regulation controller
150, and convert dq axis reference voltage V*.sub.d and V*.sub.q in
the dq rotating reference frame to an .alpha.-axis voltage command
v*.sub..alpha. and a .beta.-axis voltage command v*.sub..beta. in
the .alpha.-.beta. stationary frame based on the estimated grid
voltage vector angle .theta..sub.g, and then convert the
.alpha.-axis voltage command v*.sub..alpha. and .beta.-axis voltage
command v*.sub..beta. from two phase data representations into
three-phase data representations (e.g., three-phase
representations, such as PWM duty A, duty B and duty C for three
phases). The PWM generation module 160 may generate the three phase
power switch gate signals for the gate drive control of the
inverter power switches of the AFE inverter 500 based on the
three-phase PWM duty representations.
[0086] In other example embodiments, the PWM generation module 160
may further process the estimated grid voltage vector angle
.theta..sub.g to generate a refined estimated grid voltage vector
angle .theta..sub.g' by extrapolating the estimated grid voltage
vector angle .theta..sub.g by one and half control periods using
the PLL generated frequency to compensate for a delay associated
with the digital processing. Thereafter, the PWM generation module
160 may use the refined estimated grid voltage vector angle
.theta..sub.g' to convert the dq axis reference voltage V*.sub.d
and V*.sub.q to the .alpha.-.beta. voltage commands v*.sub..alpha.
and v*.sub..beta. in the .alpha.-.beta. reference frame.
[0087] FIG. 4 illustrates a voltage sensorless position detecting
module according to some example embodiments, and FIG. 5
illustrates a method of operating a voltage sensorless position
detecting module according to some example embodiments.
[0088] Referring to FIGS. 4 and 5, the voltage sensorless position
detecting module 110 may include an inverter terminal voltage
estimating module 112, an inverter terminal voltage vector angle
detecting module 114, a grid voltage vector angle estimating module
116, and an initial grid voltage vector angle detecting module
118.
[0089] In operation S110 illustrated in FIG. 3, the voltage
sensorless position detecting module 110 of the data processing
system 100 may estimate the grid voltage vector angle
.theta..sub.g, by performing operations S112 to S118 illustrated in
FIG. 5, discussed below.
[0090] In operation S112, the inverter terminal voltage estimating
module 112 may estimate the inverter terminal voltages Van, Vbn and
Vcn based on the power switch status information (or,
alternatively, ON/OFF status signals) and a diode voltage drop
across the power switches from the AFE inverter 500. Operation S112
will be discussed below in more detail with reference to FIG.
6.
[0091] In operation S114, the inverter terminal voltage vector
angle detecting module 114 may generate the inverter terminal
voltage vector angle .theta..sub.i based on the inverter terminal
voltages Van, Vbn and Vcn received from the inverter terminal
voltage estimating module 112 and the initial inverter voltage
vector angle .theta..sub.i.sub._.sub.init. The inverter terminal
voltage vector angle detecting module 114 may include a
Proportional and Integration (PI) controller (see FIG. 7) to
regulate the position error to force the q-axis voltage V.sub.q in
the dq rotating reference frame to 0 such that the output of the PI
controller will be the inverter terminal voltage vector angular
frequency .omega.. Operation S114 will be discussed below in more
detail with reference to FIGS. 7 and 8.
[0092] In operation S116, the grid voltage vector angle estimating
module 116 may estimate the grid voltage vector angle .theta..sub.g
without using physical voltage sensors based on the inverter
terminal voltage vector angle .theta..sub.i received from the
inverter terminal voltage vector angle detecting module 114.
Operation S116 will be discussed below in more detail with
reference to FIG. 9.
[0093] As discussed above, the grid voltage vector angle estimating
module 116 may provide the estimated grid voltage vector angle
.theta..sub.g to the abc/dq Transformation Module 120, and the
abc/dq Transformation Module 120 may use the estimated grid voltage
vector angle .theta..sub.g to perform abc-to-dq transformation on
the 3-phase grid currents I.sub.a, I.sub.b and I.sub.c to convert
the 3-phase grid currents I.sub.a, I.sub.b and I.sub.c into the
q-axis current I.sub.q and the d-axis current I.sub.d in the dq
rotating reference frame.
[0094] In operation S118, the initial grid voltage vector angle
detecting module 118 may receive phase voltage zero-crossing
signals from the AFE inverter 500, and may generate an initial
inverter voltage vector angle .theta..sub.i.sub._.sub.init to
initialize the Phase Locked Loop (PLL) controller in the inverter
terminal voltage phase angle detecting module 114. Therefore, the
PLL controller may start with the correct initial inverter terminal
voltage vector angle .theta..sub.i.sub._.sub.init. In the inverter
terminal voltage vector angle detecting module 114, the PLL
controller is utilized to detect the inverter terminal voltage
vector angle .theta..sub.i. Operation S118 will be discussed below
in more detail with reference to FIG. 10.
[0095] FIG. 6 illustrates a method of estimating the inverter
terminal voltage according to some example embodiments, and FIG. 12
is a circuit diagram illustrating an AFE inverter connected to a
load according to some example embodiments.
[0096] Referring to FIGS. 1 to 6 and 12, in operation S112-1, the
inverter termination voltage estimating module 112 may determine
the phase current direction based on the power switch status
information. For an example, the direction of the phase A current
is defined as positive direction (+la) when the phase A top switch
(see FIG. 12) is ON.
[0097] In operation S112-2, the inverter termination voltage
estimating module 112 may calculate the instantaneous phase voltage
V.sub.aN V.sub.bN and V.sub.cN using the following equations.
[0098] If the phase current I.sub.x (subscript `X` represents phase
a, b or c) is positive (the case illustrated in FIG. 12), the
following instantaneous V.sub.XN (subscript `X` represents phase a,
b or c) values can be calculated:
V.sub.XN=(Vdc-V.sub.igbt)=Top switch ON
OR
V.sub.XN=(-V.sub.diode)=Top switch OFF Eq. 1
[0099] If phase current I.sub.x is negative, the following
instantaneous V.sub.XN values can be calculated:
V.sub.XN=(Vdc+V.sub.igbt)=Bottom switch OFF
OR
V.sub.XN=(+V.sub.diode)=Bottom switch ON Eq. 2
[0100] In operation S112-3, the inverter termination voltage
estimating module 112 may calculate the line-to-line voltage
V.sub.ab between terminal a and terminal b of the AFE inverter 500
and V.sub.ca between terminal c and terminal a of the AFE inverter
500 using the following equations:
V.sub.ab=V.sub.aN-V.sub.bN
V.sub.ca=V.sub.cN-V.sub.aN Eq. 3
[0101] The voltage V.sub.xN (subscript `X` represents phase a, b or
c) in equation 3 between the AFE inverter terminal X and a negative
rail of the DC bus is estimated by examining the inverter power
switch collector to emitter voltages.
[0102] However, the line-to-line voltages V.sub.ab and V.sub.ca are
just one example of line-to-line voltages, and the inverter
termination voltage estimating module 112 may calculate other
line-to-line voltages between various terminals of the AFE inverter
500.
[0103] In operation S112-4, the inverter termination voltage
estimating module 112 may calculate the line-to-neutral voltage
Van, Vbn and Vcn using the following equations:
V.sub.an=1/3(V.sub.ab-V.sub.ca)
V.sub.bn=-1/3(2V.sub.ab+V.sub.ca)
V.sub.cn=1/3(V.sub.ab+2V.sub.ca) Eq. 4
[0104] Therefore, the inverter voltage vector angle .theta..sub.i
can be estimated in operation S114 using the line-to-neutral
voltage V.sub.an V.sub.bn and V.sub.cn. Therefore, in one or more
example embodiments, the system 1000 can detect the inverter
terminal voltages V.sub.an V.sub.bn and V.sub.cn without using
physical voltage sensors at the terminals of the AC grid 400.
[0105] FIG. 7 illustrates a block diagram of an inverter terminal
voltage vector angle detecting module 114 and FIG. 8 illustrates a
method of estimating the inverter terminal voltage vector angle
according to some example embodiments.
[0106] Referring to FIGS. 1 to 5, 7 and 8, in operation S114-1, the
inverter terminal voltage vector angle detecting module 114 may
calculate the d-axis voltage V.sub.d and the q-axis voltage V.sub.q
in the rotating dq reference frame based on the inverter terminal
line-to-neutral voltage V.sub.an, V.sub.bn, V.sub.cn and the
inverter terminal voltage vector angle .theta..sub.i using the Park
transformation in the following equation:
V .alpha. = 2 3 V an - 1 3 ( V bn - V cn ) V .beta. = 2 3 ( V bn -
V cn ) V d = V .alpha. cos ( .theta. i ) + V .beta. sin ( .theta. i
) V q = V .beta. cos ( .theta. i ) - V .alpha. sin ( .theta. i ) Eq
. 5 ##EQU00001##
[0107] In operation S114-2, the inverter terminal voltage vector
angle detecting module 114 may calculate a position error
.DELTA..theta..sub.i. The inverter terminal voltage vector angle
detecting module 114 may calculate the position error
.DELTA..theta..sub.i using the following Equation:
.DELTA..theta. i = a tan ( V q V d ) Eq . 6 ##EQU00002##
[0108] In operation S114-3, the inverter terminal voltage vector
angle detecting module 114 calculate the phase angular frequency
.omega. based on the position error .DELTA..theta..sub.i.
[0109] For example, the inverter terminal voltage vector angle
detecting module 114 may use a PI controller to regulate the
position error .DELTA..theta..sub.i to force the q-axis voltage
V.sub.q to 0, which means the d-axis in the rotating dq reference
frame will be forced to align to the grid voltage vector, so the
output of the PI controller is the grid voltage vector angular
frequency .omega..
[0110] In operation S114-4, the inverter terminal voltage vector
angle detecting module 114 may utilize the following equation to
calculate the angle .theta..sub.i of the inverter voltage vector
u.sub.s:
.theta..sub.i=.intg..sub.0.sup.t.omega.dt+.theta..sub.i.sub._.sub.init
Eq. 7
[0111] Thereafter, the inverter terminal voltage vector angle
detecting module 114 may return to operation S114-1, and
recalculate the d-axis voltage V.sub.d and the q-axis voltage
V.sub.q such that operations S114-1 to S114-4 are performed
iteratively in a phase locked loop (PLL) to reach a
convergence.
[0112] Operations S114-1 to S114-4 are illustrated in FIG. 7 in
block diagram form.
[0113] FIG. 9 illustrates a method of estimating the grid voltage
vector angle .theta..sub.g according to some example embodiments.
FIGS. 11A to 11C are vector diagrams illustrating current and
voltage vectors in the dq rotating reference frame according to
some example embodiments.
[0114] Referring to FIGS. 11A to 11C, in FIGS. 11A to 11C, .DELTA.v
is a voltage vector difference between an inverter terminal voltage
vector u.sub.s at a terminal of the AFE inverter 500, and the grid
voltage vector u.sub.g at a terminal of the AC grid 400, i.e.,
.DELTA.v=u.sub.s-u.sub.g. The angle .beta. is an angle between a
q-axis voltage vector V.sub.q and the voltage vector difference
.DELTA.v, the angle .alpha. is an angle between a d-axis voltage
vector V.sub.d and a vector j.omega.Li.sub.s. In FIGS. 11A to 11C,
the angles .alpha. and .beta. are used as intermediate calculation
angles to calculate an adjusted angle .theta. representing the
difference between .theta..sub.i and .theta..sub.g, and the angle
.psi. is a power factor angle. The angles .PSI., .beta. and .alpha.
are defined as below:
.psi. = cos - 1 ( PF * ) .alpha. = .pi. 2 - .psi. 0 <= .beta.
<= .pi. 2 Eq . 8 ##EQU00003##
Since 0<=|PF*|<=1,
[0115] 0 = < .psi. <= .pi. 2 Eq . 9 ##EQU00004##
[0116] In FIG. 11A, since the absolute value of the reference power
factor PF* is 1, the AFE inverter 500 supplies/consumes power
to/from the AC grid 400 at a unity reference power factor PF*. In
graph A1, the AFE inverter 500 supplies power to the AC grid 400.
In graph A2, the AFE inverter 500 consumes power from the AC grid
400. In both cases, the power factor angle .psi. equals 0 (Is>0
and Is<0) and the angle .alpha. is:
.alpha. = .pi. 2 - .psi. = .pi. 2 - 0 = .pi. 2 Eq . 10
##EQU00005##
[0117] In the following equations, R and L are the resistance and
inductance values of the LR line filter 300, respectively; I.sub.s
is the signed magnitude of an AFE inverter phase current reference
vector i.sub.s.
I s = { sign ( I d * ) ( I d * ) 2 + ( I q * ) 2 , when I d *
.noteq. 0 - sign ( I q * ) ( I d * ) 2 + ( I q * ) 2 , when I d * =
0 Eq . 11 ##EQU00006##
where I*.sub.d is the d-axis current reference generated from the
PI controller 130 and I*.sub.q is the q-axis current reference
generated from the reactive power control module 140.
[0118] From graph A1, when (I.sub.s>0 & |PF*|=1), .beta.,
V.sub.d and V.sub.q can be calculated using the following
equations:
.beta.=tan.sup.-1(R/.omega.L)
V.sub.d=u.sub.g+I.sub.sR=u.sub.g+.DELTA.vsin(.beta.)=u.sub.g+sin(.beta.)-
I.sub.s {square root over (R.sup.2+(.omega.L).sup.2)}
V.sub.q=.omega.LI.sub.s=.DELTA.vcos(.beta.)=cos(.beta.)I.sub.s
{square root over (R.sup.2+(.omega.L).sup.2)} Eq. 12
[0119] From graph A2, when (I.sub.s<0 & |PF*|=1), .beta.,
V.sub.d and V.sub.q can be calculated using the following
equations:
.beta. = tan - 1 ( R / .omega. L ) V d = u g + I s R = u g -
.DELTA. v sin ( .beta. ) = u g - sin ( .beta. ) I s R 2 + ( .omega.
L ) 2 = u g + sin ( .beta. ) I s R 2 + ( .omega. L ) 2 V q = -
.omega. L I s = - .DELTA. v cos ( .beta. ) = - cos ( .beta. ) I s R
2 + ( .omega. L ) 2 = cos ( .beta. ) I s R 2 + ( .omega. L ) 2 Eq .
13 ##EQU00007##
[0120] In FIG. 11B, the AFE inverter 500 supplies power to the AC
grid 400 at a non-unity reference power factor PF*. In graph B1,
the reference power factor PF* is greater than 0, and the inverter
current vector i.sub.s leads the grid voltage vector u.sub.g. In
graph B2, the reference power factor PF* is less than 0, and the
grid voltage vector u.sub.g leads the inverter current vector
i.sub.s.
[0121] From graph B1, when (I.sub.s>0 & PF*>0), .beta.,
V.sub.d and V.sub.q can be calculated using the following
equations:
.beta.=(.pi./2-.alpha.)-tan.sup.-1(R/.omega.L)=.psi.-tan.sup.-1(R/.omega-
.L)
V.sub.d=u.sub.g-.DELTA.vsin(.beta.)=u.sub.g-sin(.beta.)I.sub.s
{square root over (R.sup.2+(.omega.L).sup.2)}
V.sub.q=.DELTA.vcos(.beta.)=cos(.beta.)I.sub.s {square root over
(R.sup.2+(.omega.L).sup.2)} Eq. 14
[0122] From graph B2, when (I.sub.s>0 & PF*<0), .beta.,
V.sub.d and V.sub.q can be calculated using the following
equations:
.beta.=(.pi./2-.alpha.)+tan.sup.-1(R/.omega.L)=.psi.+tan.sup.-1(R/.omega-
.L)
V.sub.d=u.sub.g+.DELTA.vsin(.beta.)=u.sub.g+sin(.beta.)I.sub.s
{square root over (R.sup.2+(.omega.L).sup.2)}
V.sub.q=.DELTA.vcos(.beta.)=cos(.beta.)I.sub.s {square root over
(R.sup.2+(.omega.L).sup.2)} Eq. 15
[0123] In FIG. 11C, the AFE inverter 500 consumes power from the AC
grid 400 at a non-unity reference power factor PF*. In graph C1,
the reference power factor PF* is greater than 0, and the reversed
inverter current vector i.sub.s leads the grid voltage vector
u.sub.g. In graph C2, the reference power factor PF* is less than
0, and the grid voltage vector u.sub.g leads the reversed inverter
current vector i.sub.s.
[0124] From graph C1, when (I.sub.s<0 & PF*>0), V.sub.d
and V.sub.q can be calculated using the following equations:
.beta. = ( .pi. / 2 - .alpha. ) - tan - 1 ( R / .omega. L ) = .psi.
- tan - 1 ( R / .omega. L ) V d = u g + .DELTA. v sin ( .beta. ) u
g + sin ( .beta. ) I s R 2 + ( .omega. L ) 2 = u g - sin ( .beta. )
I s R 2 + ( .omega. L ) 2 V q = - .DELTA. v cos ( .beta. ) = - cos
( .beta. ) I s R 2 + ( .omega. L ) 2 = cos ( .beta. ) I s R 2 + (
.omega. L ) 2 Eq . 16 ##EQU00008##
[0125] From graph C2, when (I.sub.s<0 & PF*<0), V.sub.d
and V.sub.q can be calculated using the following equations:
.beta. = ( .pi. / 2 - .alpha. ) + tan - 1 ( R / .omega. L ) = .psi.
+ tan - 1 ( R / .omega. L ) V d = u g - .DELTA. v sin ( .beta. ) u
g - sin ( .beta. ) I s R 2 + ( .omega. L ) 2 = u g + sin ( .beta. )
I s R 2 + ( .omega. L ) 2 V q = - .DELTA. v cos ( .beta. ) = - cos
( .beta. ) I s R 2 + ( .omega. L ) 2 = cos ( .beta. ) I s R 2 + (
.omega. L ) 2 Eq . 17 ##EQU00009##
[0126] As discussed in more detail below with reference to FIG. 9,
based on analysis above for all cases in FIGS. 11A to 11C, the grid
voltage vector angle estimating module 116 may select different
ones of the following equations to calculate the adjusted angle
.theta. from the AFE inverter 500 terminal to the AC grid 400
terminal:
.psi. = cos - 1 ( PF * ) { .beta. = .psi. - tan - 1 ( R / .omega. L
) , when 1 > PF * >= 0 .beta. = .psi. + tan - 1 ( R / .omega.
L ) , when PF * = 1 or PF * < 0 { V d = u g - sin ( .beta. )
.times. I S .times. R 2 + ( .omega. L ) 2 , when 1 > PF * >=
0 V d = u g + sin ( .beta. ) .times. I S .times. R 2 + ( .omega. L
) 2 , when PF * = 1 or PF * < 0 V q = cos ( .beta. ) .times. I S
.times. R 2 + ( .omega. L ) 2 { .theta. = - tan - 1 ( V q V d ) ,
when I S >= 0 .theta. = tan - 1 ( V q V d ) , when I S < 0 Eq
. 18 ##EQU00010##
[0127] Therefore, the compensated position considering phase shift
between the inverter terminal voltage vector angle .theta..sub.i
and the grid voltage vector angle .theta..sub.g can be calculated
using the following equation:
.theta..sub.g=.theta..sub.i+.theta. Eq. 19
[0128] Referring to FIGS. 1 to 5, 9 and 11A to 11C, using various
ones of Equations 18 and 19, discussed above, the grid voltage
vector angle estimating module 116 may calculate the grid voltage
vector angle .theta..sub.g.
[0129] In operation S116-1, the grid voltage vector angle
estimating module 116 may calculate the requested power factor
angle .PSI. based on the reference power factor PF* using the
following Equation:
.PSI.=cos.sup.-1(|PF*|). Eq. 20
[0130] In operation S116-2, the grid voltage vector angle
estimating module 116 may determine whether the absolute value of
the reference power factor PF* is equal to 1 or whether the
reference power factor PF* is less than zero, and the grid voltage
vector angle estimating module 116 will use this information about
the reference power factor PF* to determine which of the equations
included in Equation 18 will be used to calculate the intermediate
calculation angle .beta. and the d-axis voltage V.sub.d.
[0131] In operation S116-3, the grid voltage vector angle
estimating module 116 may calculate the intermediate calculation
angle .beta. based on the power factor angle .PSI. determined in
operation S116-1, the grid voltage vector angular frequency .omega.
calculated in operation S114, and known line filter parameters L
and R, which are the inductance and resistance values of the LR
line filter 300, respectively. Further, the grid voltage vector
angle estimating module 116 may calculate the d-axis voltage
V.sub.d based on the intermediate calculation angle .beta., the
line filter parameters R and L, the grid voltage vector angular
frequency .omega. calculated in operation S114, the signed
magnitude of the AFE inverter phase current vector reference
i.sub.s, and a magnitude of the d voltage vector u.sub.g.
[0132] The grid voltage vector angle estimating module 116 may
calculate the angle .beta. and d-axis voltage V.sub.d using
different ones of the equations included in Equation 18 based on
the reference power factor PF*.
[0133] For example, if the absolute value of the reference power
factor PF* is equal to 1 or the reference power factor is less than
zero, the grid voltage vector angle estimating module 116 may
determine the angle .beta. and V.sub.d using the following
equations:
.beta.=.psi.+tan.sup.-(R/.omega.L)
V.sub.d=u.sub.g+sin(.beta.).times.I.sub.s.times. {square root over
(R.sup.2+(.omega.L).sup.2)} Eq. 20
[0134] Alternatively, if the absolute value of the reference power
factor PF* is not equal to 1 or the reference power factor PF* is
greater than or equal to zero, the grid voltage vector angle
estimating module 116 may determine the angle .beta. and V.sub.d
using the following two equations:
.beta.=.psi.-tan.sup.-1(R/.omega.L)
V.sub.d=u.sub.g-sin(.beta.).times.I.sub.s.times. {square root over
(R.sup.2+(.omega.L).sup.2)} Eq. 21
[0135] In operation S116-4, the grid voltage vector angle
estimating module 116 may calculate the q-axis voltage V.sub.q
based on the angle .beta. determined in operation S116-3, the line
filter parameters L and R, the grid voltage vector angular
frequency ca calculated in operation S114, and the magnitude of the
AFE inverter phase current vector reference I.sub.s. For example,
the grid voltage vector angle estimating module may calculate
V.sub.q using the following Equation:
V.sub.q=cos(.beta.).times.|I.sub.s|.times. {square root over
(R.sup.2+(.omega.L).sup.2)} Eq. 22
[0136] In operation S116-5, the grid voltage vector angle
estimating module 116 may determine whether the signed magnitude of
the inverter phase current vector I.sub.s is positive or negative,
and the grid voltage vector angle estimating module 116 may
determine which of the equations in Equation 18 to use to calculate
the adjusted angle .theta. based on the signed magnitude of the
inverter phase current vector I.sub.s.
[0137] In operation S116-6, the grid voltage vector angle
estimating module 116 may calculate the adjusted angle .theta.
based on the equation determined in operation S116-5, such that
different ones of the equations included in. Equation 18 are
utilized to determine the adjusted angle .theta. based on the
signed magnitude of the inverter phase current vector I.sub.s
[0138] In operation S116-7, the grid voltage vector angle
estimating module 116 may calculate the grid voltage vector angle
.theta..sub.g based on the adjusted angle .theta. determined in
operation S116-6 and the inverter terminal voltage vector angle
.theta..sub.i determined in operation S114.
[0139] FIG. 10 illustrates a method of generating an initial
inverter terminal voltage vector angle according to some example
embodiments.
[0140] Referring to FIGS. 1 to 5 and 10, in operation S118-1, the
initial inverter terminal voltage vector angle detecting module 118
may detect the inverter terminal voltage zero-crossing instants and
record the time stamps when the AFE inverter 500 is disabled. For
example, a hardware device, such as a PSoC chip, can baa utilized
to detect the zero-crossing instants of the inverter terminal
voltage u.sub.s.
[0141] Based on the recorded time stamps information at each
zero-crossing instant, the initial inverter terminal voltage vector
angle detecting module 118 may estimate the angle .theta..sub.i of
the inverter terminal voltage vector u.sub.s before the AFE
inverter 500 is enabled, and use the estimated angle .theta..sub.i
of the inverter terminal voltage vector u.sub.s to initialize the
PLL controller.
[0142] In operation S118-2, the initial terminal voltage vector
angle detecting module 118 may calculate the inverter terminal
voltage angular frequency .omega. based on the inverter terminal
voltage zero-crossing instants before the AFE inverter 500 is
enabled. For example, the initial terminal voltage vector angle
detecting module 118 may calculate the inverter terminal voltage
angular frequency .omega. in rad/sec using the following
Equation:
.omega.=.pi./.DELTA.t, Eq. 23
where .DELTA.t is the time stamp difference in seconds between two
zero-crossing instants.
[0143] In operation S118-3, the initial terminal voltage vector
angle detecting module 118 may calculate the initial inverter
terminal voltage vector angle .theta..sub.i.sub._.sub.init based on
the inverter terminal voltage angular frequency .omega.. For
example, the initial inverter terminal voltage vector angle
detecting module 118 may calculate the initial inverter terminal
voltage vector angle .theta..sub.i.sub._.sub.init using the
following Equation:
.theta..sub.i.sub._.sub.init=.intg..sub.0.sup.i.omega.dt+.theta..sub.zer-
o.sub._.sub.crossing Eq. 24
where .theta..sub.i.sub._.sub.init is the calculated initial
inverter terminal voltage vector angle and
.theta..sub.zero.sub._.sub.crossing is the inverter terminal
voltage vector angle corresponding to the most recent zero-crossing
instant.
[0144] The initial terminal voltage vector angle detecting module
118 may provide the initial inverter terminal voltage vector angle
.theta..sub.i.sub._.sub.init to the inverter terminal voltage
vector angle detecting module 114. As discussed above, the inverter
terminal voltage vector angle detecting module 114 may use the
initial inverter terminal voltage vector angle
.theta..sub.i.sub._.sub.init to initialize the integrator of the
PLL controller in the inverter terminal voltage vector angle
detecting module 114. Therefore, the PLL controller may start with
the correct initial inverter terminal voltage vector angle
.theta..sub.i.sub._.sub.init without using the bulkiness of sensors
at the AC grid terminal 400.
[0145] Example embodiments being thus described, it will be obvious
that the same may be varied in many ways. Such variations are not
to be regarded as a departure from the spirit and scope of example
embodiments, and all such modifications as would be obvious to one
skilled in the art are intended to be included within the scope of
the claims.
* * * * *