U.S. patent application number 16/129578 was filed with the patent office on 2019-04-18 for impedance measuring semiconductor circuit and blood-sugar level meter.
The applicant listed for this patent is Renesas Electronics Corporation. Invention is credited to Gaku MASUMOTO, Kazuo OKADO, Kunihiko WATANABE.
Application Number | 20190113472 16/129578 |
Document ID | / |
Family ID | 66095687 |
Filed Date | 2019-04-18 |
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United States Patent
Application |
20190113472 |
Kind Code |
A1 |
WATANABE; Kunihiko ; et
al. |
April 18, 2019 |
IMPEDANCE MEASURING SEMICONDUCTOR CIRCUIT AND BLOOD-SUGAR LEVEL
METER
Abstract
There is a need to provide an impedance measuring semiconductor
circuit and a blood-sugar level meter capable of improving the
accuracy of measuring the impedance of a specimen, reducing an area
in an analog front-end LSI chip, and reducing the LSI chip size.
According to an embodiment, an impedance measuring semiconductor
circuit includes: an operational amplifier; a resistance coupled
between a negative input terminal and an output terminal of the
operational amplifier; a D/A converter coupled to a positive input
terminal; a switch; an A/D converter that is coupled with the
output terminal of the operational amplifier and a one-side
terminal of a specimen and measures an output voltage from the
operational amplifier and a one-side terminal voltage; and a
controller that controls an output voltage from the D/A converter
based on a one-side terminal voltage measured by the A/D
converter.
Inventors: |
WATANABE; Kunihiko; (Tokyo,
JP) ; MASUMOTO; Gaku; (Tokyo, JP) ; OKADO;
Kazuo; (Tokyo, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Renesas Electronics Corporation |
Tokyo |
|
JP |
|
|
Family ID: |
66095687 |
Appl. No.: |
16/129578 |
Filed: |
September 12, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
C12Q 1/006 20130101;
G01N 27/028 20130101; G01N 27/3272 20130101; G01N 27/3274 20130101;
G01N 33/66 20130101; G01N 27/3273 20130101; G01N 33/48707
20130101 |
International
Class: |
G01N 27/02 20060101
G01N027/02; G01N 33/487 20060101 G01N033/487; G01N 33/66 20060101
G01N033/66; G01N 27/327 20060101 G01N027/327; C12Q 1/00 20060101
C12Q001/00 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 18, 2017 |
JP |
2017-201532 |
Claims
1. An impedance measuring semiconductor circuit that measures
impedance of a specimen having a one-side terminal and a
different-side terminal, comprising: an operational amplifier; a
resistance coupled between a negative input terminal of the
operational amplifier and an output terminal of the operational
amplifier; a D/A converter coupled to a positive input terminal of
the operational amplifier; a switch placed between the one-side
terminal and the negative input terminal; an A/D converter that is
coupled with an output terminal of the operational amplifier and
the one-side terminal and measures an output voltage from the
operational amplifier and a one-side terminal voltage as a terminal
voltage of the one-side terminal; and a controller that controls an
output voltage from the D/A converter based on the one-side
terminal voltage measured by the A/D converter, wherein a
different-side terminal voltage as a terminal voltage of the
different-side terminal is set to a predetermined voltage; and
wherein an output voltage from the operational amplifier is used to
measure impedance of the specimen.
2. The impedance measuring semiconductor circuit according to claim
1, wherein the different-side terminal voltage is grounded to be
set to a predetermined voltage.
3. The impedance measuring semiconductor circuit according to claim
1, wherein the controller increases an output voltage from the D/A
converter in case of the one-side terminal voltage being lower than
a predetermined target value and decreases an output voltage from
the D/A converter in case of the one-side terminal voltage being
higher than or equal to the target value.
4. The impedance measuring semiconductor circuit according to claim
1, wherein the specimens are provided; and wherein the switch is
placed between a one-side terminal of each of the specimens and the
negative input terminal.
5. The impedance measuring semiconductor circuit according to claim
1, further comprising: a buffer amplifier that includes an output
terminal and a negative input terminal coupled to each other and is
supplied with a reference voltage at a positive input terminal of
the buffer amplifier, wherein the different-side terminal voltage
is set to a predetermined voltage by being coupled to an output
terminal of the buffer amplifier.
6. The impedance measuring semiconductor circuit according to claim
5, wherein the controller controls the D/A converter to cause the
one-side terminal voltage to be lower than the different-side
terminal voltage.
7. The impedance measuring semiconductor circuit according to claim
1, wherein at least one of the operational amplifier, the A/D
converter, the D/A converter, and the switch includes a CMOS
structure formed over a semiconductor substrate.
8. An impedance measuring semiconductor circuit that measures
impedance of a specimen having a one-side terminal and a
different-side terminal, comprising: an operational amplifier; a
resistance coupled between a negative input terminal of the
operational amplifier and an output terminal of the operational
amplifier; a first D/A converter coupled to a positive input
terminal of the operational amplifier; a switch placed between the
one-side terminal and a negative input terminal of the operational
amplifier; an A/D converter that is coupled with an output terminal
of the operational amplifier and the one-side terminal and measures
an output voltage from the operational amplifier and a one-side
terminal voltage as a terminal voltage of the one-side terminal;
and a buffer amplifier that includes an output terminal and a
negative input terminal coupled to each other; a second D/A
converter coupled to a positive input terminal of the buffer
amplifier; and a controller that controls at least one of an output
voltage from the first D/A converter and an output voltage from the
second D/A converter based on a terminal-to-terminal voltage
between the one-side terminal and the different-side terminal, the
terminal-to-terminal voltage being calculated by using the one-side
terminal voltage measured by the A/D converter, wherein an output
voltage from the operational amplifier is used to measure impedance
of the specimen.
9. The impedance measuring semiconductor circuit according to claim
8, wherein the controller controls the first D/A converter to cause
the one-side terminal voltage to be higher than a different-side
terminal voltage as a terminal voltage of the different-side
terminal;
10. The impedance measuring semiconductor circuit according to
claim 9, wherein the controller increases an output voltage from
the first D/A converter in case of the terminal-to-terminal voltage
being lower than a predetermined target value and decreases an
output voltage from the first D/A converter in case of the
terminal-to-terminal voltage being higher than or equal to the
target value.
11. The impedance measuring semiconductor circuit according to
claim 8, wherein the controller controls the first D/A converter to
cause the one-side terminal voltage to be lower than a
different-side terminal voltage as a terminal voltage of the
different-side terminal.
12. The impedance measuring semiconductor circuit according to
claim 11, wherein the controller decreases an output voltage from
the first D/A converter in case of the terminal-to-terminal voltage
being lower than a predetermined target value and increases an
output voltage from the first D/A converter in case of the
terminal-to-terminal voltage being higher than or equal to the
target value.
13. The impedance measuring semiconductor circuit according to
claim 8, wherein the controller controls the second D/A converter
to cause the one-side terminal voltage to be higher than a
different-side terminal voltage as a terminal voltage of the
different-side terminal.
14. The impedance measuring semiconductor circuit according to
claim 13, wherein the controller decreases an output voltage from
the second D/A converter in case of the terminal-to-terminal
voltage being lower than a predetermined target value and increases
an output voltage from the second D/A converter in case of the
terminal-to-terminal voltage being higher than or equal to the
target value.
15. The impedance measuring semiconductor circuit according to
claim 8, wherein the controller controls the second D/A converter
to cause the one-side terminal voltage to be lower than a
different-side terminal voltage as a terminal voltage of the
different-side terminal.
16. The impedance measuring semiconductor circuit according to
claim 15, wherein the controller increases an output voltage from
the second D/A converter in case of the terminal-to-terminal
voltage being lower than a predetermined target value and decreases
an output voltage from the second D/A converter in case of the
terminal-to-terminal voltage being higher than or equal to the
target value.
17. The impedance measuring semiconductor circuit according to
claim 8, wherein at least one of the operational amplifier, the A/D
converter, the first D/A converter, the second D/A converter, and
the switch includes a CMOS structure formed over a semiconductor
substrate.
18. The impedance measuring semiconductor circuit according to
claim 1, wherein the specimen is a test strip including a sensor
whose electrode is applied with enzyme.
19. The impedance measuring semiconductor circuit according to
claim 1, further comprising: an operation part that calculates a
blood-sugar level from the measured impedance.
20. A blood-sugar level meter comprising the impedance measuring
semiconductor circuit according to claim 1.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The disclosure of Japanese Patent Application No.
2017-201532 filed on Oct. 18, 2017 including the specification,
drawings and abstract is incorporated herein by reference in its
entirety.
BACKGROUND
[0002] The present invention relates to an impedance measuring
semiconductor circuit and a blood-sugar level meter and more
particularly to an impedance measuring semiconductor circuit and a
blood-sugar level meter capable of accurately measuring impedances
and blood-sugar levels of a specimen such as a test strip.
[0003] Patent literatures 1 through 4 describe a biosensor whose
electrode is coated with enzyme. The biosensor according to patent
literatures 1 through 4 includes one-side terminal and the
different-side terminal. A voltage is applied between both
terminals of the biosensor to measure a blood-sugar level in blood,
for example.
[0004] Patent Literature 1: Japanese Unexamined Patent Application
Publication No. 2016-200588
[0005] Patent Literature 2: Japanese Unexamined Patent Application
Publication No. 2016-200589
[0006] Patent Literature 3: International Unexamined Patent
Application No. 2005/054840
[0007] Patent Literature 4: Japanese Translation of Unexamined PCT
Application No. 2007-507711
SUMMARY
[0008] A measured voltage may contain an error due to on-resistance
when an element such as a switch is provided for a current pathway
of a measuring circuit that measures blood-sugar levels.
[0009] These and other objects and novel features may be readily
ascertained by referring to the following description of the
present specification and appended drawings.
[0010] According to an embodiment, an impedance measuring
semiconductor circuit measures impedance of a specimen having a
one-side terminal and a different-side terminal and includes: an
operational amplifier; a resistance coupled between a negative
input terminal of the operational amplifier and an output terminal
of the operational amplifier; a D/A converter coupled to a positive
input terminal of the operational amplifier; a switch placed
between the one-side terminal and the negative input terminal; an
A/D converter that is coupled with an output terminal of the
operational amplifier and the one-side terminal and measures an
output voltage from the operational amplifier and a one-side
terminal voltage as a terminal voltage of the one-side terminal;
and a controller that controls an output voltage from the D/A
converter based on the one-side terminal voltage measured by the
A/D converter. A different-side terminal voltage as a terminal
voltage of the different-side terminal is set to a predetermined
voltage. An output voltage from the operational amplifier is used
to measure impedance of the specimen.
[0011] The above-mentioned embodiment can provide an impedance
measuring semiconductor circuit and a blood-sugar level meter
capable of improving the accuracy of measuring the impedance of a
specimen, reducing an area in an analog front-end LSI chip, and
reducing the LSI chip size.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a circuit diagram illustrating a configuration of
an impedance measuring semiconductor circuit according to a
comparative example;
[0013] FIG. 2 is a graph illustrating a current flowing through a
test strip using an impedance measuring semiconductor circuit, in
which the horizontal axis represents the time and the vertical axis
represents a current;
[0014] FIG. 3 is a circuit diagram illustrating a configuration to
measure a plurality of test strips using the impedance measuring
semiconductor circuit according to the comparative example;
[0015] FIG. 4 is a circuit diagram illustrating a configuration of
an impedance measuring semiconductor circuit according to a first
embodiment;
[0016] FIG. 5 is a flowchart illustrating operation of the
impedance measuring semiconductor circuit according to the first
embodiment;
[0017] FIG. 6 is a graph illustrating operation of the impedance
measuring semiconductor circuit according to the first embodiment,
in which the horizontal axis represents the time and the vertical
axis represents a voltage at one-side terminal of a test strip;
[0018] FIG. 7 is a graph illustrating operation of the impedance
measuring semiconductor circuit according to the first embodiment,
in which the horizontal axis represents the time and the vertical
axis represents a current flowing through a test strip;
[0019] FIG. 8 is a circuit diagram illustrating a configuration of
an impedance measuring semiconductor circuit according to a second
embodiment;
[0020] FIG. 9 is a circuit diagram illustrating a configuration of
an impedance measuring semiconductor circuit according to a third
embodiment;
[0021] FIG. 10 is a circuit diagram illustrating a configuration of
an impedance measuring semiconductor circuit according to a fourth
embodiment;
[0022] FIG. 11 is a diagram illustrating operation of the impedance
measuring semiconductor circuit according to the fourth
embodiment;
[0023] FIG. 12 is a flowchart illustrating operation of the
impedance measuring semiconductor circuit according to the fourth
embodiment in a first case;
[0024] FIG. 13 is a flowchart illustrating operation of the
impedance measuring semiconductor circuit according to the fourth
embodiment in a second case;
[0025] FIG. 14 is a flowchart illustrating operation of the
impedance measuring semiconductor circuit according to the fourth
embodiment in a third case;
[0026] FIG. 15 is a flowchart illustrating operation of the
impedance measuring semiconductor circuit according to the fourth
embodiment in a fourth case;
[0027] FIG. 16 is a graph illustrating operation of the impedance
measuring semiconductor circuit according to the fourth embodiment,
in which the horizontal axis represents the time and the vertical
axis represents a voltage at one-side terminal of a test strip;
and
[0028] FIG. 17 is a graph illustrating operation of the impedance
measuring semiconductor circuit according to the fourth embodiment,
in which the horizontal axis represents the time and the vertical
axis represents a current flowing through a test strip.
DETAILED DESCRIPTION
[0029] The following description and drawings are omitted and
simplified as needed in order to clarify the explanation. In the
drawings, mutually corresponding elements are designated by the
same reference symbols and a duplicate explanation is omitted as
needed.
[0030] Firstly, a comparative example is used to explain a
measurement error found by the inventors with respect to an
impedance measuring semiconductor circuit. This will moreover
clarify the impedance measuring semiconductor circuit according to
each embodiment.
Comparative Example
[0031] The description below first explains a configuration of the
impedance measuring semiconductor circuit according to the
comparative example. FIG. 1 is a circuit diagram illustrating the
configuration of the impedance measuring semiconductor circuit
according to the comparative example. As illustrated in FIG. 1, an
impedance measuring semiconductor circuit 100 according to the
comparative example includes an operational amplifier AMP1, a D/A
converter DAC1, a feedback resistance R1, and an A/D converter ADC.
The impedance measuring semiconductor circuit 100 measures
impedance of a specimen having one-side terminal T1a and a
different-side terminal T1b.
[0032] The operational amplifier AMP1 includes a positive input
terminal, a negative input terminal, and an output terminal. The
operational amplifier AMP1 outputs output voltage Vamp1o from the
output terminal by using positive input voltage Vamp1p input to the
positive input terminal and negative input voltage Vamp1n input to
the negative input terminal. The D/A converter DAC1 is coupled to
the positive input terminal of the operational amplifier AMP1. One
end of the resistance R1 is coupled to the negative input terminal
of the operational amplifier AMP1. The other end of the resistance
R1 is coupled to the output terminal of the operational amplifier
AMP1. The A/D converter ADC is coupled to the output terminal of
the operational amplifier AMP1.
[0033] The resistance R1 is coupled between the negative input
terminal of the operational amplifier AMP1 and the output terminal
of the operational amplifier AMP1. The resistance R1 is provided as
a feedback resistance for the operational amplifier AMP1.
[0034] The D/A converter DAC1 is coupled to the positive input
terminal of the operational amplifier AMP1. The D/A converter DAC1
outputs a predetermined voltage to the positive input terminal of
the operational amplifier AMP1.
[0035] The A/D converter ADC is coupled to the output terminal of
the operational amplifier AMP1. The A/D converter ADC measures an
output voltage from the operational amplifier AMP1.
[0036] The specimen is provided as a test strip T1, for example.
The description below assumes the specimen to be the test strip T1.
The specimen is not limited to the test strip T1 but may be
provided as a biosensor when the one-side terminal T1a and the
different-side terminal T1b are included. A measurement target such
as a blood-sugar level is measured by using the test strip T1 as a
specimen. The test strip T1 includes a sensor whose electrode is
coated with enzyme. The impedance of the test strip T1 changes when
a drop of blood is applied to the electrode of the test strip T1.
The change in the impedance is used to measure a reaction between
the enzyme and the blood.
[0037] Specifically, a voltage is applied between the one-side
terminal T1a and the different-side terminal T1b of the test strip
T1 having the electrode to which a drop of blood is applied. An
electric charge is then generated, allowing an electric current to
flow. A charge amount is measured from a total amount of the
current. A blood-sugar level correlated with the charge amount is
thereby measured.
[0038] The one-side terminal T1a of the test strip T1 is coupled to
the resistance R1. The one-side terminal T1a of test strip T1 is
coupled to the negative input terminal of the operational amplifier
AMP1. The one-side terminal T1a of the test strip T1 is coupled to
a contact point P1 along a wiring that couples the resistance R1
with the negative input terminal of the operational amplifier AMP1.
The different-side terminal T1b of the test strip T1 is
grounded.
[0039] Operation of the impedance measuring semiconductor circuit
100 will be described. The D/A converter DAC1 is forced to input a
predetermined voltage to the positive input terminal of the
operational amplifier AMP1. A voltage is thereby applied to the
test strip T1. For example, a voltage of several hundreds of
millivolts to several volts is applied between both terminals of
the test strip T1. A current It1 of several hundreds of
microamperes then flows through the test strip T1.
[0040] FIG. 2 is a graph illustrating a current flowing through the
test strip T1 using the impedance measuring semiconductor circuit,
in which the horizontal axis represents the time and the vertical
axis represents a current. As illustrated in FIG. 2, applying a
predetermined voltage between both terminals of the test strip T1
generates a charge at the test strip, allowing the current It1 to
flow. The current It1 increases as the time elapses. The total
amount of generated charge is found from values of integral for the
current It1 during a predetermined time period. A blood-sugar level
correlated to the total amount of charge is calculated.
[0041] The current It1 flowing through the test strip T1 is equal
to the current Ir1 flowing through resistance R1. It is therefore
possible to measure the current It1 flowing through the test strip
T1 by measuring the current Ir1 flowing through resistance R1.
Measuring a current flowing through the resistance R1 requires
measuring a voltage Vr1 applied to both ends of the resistance R1.
The voltage Vr1 applied to both ends of the resistance R1 is
measured by measuring an output voltage from the operational
amplifier AMP1 using the A/D converter ADC. The current It1 flowing
through the test strip T1 can be found by dividing the measured
voltage Vr1 by a known resistance value of the resistance R1.
[0042] Varying a voltage applied between both terminals of the test
strip T1 can vary the magnitude and the direction of the current
It1 flowing through the test strip T1. It is therefore possible to
measure various parameters such as hematocrit values as well as
blood-sugar levels. A voltage at the one-side terminal T1a is
referred to as a one-side terminal voltage Vt1a. A voltage at the
different-side terminal T1b is referred to as a different-side
terminal voltage Vt1b. A voltage applied between both terminals of
the test strip T1 is referred to as a terminal-to-terminal voltage
Vt1. When the different-side terminal T1b is grounded, the
terminal-to-terminal voltage Vt1 is equal to the one-side terminal
voltage Vt1a.
[0043] FIG. 3 is a circuit diagram illustrating a configuration to
measure a plurality of test strips using the impedance measuring
semiconductor circuit according to the comparative example. When
there is a plurality of test strips T1 and T2 as illustrated in
FIG. 3, the test strips T1 and T2 are provided for the impedance
measuring semiconductor circuit 100. The analog switches SW1 and
SW2 are coupled to the test strips T1 and T2. The analog switch is
also simply referred to as a switch.
[0044] Specifically, the one-side terminal T1a of the test strip T1
is coupled to the resistance R1 and the negative input terminal of
the operational amplifier AMP1 via the switch SW1. The switch SW1
is coupled between the one-side terminal T1a of the test strip T1
and the contact point P1. The switch SW1 is therefore placed
between the one-side terminal T1a of the test strip T1 and the
negative input terminal. The different-side terminal T1b of the
test strip T1 is grounded.
[0045] The one-side terminal T2a of the test strip T2 is coupled to
the resistance R1 and the negative input terminal of the
operational amplifier AMP1 via the switch SW2. The switch SW2 is
coupled between the one-side terminal T2a of the test strip T2 and
the contact point P1. The switch SW2 is therefore placed between
the one-side terminal T2a of the test strip T2 and the negative
input terminal. The different terminal T2b of the test strip T2 is
grounded. As for the rest, the operational amplifier AMP1, the D/A
converter DAC1, the feedback resistance R1, and the A/D converter
ADC are configured similarly to those in FIG. 1.
[0046] Each of the test strips T1 and T2 is measured by selecting
each of the switches SW1 and SW2. Measuring the test strip T1
requires turning on the switch SW1 and turning off the switch SW2.
A current flowing through the resistance R1 is measured by
measuring the voltage Vr1 applied to both ends of the resistance
R1. As above, the current It1 flowing through the test strip T1 is
measured.
[0047] Measuring the test strip T2 requires turning on the switch
SW2 and turning off the switch SW1. A current flowing through the
resistance R1 is measured by measuring the voltage Vr1 applied to
both ends of the resistance R1. As above, the current It2 flowing
through the test strip T2 is measured.
[0048] When the current It1 and the current It2 are measured, the
voltage Vr1 applied to both ends of the resistance R1 contains a
voltage applied to both ends of the switches SW1 and SW2 in
addition to the terminal-to-terminal voltages Vt1 and Vt2 for the
test strip T1 and the test strip T2. Therefore, accurately
measuring the currents It1 and It2 flowing through the test strip
T1 and the test strip T2 needs to take into account a voltage drop
due to an on-resistance of the switches SW1 and SW2.
[0049] An available method of taking into account an on-resistance
of the switches SW1 and SW2 is to couple a highly accurate
resistance having a highly accurately measured resistance value
instead of the test strips T1 and T2 for measurement and
calibration. However, this method provides the calibration based on
a predetermined resistance value. Accurate calibration is therefore
difficult even when the method is applied to a case where the
currents It1 and It2 flowing through the test strips T1 and T2 vary
and the impedance of the test strips T1 and T2 varies.
[0050] As above, measuring the test strips T1 and T2 requires the
switches SW1 and SW2 to select each of the test strips T1 and T2.
However, the resistance component of the switch SW1, for example,
causes a measurement error. There is a variation in the resistance
of the switch SW1, for example. Measuring the test strip T1, for
example, includes the varied resistance of the switch SW1, for
example.
[0051] Therefore, ideally, the resistance of the switch SW1, for
example, favorably approximates to zero ohms. At least one of the
operational amplifier AMP1, the A/D converter ADC, the D/A
converter DAC1, and the switch SW1, for example, is formed to
include the CMOS structure formed over a semiconductor substrate.
Accordingly, the switch SW1, for example, is also formed in
accordance with a CMOS fabrication process. It is necessary to
increase an area occupied by the switch SW1, for example, over a
chip in order to provide the switch SW1, for example, having the
resistance approximate to zero ohms by using the CMOS fabrication
process. In this case, the chip size cannot be reduced.
[0052] Increasing measurement targets in addition to the
blood-sugar level complicates the measurement. The number of the
switches SW1, for example, increases accordingly. Therefore, the
chip size further increases.
[0053] Therefore, there is a demand for the impedance measuring
semiconductor circuit capable of improving the accuracy of
measuring the impedance of the test strip T1, for example, reducing
an area in the chip, and reducing the chip size.
First Embodiment
[0054] The description below explains the impedance measuring
semiconductor circuit according to the first embodiment. The
impedance measuring semiconductor circuit according to the present
embodiment can improve the accuracy of measuring the impedance of a
specimen, reduce an area in the chip, and reduce the chip size.
[0055] (Configuration of the Impedance Measuring Semiconductor
Circuit)
[0056] The configuration of the impedance measuring semiconductor
circuit according to the present embodiment will be first
described. Operation of the impedance measuring semiconductor
circuit will be then described. FIG. 4 is a circuit diagram
illustrating the configuration of the impedance measuring
semiconductor circuit according to the first embodiment.
[0057] As illustrated in FIG. 4, an impedance measuring
semiconductor circuit 1 includes the operational amplifier AMP1,
the D/A converter DAC1, the feedback resistance R1, the A/D
converter ADC, the switches SW1 and SW2, and a controller 10. The
impedance measuring semiconductor circuit 1 may include an
operation part that calculates a blood-sugar level from the
measured impedance. The impedance measuring semiconductor circuit 1
measures the impedance of a specimen. The impedance measuring
semiconductor circuit 1 will be described by using an analog
front-end as an example. The impedance measuring semiconductor
circuit 1 may be formed over a semiconductor substrate
(semiconductor chip) such as monocrystalline silicon by using the
CMOS fabrication process.
[0058] The operational amplifier AMP1 includes the positive input
terminal, the negative input terminal, and the output terminal. The
operational amplifier AMP1 outputs output voltage Vamp1o from the
output terminal by using positive input voltage Vamp1p input to the
positive input terminal and negative input voltage Vamp1n input to
the negative input terminal. The D/A converter DAC1 is coupled to
the positive input terminal of the operational amplifier AMP1. One
end of the resistance R1 is coupled to the negative input terminal
of the operational amplifier AMP1. The other end of the resistance
R1 is coupled to the output terminal of the operational amplifier
AMP1. The A/D converter ADC is coupled to the output terminal of
the operational amplifier AMP1.
[0059] The resistance R1 is coupled between the negative input
terminal of the operational amplifier AMP1 and the output terminal
of the operational amplifier AMP1. The resistance R1 is provided as
a feedback resistance for the operational amplifier AMP1.
[0060] The D/A converter DAC1 is coupled to the positive input
terminal of the operational amplifier AMP1. The controller 10
controls an output voltage from the D/A converter DAC1. Under
control of the controller 10, the D/A converter DAC1 outputs a
predetermined voltage to the positive input terminal of the
operational amplifier AMP1.
[0061] The A/D converter ADC is coupled to the output terminal of
the operational amplifier AMP1. The A/D converter ADC measures an
output voltage from the operational amplifier AMP1. The A/D
converter ADC transmits information about the measured output
voltage from the operational amplifier AMP1 to the controller
10.
[0062] The A/D converter ADC is coupled with one-side terminal T1a
of each test strip T1, for example. The A/D converter ADC thereby
measures the one-side terminal voltage Vt1a at one-side terminal
T1a of each test strip T1, for example. The A/D converter ADC
transmits information about the measured one-side terminal voltage
Vt1a of each test strip T1, for example, to the controller 10.
[0063] The test strip T1, for example, is assumed to be a
measurement target. The test strip T1, for example, includes the
one-side terminal T1a and the different-side terminal T1b, for
example. The use of the test strip T1, for example, can measure a
blood-sugar level, for example. Configurations of the test strips
T1 and T2 are similar to those described above.
[0064] The one-side terminal T1a of the test strip T1 is coupled to
the resistance R1 via the switch SW1. The one-side terminal T1a of
the test strip T1 is coupled to the negative input terminal of the
operational amplifier AMP1 via the switch SW1.
[0065] The one-side terminal T1a of the test strip T1 is coupled,
via the switch SW1, to the contact point P1 along the wiring that
couples the resistance R1 with the negative input terminal of the
operational amplifier AMP1. Namely, the switch SW1 is provided
between the one-side terminal T1a and the contact point P1. The
switch SW1 is therefore provided between the one-side terminal T1a
of the test strip T1 and the negative input terminal.
[0066] The one-side terminal T1a of the test strip T1 is coupled to
the A/D converter ADC. The switch SW1 is provided between the
contact point P1 and the contact point Q1 along a wiring that
couples the one-side terminal T1a of the test strip T1 with the A/D
converter ADC. The different-side terminal T1b of the test strip T1
is grounded. The different-side terminal voltage Vt1b is thereby
set to a predetermined voltage.
[0067] The one-side terminal T2a of the test strip T2 is coupled to
the resistance R1 via the switch SW2. The one-side terminal T2a of
the test strip T2 is coupled to the negative input terminal of the
operational amplifier AMP1 via the switch SW2.
[0068] The one-side terminal T2a of the test strip T2 is coupled,
via the switch SW2, to the contact point P1 along the wiring that
couples the resistance R1 with the negative input terminal of the
operational amplifier AMP1. Namely, the switch SW2 is provided
between the one-side terminal T2a and the contact point P1. The
switch SW2 is therefore provided between the one-side terminal T2a
of the test strip T2 and the negative input terminal.
[0069] The one-side terminal T2a of the test strip T2 is coupled to
the A/D converter ADC. The switch SW2 is provided between the
contact point P1 and the contact point Q2 along the wiring that
couples the one-side terminal T2a of the test strip T2 with the A/D
converter ADC. The different-side terminal T2b of the test strip T2
is grounded. The different-side terminal voltage Vt2b is thereby
set to a predetermined voltage.
[0070] The controller 10 controls an output voltage from the D/A
converter DAC1 based on the one-side terminal voltages Vt1a and
Vt2a measured by the A/D converter ADC at the test strips T1 and
T2. For example, the controller 10 controls the D/A converter DAC1
so that the one-side terminal voltage Vt1a of the test strip T1,
for example, reaches a predetermined target value Vtarget. The
predetermined target value Vtarget is to be applied to a
measurement target such as the test strip T1, for example. A
negative input voltage and a positive input voltage to the
operational amplifier AMP1 increase by a voltage drop due to the
on-resistance of the switch SW1. However, as will be described
below, a voltage corresponding to the predetermined target value
Vtarget can be applied between both terminals of the test strip T1,
for example. A control method for the controller 10 may use a
special-purpose sequencer or a microcomputer.
[0071] (Operation of the Impedance Measuring Semiconductor
Circuit)
[0072] The description below explains operation of the impedance
measuring semiconductor circuit 1. FIG. 5 is a flowchart
illustrating operation of the impedance measuring semiconductor
circuit according to the first embodiment. In FIG. 5, the test
strip T1 is used as a specimen to measure impedance and a
blood-sugar level of the test strip T1. The switch SW1 is therefore
coupled as being turned on and the other switch is not coupled as
being turned off. A similar method can be used to measure, for
example, impedance of other specimens than the test strip T1.
[0073] At step S11 in FIG. 5, the controller 10 sets an initial
value for an output voltage from the D/A converter DAC1. The
initial value corresponds to the target value Vtarget applied to
the test strip T1.
[0074] At step S12, the controller 10 controls the D/A converter
DAC1 to output the initial value set for the D/A converter DAC1.
The D/A converter DAC1 thereby outputs the initial value to the
positive output terminal of the operational amplifier AMP1. Virtual
ground for the operational amplifier AMP1 then causes the test
strip T1 to be applied with a differential voltage between the
output voltage from the D/A converter DAC1 and GND.
[0075] The initial value for the DAC1 is applied between the test
strip T1 and the switch SW1 before a current flows through the test
strip T1. The one-side terminal voltage measured by the A/D
converter ADC at the test strip T1 is comparable to the output
voltage from the D/A converter DAC1.
[0076] Immediately after that, as illustrated in FIG. 2, the
current starts flowing between the test strip T1 and the switch
SW1. A voltage drop thereby occurs due to the on-resistance of the
switch SW1. The test strip T1 is therefore applied with a voltage
acquired by subtracting the voltage drop for the switch SW1 from
the output voltage of the D/A converter DAC1. The A/D converter ADC
measures the one-side terminal voltage Vt1a at the test strip
T1.
[0077] At step S13, the controller 10 acquires the one-side
terminal voltage Vt1a of the test strip T1 from the A/D converter
ADC.
[0078] At step S14, the controller 10 determines whether the
acquired one-side terminal voltage Vt1a is lower than the target
value Vtarget. The one-side terminal voltage Vt1a may be lower than
the predetermined target value Vtarget (Yes). In this case, at step
S15, the controller 10 provides control to increase the setup value
for the D/A converter DAC1. The output voltage from the D/A
converter DAC1 is thereby increased.
[0079] At step S14, the one-side terminal voltage Vt1a may be
higher than or equal to the target value Vtarget (No). In this
case, at step S16, the controller 10 provides control to decrease
the setup value for the D/A converter DAC1. The output voltage from
the D/A converter DAC1 is thereby decreased.
[0080] Suppose the one-side terminal voltage Vt1a is confirmed to
fall within a predetermined voltage setup range. At step S17, the
controller 10 then uses the A/D converter ADC to acquire the output
voltage Vamp1o from the operational amplifier AMP1. The impedance
measuring semiconductor circuit 1 measures the impedance of the
test strip T1 by using the output voltage Vamp1o from the
operational amplifier AMP1.
[0081] At step S18, the controller 10 determines whether the
measurement is performed for a specified number of times. When the
measurement is not performed for a specified number of times (No),
the process returns to step S13 and acquires the one-side terminal
voltage Vt1a of the test strip T1 by using the A/D converter ADC.
The process is repeated from step S13 to step S18. Repeating the
process at a specified interval can approximate the one-side
terminal voltage Vt1a of the test strip to the target value
Vtarget.
[0082] When the measurement is performed for a specified number of
times (Yes), the process proceeds to step S19 and calculates the
blood-sugar level. For example, the operation part 20 calculates
the blood-sugar level correlated to the charge amount based on the
graph as illustrated in FIG. 2. The process then terminates. As
above, the impedance measuring semiconductor circuit 1 measures the
impedance of the test strip T1 as a specimen.
[0083] FIG. 6 is a graph illustrating operation of the impedance
measuring semiconductor circuit according to the first embodiment,
in which the horizontal axis represents the time and the vertical
axis represents a voltage at one-side terminal of a test strip.
FIG. 7 is a graph illustrating operation of the impedance measuring
semiconductor circuit according to the first embodiment, in which
the horizontal axis represents the time and the vertical axis
represents a current flowing through a test strip.
[0084] Measuring a blood-sugar level at the test strip T1 may
require measuring other substances such as a hematocrit value in
order to correct the measured blood-sugar level. In order to
measure such a different substance, a voltage applied to the test
strip T1 is varied stepwise and corresponding values are
measured.
[0085] As illustrated in FIGS. 6 and 7, for example, the
blood-sugar level measurement uses the one-side terminal voltage
Vt1a set to +0.5 [V] as a target value. In this case, a current of
+100 [.mu.A] flows through the test strip T1. The hematocrit value
measurement uses the one-side terminal voltage Vt1a set to +2.0 [V]
as a target value. In this case, a current of +400 [.mu.A] flows
through the test strip T1.
[0086] The present embodiment can versatilely control the magnitude
of the one-side terminal voltage Vt1a for the test strip T1 and is
therefore applicable to a case where a voltage to be applied varies
with a substance or enzyme to be measured.
[0087] The switch SW1 is then turned off and the switch SW2 for the
test strip T2 is turned on. The same method is used to continue
measuring the test strip T2. There is no limitation on a sequence
of measuring the test strips. The test strip T1 may be measured
after the test strip T2, or otherwise. The measurement terminates
when the measurement of the targeted test strip terminates.
[0088] An effect of the impedance measuring semiconductor circuit 1
will be described.
[0089] The controller 10 of the impedance measuring semiconductor
circuit 1 according to the present embodiment controls an output
voltage from the D/A converter DAC1 coupled to the positive input
terminal of the operational amplifier AMP1 based on the one-side
terminal voltage Vt1a for the test strip T1 acquired from the A/D
converter ADC. The one-side terminal voltage Vt1a for the test
strip T1 can be accurately used as the target value Vtarget. It is
therefore possible to improve the accuracy of measuring the
impedance of the test strip T1.
[0090] The impedance measuring semiconductor circuit 1 according to
the present embodiment can suppress an effect of voltage drop due
to the on-resistance of the switch SW1. It is therefore possible to
decrease an area of the switch SW1 inversely proportional to the
square of the on-resistance of the switch SW1. The chip size can be
thereby decreased.
[0091] For example, the current It1 of 100 [.mu.A] flows through
the test strip T1 when a voltage of 0.5 [V] is applied between both
terminals of the test strip T1. In this case, supposing that the
measurement error to be 0.1[%], the on-resistance value Rsw1
allowed for the switch SW1 is then calculated as
Rsw1=0.5/0.0001.times.0.001=5 [.OMEGA.]. The size of the switch
SW1, for example, is equal to several hundreds of square
micrometers per switch. This area greatly affects on the chip size.
Increasing the measurement target and the number of switches
further increases an effect on the chip size.
[0092] However, the present embodiment can suppress an effect of
voltage drop due to the on-resistance of the switch SW1, for
example. The chip size can be reduced without the need to decrease
the on-resistance of the switch SW1, for example.
Second Embodiment
[0093] The impedance measuring semiconductor circuit according to
the second embodiment will be described. The impedance measuring
semiconductor circuit according to the present embodiment provides
an example of using n (three or more) test strips T1. FIG. 8 is a
circuit diagram illustrating a configuration of the impedance
measuring semiconductor circuit according to the second
embodiment.
[0094] As illustrated in FIG. 8, an impedance measuring
semiconductor circuit 2 includes n test strips T1 through Tn. Each
of the n test strips T1 through Tn is coupled to the contact point
P1 via the switches SW1 through SWn. The impedance measuring
semiconductor circuit 2 is provided with a plurality of test strips
T1 as specimens. The switch SW1, for example, is placed between the
one-side terminal of each measurement target and the negative input
terminal.
[0095] Specifically, for example, one-side terminal Tna of the nth
test strip Tn out of the test strips T1 through Tn is coupled to
the resistance R1 via the switch SWn. The one-side terminal Tna of
the test strip Tn is coupled to the negative input terminal of the
operational amplifier AMP1 via the switch SWn.
[0096] The one-side terminal Tna of the test strip Tn is coupled,
via the switch SWn, to the contact point P1 along the wiring that
couples the resistance R1 with the negative input terminal of the
operational amplifier AMP1. Namely, the switch SWn is provided
between the one-side terminal Tna and the contact point P1.
[0097] The one-side terminal Tna of the test strip Tn is coupled to
the A/D converter ADC. The switch SWn is provided between the
contact point P1 and a contact point Qn along a wiring that couples
the one-side terminal Tna of the test strip Tn with the A/D
converter ADC. A different-side terminal Tnb of the test strip Tn
is grounded. The other configurations are equal to the first
embodiment.
[0098] The operation of the impedance measuring semiconductor
circuit 2 is equal to that of the first embodiment except that the
impedance measuring semiconductor circuit 2 repeatedly performs the
operation of the impedance measuring semiconductor circuit 1
illustrated in FIG. 5 on each of the n test strips Tn.
[0099] An effect of the impedance measuring semiconductor circuit 2
according to the second embodiment will be described. The impedance
measuring semiconductor circuit 2 includes switch SWn corresponding
to each of the n test strips Tn. It is therefore possible to
perform complicated measurement containing more types and items,
for example. It is also possible to perform accurate measurement on
a current flowing through each path for the test strip Tn
regardless of on-resistance values of the switch SWn.
[0100] It is possible to reduce an area in the chip occupied by the
n switches SWn corresponding to the n test strips Tn, for example.
The effect of reducing the chip size is more remarkable. The other
configurations and effects are contained in the description of the
first embodiment.
Third Embodiment
[0101] The impedance measuring semiconductor circuit according to
the third embodiment will be described. The impedance measuring
semiconductor circuit according to the present embodiment provides
an example of reversing the direction of a current flowing through
the test strips T1 and T2, for example. FIG. 9 is a circuit diagram
illustrating a configuration of the impedance measuring
semiconductor circuit according to the third embodiment.
[0102] As illustrated in FIG. 9, an impedance measuring
semiconductor circuit 3 according to the present embodiment further
includes a buffer amplifier AMP2. The buffer amplifier AMP2
includes a positive input terminal, a negative input terminal, and
an output terminal. The output terminal of the buffer amplifier
AMP2 is coupled to the negative input terminal of the buffer
amplifier. A reference voltage is input to the positive input
terminal of the buffer amplifier. For example, a reference voltage
generator generates a reference voltage Vref1.
[0103] In the impedance measuring semiconductor circuit 3 according
to the present embodiment, the different-side terminals T1b and T2b
of the test strips T1 and T2 are coupled to the output terminal of
the buffer amplifier AMP2. The different-side terminal voltages
Vt1b and Vt2b of the impedance measuring semiconductor circuit 3
are coupled to the output terminal of the buffer amplifier AMP2 and
thereby remain constant. For example, the different-side terminal
voltages Vt1b and Vt2b of the test strips T1 and T2 are set to the
reference voltage Vref1 by using the buffer amplifier AMP2.
[0104] The controller 10 controls the D/A converter DAC1 so that
the one-side terminal voltages Vt1a and Vt2a of the test strips T1
and T2 are lower than the different-side terminal voltages Vt1b and
Vt2b. This allows the direction of a current flowing through the
test strips T1 and T2 to be contrary to the first embodiment. For
example, the direction of the current is configured so that the
current flows from the different-side terminals T1b and T2b to the
one-side terminals T1a and T2a.
[0105] As in the first embodiment, the direction of a current
flowing from the one-side terminals T1a and T2a to the
different-side terminals T1b and T2b is defined as direction A. The
direction of a current flowing from the different-side terminals
T1b and T2b to the one-side terminals T1a and T2a is defined as
direction B.
[0106] The description below explains operation of the impedance
measuring semiconductor circuit 3 according to the third
embodiment. The operation of the impedance measuring semiconductor
circuit 3 differs from the operation of the impedance measuring
semiconductor circuit 1 only in the direction of a current. A
method of finding a blood-sugar level from the impedance can be
therefore found based on the flowchart at step S11 through step S19
illustrated in FIG. 5.
[0107] An effect of the impedance measuring semiconductor circuit 3
according to the third embodiment will be described. The present
embodiment can allow the direction of a current flowing through the
test strips T1 and T2 to be contrary to the above-mentioned first
and second embodiments. Similarly to the first embodiment, even the
reverse current direction can also perform accurate measurement
regardless of the on-resistance of the switches SW1 and SW2, for
example.
[0108] For example, direction A as the current direction can
measure oxidation reaction at an electrode. Direction B can measure
reduction reaction. The measurement can be applied to various types
of reaction of the test strips T1 and T2, for example. Even during
the measurement of various types of reaction, a measurement target
can be highly accurately measured regardless of the on-resistance
of the switches SW1 and SW2. The relation between the current
direction and the oxidation reaction or the reduction reaction is
not unchangeable. The other configurations and effects are included
in the description of the first and second embodiments
Fourth Embodiment
[0109] The impedance measuring semiconductor circuit according to
the fourth embodiment will be described. The impedance measuring
semiconductor circuit according to the present embodiment controls
voltages at both ends of the test strips T1 and T2.
[0110] FIG. 10 is a circuit diagram illustrating a configuration of
the impedance measuring semiconductor circuit according to the
fourth embodiment. As illustrated in FIG. 10, an impedance
measuring semiconductor circuit 4 according to the present
embodiment includes the operational amplifier AMP1, the buffer
amplifier AMP2, a first D/A converter DAC1, a second D/A converter
DAC2, the feedback resistance R1, the A/D converter ADC, the
switches SW1 and SW2, and the controller 10.
[0111] The impedance measuring semiconductor circuit 4 according to
the present embodiment differs from the impedance measuring
semiconductor circuit 3 according to the third embodiment in the
positive input terminal side of the buffer amplifier AMP2. Namely,
the second D/A converter DAC2 is coupled to the positive input
terminal of the buffer amplifier AMP2. An output voltage from the
second D/A converter DAC2 is input instead of the reference voltage
Vref1 as input. The D/A converter DAC1 coupled to the positive
input terminal of the operational amplifier AMP1 is referred to as
the first D/A converter DAC1.
[0112] The controller 10 controls at least one of an output voltage
from the first D/A converter DAC1 and an output voltage from the
second D/A converter DAC2 based on the terminal-to-terminal
voltages Vt1 and Vt2 calculated by using the one-side terminal
voltages Vt1a and Vt2a measured by the A/D converter ADC at the
test strips T1 and T2.
[0113] Alternatively, the controller 10 controls the first D/A
converter DAC1 and the second D/A converter DAC2 so that the
one-side terminal voltages Vt1a and Vt2a of the test strips T1 and
T2 are higher than the different-side terminal voltages Vt1b and
Vt2b. The direction of a current flowing through the test strips T1
and T2 is thereby selected as direction A that allows the current
to flow from the one-side terminals T1a and T2a to the
different-side terminals T1b and T2b.
[0114] The controller 10 further controls the first D/A converter
DAC1 and the second D/A converter DAC2 so that the one-side
terminal voltages Vt1a and Vt2a of the test strips T1 and T2 are
lower than the different-side terminal voltages Vt1b and Vt2b. The
direction of a current flowing through the test strips T1 and T2 is
thereby selected as direction B that allows the current to flow
from the different-side terminals T1b and T2b to the one-side
terminals T1a and T2a.
[0115] Configurations of the A/D converter ADC and the switches SW1
and SW2 are similar to those of the third embodiment.
[0116] The description below explains operation of the impedance
measuring semiconductor circuit 4 according to the fourth
embodiment. FIG. 11 is a diagram illustrating operation of the
impedance measuring semiconductor circuit 4 according to the fourth
embodiment. As illustrated in FIG. 11, the operation of the
impedance measuring semiconductor circuit 4 will be described
according to a first case, a second case, a third case, and a
fourth case. The first case uses direction A as the current
direction and adjusts the first D/A converter DAC1 to thereby
provide control so that the terminal-to-terminal voltage Vt1
approximates to the target value Vtarget. The second case uses
direction B as the current direction and adjusts the first D/A
converter DAC1 to thereby provide control so that the
terminal-to-terminal voltage Vt1 approximates to the target value
Vtarget. The third case uses direction A as the current direction
and adjusts the second D/A converter DAC2 to thereby provide
control so that the terminal-to-terminal voltage Vt1 approximates
to the target value Vtarget. The fourth case uses direction B as
the current direction and adjusts the second D/A converter DAC2 to
thereby provide control so that the terminal-to-terminal voltage
Vt1 approximates to the target value Vtarget. The first case will
be described first.
[0117] FIG. 12 is a flowchart illustrating operation of the
impedance measuring semiconductor circuit according to the fourth
embodiment in the first case. The test strip T1 is used as a
specimen. The same applies to the other specimens than the test
strip T1.
[0118] At step S21 in FIG. 12, the controller 10 sets initial
values for output voltages from the first D/A converter DAC1 and
the second D/A converter DAC2. A potential difference between the
initial value for the first D/A converter DAC1 and the initial
value for the second D/A converter DAC2 corresponds to the target
value Vtarget to be applied to the test strip T1.
[0119] At step S22, the controller 10 controls the first D/A
converter DAC1 to output the initial value set for the first D/A
converter DAC1. The controller 10 controls the second D/A converter
DAC2 to output the initial value set for the second D/A converter
DAC2.
[0120] The first D/A converter DAC1 thereby outputs the initial
value to the positive output terminal of the operational amplifier
AMP1. The second D/A converter DAC2 outputs the initial value to
the positive output terminal of the buffer amplifier AMP2.
[0121] The virtual ground of the operational amplifier AMP1
supplies the test strip T1 with a differential voltage between the
output voltage from the first D/A converter DAC1 and the output
voltage from the second D/A converter DAC2.
[0122] In the first case, the controller 10 controls at least one
of the first D/A converter DAC1 and the second D/A converter DAC2
so that the one-side terminal voltage Vt1a is higher than the
different-side terminal voltage Vt1b. The current direction is then
selected as direction A from the one-side terminal T1a to the
different-side terminal T1b. In the first case, the controller 10
favorably controls the first D/A converter DAC1 so that the
one-side terminal voltage Vt1a is higher than the different-side
terminal voltage Vt1b. Only the first D/A converter DAC1 needs to
be controlled and the control is facilitated.
[0123] Before a current flows through the test strip T1, a
differential voltage between the initial value for the first D/A
converter DAC1 and the initial value for the second D/A converter
DAC2 is applied between the test strip T1 and the switch SW1.
[0124] Immediately after that, a current starts to flow between the
test strip T1 and the switch SW1. This causes a voltage drop due to
the on-resistance of the switch SW1. The test strip T1 is therefore
applied with a voltage acquired by subtracting the voltage drop at
the switch SW1 from the differential voltage between the first and
second D/A converters DAC1 and DAC2. The A/D converter ADC measures
the one-side terminal voltage Vt1a of the test strip T1.
[0125] At step S23, the controller 10 acquires the
terminal-to-terminal voltage Vt1 of the test strip T1. For example,
the controller 10 calculates the terminal-to-terminal voltage Vt1
by using the one-side terminal voltage Vt1a measured by the A/D
converter ADC and the output voltage from the second D/A converter
DAC2.
[0126] At step S24, the controller 10 determines whether the
acquired terminal-to-terminal voltage Vt1 is lower than the target
value Vtarget. The terminal-to-terminal voltage Vt1 may be lower
than the target value Vtarget (Yes). In this case, at step S25 and
as illustrated in FIG. 11, the controller 10 controls the first D/A
converter DAC1 so as to increase the setup value for the first D/A
converter DAC1. The output voltage from the first D/A converter
DAC1 is thereby increased.
[0127] At step S24, the terminal-to-terminal voltage Vt1 may be
higher than or equal to the target value Vtarget (No). In this
case, at step S26 and as illustrated in FIG. 11, the controller 10
controls the first D/A converter DAC1 so as to decrease the setup
value for the first D/A converter DAC1. The output voltage from the
first D/A converter DAC1 is thereby decreased.
[0128] At step S27, the controller 10 uses the A/D converter ADC to
acquire the output voltage Vamp1o from the operational amplifier
AMP1. The impedance measuring semiconductor circuit 4 measures the
impedance of the specimen by using the output voltage Vamp1o from
the operational amplifier AMP1.
[0129] At step S28, the controller 10 determines whether the
measurement is performed for a specified number of times. When the
measurement is not performed for a specified number of times (No),
the process returns to step S23 and uses the A/D converter ADC to
acquire the terminal-to-terminal voltage Vt1 of the test strip T1.
The process is repeated from step S23 to step S28. Repeating the
process at a specified interval can approximate the
terminal-to-terminal voltage Vt1 applied to both ends of the test
strip T1 to the target value Vtarget.
[0130] At step S28, the measurement may be performed for a
specified number of times (Yes). In this case, the process proceeds
to step S29 and calculates a blood-sugar level. For example, the
operation part 20 calculates the blood-sugar level correlated to
the charge amount based on the graph as illustrated in FIG. 2. The
process then restarts from step S21 when there is a need to measure
other quantities such as a hematocrit value at the test strip T1.
When the measurement on the test strip T1 terminates, the switch
SW1 is turned off and the switch SW for a test strip other than the
test strip T1 is turned on to continue measuring the test strip. A
sequence of measuring test strips is not limited. The test strip T1
may be measured after measurement of a test strip other than the
test strip T1. The other sequences may also be available.
[0131] The description below explains operation of the impedance
measuring semiconductor circuit according to the fourth embodiment
in the second case. FIG. 13 is a flowchart illustrating the
operation of the impedance measuring semiconductor circuit
according to the fourth embodiment in the second case. The test
strip T1 is used as a specimen. The same applies to the other
specimens than the test strip T1.
[0132] At step S31 in FIG. 13, the controller 10 sets initial
values for output voltages from the first D/A converter DAC1 and
the second D/A converter DAC2. A potential difference between the
initial value for the first D/A converter DAC1 and the initial
value for the second D/A converter DAC2 corresponds to the target
value Vtarget to be applied to the test strip T1.
[0133] At step S32, the controller 10 controls the first D/A
converter DAC1 to output the initial value set for the first D/A
converter DAC1. The controller 10 controls the second D/A converter
DAC2 to output the initial value set for the second D/A converter
DAC2.
[0134] The first D/A converter DAC1 thereby outputs the initial
value to the positive output terminal of the operational amplifier
AMP1. The second D/A converter DAC2 outputs the initial value to
the positive output terminal of the buffer amplifier AMP2.
[0135] The virtual ground of the operational amplifier AMP1
supplies the test strip T1 with a differential voltage between the
output voltage from the first D/A converter DAC1 and the output
voltage from the second D/A converter DAC2.
[0136] In the second case, the controller 10 controls at least one
of the first D/A converter DAC1 and the second D/A converter DAC2
so that the one-side terminal voltage Vt1a is lower than the
different-side terminal voltage Vt1b. The current direction is then
selected as direction B from the different-side terminal T1b to the
one-side terminal T1a. In the second case, the controller 10
favorably controls the first D/A converter DAC1 so that the
one-side terminal voltage Vt1a is lower than the different-side
terminal voltage Vt1b. Only the first D/A converter DAC1 needs to
be controlled and the control is facilitated.
[0137] A current starts to flow between the test strip T1 and the
switch SW1, and then a voltage drop occurs due to the on-resistance
of the switch SW1. The test strip T1 is therefore applied with a
voltage acquired by subtracting the voltage drop at the switch SW1
from the differential voltage between the first and second D/A
converters DAC1 and DAC2. The A/D converter ADC measures the
one-side terminal voltage Vt1a of the test strip T1.
[0138] At step S33, the controller 10 acquires the
terminal-to-terminal voltage Vt1 of the test strip T1. For example,
the controller 10 calculates the terminal-to-terminal voltage Vt1
by using the one-side terminal voltage Vt1a measured by the A/D
converter ADC and the output voltage from the second D/A converter
DAC2.
[0139] At step S34, the controller 10 determines whether the
acquired terminal-to-terminal voltage Vt1 is lower than the target
value Vtarget. The terminal-to-terminal voltage Vt1 may be lower
than the target value Vtarget (Yes). In this case, at step S35 and
as illustrated in FIG. 11, the controller 10 controls the first D/A
converter DAC1 so as to decrease the setup value for the first D/A
converter DAC1. The output voltage from the first D/A converter
DAC1 is thereby decreased.
[0140] At step S34, the terminal-to-terminal voltage Vt1 may be
higher than or equal to the target value Vtarget (No). In this
case, at step S36 and as illustrated in FIG. 11, the controller 10
controls the first D/A converter DAC1 so as to increase the setup
value for the first D/A converter DAC1. The output voltage from the
first D/A converter DAC1 is thereby increased. Step S37 through
step S39 are similar to step S27 through step S29 as above.
[0141] The description below explains operation of the impedance
measuring semiconductor circuit according to the fourth embodiment
in the third case. FIG. 14 is a flowchart illustrating the
operation of the impedance measuring semiconductor circuit
according to the fourth embodiment in the third case. The test
strip T1 is used as a specimen. The same applies to the other
specimens than the test strip T1.
[0142] At step S41 in FIG. 14, the controller 10 sets initial
values for output voltages from the first D/A converter DAC1 and
the second D/A converter DAC2. A potential difference between the
initial value for the first D/A converter DAC1 and the initial
value for the second D/A converter DAC2 corresponds to the target
value Vtarget to be applied to the test strip T1.
[0143] At step S42, the controller 10 controls the first D/A
converter DAC1 to output the initial value set for the first D/A
converter DAC1. The controller 10 controls the second D/A converter
DAC2 to output the initial value set for the second D/A converter
DAC2.
[0144] The first D/A converter DAC1 thereby outputs the initial
value to the positive output terminal of the operational amplifier
AMP1. The second D/A converter DAC2 outputs the initial value to
the positive output terminal of the buffer amplifier AMP2.
[0145] The virtual ground of the operational amplifier AMP1
supplies the test strip T1 with a differential voltage between the
output voltage from the first D/A converter DAC1 and the output
voltage from the second D/A converter DAC2.
[0146] In the third case, the controller 10 controls at least one
of the first D/A converter DAC1 and the second D/A converter DAC2
so that the one-side terminal voltage Vt1a is higher than the
different-side terminal voltage Vt1b. The current direction is then
selected as direction A from the one-side terminals T1a and T2a to
the different-side terminals T1b and T2b. In the third case, the
controller 10 favorably controls the second D/A converter DAC2 so
that the one-side terminal voltage Vt1a is higher than the
different-side terminal voltage Vt1b. Only the second D/A converter
DAC2 needs to be controlled and the control is facilitated.
[0147] A current starts to flow between the test strip T1 and the
switch SW1, and then a voltage drop occurs due to the on-resistance
of the switch SW1. The test strip T1 is therefore applied with a
voltage acquired by subtracting the voltage drop at the switch SW1
from the differential voltage between the first and second D/A
converters DAC1 and DAC2. The A/D converter ADC measures the
one-side terminal voltage Vt1a of the test strip T1.
[0148] At step S43, the controller 10 acquires the
terminal-to-terminal voltage Vt1 of the test strip T1. For example,
the controller 10 calculates the terminal-to-terminal voltage Vt1
by using the one-side terminal voltage Vt1a measured by the A/D
converter ADC at the test strip T1 and the output voltage from the
second D/A converter DAC2.
[0149] At step S44, the controller 10 determines whether the
acquired terminal-to-terminal voltage Vt1 is lower than the target
value Vtarget. The terminal-to-terminal voltage Vt1 maybe lower
than the target value Vtarget (Yes). In this case, at step S45 and
as illustrated in FIG. 11, the controller 10 controls the second
D/A converter DAC2 so as to decrease the setup value for the second
D/A converter DAC2. The output voltage from the second D/A
converter DAC2 is thereby decreased.
[0150] At step S44, the terminal-to-terminal voltage Vt1 may be
higher than or equal to the target value Vtarget (No). In this
case, at step S46 and as illustrated in FIG. 11, the controller 10
controls the second D/A converter DAC2 so as to increase the setup
value for the second D/A converter DAC2. The output voltage from
the second D/A converter DAC2 is thereby increased. Step S47
through step S49 are similar to step S27 through step S29 as
above.
[0151] The description below explains operation of the impedance
measuring semiconductor circuit according to the fourth embodiment
in the fourth case. FIG. 15 is a flowchart illustrating the
operation of the impedance measuring semiconductor circuit
according to the fourth embodiment in the fourth case. The test
strip T1 is used as a specimen. The same applies to the other
specimens than the test strip T1.
[0152] At step S51 in FIG. 15, the controller 10 sets initial
values for output voltages from the first D/A converter DAC1 and
the second D/A converter DAC2. A potential difference between the
initial value for the first D/A converter DAC1 and the initial
value for the second D/A converter DAC2 corresponds to the target
value Vtarget to be applied to the test strip T1.
[0153] At step S52, the controller 10 controls the first D/A
converter DAC1 to output the initial value set for the first D/A
converter DAC1. The controller 10 controls the second D/A converter
DAC2 to output the initial value set for the second D/A converter
DAC2.
[0154] The first D/A converter DAC1 thereby outputs the initial
value to the positive output terminal of the operational amplifier
AMP1. The second D/A converter DAC2 outputs the initial value to
the positive output terminal of the buffer amplifier AMP2.
[0155] The virtual ground of the operational amplifier AMP1
supplies the test strip T1 with a differential voltage between the
output voltage from the first D/A converter DAC1 and the output
voltage from the second D/A converter DAC2.
[0156] In the fourth case, the controller 10 controls at least one
of the first D/A converter DAC1 and the second D/A converter DAC2
so that the one-side terminal voltage Vt1a is lower than the
different-side terminal voltage Vt1b. The current direction is then
selected as direction B from the different-side terminal T1b to the
one-side terminal T1a. In the fourth case, the controller 10
favorably controls the second D/A converter DAC2 so that the
one-side terminal voltage Vt1a is lower than the different-side
terminal voltage Vt1b. Only the second D/A converter DAC2 needs to
be controlled and the control is facilitated.
[0157] A current starts to flow between the test strip T1 and the
switch SW1, and then a voltage drop occurs due to the on-resistance
of the switch SW1. The test strip T1 is therefore applied with a
voltage acquired by subtracting the voltage drop at the switch SW1
from the differential voltage between the first and second D/A
converters DAC1 and DAC2. The A/D converter ADC measures the
one-side terminal voltage Vt1a of the test strip T1.
[0158] At step S53, the controller 10 acquires the
terminal-to-terminal voltage Vt1 of the test strip T1. For example,
the controller 10 calculates the terminal-to-terminal voltage Vt1
by using the one-side terminal voltage Vt1a measured by the A/D
converter ADC and the output voltage from the second D/A converter
DAC2.
[0159] At step S54, the controller 10 determines whether the
acquired terminal-to-terminal voltage Vt1 is lower than the target
value Vtarget. The terminal-to-terminal voltage Vt1 may be lower
than the target value Vtarget (Yes). In this case, at step S55 and
as illustrated in FIG. 11, the controller 10 controls the second
D/A converter DAC2 so as to increase the setup value for the second
D/A converter DAC2. The output voltage from the second D/A
converter DAC2 is thereby increased.
[0160] At step S54, the terminal-to-terminal voltage Vt1 may be
higher than or equal to the target value Vtarget (No). In this
case, at step S56 and as illustrated in FIG. 11, the controller 10
controls the second D/A converter DAC2 so as to decrease the setup
value for the second D/A converter DAC2. The output voltage from
the second D/A converter DAC2 is thereby decreased. Step S57
through step S59 are similar to step S27 through step S29 as
above.
[0161] The process then terminates. As above, the impedance
measuring semiconductor circuit 1 measures the impedance of the
test strip T1 as a specimen.
[0162] FIG. 16 is a graph illustrating operation of the impedance
measuring semiconductor circuit according to the fourth embodiment,
in which the horizontal axis represents the time and the vertical
axis represents a voltage at the one-side terminal of the test
strip T1. FIG. 17 is a graph illustrating operation of the
impedance measuring semiconductor circuit according to the fourth
embodiment, in which the horizontal axis represents the time and
the vertical axis represents a current flowing through a test
strip.
[0163] The present embodiment can also measure other substances
such as a hematocrit value other than the blood-sugar level at the
test strip T1. The present embodiment can stepwise vary a voltage
applied to the test strip T1 and reverse a current.
[0164] As illustrated in FIGS. 16 and 17, for example, the
blood-sugar level measurement uses the one-side terminal voltage
Vt1a of +0.5[V] as a target value. In this case, a current of
+100[.mu.A] flows through the test strip T1. The hematocrit value
measurement uses the one-side terminal voltage Vt1a of +2.0[V] as a
target value. In this case, a current of +400[.mu.A] flows through
the test strip T1. Except blood-sugar levels and hematocrit values,
the one-side terminal voltage Vt1a of -0.5 [V] is used as a target
value. In this case, a current of -100 [.mu.A] flows through the
test strip T1.
[0165] Effects of the present embodiment will be described. The
impedance measuring semiconductor circuit 4 according to the
present embodiment can control each of the first D/A converter DAC1
and the second D/A converter DAC2. The terminal-to-terminal voltage
Vt1 applied to both ends of the test strip T1 can be therefore set
to discretionary values. It is possible to versatilely control the
magnitude and the direction of the current It1 flowing through the
test strip T1.
[0166] Voltages to be applied may vary with substances or enzyme to
be measured. There may be a case where a negative voltage is
applied. The present embodiment can versatilely control the
magnitude and the direction of the terminal-to-terminal voltage Vt1
at the test strip T1 and is therefore applicable to a case where a
voltage to be applied varies with a substance or enzyme to be
measured.
[0167] While there have been described the specific embodiments of
the invention made by the inventors, it is to be distinctly
understood that the present invention is not limited to the
above-mentioned embodiments and may be embodied in various
modifications without departing from the spirit and scope of the
invention.
[0168] For example, a blood-sugar level meter including the
impedance measuring semiconductor circuit according to the
above-mentioned embodiments also falls within the scope of the
technical idea of the embodiments. Effects of such a blood-sugar
level meter are included in the description of the first through
fourth embodiments. The above-mentioned embodiments measure the
one-side terminal voltage Vt1a and the terminal-to-terminal voltage
Vt1 of the test strip T1, for example, and control an output
voltage from the D/A converter DAC1, for example, based on the
values. Alternatively, it may be possible to detect an anomaly or
diagnose degradation of a sensor included in the test strip T1 by
measuring whether the one-side terminal voltage Vt1a and the
terminal-to-terminal voltage Vt1 of the test strip T1 being
measured, for example, exceed a predetermined threshold value.
* * * * *