U.S. patent application number 16/188237 was filed with the patent office on 2019-03-14 for method of forming semiconductor memory device with bit line contact structure.
The applicant listed for this patent is Fujian Jinhua Integrated Circuit Co., Ltd., UNITED MICROELECTRONICS CORP.. Invention is credited to Feng-Yi Chang, Ming-Feng Kuo, Fu-Che Lee, Yu-Cheng Tung, Shih-Fang Tzou.
Application Number | 20190080961 16/188237 |
Document ID | / |
Family ID | 63167920 |
Filed Date | 2019-03-14 |
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United States Patent
Application |
20190080961 |
Kind Code |
A1 |
Chang; Feng-Yi ; et
al. |
March 14, 2019 |
METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE CONTACT
STRUCTURE
Abstract
The present invention provides a method of forming a
semiconductor device. First, a substrate is provided and an STI is
forming in the substrate to define a plurality of active regions.
Then a first etching process is performed to form a bit line
contact opening, which is corresponding to one of the active
regions. A second etching process is performed to remove a part of
the active region and its adjacent STI so a top surface of active
region is higher than a top surface of the STI. Next, a bit line
contact is formed in the opening. The present invention further
provides a semiconductor structure.
Inventors: |
Chang; Feng-Yi; (Tainan
City, TW) ; Tzou; Shih-Fang; (Tainan City, TW)
; Tung; Yu-Cheng; (Kaohsiung City, TW) ; Lee;
Fu-Che; (Taichung City, TW) ; Kuo; Ming-Feng;
(Tainan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP.
Fujian Jinhua Integrated Circuit Co., Ltd. |
Hsin-Chu City
Quanzhou City |
|
TW
CN |
|
|
Family ID: |
63167920 |
Appl. No.: |
16/188237 |
Filed: |
November 12, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15472295 |
Mar 29, 2017 |
10170362 |
|
|
16188237 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0649 20130101;
H01L 27/10894 20130101; H01L 27/10888 20130101; H01L 21/76224
20130101; H01L 23/528 20130101 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 23/528 20060101 H01L023/528; H01L 27/108 20060101
H01L027/108; H01L 21/762 20060101 H01L021/762; H01L 29/06 20060101
H01L029/06; H01L 21/311 20060101 H01L021/311; H01L 21/02 20060101
H01L021/02; H01L 23/535 20060101 H01L023/535 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 23, 2017 |
CN |
201710099769.7 |
Claims
1. A method of forming a semiconductor memory device, comprising:
providing a substrate, wherein a shallow trench isolation (STI) is
formed in the substrate to define a plurality of active regions;
performing a first etching process to form a bit line contact
opening, wherein the bit line contact opening corresponds to one of
the active regions, and the bit line contact opening exposes said
one active region and the STI surrounds the active region;
performing a second etching process to remove a portion of the STI
in the bit line contact opening, making a top surface of the active
region in the bit line contact opening being exposed and higher
than a top surface of the STI in the bit line contact opening; and
forming a bit line contact structure on the substrate, wherein the
bit line contact structure is disposed in a part of the bit line
contact opening and contacts the active region in the bit line
contact opening.
2. The method of forming a semiconductor memory device according to
claim 1, wherein in the second etching process, further comprising
removing a silicon residue on the active region in the bit line
contact opening.
3. The method of forming a semiconductor memory device according to
claim 1, wherein the bit line contact opening comprises a sidewall,
and the sidewall extends to a same depth as a bottom surface of the
shallow trench isolation.
4. The method of forming a semiconductor memory device according to
claim 1, further comprising: forming a semiconductor layer on the
substrate; forming a low resistance layer on the semiconductor
layer; and patterning the semiconductor layer and the low
resistance layer.
5. The method of forming a semiconductor memory device according to
claim 4, wherein the bit line contact opening is formed and then
the semiconductor layer is formed.
6. The method of forming a semiconductor memory device according to
claim 4, wherein the semiconductor layer is formed and then the bit
line contact opening is formed.
7. The method of forming a semiconductor memory device according to
claim 1, before forming the bit line contact opening, further
comprising forming a patterned mask layer, and the first etching
process uses the patterned mask layer as a mask.
8. The method of forming a semiconductor memory device according to
claim 7, the second etching process removes the STI under the
patterned mask layer, making a sidewall of the bit line contact
opening under the patterned mask layer.
9. The method of forming a semiconductor memory device according to
claim 1, wherein the second etching process comprises using steam
HF.
10. The method of forming a semiconductor memory device according
to claim 1, wherein the second etching process comprises using
etchant HF.
11. The method of forming a semiconductor memory device according
to claim 1, wherein the second etching process comprises using
plasma containing NH.sub.3 or NF.sub.3.
12. The method of forming a semiconductor memory device according
to claim 1, wherein the first etching process comprises using
etching gas with carbon tetrafluoride (CF.sub.4), trifluoromethane
(CHF.sub.3), chlorine (Cl.sub.2), sulfur hexafluoride (SF.sub.6),
octafluorocyclobutane (C.sub.4F.sub.8) or hexafluoro butadiene
(C.sub.4F.sub.6).
13. The method of forming a semiconductor memory device according
to claim 1, after the first etching process, the top surface of the
active region in the bit line contact opening and the top surface
of the shallow trench isolation in the bit line contact opening
have a height H.sub.1, after the second etching process, the top
surface of the active region in the bit line contact opening and
the top surface of the shallow trench isolation in the bit line
contact opening have a height H.sub.2, wherein H.sub.2 is greater
than H.sub.1.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of U.S. patent application
Ser. No. 15/472,295 filed on Mar. 29, 2017, which is incorporated
herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] The present invention is related to a method of forming a
memory semiconductor device, and more particularly, to a memory
semiconductor device with bit line contact opening.
2. Description of the Prior Art
[0003] As technology advances, integrated circuit process
technology also continues to improve, so a variety of electronic
circuits can be accumulated/formed on a single wafer. The
semiconductor manufacturing process for manufacturing a wafer
includes a number of steps such as a deposition process for forming
a thin film, a photoresist coating for patterning said photoresist,
an exposure and development process, and an etching process for
patterning the film. To meet requirement, the size of the circuit
elements on the wafer is continuously downsizing, and for each of
the above-described process of routing an allowable range (process
window) requirements are increasingly stringent. Therefore, how to
increase the permissible range of the process in order to achieve
the effect of improving the yield of production has been the target
of the industry.
SUMMARY OF THE INVENTION
[0004] The present invention provides a method of forming a
semiconductor memory device having bit line contact with good
quality.
[0005] According to one embodiment, the present invention provides
a method of forming a semiconductor memory device. First, a
substrate is provided and an STI is forming in the substrate to
define a plurality of active regions. Then a first etching process
is performed to form a bit line contact opening, which is
corresponding to one of the active regions. A second etching
process is performed to remove a part of the active region and its
adjacent STI so a top surface of active region is higher than a top
surface of the STI. Next, a bit line contact structure is formed in
the opening.
[0006] According to another embodiment, the present invention
provides a semiconductor structure, including a substrate, a
shallow trench isolation, a bit line contact opening, a bit line
contact structure and a spacer. The substrate has a first active
region and a plurality of second active regions. The shallow trench
isolation is disposed in the substrate and between the first active
region and the second active regions. The bit line contact opening
is disposed in the first active region and the shallow trench
isolation. The bit line contact structure is disposed in the bit
line contact opening and contacts the first active region. The
spacer is disposed in the bit line contact opening, wherein the
spacer has a sidewall directly contacting one of the second active
regions.
[0007] The present invention provides a method of forming a bit
line contact, including performing a first etching process, a
second etching process and a third etching process, respectively.
The first etching process is to form the opening, the second
etching process ensures the quality of the active region, and the
third etching process enhances the structural stability of the bit
line.
[0008] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 to FIG. 8 show schematic diagram of the method of
manufacturing a semiconductor memory device according to a first
embodiment of the present invention.
[0010] FIG. 9 shows a schematic diagram of the method of
manufacturing a semiconductor memory device according to a second
embodiment of the present invention.
[0011] FIG. 10 to FIG. 13 show schematic diagrams of the method of
manufacturing a semiconductor memory device according to third
embodiment of the present invention.
DETAILED DESCRIPTION
[0012] To provide a better understanding of the presented
invention, preferred embodiments will be described in detail. The
preferred embodiments of the present invention are illustrated in
the accompanying drawings with numbered elements.
[0013] Please refer to FIG. 1 to FIG. 8, which show schematic
diagram of the method of manufacturing a semiconductor memory
device according to the first embodiment of the present invention,
wherein FIG. 1 shows a top view and FIG. 2 to FIG. 7 are
cross-sectional schematic view taken along line AA' in FIG. 1. The
present embodiment provides a method for manufacturing a
semiconductor memory device comprising the steps. First, as shown
in FIG. 1 and FIG. 2, a substrate 300 is provided. The substrate
300 can be any component that can serve as a base for forming
devices. In one embodiment, the substrate 300 can comprise a
semiconductor material, such as a silicon substrate, an epitaxial
silicon substrate, a silicon germanium substrate, a silicon carbide
substrate, a single crystal silicon substrate, a single crystal
silicon germanium substrate, an amorphous silicon substrate, or a
silicon on insulator (SOI), but it is not limited thereto. In a
cell region, a shallow trench isolation (STI) 302 is formed to
define a plurality of active regions 304. The shallow trench
isolation 302 may be formed by forming a plurality of trenches (not
shown) in the semiconductor substrate 300 by an etching process,
and filling in the trench with insulating material such as silicon
oxide (SiO.sub.2) or silicon oxide nitrogen (SiN) or other
insulation material. In addition, a plurality of word lines 306 may
be formed on the substrate 300, and in the present embodiment the
word lines 306 are buried word lines, but are not so limited
thereto. In some embodiments, each of the word line 306 may extend
along a first direction D1, and each of the active regions 304 may
extend along a second direction D2 different from the first
direction D1. In addition, the second direction D2 may not be
orthogonal to the first direction D1, and each of the active
regions 304 may extend along an oblique direction, thereby
increasing the density of memory cells.
[0014] A patterned mask layer 308 is formed after forming the
shallow trench isolation 302 and the word lines 306. A patterned
mask layer 308 may comprise a plurality of openings 310
respectively corresponding to the portion of the active region 304
to define the position of bit line contacts in the subsequent step,
and the sidewall of the openings 310 are positioned above the
shallow trench isolation 302 and preferably at the center of the
shallow trench isolation 302. In one embodiment, before forming the
patterned mask layer 308, a mask layer 312 can be formed on the
substrate and the shallow trench isolation 302. In one embodiment,
the mask layer 312 may include an insulating material such as
silicon nitride, and the patterned mask layer 308 may comprise
photoresist, but not limited thereto.
[0015] As shown in FIG. 3, a first etching process is performed by
using the patterned mask layer 308 as a mask to form an opening 300
in the substrate 300. The opening 314 preferably has an inclined
side wall corresponding to the shallow trench isolation 302, while
the bottom surface of the opening 314 is composed by the shallow
trench isolation 302 and located in the middle of the active region
304. In the preferred embodiment of the invention, the first
etching process 316 is a dry etching process, the etching gas
includes, for example, carbon tetrafluoride (CF.sub.4),
trifluoromethane (CHF.sub.3), chlorine (Cl.sub.2), sulfur
hexafluoride (SF.sub.6), octafluorocyclobutane (C.sub.4F.sub.8) or
hexafluoro butadiene (C.sub.4F.sub.6), but is not limited thereto.
After performing the first etching process 316, there may be Si
residue 319 formed on the upper surface 304 of the exposed active
region (including a top surface and the sidewall). The exposed
active region 304 has a height H.sub.1. Then, the patterned mask
layer 308 is removed.
[0016] As shown in FIG. 4, a second etching process 318 is then
performed and the Si residue 319 is completely removed from the
upper surface of the exposed active region 304. In one embodiment,
the second etch process 318 is to use vapor etching gas, such as
hydrofluoric acid (HF) without plasma. In another embodiment, the
second etch process 318 can use plasma etching gas, such as ammonia
(NH.sub.3) or nitrogen trifluoride (NF.sub.3), and preferably is
ion bombard free. And in another embodiment, a wet etching may also
be used, e.g., using a dilute hydrofluoric acid (dHF). After
performing a second etching process 318, a part of the shallow
trench isolation around 302 the active region 304 is also removed,
thereto expose the sidewalls and the top surface of the active
region 304 in the opening 314, so the top surface of the active
region 304 is slightly higher than the top surface of the shallow
trench isolation 302 in order to increase the stability of the
subsequently formed bit line contact. In this embodiment, the
active region 304 having a height H.sub.2 (the distance between the
top surface of the active region 304 and the top surface of the
shallow trench isolation 302), and H.sub.2 is greater than H.sub.1.
In another embodiment of the present invention, as shown in FIG. 5,
the shallow trench isolation 302 may further be etched, so the
sidewall of the opening 314 would be located below the mask layer
312. And the surface of the shallow trench isolation 312 would
further be etched, so that the height of the exposed active region
304 H.sub.3 is greater than the H.sub.2. And in still another
embodiment of the present invention, after forming the structure of
FIG. 5, a spacer 321 may be formed below the mask layer 312, above
the shallow trench isolation 302, and at two sidewalls of the
active region 304, wherein the spacer 321 has a sidewall vertically
aligned with the opening 314, as shown in FIG. 6. In one
embodiment, the spacer 321 includes silicon oxide, silicon nitride,
or combinations thereof. In one embodiment, the spacer 321 is
formed by forming spacer material layer (not shown) on the
substrate 300, which conformally fill the opening 314, and then
performing a dry etching and/or wet etching process to form said
spacer 321. In another embodiment, the process parameters can be
adjusted, so that the sidewalls of the spacer 321 can be positioned
under the mask layer 310, or can be protrude from the sidewall of
the opening 314. In the present embodiment, the exposed active
region 304 has a height H.sub.4, wherein H.sub.4 and H.sub.2 is
substantially equal. In one embodiment, H.sub.4 may be larger than
H.sub.3.
[0017] Next, as shown in FIG. 7, a plug contact layer 320', a
low-resistance layer 322', a cap 324' and a mask layer 326' are the
sequentially formed on the substrate 300. The contact plug layer
320' may fill the opening 314 and the material thereof contains
silicon, for example, poly-silicon or amorphous silicon. The
low-resistance layer 322' includes metal such as gold (Au), silver
(Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti),
tantalum (Ta), cadmium (Cd), or the nitrides thereof, or the oxides
thereof, or the above-mentioned alloys, or combinations thereof.
The cap layer 324' and mask layer 326' may be any mask material,
for example, silicon nitride (SiN), silicon oxynitride (SiON),
silicon carbide (SiC) or the advanced pattern film (APF) provided
by Applied Materials company, or any combination of these
materials. In one embodiment, the cap layer 324' is silicon
nitride, and the mask layer 326' is a silicon oxide. Moreover, a
barrier layer (not shown) can be formed between the contact plug
layer 320' and the low resistance layer 322'.
[0018] As shown in FIG. 8, a third etching process 328 is performed
by using the mask layer 326' as a mask to pattern the cap layer
324', the low-resistance layer 322' and the contact plug layer
320'. Thus, the patterned mask layer 326, the patterned cap layer
324, the patterned low resistance layer 322 and the patterned
contact plug layer 320 together forms a bit line contact structure
330 and a bit line. In one embodiment, the third etching process
328 further etches to a top surface of the shallow trench isolation
302 in the opening 314 so that the bit line contact sidewall 330 is
substantially a 90 degree angle.
[0019] Please refer to FIG. 9, when the embodiment with a spacer in
FIG. 6 is provided, the final formation of the bit line contact
structure 330 is as shown in FIG. 9. As shown in FIG. 9, this
semiconductor memory structure comprises a substrate 300 having a
first active region 304A and a plurality of second active regions
304B located on both sides of the first active region 304A. The
shallow trench isolation 302 is disposed between the first active
region 304A and the second active region 304B. The bit line contact
opening 314 is provided in the first active region 304A and the
shallow trench isolation 302. The bit line contact structure 330 is
disposed in the bit line contact opening 314 and contacts with the
first active region 304A. The spacer 321 is disposed in the bit
line contact opening 314, and preferably located above the shallow
trench isolation 302, below the mask layer 310, and it has a
sidewall direct contacting the sidewall of the second active region
304B. In one embodiment, the spacer 321 has a sidewall under the
mask layer 310. In another embodiment, the sidewall of the spacer
321 vertically aligns with the mask layer 321. In yet another
embodiment, the sidewall of the spacer 321 protrudes from the side
wall of the mask layer 310.
[0020] Please refer to FIG. 10 to FIG. 13, which shows schematic
diagrams of the method of manufacturing a semiconductor memory
device according to second embodiment of the present invention. As
shown in FIG. 10, a substrate 300 is provided, and then forming the
shallow trench isolation 302 the active region 304 and the mask
layer 310 on the substrate 300, wherein detail embodiment is the
same as that in the first embodiment. Then, a first contact plug
layer 320 is formed such as poly-silicon or amorphous silicon. This
first contact plug layer 320' can also be used as a gate of
transistor in the peripheral region, that is, in the present
embodiment, the transistor gate will be formed simultaneously with
the bit line contact structure in the cell region. Then, a
patterned mask layer 308, for example, a photoresist layer is
formed on the first contact plug layer 320.
[0021] Next, as shown in FIG. 11, a first etch process 316 is
performed by using the patterned mask layer 308 as a mask to form
an opening 314. Thereafter, a second etching process 318 is
performed. Details of the first etch process 316 and the second
etching process 318 is described in the above first embodiment.
[0022] A second contact plug layer 320 is filled into the opening
314, and a planarization step is performed to make the first
contact plug layer 320' level with the second contact layer plug
layer 320. The first contact plug material layer 320 and the second
contact plug layer 320' may have the same material or different
material. A low-resistance layer 322, a cap 324, and a mask layer
326 are then formed, which is the same as that in the first
embodiment. Finally, as shown in FIG. 8, the third etching process
328 is performed, and the bit line contact structure 330 and bit
line can also be obtained.
[0023] In summary, the present invention provides a method of
forming a bit line contact, including performing a first etching
process, a second etching process and a third etching process,
respectively. The first etching process is to form the opening, the
second etching process ensures the quality of the active region,
and the third etching process enhances the structural stability of
the bit line.
[0024] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *