U.S. patent application number 15/858549 was filed with the patent office on 2019-02-28 for technologies for providing efficient memory access on an accelerator sled.
The applicant listed for this patent is Intel Corporation. Invention is credited to Paul Dormitzer.
Application Number | 20190065401 15/858549 |
Document ID | / |
Family ID | 65434219 |
Filed Date | 2019-02-28 |
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United States Patent
Application |
20190065401 |
Kind Code |
A1 |
Dormitzer; Paul |
February 28, 2019 |
TECHNOLOGIES FOR PROVIDING EFFICIENT MEMORY ACCESS ON AN
ACCELERATOR SLED
Abstract
Technologies for providing efficient access to the memory of an
accelerator device include an accelerator sled. The accelerator
sled includes an accelerator device including a memory. The
accelerator sled also includes a network interface controller that
includes a memory access logic unit. The memory access logic unit
is to determine a memory address region usable by a remote compute
device to access the memory of the accelerator device, receive,
from the remote compute device, a memory access request to remotely
access the memory of the accelerator device associated with the
memory address region, and perform, in response to the memory
access request, a direct memory access operation on the memory.
Other embodiments are also described and claimed.
Inventors: |
Dormitzer; Paul; (Acton,
MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Family ID: |
65434219 |
Appl. No.: |
15/858549 |
Filed: |
December 29, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62584401 |
Nov 10, 2017 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 1/183 20130101;
H04L 49/40 20130101; H05K 7/1498 20130101; G06F 1/20 20130101; H04L
43/065 20130101; H05K 7/20736 20130101; G06F 9/5061 20130101; G06F
11/3409 20130101; H04L 41/5019 20130101; H04L 41/5025 20130101;
G06F 11/3466 20130101; H05K 7/18 20130101; G06F 13/4022 20130101;
G06F 21/105 20130101; H04L 41/044 20130101; H04L 43/16 20130101;
Y02D 30/00 20180101; H05K 7/1489 20130101; G06Q 30/0283 20130101;
H04L 67/1008 20130101; H04L 43/0876 20130101; G06F 15/7867
20130101; G06Q 10/0631 20130101; G06F 2201/86 20130101; H04L
63/0428 20130101; G06F 11/3442 20130101; H04L 41/0896 20130101;
G06N 3/063 20130101; H04L 41/0816 20130101; G06F 15/7807 20130101;
G06F 2201/885 20130101; G06F 9/5088 20130101; G06F 2200/201
20130101; H04L 41/14 20130101; Y02D 10/00 20180101; G06F 9/4856
20130101; G06F 9/505 20130101; G06F 11/3006 20130101; B25J 15/0014
20130101; G06F 9/44 20130101 |
International
Class: |
G06F 12/1081 20060101
G06F012/1081; G06F 13/28 20060101 G06F013/28; G06F 13/42 20060101
G06F013/42; G06F 13/16 20060101 G06F013/16; G06F 13/40 20060101
G06F013/40 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 30, 2017 |
IN |
201741030632 |
Claims
1. An accelerator sled comprising: an accelerator device including
a memory; a network interface controller including a memory access
logic unit to (i) determine a memory address region usable by a
remote compute device to access the memory of the accelerator
device, (ii) receive, from the remote compute device, a memory
access request to remotely access the memory of the accelerator
device associated with the memory address region, and (iii)
perform, in response to the memory access request, a direct memory
access operation on the memory.
2. The accelerator sled of claim 1, wherein to perform the direct
memory access operation comprises to perform the direct memory
access operation using a peripheral component interconnect express
protocol in which the network interface controller is an endpoint
device and the accelerator device is a root device.
3. The accelerator sled of claim 1, wherein the memory access logic
unit is further to: establish a write queue in the memory, wherein
the write queue is usable to track one or more write operations to
be performed on the memory; provide, to the remote compute device,
a unique identifier that identifies the queue.
4. The accelerator sled of claim 1, wherein the memory access logic
unit is further to receive a request from the remote compute device
to establish the write queue, wherein the request defines a length
for the write queue and wherein to establish the write queue
comprises to establish the write queue with the length defined in
the request.
5. The accelerator sled of claim 1, wherein the memory access logic
unit is further to: establish a read queue in the memory, wherein
the read queue is usable to track one or more write operations to
be performed on the memory; provide, to the remote compute device,
a unique identifier that identifies the queue.
6. The accelerator sled of claim 1, wherein the memory access logic
unit is further to receive a request from the remote compute device
to establish the read queue, wherein the request defines a length
for the read queue and wherein to establish the read queue
comprises to establish the read queue with the length defined in
the request.
7. The accelerator sled of claim 1, wherein the accelerator device
is a first accelerator device, the memory is a first memory,
accelerator sled further comprises a second accelerator device that
includes a second memory, the memory access request includes a
unique identifier associated with a read queue or a write queue,
and the memory access logic unit is further to determine, from the
unique identifier, whether the direct memory access operation is to
be performed on the first memory or the second memory.
8. The accelerator sled of claim 1, wherein the accelerator device
is a first accelerator device connected to the network interface
controller, the accelerator sled further comprising a second
accelerator device that is indirectly connected to the network
interface controller through the first accelerator device, and the
memory access request includes a memory address on which the direct
memory access operation is to be performed, and wherein the memory
access logic unit is further to determine, as a function of the
memory address, whether the memory access request corresponds to
the first accelerator device or the second accelerator device.
9. The accelerator sled of claim 1, wherein the accelerator device
is a first accelerator device, the accelerator sled further
comprising a second accelerator device that is connected to the
network interface controller, the memory access request includes a
memory address on which the direct memory access operation is to be
performed, and the memory access logic unit is further to
determine, as a function of the memory address, whether the memory
access request corresponds to the first accelerator device or the
second accelerator device.
10. The accelerator sled of claim 1, wherein to perform the direct
memory access operation comprises to perform the direct memory
access operation on a register of the accelerator device.
11. The accelerator sled of claim 1, wherein to perform the direct
memory access operation comprises to perform the direct memory
access operation on a random access memory of the accelerator
device.
12. The accelerator sled of claim 1, wherein to perform the direct
memory access operation comprises to perform a read operation.
13. One or more machine-readable storage media comprising a
plurality of instructions stored thereon that, in response to being
executed, cause an accelerator sled to: determine, with a memory
access logic unit of a network interface controller of the
accelerator sled, a memory address region usable by a remote
compute device to access the memory of an accelerator device of the
accelerator sled; receive, with the memory access logic unit and
from the remote compute device, a memory access request to remotely
access the memory of the accelerator device associated with the
memory address region; and perform, with the memory access logic
unit and in response to the memory access request, a direct memory
access operation on the memory.
14. The one or more machine-readable storage media of claim 13,
wherein to perform the direct memory access operation comprises to
perform the direct memory access operation using a peripheral
component interconnect express protocol in which the network
interface controller is an endpoint device and the accelerator
device is a root device.
15. The one or more machine-readable storage media of claim 13,
wherein the plurality of instructions further cause the accelerator
sled to: establish, with the memory access logic unit, a write
queue in the memory, wherein the write queue is usable to track one
or more write operations to be performed on the memory; provide,
with the memory access logic unit and to the remote compute device,
a unique identifier that identifies the queue.
16. The one or more machine-readable storage media of claim 13,
wherein the plurality of instructions further cause the accelerator
sled to receive, with the memory access logic unit, a request from
the remote compute device to establish the write queue, wherein the
request defines a length for the write queue and wherein to
establish the write queue comprises to establish the write queue
with the length defined in the request.
17. The one or more machine-readable storage media of claim 13,
wherein the plurality of instructions further cause the accelerator
sled to: establish, with the memory access logic unit, a read queue
in the memory, wherein the read queue is usable to track one or
more write operations to be performed on the memory; provide, with
the memory access logic unit and to the remote compute device, a
unique identifier that identifies the queue.
18. The one or more machine-readable storage media of claim 13,
wherein the plurality of instructions further cause the accelerator
sled to receive, with the memory access logic unit, a request from
the remote compute device to establish the read queue, wherein the
request defines a length for the read queue and wherein to
establish the read queue comprises to establish the read queue with
the length defined in the request.
19. The one or more machine-readable storage media of claim 13,
wherein the accelerator device is a first accelerator device, the
memory is a first memory, the accelerator sled additionally
includes a second accelerator device that includes a second memory,
and the memory access request includes a unique identifier
associated with a read queue or a write queue, wherein the
plurality of instructions further cause the accelerator sled to
determine, with the memory access logic unit and from the unique
identifier, whether the direct memory access operation is to be
performed on the first memory or the second memory.
20. The one or more machine-readable storage media of claim 13,
wherein the accelerator device is a first accelerator device
connected to the network interface controller, the accelerator sled
further includes a second accelerator device that is indirectly
connected to the network interface controller through the first
accelerator device, and the memory access request includes a memory
address on which the direct memory access operation is to be
performed, wherein the plurality of instructions further cause the
accelerator sled to determine, with the memory access logic unit
and as a function of the memory address, whether the memory access
request corresponds to the first accelerator device or the second
accelerator device.
21. The one or more machine-readable storage media of claim 13,
wherein the accelerator device is a first accelerator device, the
accelerator sled further comprising a second accelerator sled that
is connected to the network interface, and the memory access
request includes a memory address on which the direct memory access
operation is to be performed, wherein the plurality of instructions
further cause the accelerator sled to determine, with the memory
access logic unit and as a function of the memory address, whether
the memory access request corresponds to the first accelerator
device or the second accelerator device.
22. The one or more machine-readable storage media of claim 13,
wherein to perform the direct memory access operation comprises to
perform the direct memory access operation on a register of the
accelerator device.
23. The one or more machine-readable storage media of claim 13,
wherein to perform the direct memory access operation comprises to
perform the direct memory access operation on a random access
memory of the accelerator device.
24. The one or more machine-readable storage media of claim 13,
wherein to perform the direct memory access operation comprises to
perform a read operation.
25. An accelerator sled comprising: an accelerator device including
a memory; a network interface controller including memory access
manager circuitry to (i) determine a memory address region usable
by a remote compute device to access the memory of the accelerator
device, (ii) receive, from the remote compute device, a memory
access request to remotely access the memory of the accelerator
device associated with the memory address region, and (iii)
perform, in response to the memory access request, a direct memory
access operation on the memory.
26. A method comprising: determining, by a memory access logic unit
of a network interface controller of an accelerator sled, a memory
address region usable by a remote compute device to access the
memory of an accelerator device of the accelerator sled; receiving,
by the memory access logic unit and from the remote compute device,
a memory access request to remotely access the memory of the
accelerator device associated with the memory address region; and
performing, by the memory access logic unit and in response to the
memory access request, a direct memory access operation on the
memory.
27. The method of claim 26, wherein performing the direct memory
access operation comprises performing the direct memory access
operation using a peripheral component interconnect express
protocol in which the network interface controller is an endpoint
device and the accelerator device is a root device.
28. The method of claim 26, further comprising: establishing, by
the memory access logic unit, a write queue in the memory, wherein
the write queue is usable to track one or more write operations to
be performed on the memory; providing, by the memory access logic
unit and to the remote compute device, a unique identifier that
identifies the queue.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims the benefit of Indian
Provisional Patent Application No. 201741030632, filed Aug. 30,
2017 and U.S. Provisional Patent Application No. 62/584,401, filed
Nov. 10, 2017.
BACKGROUND
[0002] In some data centers, a compute device may by physically
separated from (e.g., connected through a network to) an
accelerator device which may be physically located on a board with
one or more other accelerator devices. In such systems, a general
purpose processor is coupled between a network interface controller
that provides connectivity to the network and the set of
accelerator devices. The compute device may issue requests for
operations to be performed by one of the accelerator devices, such
as to read or write from a memory of the accelerator device (e.g.,
to provide a data set on which to perform a function or to read
output data resulting from the execution of the function) to
increase the speed of execution of a workload (e.g., an
application). In such operations, the request and any accompanying
data, is received by the network interface controller, passed to
the general purpose processor, which acts as an intermediary, and
then is passed to the corresponding accelerator device. This series
of transactions that occur to access the memory of the accelerator
device can incur latency that may diminish the speed improvement
provided by offloading the function from the compute device to the
accelerator device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The concepts described herein are illustrated by way of
example and not by way of limitation in the accompanying figures.
For simplicity and clarity of illustration, elements illustrated in
the figures are not necessarily drawn to scale. Where considered
appropriate, reference labels have been repeated among the figures
to indicate corresponding or analogous elements.
[0004] FIG. 1 is a simplified diagram of at least one embodiment of
a data center for executing workloads with disaggregated
resources;
[0005] FIG. 2 is a simplified diagram of at least one embodiment of
a pod of the data center of FIG. 1;
[0006] FIG. 3 is a perspective view of at least one embodiment of a
rack that may be included in the pod of FIG. 2;
[0007] FIG. 4 is a side plan elevation view of the rack of FIG.
3;
[0008] FIG. 5 is a perspective view of the rack of FIG. 3 having a
sled mounted therein;
[0009] FIG. 6 is a is a simplified block diagram of at least one
embodiment of a top side of the sled of FIG. 5;
[0010] FIG. 7 is a simplified block diagram of at least one
embodiment of a bottom side of the sled of FIG. 6;
[0011] FIG. 8 is a simplified block diagram of at least one
embodiment of a compute sled usable in the data center of FIG.
1;
[0012] FIG. 9 is a top perspective view of at least one embodiment
of the compute sled of FIG. 8;
[0013] FIG. 10 is a simplified block diagram of at least one
embodiment of an accelerator sled usable in the data center of FIG.
1;
[0014] FIG. 11 is a top perspective view of at least one embodiment
of the accelerator sled of FIG. 10;
[0015] FIG. 12 is a simplified block diagram of at least one
embodiment of a storage sled usable in the data center of FIG.
1;
[0016] FIG. 13 is a top perspective view of at least one embodiment
of the storage sled of FIG. 12;
[0017] FIG. 14 is a simplified block diagram of at least one
embodiment of a memory sled usable in the data center of FIG. 1;
and
[0018] FIG. 15 is a simplified block diagram of a system that may
be established within the data center of FIG. 1 to execute
workloads with managed nodes composed of disaggregated
resources.
[0019] FIG. 16 is a simplified block diagram of at least one
embodiment of a system for providing efficient memory access on an
accelerator sled;
[0020] FIG. 17 is a simplified block diagram of at least one
embodiment of an accelerator sled of the system of FIG. 16;
[0021] FIG. 18 is a simplified block diagram of at least one
embodiment of an environment that may be established by the
accelerator sled of FIGS. 16 and 17; and
[0022] FIGS. 19-22 are a simplified flow diagram of at least one
embodiment of a method for providing efficient memory access that
may be performed by the accelerator sled of FIGS. 16 and 17.
DETAILED DESCRIPTION OF THE DRAWINGS
[0023] While the concepts of the present disclosure are susceptible
to various modifications and alternative forms, specific
embodiments thereof have been shown by way of example in the
drawings and will be described herein in detail. It should be
understood, however, that there is no intent to limit the concepts
of the present disclosure to the particular forms disclosed, but on
the contrary, the intention is to cover all modifications,
equivalents, and alternatives consistent with the present
disclosure and the appended claims.
[0024] References in the specification to "one embodiment," "an
embodiment," "an illustrative embodiment," etc., indicate that the
embodiment described may include a particular feature, structure,
or characteristic, but every embodiment may or may not necessarily
include that particular feature, structure, or characteristic.
Moreover, such phrases are not necessarily referring to the same
embodiment. Further, when a particular feature, structure, or
characteristic is described in connection with an embodiment, it is
submitted that it is within the knowledge of one skilled in the art
to effect such feature, structure, or characteristic in connection
with other embodiments whether or not explicitly described.
Additionally, it should be appreciated that items included in a
list in the form of "at least one A, B, and C" can mean (A); (B);
(C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly,
items listed in the form of "at least one of A, B, or C" can mean
(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and
C).
[0025] The disclosed embodiments may be implemented, in some cases,
in hardware, firmware, software, or any combination thereof. The
disclosed embodiments may also be implemented as instructions
carried by or stored on a transitory or non-transitory
machine-readable (e.g., computer-readable) storage medium, which
may be read and executed by one or more processors. A
machine-readable storage medium may be embodied as any storage
device, mechanism, or other physical structure for storing or
transmitting information in a form readable by a machine (e.g., a
volatile or non-volatile memory, a media disc, or other media
device).
[0026] In the drawings, some structural or method features may be
shown in specific arrangements and/or orderings. However, it should
be appreciated that such specific arrangements and/or orderings may
not be required. Rather, in some embodiments, such features may be
arranged in a different manner and/or order than shown in the
illustrative figures. Additionally, the inclusion of a structural
or method feature in a particular figure is not meant to imply that
such feature is required in all embodiments and, in some
embodiments, may not be included or may be combined with other
features.
[0027] Referring now to FIG. 1, a data center 100 in which
disaggregated resources may cooperatively execute one or more
workloads (e.g., applications on behalf of customers) includes
multiple pods 110, 120, 130, 140, each of which includes one or
more rows of racks. As described in more detail herein, each rack
houses multiple sleds, which each may be embodied as a compute
device, such as a server, that is primarily equipped with a
particular type of resource (e.g., memory devices, data storage
devices, accelerator devices, general purpose processors). In the
illustrative embodiment, the sleds in each pod 110, 120, 130, 140
are connected to multiple pod switches (e.g., switches that route
data communications to and from sleds within the pod). The pod
switches, in turn, connect with spine switches 150 that switch
communications among pods (e.g., the pods 110, 120, 130, 140) in
the data center 100. In some embodiments, the sleds may be
connected with a fabric using Intel Omni-Path technology. As
described in more detail herein, resources within sleds in the data
center 100 may be allocated to a group (referred to herein as a
"managed node") containing resources from one or more other sleds
to be collectively utilized in the execution of a workload. The
workload can execute as if the resources belonging to the managed
node were located on the same sled. The resources in a managed node
may even belong to sleds belonging to different racks, and even to
different pods 110, 120, 130, 140. Some resources of a single sled
may be allocated to one managed node while other resources of the
same sled are allocated to a different managed node (e.g., one
processor assigned to one managed node and another processor of the
same sled assigned to a different managed node). By disaggregating
resources to sleds comprised predominantly of a single type of
resource (e.g., compute sleds comprising primarily compute
resources, memory sleds containing primarily memory resources), and
selectively allocating and deallocating the disaggregated resources
to form a managed node assigned to execute a workload, the data
center 100 provides more efficient resource usage over typical data
centers comprised of hyperconverged servers containing compute,
memory, storage and perhaps additional resources). As such, the
data center 100 may provide greater performance (e.g., throughput,
operations per second, latency, etc.) than a typical data center
that has the same number of resources.
[0028] Referring now to FIG. 2, the pod 110, in the illustrative
embodiment, includes a set of rows 200, 210, 220, 230 of racks 240.
Each rack 240 may house multiple sleds (e.g., sixteen sleds) and
provide power and data connections to the housed sleds, as
described in more detail herein. In the illustrative embodiment,
the racks in each row 200, 210, 220, 230 are connected to multiple
pod switches 250, 260. The pod switch 250 includes a set of ports
252 to which the sleds of the racks of the pod 110 are connected
and another set of ports 254 that connect the pod 110 to the spine
switches 150 to provide connectivity to other pods in the data
center 100. Similarly, the pod switch 260 includes a set of ports
262 to which the sleds of the racks of the pod 110 are connected
and a set of ports 264 that connect the pod 110 to the spine
switches 150. As such, the use of the pair of switches 250, 260
provides an amount of redundancy to the pod 110. For example, if
either of the switches 250, 260 fails, the sleds in the pod 110 may
still maintain data communication with the remainder of the data
center 100 (e.g., sleds of other pods) through the other switch
250, 260. Furthermore, in the illustrative embodiment, the switches
150, 250, 260 may be embodied as dual-mode optical switches,
capable of routing both Ethernet protocol communications carrying
Internet Protocol (IP) packets and communications according to a
second, high-performance link-layer protocol (e.g., Intel's
Omni-Path Architecture's, Infiniband) via optical signaling media
of an optical fabric.
[0029] It should be appreciated that each of the other pods 120,
130, 140 (as well as any additional pods of the data center 100)
may be similarly structured as, and have components similar to, the
pod 110 shown in and described in regard to FIG. 2 (e.g., each pod
may have rows of racks housing multiple sleds as described above).
Additionally, while two pod switches 250, 260 are shown, it should
be understood that in other embodiments, each pod 110, 120, 130,
140 may be connected to different number of pod switches (e.g.,
providing even more failover capacity).
[0030] Referring now to FIGS. 3-5, each illustrative rack 240 of
the data center 100 includes two elongated support posts 302, 304,
which are arranged vertically. For example, the elongated support
posts 302, 304 may extend upwardly from a floor of the data center
100 when deployed. The rack 240 also includes one or more
horizontal pairs 310 of elongated support arms 312 (identified in
FIG. 3 via a dashed ellipse) configured to support a sled of the
data center 100 as discussed below. One elongated support arm 312
of the pair of elongated support arms 312 extends outwardly from
the elongated support post 302 and the other elongated support arm
312 extends outwardly from the elongated support post 304.
[0031] In the illustrative embodiments, each sled of the data
center 100 is embodied as a chassis-less sled. That is, each sled
has a chassis-less circuit board substrate on which physical
resources (e.g., processors, memory, accelerators, storage, etc.)
are mounted as discussed in more detail below. As such, the rack
240 is configured to receive the chassis-less sleds. For example,
each pair 310 of elongated support arms 312 defines a sled slot 320
of the rack 240, which is configured to receive a corresponding
chassis-less sled. To do so, each illustrative elongated support
arm 312 includes a circuit board guide 330 configured to receive
the chassis-less circuit board substrate of the sled. Each circuit
board guide 330 is secured to, or otherwise mounted to, a top side
332 of the corresponding elongated support arm 312. For example, in
the illustrative embodiment, each circuit board guide 330 is
mounted at a distal end of the corresponding elongated support arm
312 relative to the corresponding elongated support post 302, 304.
For clarity of the Figures, not every circuit board guide 330 may
be referenced in each Figure.
[0032] Each circuit board guide 330 includes an inner wall that
defines a circuit board slot 380 configured to receive the
chassis-less circuit board substrate of a sled 400 when the sled
400 is received in the corresponding sled slot 320 of the rack 240.
To do so, as shown in FIG. 4, a user (or robot) aligns the
chassis-less circuit board substrate of an illustrative
chassis-less sled 400 to a sled slot 320. The user, or robot, may
then slide the chassis-less circuit board substrate forward into
the sled slot 320 such that each side edge 414 of the chassis-less
circuit board substrate is received in a corresponding circuit
board slot 380 of the circuit board guides 330 of the pair 310 of
elongated support arms 312 that define the corresponding sled slot
320 as shown in FIG. 4. By having robotically accessible and
robotically manipulable sleds comprising disaggregated resources,
each type of resource can be upgraded independently of each other
and at their own optimized refresh rate. Furthermore, the sleds are
configured to blindly mate with power and data communication cables
in each rack 240, enhancing their ability to be quickly removed,
upgraded, reinstalled, and/or replaced. As such, in some
embodiments, the data center 100 may operate (e.g., execute
workloads, undergo maintenance and/or upgrades, etc.) without human
involvement on the data center floor. In other embodiments, a human
may facilitate one or more maintenance or upgrade operations in the
data center 100.
[0033] It should be appreciated that each circuit board guide 330
is dual sided. That is, each circuit board guide 330 includes an
inner wall that defines a circuit board slot 380 on each side of
the circuit board guide 330. In this way, each circuit board guide
330 can support a chassis-less circuit board substrate on either
side. As such, a single additional elongated support post may be
added to the rack 240 to turn the rack 240 into a two-rack solution
that can hold twice as many sled slots 320 as shown in FIG. 3. The
illustrative rack 240 includes seven pairs 310 of elongated support
arms 312 that define a corresponding seven sled slots 320, each
configured to receive and support a corresponding sled 400 as
discussed above. Of course, in other embodiments, the rack 240 may
include additional or fewer pairs 310 of elongated support arms 312
(i.e., additional or fewer sled slots 320). It should be
appreciated that because the sled 400 is chassis-less, the sled 400
may have an overall height that is different than typical servers.
As such, in some embodiments, the height of each sled slot 320 may
be shorter than the height of a typical server (e.g., shorter than
a single rank unit, "1U"). That is, the vertical distance between
each pair 310 of elongated support arms 312 may be less than a
standard rack unit "1U." Additionally, due to the relative decrease
in height of the sled slots 320, the overall height of the rack 240
in some embodiments may be shorter than the height of traditional
rack enclosures. For example, in some embodiments, each of the
elongated support posts 302, 304 may have a length of six feet or
less. Again, in other embodiments, the rack 240 may have different
dimensions. Further, it should be appreciated that the rack 240
does not include any walls, enclosures, or the like. Rather, the
rack 240 is an enclosure-less rack that is opened to the local
environment. Of course, in some cases, an end plate may be attached
to one of the elongated support posts 302, 304 in those situations
in which the rack 240 forms an end-of-row rack in the data center
100.
[0034] In some embodiments, various interconnects may be routed
upwardly or downwardly through the elongated support posts 302,
304. To facilitate such routing, each elongated support post 302,
304 includes an inner wall that defines an inner chamber in which
the interconnect may be located. The interconnects routed through
the elongated support posts 302, 304 may be embodied as any type of
interconnects including, but not limited to, data or communication
interconnects to provide communication connections to each sled
slot 320, power interconnects to provide power to each sled slot
320, and/or other types of interconnects.
[0035] The rack 240, in the illustrative embodiment, includes a
support platform on which a corresponding optical data connector
(not shown) is mounted. Each optical data connector is associated
with a corresponding sled slot 320 and is configured to mate with
an optical data connector of a corresponding sled 400 when the sled
400 is received in the corresponding sled slot 320. In some
embodiments, optical connections between components (e.g., sleds,
racks, and switches) in the data center 100 are made with a blind
mate optical connection. For example, a door on each cable may
prevent dust from contaminating the fiber inside the cable. In the
process of connecting to a blind mate optical connector mechanism,
the door is pushed open when the end of the cable enters the
connector mechanism. Subsequently, the optical fiber inside the
cable enters a gel within the connector mechanism and the optical
fiber of one cable comes into contact with the optical fiber of
another cable within the gel inside the connector mechanism.
[0036] The illustrative rack 240 also includes a fan array 370
coupled to the cross-support arms of the rack 240. The fan array
370 includes one or more rows of cooling fans 372, which are
aligned in a horizontal line between the elongated support posts
302, 304. In the illustrative embodiment, the fan array 370
includes a row of cooling fans 372 for each sled slot 320 of the
rack 240. As discussed above, each sled 400 does not include any
on-board cooling system in the illustrative embodiment and, as
such, the fan array 370 provides cooling for each sled 400 received
in the rack 240. Each rack 240, in the illustrative embodiment,
also includes a power supply associated with each sled slot 320.
Each power supply is secured to one of the elongated support arms
312 of the pair 310 of elongated support arms 312 that define the
corresponding sled slot 320. For example, the rack 240 may include
a power supply coupled or secured to each elongated support arm 312
extending from the elongated support post 302. Each power supply
includes a power connector configured to mate with a power
connector of the sled 400 when the sled 400 is received in the
corresponding sled slot 320. In the illustrative embodiment, the
sled 400 does not include any on-board power supply and, as such,
the power supplies provided in the rack 240 supply power to
corresponding sleds 400 when mounted to the rack 240.
[0037] Referring now to FIG. 6, the sled 400, in the illustrative
embodiment, is configured to be mounted in a corresponding rack 240
of the data center 100 as discussed above. In some embodiments,
each sled 400 may be optimized or otherwise configured for
performing particular tasks, such as compute tasks, acceleration
tasks, data storage tasks, etc. For example, the sled 400 may be
embodied as a compute sled 800 as discussed below in regard to
FIGS. 8-9, an accelerator sled 1000 as discussed below in regard to
FIGS. 10-11, a storage sled 1200 as discussed below in regard to
FIGS. 12-13, or as a sled optimized or otherwise configured to
perform other specialized tasks, such as a memory sled 1400,
discussed below in regard to FIG. 14.
[0038] As discussed above, the illustrative sled 400 includes a
chassis-less circuit board substrate 602, which supports various
physical resources (e.g., electrical components) mounted thereon.
It should be appreciated that the circuit board substrate 602 is
"chassis-less" in that the sled 400 does not include a housing or
enclosure. Rather, the chassis-less circuit board substrate 602 is
open to the local environment. The chassis-less circuit board
substrate 602 may be formed from any material capable of supporting
the various electrical components mounted thereon. For example, in
an illustrative embodiment, the chassis-less circuit board
substrate 602 is formed from an FR-4 glass-reinforced epoxy
laminate material. Of course, other materials may be used to form
the chassis-less circuit board substrate 602 in other
embodiments.
[0039] As discussed in more detail below, the chassis-less circuit
board substrate 602 includes multiple features that improve the
thermal cooling characteristics of the various electrical
components mounted on the chassis-less circuit board substrate 602.
As discussed, the chassis-less circuit board substrate 602 does not
include a housing or enclosure, which may improve the airflow over
the electrical components of the sled 400 by reducing those
structures that may inhibit air flow. For example, because the
chassis-less circuit board substrate 602 is not positioned in an
individual housing or enclosure, there is no backplane (e.g., a
backplate of the chassis) to the chassis-less circuit board
substrate 602, which could inhibit air flow across the electrical
components. Additionally, the chassis-less circuit board substrate
602 has a geometric shape configured to reduce the length of the
airflow path across the electrical components mounted to the
chassis-less circuit board substrate 602. For example, the
illustrative chassis-less circuit board substrate 602 has a width
604 that is greater than a depth 606 of the chassis-less circuit
board substrate 602. In one particular embodiment, for example, the
chassis-less circuit board substrate 602 has a width of about 21
inches and a depth of about 9 inches, compared to a typical server
that has a width of about 17 inches and a depth of about 39 inches.
As such, an airflow path 608 that extends from a front edge 610 of
the chassis-less circuit board substrate 602 toward a rear edge 612
has a shorter distance relative to typical servers, which may
improve the thermal cooling characteristics of the sled 400.
Furthermore, although not illustrated in FIG. 6, the various
physical resources mounted to the chassis-less circuit board
substrate 602 are mounted in corresponding locations such that no
two substantively heat-producing electrical components shadow each
other as discussed in more detail below. That is, no two electrical
components, which produce appreciable heat during operation (i.e.,
greater than a nominal heat sufficient enough to adversely impact
the cooling of another electrical component), are mounted to the
chassis-less circuit board substrate 602 linearly in-line with each
other along the direction of the airflow path 608 (i.e., along a
direction extending from the front edge 610 toward the rear edge
612 of the chassis-less circuit board substrate 602).
[0040] As discussed above, the illustrative sled 400 includes one
or more physical resources 620 mounted to a top side 650 of the
chassis-less circuit board substrate 602. Although two physical
resources 620 are shown in FIG. 6, it should be appreciated that
the sled 400 may include one, two, or more physical resources 620
in other embodiments. The physical resources 620 may be embodied as
any type of processor, controller, or other compute circuit capable
of performing various tasks such as compute functions and/or
controlling the functions of the sled 400 depending on, for
example, the type or intended functionality of the sled 400. For
example, as discussed in more detail below, the physical resources
620 may be embodied as high-performance processors in embodiments
in which the sled 400 is embodied as a compute sled, as accelerator
co-processors or circuits in embodiments in which the sled 400 is
embodied as an accelerator sled, storage controllers in embodiments
in which the sled 400 is embodied as a storage sled, or a set of
memory devices in embodiments in which the sled 400 is embodied as
a memory sled.
[0041] The sled 400 also includes one or more additional physical
resources 630 mounted to the top side 650 of the chassis-less
circuit board substrate 602. In the illustrative embodiment, the
additional physical resources include a network interface
controller (NIC) as discussed in more detail below. Of course,
depending on the type and functionality of the sled 400, the
physical resources 630 may include additional or other electrical
components, circuits, and/or devices in other embodiments.
[0042] The physical resources 620 are communicatively coupled to
the physical resources 630 via an input/output (I/O) subsystem 622.
The I/O subsystem 622 may be embodied as circuitry and/or
components to facilitate input/output operations with the physical
resources 620, the physical resources 630, and/or other components
of the sled 400. For example, the I/O subsystem 622 may be embodied
as, or otherwise include, memory controller hubs, input/output
control hubs, integrated sensor hubs, firmware devices,
communication links (e.g., point-to-point links, bus links, wires,
cables, light guides, printed circuit board traces, etc.), and/or
other components and subsystems to facilitate the input/output
operations. In the illustrative embodiment, the I/O subsystem 622
is embodied as, or otherwise includes, a double data rate 4 (DDR4)
data bus or a DDR5 data bus.
[0043] In some embodiments, the sled 400 may also include a
resource-to-resource interconnect 624. The resource-to-resource
interconnect 624 may be embodied as any type of communication
interconnect capable of facilitating resource-to-resource
communications. In the illustrative embodiment, the
resource-to-resource interconnect 624 is embodied as a high-speed
point-to-point interconnect (e.g., faster than the I/O subsystem
622). For example, the resource-to-resource interconnect 624 may be
embodied as a QuickPath Interconnect (QPI), an UltraPath
Interconnect (UPI), or other high-speed point-to-point interconnect
dedicated to resource-to-resource communications.
[0044] The sled 400 also includes a power connector 640 configured
to mate with a corresponding power connector of the rack 240 when
the sled 400 is mounted in the corresponding rack 240. The sled 400
receives power from a power supply of the rack 240 via the power
connector 640 to supply power to the various electrical components
of the sled 400. That is, the sled 400 does not include any local
power supply (i.e., an on-board power supply) to provide power to
the electrical components of the sled 400. The exclusion of a local
or on-board power supply facilitates the reduction in the overall
footprint of the chassis-less circuit board substrate 602, which
may increase the thermal cooling characteristics of the various
electrical components mounted on the chassis-less circuit board
substrate 602 as discussed above. In some embodiments, power is
provided to the processors 820 through vias directly under the
processors 820 (e.g., through the bottom side 750 of the
chassis-less circuit board substrate 602), providing an increased
thermal budget, additional current and/or voltage, and better
voltage control over typical boards.
[0045] In some embodiments, the sled 400 may also include mounting
features 642 configured to mate with a mounting arm, or other
structure, of a robot to facilitate the placement of the sled 600
in a rack 240 by the robot. The mounting features 642 may be
embodied as any type of physical structures that allow the robot to
grasp the sled 400 without damaging the chassis-less circuit board
substrate 602 or the electrical components mounted thereto. For
example, in some embodiments, the mounting features 642 may be
embodied as non-conductive pads attached to the chassis-less
circuit board substrate 602. In other embodiments, the mounting
features may be embodied as brackets, braces, or other similar
structures attached to the chassis-less circuit board substrate
602. The particular number, shape, size, and/or make-up of the
mounting feature 642 may depend on the design of the robot
configured to manage the sled 400.
[0046] Referring now to FIG. 7, in addition to the physical
resources 630 mounted on the top side 650 of the chassis-less
circuit board substrate 602, the sled 400 also includes one or more
memory devices 720 mounted to a bottom side 750 of the chassis-less
circuit board substrate 602. That is, the chassis-less circuit
board substrate 602 is embodied as a double-sided circuit board.
The physical resources 620 are communicatively coupled to the
memory devices 720 via the I/O subsystem 622. For example, the
physical resources 620 and the memory devices 720 may be
communicatively coupled by one or more vias extending through the
chassis-less circuit board substrate 602. Each physical resource
620 may be communicatively coupled to a different set of one or
more memory devices 720 in some embodiments. Alternatively, in
other embodiments, each physical resource 620 may be
communicatively coupled to each memory devices 720.
[0047] The memory devices 720 may be embodied as any type of memory
device capable of storing data for the physical resources 620
during operation of the sled 400, such as any type of volatile
(e.g., dynamic random access memory (DRAM), etc.) or non-volatile
memory. Volatile memory may be a storage medium that requires power
to maintain the state of data stored by the medium. Non-limiting
examples of volatile memory may include various types of random
access memory (RAM), such as dynamic random access memory (DRAM) or
static random access memory (SRAM). One particular type of DRAM
that may be used in a memory module is synchronous dynamic random
access memory (SDRAM). In particular embodiments, DRAM of a memory
component may comply with a standard promulgated by JEDEC, such as
JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3
SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR),
JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for
LPDDR4 (these standards are available at www.jedec.org). Such
standards (and similar standards) may be referred to as DDR-based
standards and communication interfaces of the storage devices that
implement such standards may be referred to as DDR-based
interfaces.
[0048] In one embodiment, the memory device is a block addressable
memory device, such as those based on NAND or NOR technologies. A
memory device may also include next-generation nonvolatile devices,
such as Intel 3D XPoint.TM. memory or other byte addressable
write-in-place nonvolatile memory devices. In one embodiment, the
memory device may be or may include memory devices that use
chalcogenide glass, multi-threshold level NAND flash memory, NOR
flash memory, single or multi-level Phase Change Memory (PCM), a
resistive memory, nanowire memory, ferroelectric transistor random
access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive
random access memory (MRAM) memory that incorporates memristor
technology, resistive memory including the metal oxide base, the
oxygen vacancy base and the conductive bridge Random Access Memory
(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic
junction memory based device, a magnetic tunneling junction (MTJ)
based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer)
based device, a thyristor based memory device, or a combination of
any of the above, or other memory. The memory device may refer to
the die itself and/or to a packaged memory product. In some
embodiments, the memory device may comprise a transistor-less
stackable cross point architecture in which memory cells sit at the
intersection of word lines and bit lines and are individually
addressable and in which bit storage is based on a change in bulk
resistance.
[0049] Referring now to FIG. 8, in some embodiments, the sled 400
may be embodied as a compute sled 800. The compute sled 800 is
optimized, or otherwise configured, to perform compute tasks. Of
course, as discussed above, the compute sled 800 may rely on other
sleds, such as acceleration sleds and/or storage sleds, to perform
such compute tasks. The compute sled 800 includes various physical
resources (e.g., electrical components) similar to the physical
resources of the sled 400, which have been identified in FIG. 8
using the same reference numbers. The description of such
components provided above in regard to FIGS. 6 and 7 applies to the
corresponding components of the compute sled 800 and is not
repeated herein for clarity of the description of the compute sled
800.
[0050] In the illustrative compute sled 800, the physical resources
620 are embodied as processors 820. Although only two processors
820 are shown in FIG. 8, it should be appreciated that the compute
sled 800 may include additional processors 820 in other
embodiments. Illustratively, the processors 820 are embodied as
high-performance processors 820 and may be configured to operate at
a relatively high power rating. Although the processors 820
generate additional heat operating at power ratings greater than
typical processors (which operate at around 155-230 W), the
enhanced thermal cooling characteristics of the chassis-less
circuit board substrate 602 discussed above facilitate the higher
power operation. For example, in the illustrative embodiment, the
processors 820 are configured to operate at a power rating of at
least 250 W. In some embodiments, the processors 820 may be
configured to operate at a power rating of at least 350 W.
[0051] In some embodiments, the compute sled 800 may also include a
processor-to-processor interconnect 842. Similar to the
resource-to-resource interconnect 624 of the sled 400 discussed
above, the processor-to-processor interconnect 842 may be embodied
as any type of communication interconnect capable of facilitating
processor-to-processor interconnect 842 communications. In the
illustrative embodiment, the processor-to-processor interconnect
842 is embodied as a high-speed point-to-point interconnect (e.g.,
faster than the I/O subsystem 622). For example, the
processor-to-processor interconnect 842 may be embodied as a
QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or
other high-speed point-to-point interconnect dedicated to
processor-to-processor communications.
[0052] The compute sled 800 also includes a communication circuit
830. The illustrative communication circuit 830 includes a network
interface controller (NIC) 832, which may also be referred to as a
host fabric interface (HFI). The NIC 832 may be embodied as, or
otherwise include, any type of integrated circuit, discrete
circuits, controller chips, chipsets, add-in-boards, daughtercards,
network interface cards, other devices that may be used by the
compute sled 800 to connect with another compute device (e.g., with
other sleds 400). In some embodiments, the NIC 832 may be embodied
as part of a system-on-a-chip (SoC) that includes one or more
processors, or included on a multichip package that also contains
one or more processors. In some embodiments, the NIC 832 may
include a local processor (not shown) and/or a local memory (not
shown) that are both local to the NIC 832. In such embodiments, the
local processor of the NIC 832 may be capable of performing one or
more of the functions of the processors 820. Additionally or
alternatively, in such embodiments, the local memory of the NIC 832
may be integrated into one or more components of the compute sled
at the board level, socket level, chip level, and/or other
levels.
[0053] The communication circuit 830 is communicatively coupled to
an optical data connector 834. The optical data connector 834 is
configured to mate with a corresponding optical data connector of
the rack 240 when the compute sled 800 is mounted in the rack 240.
Illustratively, the optical data connector 834 includes a plurality
of optical fibers which lead from a mating surface of the optical
data connector 834 to an optical transceiver 836. The optical
transceiver 836 is configured to convert incoming optical signals
from the rack-side optical data connector to electrical signals and
to convert electrical signals to outgoing optical signals to the
rack-side optical data connector. Although shown as forming part of
the optical data connector 834 in the illustrative embodiment, the
optical transceiver 836 may form a portion of the communication
circuit 830 in other embodiments.
[0054] In some embodiments, the compute sled 800 may also include
an expansion connector 840. In such embodiments, the expansion
connector 840 is configured to mate with a corresponding connector
of an expansion chassis-less circuit board substrate to provide
additional physical resources to the compute sled 800. The
additional physical resources may be used, for example, by the
processors 820 during operation of the compute sled 800. The
expansion chassis-less circuit board substrate may be substantially
similar to the chassis-less circuit board substrate 602 discussed
above and may include various electrical components mounted
thereto. The particular electrical components mounted to the
expansion chassis-less circuit board substrate may depend on the
intended functionality of the expansion chassis-less circuit board
substrate. For example, the expansion chassis-less circuit board
substrate may provide additional compute resources, memory
resources, and/or storage resources. As such, the additional
physical resources of the expansion chassis-less circuit board
substrate may include, but is not limited to, processors, memory
devices, storage devices, and/or accelerator circuits including,
for example, field programmable gate arrays (FPGA),
application-specific integrated circuits (ASICs), security
co-processors, graphics processing units (GPUs), machine learning
circuits, or other specialized processors, controllers, devices,
and/or circuits.
[0055] Referring now to FIG. 9, an illustrative embodiment of the
compute sled 800 is shown. As shown, the processors 820,
communication circuit 830, and optical data connector 834 are
mounted to the top side 650 of the chassis-less circuit board
substrate 602. Any suitable attachment or mounting technology may
be used to mount the physical resources of the compute sled 800 to
the chassis-less circuit board substrate 602. For example, the
various physical resources may be mounted in corresponding sockets
(e.g., a processor socket), holders, or brackets. In some cases,
some of the electrical components may be directly mounted to the
chassis-less circuit board substrate 602 via soldering or similar
techniques.
[0056] As discussed above, the individual processors 820 and
communication circuit 830 are mounted to the top side 650 of the
chassis-less circuit board substrate 602 such that no two
heat-producing, electrical components shadow each other. In the
illustrative embodiment, the processors 820 and communication
circuit 830 are mounted in corresponding locations on the top side
650 of the chassis-less circuit board substrate 602 such that no
two of those physical resources are linearly in-line with others
along the direction of the airflow path 608. It should be
appreciated that, although the optical data connector 834 is
in-line with the communication circuit 830, the optical data
connector 834 produces no or nominal heat during operation.
[0057] The memory devices 720 of the compute sled 800 are mounted
to the bottom side 750 of the of the chassis-less circuit board
substrate 602 as discussed above in regard to the sled 400.
Although mounted to the bottom side 750, the memory devices 720 are
communicatively coupled to the processors 820 located on the top
side 650 via the I/O subsystem 622. Because the chassis-less
circuit board substrate 602 is embodied as a double-sided circuit
board, the memory devices 720 and the processors 820 may be
communicatively coupled by one or more vias, connectors, or other
mechanisms extending through the chassis-less circuit board
substrate 602. Of course, each processor 820 may be communicatively
coupled to a different set of one or more memory devices 720 in
some embodiments. Alternatively, in other embodiments, each
processor 820 may be communicatively coupled to each memory device
720. In some embodiments, the memory devices 720 may be mounted to
one or more memory mezzanines on the bottom side of the
chassis-less circuit board substrate 602 and may interconnect with
a corresponding processor 820 through a ball-grid array.
[0058] Each of the processors 820 includes a heatsink 850 secured
thereto. Due to the mounting of the memory devices 720 to the
bottom side 750 of the chassis-less circuit board substrate 602 (as
well as the vertical spacing of the sleds 400 in the corresponding
rack 240), the top side 650 of the chassis-less circuit board
substrate 602 includes additional "free" area or space that
facilitates the use of heatsinks 850 having a larger size relative
to traditional heatsinks used in typical servers. Additionally, due
to the improved thermal cooling characteristics of the chassis-less
circuit board substrate 602, none of the processor heatsinks 850
include cooling fans attached thereto. That is, each of the
heatsinks 850 is embodied as a fan-less heatsinks.
[0059] Referring now to FIG. 10, in some embodiments, the sled 400
may be embodied as an accelerator sled 1000. The accelerator sled
1000 is optimized, or otherwise configured, to perform specialized
compute tasks, such as machine learning, encryption, hashing, or
other computational-intensive task. In some embodiments, for
example, a compute sled 800 may offload tasks to the accelerator
sled 1000 during operation. The accelerator sled 1000 includes
various components similar to components of the sled 400 and/or
compute sled 800, which have been identified in FIG. 10 using the
same reference numbers. The description of such components provided
above in regard to FIGS. 6, 7, and 8 apply to the corresponding
components of the accelerator sled 1000 and is not repeated herein
for clarity of the description of the accelerator sled 1000.
[0060] In the illustrative accelerator sled 1000, the physical
resources 620 are embodied as accelerator circuits 1020. Although
only two accelerator circuits 1020 are shown in FIG. 10, it should
be appreciated that the accelerator sled 1000 may include
additional accelerator circuits 1020 in other embodiments. For
example, as shown in FIG. 11, the accelerator sled 1000 may include
four accelerator circuits 1020 in some embodiments. The accelerator
circuits 1020 may be embodied as any type of processor,
co-processor, compute circuit, or other device capable of
performing compute or processing operations. For example, the
accelerator circuits 1020 may be embodied as, for example, field
programmable gate arrays (FPGA), application-specific integrated
circuits (ASICs), security co-processors, graphics processing units
(GPUs), machine learning circuits, or other specialized processors,
controllers, devices, and/or circuits.
[0061] In some embodiments, the accelerator sled 1000 may also
include an accelerator-to-accelerator interconnect 1042. Similar to
the resource-to-resource interconnect 624 of the sled 600 discussed
above, the accelerator-to-accelerator interconnect 1042 may be
embodied as any type of communication interconnect capable of
facilitating accelerator-to-accelerator communications. In the
illustrative embodiment, the accelerator-to-accelerator
interconnect 1042 is embodied as a high-speed point-to-point
interconnect (e.g., faster than the I/O subsystem 622). For
example, the accelerator-to-accelerator interconnect 1042 may be
embodied as a QuickPath Interconnect (QPI), an UltraPath
Interconnect (UPI), or other high-speed point-to-point interconnect
dedicated to processor-to-processor communications. In some
embodiments, the accelerator circuits 1020 may be daisy-chained
with a primary accelerator circuit 1020 connected to the NIC 832
and memory 720 through the I/O subsystem 622 and a secondary
accelerator circuit 1020 connected to the NIC 832 and memory 720
through a primary accelerator circuit 1020.
[0062] Referring now to FIG. 11, an illustrative embodiment of the
accelerator sled 1000 is shown. As discussed above, the accelerator
circuits 1020, communication circuit 830, and optical data
connector 834 are mounted to the top side 650 of the chassis-less
circuit board substrate 602. Again, the individual accelerator
circuits 1020 and communication circuit 830 are mounted to the top
side 650 of the chassis-less circuit board substrate 602 such that
no two heat-producing, electrical components shadow each other as
discussed above. The memory devices 720 of the accelerator sled
1000 are mounted to the bottom side 750 of the of the chassis-less
circuit board substrate 602 as discussed above in regard to the
sled 600. Although mounted to the bottom side 750, the memory
devices 720 are communicatively coupled to the accelerator circuits
1020 located on the top side 650 via the I/O subsystem 622 (e.g.,
through vias). Further, each of the accelerator circuits 1020 may
include a heatsink 1070 that is larger than a traditional heatsink
used in a server. As discussed above with reference to the
heatsinks 870, the heatsinks 1070 may be larger than tradition
heatsinks because of the "free" area provided by the memory devices
750 being located on the bottom side 750 of the chassis-less
circuit board substrate 602 rather than on the top side 650.
[0063] Referring now to FIG. 12, in some embodiments, the sled 400
may be embodied as a storage sled 1200. The storage sled 1200 is
optimized, or otherwise configured, to store data in a data storage
1250 local to the storage sled 1200. For example, during operation,
a compute sled 800 or an accelerator sled 1000 may store and
retrieve data from the data storage 1250 of the storage sled 1200.
The storage sled 1200 includes various components similar to
components of the sled 400 and/or the compute sled 800, which have
been identified in FIG. 12 using the same reference numbers. The
description of such components provided above in regard to FIGS. 6,
7, and 8 apply to the corresponding components of the storage sled
1200 and is not repeated herein for clarity of the description of
the storage sled 1200.
[0064] In the illustrative storage sled 1200, the physical
resources 620 are embodied as storage controllers 1220. Although
only two storage controllers 1220 are shown in FIG. 12, it should
be appreciated that the storage sled 1200 may include additional
storage controllers 1220 in other embodiments. The storage
controllers 1220 may be embodied as any type of processor,
controller, or control circuit capable of controlling the storage
and retrieval of data into the data storage 1250 based on requests
received via the communication circuit 830. In the illustrative
embodiment, the storage controllers 1220 are embodied as relatively
low-power processors or controllers. For example, in some
embodiments, the storage controllers 1220 may be configured to
operate at a power rating of about 75 watts.
[0065] In some embodiments, the storage sled 1200 may also include
a controller-to-controller interconnect 1242. Similar to the
resource-to-resource interconnect 624 of the sled 400 discussed
above, the controller-to-controller interconnect 1242 may be
embodied as any type of communication interconnect capable of
facilitating controller-to-controller communications. In the
illustrative embodiment, the controller-to-controller interconnect
1242 is embodied as a high-speed point-to-point interconnect (e.g.,
faster than the I/O subsystem 622). For example, the
controller-to-controller interconnect 1242 may be embodied as a
QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or
other high-speed point-to-point interconnect dedicated to
processor-to-processor communications.
[0066] Referring now to FIG. 13, an illustrative embodiment of the
storage sled 1200 is shown. In the illustrative embodiment, the
data storage 1250 is embodied as, or otherwise includes, a storage
cage 1252 configured to house one or more solid state drives (SSDs)
1254. To do so, the storage cage 1252 includes a number of mounting
slots 1256, each of which is configured to receive a corresponding
solid state drive 1254. Each of the mounting slots 1256 includes a
number of drive guides 1258 that cooperate to define an access
opening 1260 of the corresponding mounting slot 1256. The storage
cage 1252 is secured to the chassis-less circuit board substrate
602 such that the access openings face away from (i.e., toward the
front of) the chassis-less circuit board substrate 602. As such,
solid state drives 1254 are accessible while the storage sled 1200
is mounted in a corresponding rack 204. For example, a solid state
drive 1254 may be swapped out of a rack 240 (e.g., via a robot)
while the storage sled 1200 remains mounted in the corresponding
rack 240.
[0067] The storage cage 1252 illustratively includes sixteen
mounting slots 1256 and is capable of mounting and storing sixteen
solid state drives 1254. Of course, the storage cage 1252 may be
configured to store additional or fewer solid state drives 1254 in
other embodiments. Additionally, in the illustrative embodiment,
the solid state drivers are mounted vertically in the storage cage
1252, but may be mounted in the storage cage 1252 in a different
orientation in other embodiments. Each solid state drive 1254 may
be embodied as any type of data storage device capable of storing
long term data. To do so, the solid state drives 1254 may include
volatile and non-volatile memory devices discussed above.
[0068] As shown in FIG. 13, the storage controllers 1220, the
communication circuit 830, and the optical data connector 834 are
illustratively mounted to the top side 650 of the chassis-less
circuit board substrate 602. Again, as discussed above, any
suitable attachment or mounting technology may be used to mount the
electrical components of the storage sled 1200 to the chassis-less
circuit board substrate 602 including, for example, sockets (e.g.,
a processor socket), holders, brackets, soldered connections,
and/or other mounting or securing techniques.
[0069] As discussed above, the individual storage controllers 1220
and the communication circuit 830 are mounted to the top side 650
of the chassis-less circuit board substrate 602 such that no two
heat-producing, electrical components shadow each other. For
example, the storage controllers 1220 and the communication circuit
830 are mounted in corresponding locations on the top side 650 of
the chassis-less circuit board substrate 602 such that no two of
those electrical components are linearly in-line with other along
the direction of the airflow path 608.
[0070] The memory devices 720 of the storage sled 1200 are mounted
to the bottom side 750 of the of the chassis-less circuit board
substrate 602 as discussed above in regard to the sled 400.
Although mounted to the bottom side 750, the memory devices 720 are
communicatively coupled to the storage controllers 1220 located on
the top side 650 via the I/O subsystem 622. Again, because the
chassis-less circuit board substrate 602 is embodied as a
double-sided circuit board, the memory devices 720 and the storage
controllers 1220 may be communicatively coupled by one or more
vias, connectors, or other mechanisms extending through the
chassis-less circuit board substrate 602. Each of the storage
controllers 1220 includes a heatsink 1270 secured thereto. As
discussed above, due to the improved thermal cooling
characteristics of the chassis-less circuit board substrate 602 of
the storage sled 1200, none of the heatsinks 1270 include cooling
fans attached thereto. That is, each of the heatsinks 1270 is
embodied as a fan-less heatsink.
[0071] Referring now to FIG. 14, in some embodiments, the sled 400
may be embodied as a memory sled 1400. The storage sled 1400 is
optimized, or otherwise configured, to provide other sleds 400
(e.g., compute sleds 800, accelerator sleds 1000, etc.) with access
to a pool of memory (e.g., in two or more sets 1430, 1432 of memory
devices 720) local to the memory sled 1200. For example, during
operation, a compute sled 800 or an accelerator sled 1000 may
remotely write to and/or read from one or more of the memory sets
1430, 1432 of the memory sled 1200 using a logical address space
that maps to physical addresses in the memory sets 1430, 1432. The
memory sled 1400 includes various components similar to components
of the sled 400 and/or the compute sled 800, which have been
identified in FIG. 14 using the same reference numbers. The
description of such components provided above in regard to FIGS. 6,
7, and 8 apply to the corresponding components of the memory sled
1400 and is not repeated herein for clarity of the description of
the memory sled 1400.
[0072] In the illustrative memory sled 1400, the physical resources
620 are embodied as memory controllers 1420. Although only two
memory controllers 1420 are shown in FIG. 14, it should be
appreciated that the memory sled 1400 may include additional memory
controllers 1420 in other embodiments. The memory controllers 1420
may be embodied as any type of processor, controller, or control
circuit capable of controlling the writing and reading of data into
the memory sets 1430, 1432 based on requests received via the
communication circuit 830. In the illustrative embodiment, each
storage controller 1220 is connected to a corresponding memory set
1430, 1432 to write to and read from memory devices 720 within the
corresponding memory set 1430, 1432 and enforce any permissions
(e.g., read, write, etc.) associated with sled 400 that has sent a
request to the memory sled 1400 to perform a memory access
operation (e.g., read or write).
[0073] In some embodiments, the memory sled 1400 may also include a
controller-to-controller interconnect 1442. Similar to the
resource-to-resource interconnect 624 of the sled 400 discussed
above, the controller-to-controller interconnect 1442 may be
embodied as any type of communication interconnect capable of
facilitating controller-to-controller communications. In the
illustrative embodiment, the controller-to-controller interconnect
1442 is embodied as a high-speed point-to-point interconnect (e.g.,
faster than the I/O subsystem 622). For example, the
controller-to-controller interconnect 1442 may be embodied as a
QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or
other high-speed point-to-point interconnect dedicated to
processor-to-processor communications. As such, in some
embodiments, a memory controller 1420 may access, through the
controller-to-controller interconnect 1442, memory that is within
the memory set 1432 associated with another memory controller 1420.
In some embodiments, a scalable memory controller is made of
multiple smaller memory controllers, referred to herein as
"chiplets", on a memory sled (e.g., the memory sled 1400). The
chiplets may be interconnected (e.g., using EMIB (Embedded
Multi-Die Interconnect Bridge)). The combined chiplet memory
controller may scale up to a relatively large number of memory
controllers and I/O ports, (e.g., up to 16 memory channels). In
some embodiments, the memory controllers 1420 may implement a
memory interleave (e.g., one memory address is mapped to the memory
set 1430, the next memory address is mapped to the memory set 1432,
and the third address is mapped to the memory set 1430, etc.). The
interleaving may be managed within the memory controllers 1420, or
from CPU sockets (e.g., of the compute sled 800) across network
links to the memory sets 1430, 1432, and may improve the latency
associated with performing memory access operations as compared to
accessing contiguous memory addresses from the same memory
device.
[0074] Further, in some embodiments, the memory sled 1400 may be
connected to one or more other sleds 400 (e.g., in the same rack
240 or an adjacent rack 240) through a waveguide, using the
waveguide connector 1480. In the illustrative embodiment, the
waveguides are 64 millimeter waveguides that provide 16 Rx (i.e.,
receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the
illustrative embodiment, is either 16 Ghz or 32 Ghz. In other
embodiments, the frequencies may be different. Using a waveguide
may provide high throughput access to the memory pool (e.g., the
memory sets 1430, 1432) to another sled (e.g., a sled 400 in the
same rack 240 or an adjacent rack 240 as the memory sled 1400)
without adding to the load on the optical data connector 834.
[0075] Referring now to FIG. 15, a system for executing one or more
workloads (e.g., applications) may be implemented in accordance
with the data center 100. In the illustrative embodiment, the
system 1510 includes an orchestrator server 1520, which may be
embodied as a managed node comprising a compute device (e.g., a
compute sled 800) executing management software (e.g., a cloud
operating environment, such as OpenStack) that is communicatively
coupled to multiple sleds 400 including a large number of compute
sleds 1530 (e.g., each similar to the compute sled 800), memory
sleds 1540 (e.g., each similar to the memory sled 1400),
accelerator sleds 1550 (e.g., each similar to the memory sled
1000), and storage sleds 1560 (e.g., each similar to the storage
sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 may be
grouped into a managed node 1570, such as by the orchestrator
server 1520, to collectively perform a workload (e.g., an
application 1232 executed in a virtual machine or in a container).
The managed node 1570 may be embodied as an assembly of physical
resources 620, such as processors 820, memory resources 720,
accelerator circuits 1020, or data storage 1250, from the same or
different sleds 400. Further, the managed node may be established,
defined, or "spun up" by the orchestrator server 1520 at the time a
workload is to be assigned to the managed node or at any other
time, and may exist regardless of whether any workloads are
presently assigned to the managed node. In the illustrative
embodiment, the orchestrator server 1520 may selectively allocate
and/or deallocate physical resources 620 from the sleds 400 and/or
add or remove one or more sleds 400 from the managed node 1570 as a
function of quality of service (QoS) targets (e.g., performance
targets associated with a throughput, latency, instructions per
second, etc.) associated with a service level agreement for the
workload (e.g., the application 1532). In doing so, the
orchestrator server 1520 may receive telemetry data indicative of
performance conditions (e.g., throughput, latency, instructions per
second, etc.) in each sled 400 of the managed node 1570 and compare
the telemetry data to the quality of service targets to determine
whether the quality of service targets are being satisfied. If the
so, the orchestrator server 1520 may additionally determine whether
one or more physical resources may be deallocated from the managed
node 1570 while still satisfying the QoS targets, thereby freeing
up those physical resources for use in another managed node (e.g.,
to execute a different workload). Alternatively, if the QoS targets
are not presently satisfied, the orchestrator server 1520 may
determine to dynamically allocate additional physical resources to
assist in the execution of the workload (e.g., the application
1532) while the workload is executing
[0076] Additionally, in some embodiments, the orchestrator server
1520 may identify trends in the resource utilization of the
workload (e.g., the application 1532), such as by identifying
phases of execution (e.g., time periods in which different
operations, each having different resource utilizations
characteristics, are performed) of the workload (e.g., the
application 1532) and pre-emptively identifying available resources
in the data center 100 and allocating them to the managed node 1570
(e.g., within a predefined time period of the associated phase
beginning). In some embodiments, the orchestrator server 1520 may
model performance based on various latencies and a distribution
scheme to place workloads among compute sleds and other resources
(e.g., accelerator sleds, memory sleds, storage sleds) in the data
center 100. For example, the orchestrator server 1520 may utilize a
model that accounts for the performance of resources on the sleds
400 (e.g., FPGA performance, memory access latency, etc.) and the
performance (e.g., congestion, latency, bandwidth) of the path
through the network to the resource (e.g., FPGA). As such, the
orchestrator server 1520 may determine which resource(s) should be
used with which workloads based on the total latency associated
with each potential resource available in the data center 100
(e.g., the latency associated with the performance of the resource
itself in addition to the latency associated with the path through
the network between the compute sled executing the workload and the
sled 400 on which the resource is located).
[0077] In some embodiments, the orchestrator server 1520 may
generate a map of heat generation in the data center 100 using
telemetry data (e.g., temperatures, fan speeds, etc.) reported from
the sleds 400 and allocate resources to managed nodes as a function
of the map of heat generation and predicted heat generation
associated with different workloads, to maintain a target
temperature and heat distribution in the data center 100.
Additionally or alternatively, in some embodiments, the
orchestrator server 1520 may organize received telemetry data into
a hierarchical model that is indicative of a relationship between
the managed nodes (e.g., a spatial relationship such as the
physical locations of the resources of the managed nodes within the
data center 100 and/or a functional relationship, such as groupings
of the managed nodes by the customers the managed nodes provide
services for, the types of functions typically performed by the
managed nodes, managed nodes that typically share or exchange
workloads among each other, etc.). Based on differences in the
physical locations and resources in the managed nodes, a given
workload may exhibit different resource utilizations (e.g., cause a
different internal temperature, use a different percentage of
processor or memory capacity) across the resources of different
managed nodes. The orchestrator server 1520 may determine the
differences based on the telemetry data stored in the hierarchical
model and factor the differences into a prediction of future
resource utilization of a workload if the workload is reassigned
from one managed node to another managed node, to accurately
balance resource utilization in the data center 100.
[0078] To reduce the computational load on the orchestrator server
1520 and the data transfer load on the network, in some
embodiments, the orchestrator server 1520 may send self-test
information to the sleds 400 to enable each sled 400 to locally
(e.g., on the sled 400) determine whether telemetry data generated
by the sled 400 satisfies one or more conditions (e.g., an
available capacity that satisfies a predefined threshold, a
temperature that satisfies a predefined threshold, etc.). Each sled
400 may then report back a simplified result (e.g., yes or no) to
the orchestrator server 1520, which the orchestrator server 1520
may utilize in determining the allocation of resources to managed
nodes.
[0079] Referring now to FIG. 16, a system 1610 for providing
efficient remote access to the memory of accelerator devices on an
accelerator sled may be implemented in accordance with the data
center 100 described above with reference to FIGS. 1-15. In the
illustrative embodiment, the system 1610 includes an orchestrator
server 1620 communicatively coupled to multiple sleds including a
compute sled 1630 and an accelerator sled 1640. One or more of the
sleds 1630, 1640 may be grouped into a managed node, such as by the
orchestrator server 1620, to collectively perform a workload (e.g.,
an application 1632). A managed node may be embodied as an assembly
of resources (e.g., physical resources 620), such as compute
resources, memory resources, storage resources, or other resources
(e.g., accelerator resources), from the same or different sleds
(e.g., the sleds 400, 800, 1000, 1200, 1400, etc.) or racks (e.g.,
one or more racks 240). Further, a managed node may be established,
defined, or "spun up" by the orchestrator server 1620 at the time a
workload is to be assigned to the managed node or at any other
time, and may exist regardless of whether any workloads are
presently assigned to the managed node. The system 1610 may be
located in a data center and provide storage and compute services
(e.g., cloud services) to a client device 1614 that is in
communication with the system 1610 through a network 1612. The
orchestrator server 1620 may support a cloud operating environment,
such as OpenStack, and managed nodes established by the
orchestrator server 1620 may execute one or more applications or
processes (i.e., workloads), such as in virtual machines or
containers, on behalf of a user of the client device 1614.
[0080] In the illustrative embodiment, the compute sled 1630 is
similar to the sled 800 of FIG. 8, and, in operation, executes the
application 1632 (e.g., a workload). The accelerator sled 1640
includes a network interface controller (NIC) 1652 connected to
multiple accelerator devices 1660. In the illustrative embodiment,
the NIC 1652 includes a memory access logic unit 1654 connected to
one or more accelerator devices 1670, 1674. The accelerator devices
1670, 1674 may be connected with other accelerator devices 1672,
1676, which are indirectly connected to the memory access logic
unit 1654. Each accelerator device 1660 may be embodied as any
device or circuitry (e.g., a field-programmable gate array (FPGA),
an application specific integrated circuit (ASIC), a specialized
processor, etc.) capable of performing a function at a speed
greater than a general purpose processor could execute the
function. Further, each accelerator device 1660 has a corresponding
memory 1680, 1682, 1684, 1686 and each memory may include a
register space 1690, 1692, 1694, 1696 which may include control and
status registers usable to control the operation and check the
status of the corresponding accelerator device 1660. The memory
access logic unit 1654 may be embodied as any device or circuitry
(e.g., an application specific integrated circuit (ASIC), a
specialized processor, etc.) capable of enabling the NIC 1652 to
perform direct memory access operations on the memory of the
accelerator devices 1660, rather than relying on a general purpose
processor to act as an intermediary between the NIC 1652 and the
memory of the accelerator devices 1660 (e.g., a single direct
memory access operation on the memory 1680, rather than a memory
access operation on a memory associated with a general purpose
processor followed by a memory access operation from the general
purpose processor's memory to the memory 1680). As such, the memory
access logic unit 1654 enables the compute sled 1630 to more
efficiently perform remote direct memory access operations (e.g.,
direct memory access operations on behalf of a remote compute
device) on the memory of any accelerator device 1660 and increase
the speed at which workloads are performed.
[0081] Referring now to FIG. 17, the accelerator sled 1640 may be
embodied as any type of compute device capable of performing the
functions described herein, including determining a memory address
region usable by a remote compute device to access the memory of an
accelerator device on the accelerator sled, receiving, from the
remote compute device, a memory access request to remotely access
the memory of the accelerator device associated with the memory
address region, and performing, in response to the memory access
request, a direct memory access operation on the memory. As shown
in FIG. 17, the illustrative accelerator sled 1640 includes
communication circuitry 1702, an input/output (I/O) subsystem 1704,
and one or more accelerator devices 1660. The accelerator sled 1640
may also include a compute engine 1706. Of course, in other
embodiments, the accelerator sled 1640 may include other or
additional components, such as those commonly found in a computer
(e.g., display, peripheral devices, etc.). Additionally, in some
embodiments, one or more of the illustrative components may be
incorporated in, or otherwise form a portion of, another
component.
[0082] The compute engine 1706, if included in the accelerator sled
1640, may be embodied as any type of device or collection of
devices capable of performing various compute functions described
below. In some embodiments, the compute engine 1706 may be embodied
as a single device such as an integrated circuit, an embedded
system, a field-programmable gate array (FPGA), a system-on-a-chip
(SOC), or other integrated system or device. In the illustrative
embodiment, the compute engine 1706 includes or is embodied as a
processor 1708 and a memory 1710. The processor 1708 may be
embodied as any type of device or circuitry capable of performing
general computations and management of other components of the
accelerator sled 1640. For example, the processor 1708 may be
embodied as a microcontroller, a single or multi-core processor(s),
or other processor or processing/controlling circuit. In some
embodiments, the processor 1708 may be embodied as, include, or be
coupled to an FPGA, an application specific integrated circuit
(ASIC), reconfigurable hardware or hardware circuitry, or other
specialized hardware to facilitate performance of the functions
described herein.
[0083] The memory 1710 may be embodied as any type of volatile
(e.g., dynamic random access memory (DRAM), etc.) or non-volatile
memory or data storage capable of performing the functions
described herein. Volatile memory may be a storage medium that
requires power to maintain the state of data stored by the medium.
Non-limiting examples of volatile memory may include various types
of random access memory (RAM), such as dynamic random access memory
(DRAM) or static random access memory (SRAM). One particular type
of DRAM that may be used in a memory module is synchronous dynamic
random access memory (SDRAM). In particular embodiments, DRAM of a
memory component may comply with a standard promulgated by JEDEC,
such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F
for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR
(LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4
for LPDDR4 (these standards are available at www.jedec.org). Such
standards (and similar standards) may be referred to as DDR-based
standards and communication interfaces of the storage devices that
implement such standards may be referred to as DDR-based
interfaces.
[0084] In one embodiment, the memory device is a block addressable
memory device, such as those based on NAND or NOR technologies. A
memory device may also include future generation nonvolatile
devices, such as a three dimensional crosspoint memory device
(e.g., Intel 3D XPoint.TM. memory), or other byte addressable
write-in-place nonvolatile memory devices. In one embodiment, the
memory device may be or may include memory devices that use
chalcogenide glass, multi-threshold level NAND flash memory, NOR
flash memory, single or multi-level Phase Change Memory (PCM), a
resistive memory, nanowire memory, ferroelectric transistor random
access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive
random access memory (MRAM) memory that incorporates memristor
technology, resistive memory including the metal oxide base, the
oxygen vacancy base and the conductive bridge Random Access Memory
(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic
junction memory based device, a magnetic tunneling junction (MTJ)
based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer)
based device, a thyristor based memory device, or a combination of
any of the above, or other memory. The memory device may refer to
the die itself and/or to a packaged memory product.
[0085] In some embodiments, 3D crosspoint memory (e.g., Intel 3D
XPoint.TM. memory) may comprise a transistor-less stackable cross
point architecture in which memory cells sit at the intersection of
word lines and bit lines and are individually addressable and in
which bit storage is based on a change in bulk resistance. In some
embodiments, all or a portion of the memory 1710 may be integrated
into the processor 1708. In operation, the memory 1710 may store
various software and data used during operation such as
applications, programs, and libraries.
[0086] The components of the accelerator sled 1640 are connected
together via the I/O subsystem 1704, which may be embodied as
circuitry and/or devices to facilitate input/output operations with
the communication circuitry 1702, the accelerator device(s) 1660,
the compute engine 1706, and other components of the accelerator
sled 1640. For example, the I/O subsystem 1704 may be embodied as,
or otherwise include, memory controller hubs, input/output control
hubs, integrated sensor hubs, firmware devices, communication links
(e.g., point-to-point links, bus links, wires, cables, light
guides, printed circuit board traces, etc.), and/or other
components and subsystems to facilitate the input/output
operations. In some embodiments, the I/O subsystem 1704 may form a
portion of a system-on-a-chip (SoC) and be incorporated into one or
more other components of the accelerator sled 1640.
[0087] The communication circuitry 1702 may be embodied as any
communication circuit, device, or collection thereof, capable of
enabling communications over the network 1612 between the
accelerator sled 1640 and another compute device (e.g., the compute
sled 1630 or the orchestrator server 1620). The communication
circuitry 1702 may be configured to use any one or more
communication technology (e.g., wired or wireless communications)
and associated protocols (e.g., Ethernet, Bluetooth.RTM.,
Wi-Fi.RTM., WiMAX, etc.) to effect such communication.
[0088] The communication circuitry 1702, in the illustrative
embodiment, includes a network interface controller (NIC) 1652,
which may also be referred to as a host fabric interface (HFI). The
NIC 1652 may be embodied as one or more add-in-boards, daughter
cards, network interface cards, controller chips, chipsets, or
other devices that may be used by the accelerator sled 1640 to
connect with another compute device (e.g., the compute sled 1630,
the orchestrator server 1620, etc.). In some embodiments, the NIC
1652 may be embodied as part of a system-on-a-chip (SoC) that
includes one or more processors, or included on a multichip package
that also contains one or more processors. In some embodiments, the
NIC 1652 may include a local processor (not shown) and/or a local
memory (not shown) that are both local to the NIC 1652.
Additionally or alternatively, in such embodiments, the local
memory of the NIC 1652 may be integrated into one or more
components of the accelerator sled 1640 at the board level, socket
level, chip level, and/or other levels. In the illustrative
embodiment, the NIC 1652 additionally includes the memory access
logic unit 1654, described above with reference to FIG. 16.
[0089] The accelerator devices 1660, in the illustrative
embodiment, include a set of primary FPGAs (e.g., FPGAs that are
connected directly to the NIC 1652 through a local bus such as a
peripheral component interconnect express (PCIe) bus), in which
each primary FPGA 1720 operates as a PCIe root device (e.g., a PCIe
root complex) and the NIC 1652 operates as a PCIe endpoint device.
Additionally, the accelerator devices 1660 may include one or more
secondary FPGAs 1730 that are daisy-chained (e.g., connected to
another FPGA, such as a primary FPGA 1720) and, as such, are
indirectly connected to the NIC 1652. Each FPGA 1720, 1730 is
connected to a corresponding memory 1722, 1732, similar to the
memory 1710. Each memory 1722, 1732 may include a register space,
similar to the register spaces 1690, 1692, 1694, 1696 described
with reference to FIG. 16.
[0090] The accelerator sled 1640 may also include one or more data
storage devices 1740, which may be embodied as any type of devices
configured for short-term or long-term storage of data such as, for
example, memory devices and circuits, memory cards, hard disk
drives, solid-state drives, or other data storage devices. Each
data storage device 1740 may include a system partition that stores
data and firmware code for the data storage device 1740. Each data
storage device 1740 may also include one or more operating system
partitions that store data files and executables for operating
systems.
[0091] The orchestrator server 1620, the compute sled 1630, and the
client device 1614 may have components similar to those described
in FIG. 17, with the exception that, in some embodiments,
orchestrator server 1620, the compute sled 1630, and/or the client
device 1614 may not include the accelerator devices 1660 or the
memory access logic unit 1654. The description of those components
of the accelerator sled 1640 is equally applicable to the
description of components of those devices and is not repeated
herein for clarity of the description. Further, it should be
appreciated that any of the accelerator sled 1640, the compute sled
1630, the orchestrator server 1620, or the client device 1614 may
include other components, sub-components, and devices commonly
found in a computing device, which are not discussed above in
reference to the accelerator sled 1640 and not discussed herein for
clarity of the description.
[0092] As described above, the orchestrator server 1620, the sleds
1630, 1640, and the client device 1614 are illustratively in
communication via the network 1612, which may be embodied as any
type of wired or wireless communication network, including global
networks (e.g., the Internet), local area networks (LANs) or wide
area networks (WANs), cellular networks (e.g., Global System for
Mobile Communications (GSM), 3G, Long Term Evolution (LTE),
Worldwide Interoperability for Microwave Access (WiMAX), etc.),
digital subscriber line (DSL) networks, cable networks (e.g.,
coaxial networks, fiber networks, etc.), or any combination
thereof.
[0093] Referring now to FIG. 18, the accelerator sled 1640 may
establish an environment 1800 during operation. The illustrative
environment 1800 includes a network communicator 1820 and a memory
access manager 1830. Each of the components of the environment 1800
may be embodied as hardware, firmware, software, or a combination
thereof. As such, in some embodiments, one or more of the
components of the environment 1800 may be embodied as circuitry or
a collection of electrical devices (e.g., network communicator
circuitry 1820, memory access manager circuitry 1830, etc.). It
should be appreciated that, in such embodiments, one or more of the
network communicator circuitry 1820 or the memory access manager
circuitry 1830 may form a portion of one or more of the
communication circuitry 1702, the NIC 1652, the memory access logic
unit 1654, the accelerator devices 1660, the I/O subsystem 1704,
and/or other components of the accelerator sled 1640. In the
illustrative embodiment, the environment 1800 includes memory
address data 1802, which may be embodied as any data indicative of
address regions (e.g., sets of contiguous memory addresses) mapped
to each of the accelerator devices 1660, including regions usable
for temporary data, such as input data sets to be operated on,
output data sets, bit streams (e.g., data that defines a function
that can be executed by a corresponding accelerator device 1660),
and register spaces (e.g., memory usable to issue user-level
requests, such as to load a bit stream, to execute a function
defined by a bit stream on an input data set present in the memory,
or to check the status of execution of a function). Additionally,
in the illustrative embodiment, the environment 1800 includes queue
data 1804, which may be embodied as any data indicative of queues
for read operations (e.g., read queues) and queues for write
operations (e.g., write queues) associated with each accelerator
device 1660. Additionally, in the illustrative embodiment, the
queue data 1804 includes related data about the queues, including a
starting memory address of each queue, a length of each queue, and
a unique identifier (e.g., a key) associated with each queue.
Further, in the illustrative embodiment, the environment 1800
includes remotely accessible data 1806 which may be embodied as
data in the memory 1722, 1732 that is present in the regions that
are mapped to the addresses in the memory address data 1802 and is
available to a remote compute device (e.g., the compute sled 1630)
for remote access (e.g., via the memory access logic unit
1654).
[0094] In the illustrative environment 1800, the network
communicator 1820, which may be embodied as hardware, firmware,
software, virtualized hardware, emulated architecture, and/or a
combination thereof as discussed above, is configured to facilitate
inbound and outbound network communications (e.g., network traffic,
network packets, network flows, etc.) to and from the accelerator
sled 1640, respectively. To do so, the network communicator 1820 is
configured to receive and process data packets from one system or
computing device (e.g., the compute sled 1630, the orchestrator
server 1620, etc.) and to prepare and send data packets to a
computing device or system (e.g., the compute sled 1630, the
orchestrator server 1620, etc.). Accordingly, in some embodiments,
at least a portion of the functionality of the network communicator
1820 may be performed by the communication circuitry 1702, and, in
the illustrative embodiment, by the NIC 1652.
[0095] The memory access manager 1830, which may be embodied as
hardware, firmware, software, virtualized hardware, emulated
architecture, and/or a combination thereof, is configured to route
memory access requests from a remote compute device (e.g., the
compute sled 1630) to the corresponding accelerator devices 1660 as
direct memory access operations (e.g., without relying on a general
purpose processor as an intermediary) to reduce the latency that
may otherwise be incurred in performing write or read operations on
the memories of the accelerator devices 1660. To do so, in the
illustrative embodiment, the memory access manager 1830 includes an
address establisher 1832, a write manager 1834, and a read manager
1836.
[0096] The address establisher 1832, in the illustrative
embodiment, is configured to establish (e.g., determine) the memory
addresses to be mapped to regions of memory (e.g., random access
memory (RAM), registers, etc.) that are to be remotely accessible
by the compute sled 1630 or another remote compute device. In some
embodiments, the address establisher may additionally establish
queue pairs (e.g., a read queue and a write queue) for use in
tracking the completion of remote direct memory access operations
that have been requested (e.g., by the compute sled 1630) on the
memory 1722, 1732 of a corresponding accelerator device 1660.
[0097] The write manager 1834, in the illustrative embodiment, is
configured to manage the execution of write operations that have
been requested by the compute sled 1630 or another remote compute
device to corresponding memories 1722, 1732 (e.g., based on a
memory address included in the request). Additionally, the read
manager 1836 is configured to manage the execution of read
operations that have been requested by the compute sled 1630 or
another remote compute device to the corresponding memories 1722,
1732 (e.g., based on a memory address included in the request). As
described above, the write operations and read operations, in the
illustrative embodiment, are performed as direct memory access
operations (e.g., data is copied from the NIC 1652 directly to a
memory (e.g., the memory 1722) of an accelerator device (e.g., the
FPGA 1720), without relying on an intermediate stage of copying the
data to the memory associated with a general purpose processor
(e.g., the memory 1710). It should be appreciated that each of the
address establisher 1832, the write manager 1834, and the read
manager 1836 may be separately embodied as hardware, firmware,
software, virtualized hardware, emulated architecture, and/or a
combination thereof. For example, the address establisher 1832 may
be embodied as a hardware component, while the write manger 1834
and the read manager 1836 are embodied as virtualized hardware
components or as some other combination of hardware, firmware,
software, virtualized hardware, emulated architecture, and/or a
combination thereof.
[0098] Referring now to FIG. 19, the accelerator sled 1640, in
operation, may execute a method 1900 for providing efficient access
to memory (e.g., the memory 1722, 1732) of the accelerator
device(s) 1660. The method 1900 begins with block 1902, in which
the accelerator sled 1640 determines whether to enable efficient
remote access to the memory (e.g., the memory 1722, 1732). The
accelerator sled 1640 may determine to enable efficient remote
access to the memory in response to receiving a notification from
the orchestrator server 1620 that one of the accelerator devices
1660 has been allocated for use by the compute sled 1630. In other
embodiments, the accelerator sled 1640 may determine to enable
efficient remote memory access based on other factors (e.g., by
default, pursuant to a configuration setting, etc.). Regardless, in
response to a determination to enable efficient remote memory
access, the method 1900 advances to block 1904, in which the
accelerator sled 1640 determines memory address regions usable by a
remote compute device (e.g., the compute sled 1630) to access the
memory 1722, 1732 of the accelerator devices 1660. In doing so, in
the illustrative embodiment, the accelerator sled 1640 determines
the memory addresses with the NIC 1652 (e.g., with the memory
access logic unit 1654 of the NIC 1652), as indicated in block
1906. In determining the memory address regions, the accelerator
sled 1640, in the illustrative embodiment, determines a random
access memory (RAM) region in the memory (e.g., the memory 1722 of
the accelerator device 1660) to be accessible by the compute sled
1630, as indicated in block 1908. The RAM region may be used to
write a bit stream and/or an input data set to be operated on,
and/or to read output data resulting from the execution of a
function defined by the bit stream. In some embodiments, the RAM
region may be of a predefined size, of a size reported by the
accelerator device 1660 (e.g., during a power-on process or in
response to a query), or of a size requested by the compute sled
1630. Additionally, the accelerator sled 1640 determines a register
region for each accelerator device 1660 (e.g., a section of the
memory 1722 that contains one or more control and status
registers), as indicated in block 1910. The register region may be
used by the compute sled 1630 to issue requests to the
corresponding accelerator device 1660 to perform operations (e.g.,
to configure the accelerator device 1660 with a bit stream that has
been written to the RAM, to execute the function associated with
the bit stream, etc.) and/or to read a status of the accelerator
device 1660 (e.g., whether execution of a function has completed).
In determining the memory address regions, the accelerator sled
1640, in the illustrative embodiment, assigns a unique base address
to each accelerator device 1660, as indicated in block 1912. In
doing so, and as indicated in block 1914, the accelerator sled 1640
increments the base address to be assigned to each accelerator
device 1660 by a predefined amount. For example, and as indicated
in block 1916, the accelerator sled 1640 may increment the base
address by 16 terabytes.
[0099] Additionally, in the illustrative embodiment, the
accelerator sled 1640 assigns addresses for the register region(s),
as indicated in block 1918. In doing so, the accelerator sled 1640
may assign an address space for administrative register(s) (e.g.,
registers usable to request the accelerator device 1660 to reset,
power down, etc.), as indicated in block 1920. Further, and as
indicated in block 1922, the accelerator sled 1640 assigns the
address space to a predefined offset from the base address
corresponding to each present accelerator device 1660. The
accelerator sled 1640 may prevent the compute sled 1630 from
accessing the address space associated with administrative
operations (e.g., pursuant to a set of permissions associated with
the workload 1632). Additionally, in the illustrative embodiment
and as indicated in block 1924, the accelerator sled 1640 assigns
an address space for user-level register(s) (e.g., register(s)
usable to request the accelerator device 1660 to execute a function
that was offloaded from the compute sled 1630, etc.). As indicated
in block 1926, the accelerator sled 1640, in the illustrative
embodiment, assigns an address space for user bit stream operations
(e.g., register(s) usable to request the accelerator device 1660 to
configure itself with a bit stream that is present in the RAM).
Further, as indicated in block 1928, the accelerator sled 1640, in
the illustrative embodiment, provides data indicative of the
determined memory address regions to a remote compute device (e.g.,
the compute sled 1630). Subsequently, the method 1900 advances to
block 1930 of FIG. 20, in which the accelerator sled 1640
establishes queues for remote direct memory access. As described
above, the queues are usable to track requests to read or write to
the memory of the corresponding accelerator device 1660.
[0100] Referring now to FIG. 20, in establishing the queues, the
accelerator sled 1640 establishes a write queue for each
accelerator device 1660, as indicated in block 1932. In doing so,
the accelerator sled 1640 may establish a write queue having a
length that was requested by a remote compute device (e.g., by the
compute sled 1630 or by the orchestrator server 1620), as indicated
in block 1934. Additionally, and as indicated in block 1936, the
accelerator sled establishes a read queue for each accelerator
device 1660. In doing so, the accelerator sled 1640 may establish a
read queue having a length requested by a remote compute device
(e.g., the compute sled 1630 or the orchestrator server 1620), as
indicated in block 1938. Further, as indicated in block 1940, the
accelerator sled 1640 may provide, to a remote compute device
(e.g., the compute sled 1630) a unique identifier (e.g., a key)
usable to identify an established queue (e.g., a read queue or a
write queue associated with one of the accelerator devices 1660),
such as in a memory access request.
[0101] Subsequently, in block 1942, the accelerator sled 1640 may
receive a request (e.g., from the compute sled 1630) to remotely
access the memory of one of the accelerator devices 1660. The
accelerator sled 1640, in the illustrative embodiment, receives the
request at the NIC 1652, as indicated in block 1944. Further, as
indicated in block 1946, the accelerator sled 1546 may receive a
request that identifies a memory address to access. As indicated in
block 1948, the accelerator sled 1640 may receive a request that
includes the unique identifier associated with one of the queues
(e.g., a read queue or a write queue) established in block 1930. As
indicated in block 1950, the accelerator sled 1640 may receive a
request to write data, or as indicated in block 1952, may receive a
request to read data. Subsequently, the method 1900 advances to
block 1954 of FIG. 21, in which the accelerator sled 1640
determines an accelerator device 1660 to which the request is
directed.
[0102] Referring now to FIG. 21, in determining the accelerator
device 1660 to which the request is directed, the accelerator sled
1640 may determine the accelerator device from the address
identified in the request, as indicated in block 1956. In doing so,
the accelerator sled 1640 may compare the memory address indicated
in the request to the established memory address regions (e.g.,
from block 1904), as indicated in block 1958. Further, in doing so,
the accelerator sled 1640 may determine whether the address
indicated in the request corresponds with a region of RAM or a
register space of a directly connected accelerator device 1660, as
indicated in block 1960, or of an indirectly connected accelerator
device 1660 (e.g., a daisy-chained accelerator device 1660), as
indicated in block 1962. For example, if the address indicated in
the request falls outside of the RAM address space and the register
space, but is within the 16 terabyte range of addresses associated
with a directly connected accelerator device 1660, the accelerator
sled 1640 may determine that the address corresponds with an
accelerator device 1660 that is indirectly connected to the NIC
1652 through the directly connected accelerator device 1660. In
some embodiments, the accelerator sled 1640 may determine the
accelerator device 1660 from a unique identifier (e.g., a key) for
a queue included in the request (e.g., a unique identifier from
block 1940), as indicated in block 1964.
[0103] Subsequently, in block 1966, the accelerator sled 1640
performs a direct memory access operation in response to the
received request. In doing so, and as indicated in block 1968, the
accelerator sled 1640, in the illustrative embodiment, provides the
request from the NIC 1652 (e.g., from the memory access logic unit
1654) to the accelerator device 1660 mapped to an address (e.g.,
the base address) associated with the request. As indicated in
block 1970, the accelerator sled 1640 may add the request to a
corresponding queue (e.g., a read queue or a write queue). In
situations in which the accelerator sled 1660 has determined that
the memory access request is directed to an accelerator device 1660
that is indirectly connected to the NIC 1652 (e.g., as described in
block 1962), the accelerator sled 1640 forwards the request from
the corresponding accelerator device 1660 that is directly
connected to the NIC 1652 to the accelerator device that is
indirectly connected to the NIC 1652 (e.g., from a primary FPGA
1720 to a secondary FPGA 1730), as indicated in block 1972. In the
illustrative embodiment, the NIC 1652 (e.g., the memory access
logic unit 1654 of the NIC 1652) sends, as a PCIe endpoint device,
the request to the accelerator device 1660, which is configured as
a PCIe root device (e.g., a PCIe root complex), as indicated in
block 1974. In performing the direct memory access operation, the
accelerator sled 1640 may write to the memory, as indicated in
block 1976, such as by writing to the RAM, as indicated in block
1978, or by writing to a register, as indicated in block 1980.
Alternatively, the accelerator sled 1640 may read from the memory,
as indicated in block 1982, such as by reading from the RAM, as
indicated in block 1984, or by reading from a register, as
indicated in block 1986. Subsequently, the method 1900 advances to
block 1988 of FIG. 22, in which the accelerator sled 1640 sends a
result of performing the memory access operation to the remote
compute device (e.g., the compute sled 1630). In doing so, the
accelerator sled 1640 may send data that was read from the memory,
as indicated in block 1990, or may send a confirmation that data
was written, as indicated in block 1992. Afterwards, the method
1900 loops back to block 1942, in which the accelerator sled 1640
awaits another memory access request.
EXAMPLES
[0104] Illustrative examples of the technologies disclosed herein
are provided below. An embodiment of the technologies may include
any one or more, and any combination of, the examples described
below.
[0105] Example 1 includes an accelerator sled comprising an
accelerator device including a memory; a network interface
controller including a memory access logic unit to (i) determine a
memory address region usable by a remote compute device to access
the memory of the accelerator device, (ii) receive, from the remote
compute device, a memory access request to remotely access the
memory of the accelerator device associated with the memory address
region, and (iii) perform, in response to the memory access
request, a direct memory access operation on the memory.
[0106] Example 2 includes the subject matter of Example 1, and
wherein to perform the direct memory access operation comprises to
perform the direct memory access operation using a peripheral
component interconnect express protocol in which the network
interface controller is an endpoint device and the accelerator
device is a root device.
[0107] Example 3 includes the subject matter of any of Examples 1
and 2, and wherein the memory access logic unit is further to
establish a write queue in the memory, wherein the write queue is
usable to track one or more write operations to be performed on the
memory; provide, to the remote compute device, a unique identifier
that identifies the queue.
[0108] Example 4 includes the subject matter of any of Examples
1-3, and wherein the memory access logic unit is further to receive
a request from the remote compute device to establish the write
queue, wherein the request defines a length for the write queue and
wherein to establish the write queue comprises to establish the
write queue with the length defined in the request.
[0109] Example 5 includes the subject matter of any of Examples
1-4, and wherein the memory access logic unit is further to
establish a read queue in the memory, wherein the read queue is
usable to track one or more write operations to be performed on the
memory; provide, to the remote compute device, a unique identifier
that identifies the queue.
[0110] Example 6 includes the subject matter of any of Examples
1-5, and wherein the memory access logic unit is further to receive
a request from the remote compute device to establish the read
queue, wherein the request defines a length for the read queue and
wherein to establish the read queue comprises to establish the read
queue with the length defined in the request.
[0111] Example 7 includes the subject matter of any of Examples
1-6, and wherein the accelerator device is a first accelerator
device, the memory is a first memory, accelerator sled further
comprises a second accelerator device that includes a second
memory, the memory access request includes a unique identifier
associated with a read queue or a write queue, and the memory
access logic unit is further to determine, from the unique
identifier, whether the direct memory access operation is to be
performed on the first memory or the second memory.
[0112] Example 8 includes the subject matter of any of Examples
1-7, and wherein the accelerator device is a first accelerator
device connected to the network interface controller, the
accelerator sled further comprising a second accelerator device
that is indirectly connected to the network interface controller
through the first accelerator device, and the memory access request
includes a memory address on which the direct memory access
operation is to be performed, and wherein the memory access logic
unit is further to determine, as a function of the memory address,
whether the memory access request corresponds to the first
accelerator device or the second accelerator device.
[0113] Example 9 includes the subject matter of any of Examples
1-8, and wherein the accelerator device is a first accelerator
device, the accelerator sled further comprising a second
accelerator device that is connected to the network interface
controller, the memory access request includes a memory address on
which the direct memory access operation is to be performed, and
the memory access logic unit is further to determine, as a function
of the memory address, whether the memory access request
corresponds to the first accelerator device or the second
accelerator device.
[0114] Example 10 includes the subject matter of any of Examples
1-9, and wherein to perform the direct memory access operation
comprises to perform the direct memory access operation on a
register of the accelerator device.
[0115] Example 11 includes the subject matter of any of Examples
1-10, and wherein to perform the direct memory access operation
comprises to perform the direct memory access operation on a random
access memory of the accelerator device.
[0116] Example 12 includes the subject matter of any of Examples
1-11, and wherein to perform the direct memory access operation
comprises to perform a read operation.
[0117] Example 13 includes the subject matter of any of Examples
1-12, and wherein to perform the direct memory access operation
comprises to perform a write operation.
[0118] Example 14 includes the subject matter of any of Examples
1-13, and wherein to perform the direct memory access operation
comprises to add data indicative of the memory access operation to
a queue associated with direct memory access operations to be
performed on the memory of the accelerator device.
[0119] Example 15 includes the subject matter of any of Examples
1-14, and wherein the accelerator sled does not include a general
purpose processor.
[0120] Example 16 includes the subject matter of any of Examples
1-15, and wherein the accelerator device is a field-programmable
gate array (FPGA).
[0121] Example 17 includes a method comprising determining, by a
memory access logic unit of a network interface controller of an
accelerator sled, a memory address region usable by a remote
compute device to access the memory of an accelerator device of the
accelerator sled; receiving, by the memory access logic unit and
from the remote compute device, a memory access request to remotely
access the memory of the accelerator device associated with the
memory address region; and performing, by the memory access logic
unit and in response to the memory access request, a direct memory
access operation on the memory.
[0122] Example 18 includes the subject matter of Example 17, and
wherein performing the direct memory access operation comprises
performing the direct memory access operation using a peripheral
component interconnect express protocol in which the network
interface controller is an endpoint device and the accelerator
device is a root device.
[0123] Example 19 includes the subject matter of any of Examples 17
and 18, and further including establishing, by the memory access
logic unit, a write queue in the memory, wherein the write queue is
usable to track one or more write operations to be performed on the
memory; and providing, by the memory access logic unit and to the
remote compute device, a unique identifier that identifies the
queue.
[0124] Example 20 includes the subject matter of any of Examples
17-19, and further including receiving, by the memory access logic
unit, a request from the remote compute device to establish the
write queue, wherein the request defines a length for the write
queue and wherein establishing the write queue comprises
establishing the write queue with the length defined in the
request.
[0125] Example 21 includes the subject matter of any of Examples
17-20, and further including establishing, by the memory access
logic unit, a read queue in the memory, wherein the read queue is
usable to track one or more write operations to be performed on the
memory; providing, by the memory access logic unit and to the
remote compute device, a unique identifier that identifies the
queue.
[0126] Example 22 includes the subject matter of any of Examples
17-21, and further including receiving, by the memory access logic
unit, a request from the remote compute device to establish the
read queue, wherein the request defines a length for the read queue
and wherein establishing the read queue comprises establishing the
read queue with the length defined in the request.
[0127] Example 23 includes the subject matter of any of Examples
17-22, and wherein the accelerator device is a first accelerator
device, the memory is a first memory, the accelerator sled
additionally includes a second accelerator device that includes a
second memory, and the memory access request includes a unique
identifier associated with a read queue or a write queue, the
method further comprising determining, by the memory access logic
unit and from the unique identifier, whether the direct memory
access operation is to be performed on the first memory or the
second memory.
[0128] Example 24 includes the subject matter of any of Examples
17-23, and wherein the accelerator device is a first accelerator
device connected to the network interface controller, the
accelerator sled further includes a second accelerator device that
is indirectly connected to the network interface controller through
the first accelerator device, and the memory access request
includes a memory address on which the direct memory access
operation is to be performed, the method further comprising
determining, by the memory access logic unit and as a function of
the memory address, whether the memory access request corresponds
to the first accelerator device or the second accelerator
device.
[0129] Example 25 includes the subject matter of any of Examples
17-24, and wherein the accelerator device is a first accelerator
device, the accelerator sled further comprising a second
accelerator sled that is connected to the network interface, and
the memory access request includes a memory address on which the
direct memory access operation is to be performed, the method
further comprising determining, by the memory access logic unit and
as a function of the memory address, whether the memory access
request corresponds to the first accelerator device or the second
accelerator device.
[0130] Example 26 includes the subject matter of any of Examples
17-25, and wherein performing the direct memory access operation
comprises performing the direct memory access operation on a
register of the accelerator device.
[0131] Example 27 includes the subject matter of any of Examples
17-26, and wherein performing the direct memory access operation
comprises performing the direct memory access operation on a random
access memory of the accelerator device.
[0132] Example 28 includes the subject matter of any of Examples
17-27, and wherein performing the direct memory access operation
comprises performing a read operation.
[0133] Example 29 includes the subject matter of any of Examples
17-28, and wherein performing the direct memory access operation
comprises performing a write operation.
[0134] Example 30 includes the subject matter of any of Examples
17-29, and wherein performing the direct memory access operation
comprises adding data indicative of the memory access operation to
a queue associated with direct memory access operations to be
performed on the memory of the accelerator device.
[0135] Example 31 includes an accelerator sled comprising means for
performing the method of any of Examples 17-30.
[0136] Example 32 includes one or more machine-readable storage
media comprising a plurality of instructions stored thereon that,
in response to being executed, cause an accelerator sled to perform
the method of any of Examples 17-30.
[0137] Example 33 includes an accelerator sled comprising a compute
engine to perform the method of any of Examples 17-30.
[0138] Example 34 includes an accelerator sled comprising an
accelerator device including a memory; a network interface
controller including memory access manager circuitry to (i)
determine a memory address region usable by a remote compute device
to access the memory of the accelerator device, (ii) receive, from
the remote compute device, a memory access request to remotely
access the memory of the accelerator device associated with the
memory address region, and (iii) perform, in response to the memory
access request, a direct memory access operation on the memory.
[0139] Example 35 includes the subject matter of Example 34, and
wherein to perform the direct memory access operation comprises to
perform the direct memory access operation using a peripheral
component interconnect express protocol in which the network
interface controller is an endpoint device and the accelerator
device is a root device.
[0140] Example 36 includes the subject matter of any of Examples 34
and 35, and wherein the memory access manager circuitry is further
to establish a write queue in the memory, wherein the write queue
is usable to track one or more write operations to be performed on
the memory; provide, to the remote compute device, a unique
identifier that identifies the queue.
[0141] Example 37 includes the subject matter of any of Examples
34-36, and wherein the memory access manager circuitry is further
to receive a request from the remote compute device to establish
the write queue, wherein the request defines a length for the write
queue and wherein to establish the write queue comprises to
establish the write queue with the length defined in the
request.
[0142] Example 38 includes the subject matter of any of Examples
34-37, and wherein the memory access manager circuitry is further
to establish a read queue in the memory, wherein the read queue is
usable to track one or more write operations to be performed on the
memory; provide, to the remote compute device, a unique identifier
that identifies the queue.
[0143] Example 39 includes the subject matter of any of Examples
34-38, and wherein the memory access manager circuitry is further
to receive a request from the remote compute device to establish
the read queue, wherein the request defines a length for the read
queue and wherein to establish the read queue comprises to
establish the read queue with the length defined in the
request.
[0144] Example 40 includes the subject matter of any of Examples
34-39, and wherein the accelerator device is a first accelerator
device, the memory is a first memory, accelerator sled further
comprises a second accelerator device that includes a second
memory, the memory access request includes a unique identifier
associated with a read queue or a write queue, and the memory
access manager circuitry is further to determine, from the unique
identifier, whether the direct memory access operation is to be
performed on the first memory or the second memory.
[0145] Example 41 includes the subject matter of any of Examples
34-40, and wherein the accelerator device is a first accelerator
device connected to the network interface controller, the
accelerator sled further comprising a second accelerator device
that is indirectly connected to the network interface controller
through the first accelerator device, and the memory access request
includes a memory address on which the direct memory access
operation is to be performed, and wherein the memory access manager
circuitry is further to determine, as a function of the memory
address, whether the memory access request corresponds to the first
accelerator device or the second accelerator device.
[0146] Example 42 includes the subject matter of any of Examples
34-41, and wherein the accelerator device is a first accelerator
device, the accelerator sled further comprising a second
accelerator device that is connected to the network interface
controller, the memory access request includes a memory address on
which the direct memory access operation is to be performed, and
the memory access manager circuitry is further to determine, as a
function of the memory address, whether the memory access request
corresponds to the first accelerator device or the second
accelerator device.
[0147] Example 43 includes the subject matter of any of Examples
34-42, and wherein to perform the direct memory access operation
comprises to perform the direct memory access operation on a
register of the accelerator device.
[0148] Example 44 includes the subject matter of any of Examples
34-43, and wherein to perform the direct memory access operation
comprises to perform the direct memory access operation on a random
access memory of the accelerator device.
[0149] Example 45 includes the subject matter of any of Examples
34-44, and wherein to perform the direct memory access operation
comprises to perform a read operation.
[0150] Example 46 includes the subject matter of any of Examples
34-45, and wherein to perform the direct memory access operation
comprises to perform a write operation.
[0151] Example 47 includes the subject matter of any of Examples
34-46, and wherein to perform the direct memory access operation
comprises to add data indicative of the memory access operation to
a queue associated with direct memory access operations to be
performed on the memory of the accelerator device.
[0152] Example 48 includes the subject matter of any of Examples
34-47, and wherein the accelerator sled does not include a general
purpose processor.
[0153] Example 49 includes the subject matter of any of Examples
34-48, and wherein the accelerator device is a field-programmable
gate array (FPGA).
[0154] Example 50 includes an accelerator sled comprising means for
determining, with a network interface controller of an accelerator
sled, a memory address region usable by a remote compute device to
access the memory of an accelerator device of the accelerator sled;
circuitry for receiving, from the remote compute device, a memory
access request to remotely access the memory of the accelerator
device associated with the memory address region; and means for
performing, in response to the memory access request, a direct
memory access operation on the memory.
[0155] Example 51 includes the subject matter of Example 50, and
wherein the means for performing the direct memory access operation
comprises circuitry for performing the direct memory access
operation using a peripheral component interconnect express
protocol in which the network interface controller is an endpoint
device and the accelerator device is a root device.
[0156] Example 52 includes the subject matter of any of Examples 50
and 51, and further including circuitry for establishing a write
queue in the memory, wherein the write queue is usable to track one
or more write operations to be performed on the memory; circuitry
for providing, to the remote compute device, a unique identifier
that identifies the queue.
[0157] Example 53 includes the subject matter of any of Examples
50-52, and further including circuity for receiving a request from
the remote compute device to establish the write queue, wherein the
request defines a length for the write queue and wherein the
circuitry or establishing the write queue comprises circuitry for
establishing the write queue with the length defined in the
request.
[0158] Example 54 includes the subject matter of any of Examples
50-53, and further including circuitry for establishing a read
queue in the memory, wherein the read queue is usable to track one
or more write operations to be performed on the memory; circuitry
for providing, to the remote compute device, a unique identifier
that identifies the queue.
[0159] Example 55 includes the subject matter of any of Examples
50-54, and further including circuitry for receiving a request from
the remote compute device to establish the read queue, wherein the
request defines a length for the read queue and wherein the
circuitry for establishing the read queue comprises circuitry for
establishing the read queue with the length defined in the
request.
[0160] Example 56 includes the subject matter of any of Examples
50-55, and wherein the accelerator device is a first accelerator
device, the memory is a first memory, the accelerator sled
additionally includes a second accelerator device that includes a
second memory, and the memory access request includes a unique
identifier associated with a read queue or a write queue, the
accelerator sled further comprising circuitry for determining, from
the unique identifier, whether the direct memory access operation
is to be performed on the first memory or the second memory.
[0161] Example 57 includes the subject matter of any of Examples
50-56, and wherein the accelerator device is a first accelerator
device connected to the network interface controller, the
accelerator sled further includes a second accelerator device that
is indirectly connected to the network interface controller through
the first accelerator device, and the memory access request
includes a memory address on which the direct memory access
operation is to be performed, the accelerator sled further
comprising circuitry for determining, as a function of the memory
address, whether the memory access request corresponds to the first
accelerator device or the second accelerator device.
[0162] Example 58 includes the subject matter of any of Examples
50-57, and wherein the accelerator device is a first accelerator
device, the accelerator sled further comprising a second
accelerator sled that is connected to the network interface
controller, and the memory access request includes a memory address
on which the direct memory access operation is to be performed, the
accelerator sled further comprising circuitry for determining, as a
function of the memory address, whether the memory access request
corresponds to the first accelerator device or the second
accelerator device.
[0163] Example 59 includes the subject matter of any of Examples
50-58, and wherein the means for performing the direct memory
access operation comprises circuitry for performing the direct
memory access operation on a register of the accelerator
device.
[0164] Example 60 includes the subject matter of any of Examples
50-59, and wherein the means for performing the direct memory
access operation comprises circuitry for performing the direct
memory access operation on a random access memory of the
accelerator device.
[0165] Example 61 includes the subject matter of any of Examples
50-60, and wherein the means for performing the direct memory
access operation comprises circuitry for performing a read
operation.
[0166] Example 62 includes the subject matter of any of Examples
50-61, and wherein the means for performing the direct memory
access operation comprises circuitry for performing a write
operation.
[0167] Example 63 includes the subject matter of any of Examples
50-62, and wherein the means for performing the direct memory
access operation comprises circuitry for adding data indicative of
the memory access operation to a queue associated with direct
memory access operations to be performed on the memory of the
accelerator device.
* * * * *
References