U.S. patent application number 16/107596 was filed with the patent office on 2019-02-21 for automatic detection of change in pll locking trend.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Chih-Hsien Chang, Tsung-Hsien Tsai.
Application Number | 20190058575 16/107596 |
Document ID | / |
Family ID | 60089815 |
Filed Date | 2019-02-21 |
United States Patent
Application |
20190058575 |
Kind Code |
A1 |
Tsai; Tsung-Hsien ; et
al. |
February 21, 2019 |
AUTOMATIC DETECTION OF CHANGE IN PLL LOCKING TREND
Abstract
A phase lock loop (PLL), such as an all digital phase lock loop
(ADPLL) to provide an example, of the present disclosure operates
in a frequency tracking mode to adjust a frequency of the output
signal to be proportional to a frequency of a reference input
signal, or, in a phase tracking mode to adjust a phase of the
output signal to match any variations in the reference input
signal. The ADPLL includes a phase and/or frequency detector that
provides an error signal representing a difference, in frequency
and/or phase, between the output signal and the reference input
signal. The ADPLL monitors a trend of the error signal, such as a
positive trend, a negative trend, or a flat trend to provide some
examples, and switches among the frequency tracking mode and the
phase tracking mode upon detecting a change in the trend of the
error signal.
Inventors: |
Tsai; Tsung-Hsien; (Zhongli
City, TW) ; Chang; Chih-Hsien; (New Taipei City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsinchu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
Hsinchu
TW
|
Family ID: |
60089815 |
Appl. No.: |
16/107596 |
Filed: |
August 21, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15845193 |
Dec 18, 2017 |
10090994 |
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16107596 |
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15135212 |
Apr 21, 2016 |
9853807 |
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15845193 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03L 2207/50 20130101;
H04L 7/0331 20130101; H03L 7/0994 20130101; H03L 7/093 20130101;
H03L 7/091 20130101 |
International
Class: |
H04L 7/033 20060101
H04L007/033; H03L 7/091 20060101 H03L007/091; H03L 7/099 20060101
H03L007/099; H03L 7/093 20060101 H03L007/093 |
Claims
1. A phase lock loop (PLL) controller, comprising: a trend detector
configured to: sample an error signal, the error signal
representing a difference between a reference input signal of the
PLL and an output signal of the PLL, and determine a trend of the
sampled error signal; and a trend change detector configured to
initiate a change in a mode of operation of the PLL upon detecting
a. change in the trend of the sampled error signal from a previous
trend of the sampled error signal.
2. The PLL controller of claim 1, wherein the trend comprises: a
positive trend; a negative trend; or a flat trend.
3. The PLL controller of claim 1, further comprising: a clock
generator configured to determine a trend clocking signal based
upon the reference input signal and the error signal, wherein the
trend detector is configured to sample the error signal in
accordance with the trend clocking signal.
4. The PLL controller of claim 3, wherein the clock generator is
further configured to: provide the trend clocking signal at a first
logical value when the error signal is at a first digital value,
hold the trend clocking signal at the first logical level until the
error signal changes to a second digital value, and switch the
trend clocking signal from the first logical level to the second
logical level in response to the error signal changing to the
second digital value.
5. The PLL controller of claim 1, wherein the PLL is further
configured to adjust a frequency of the output signal to be
proportional to a frequency of the reference input signal in a
frequency tracking mode of operation, wherein the PLL is further
configured to adjust a phase of the output signal to match a phase
of the reference input signal in a phase tracking mode of
operation, and wherein the trend change detector is further
configured to switch a mode of operation of the PLL among the
frequency tracking mode of operation and the phase tracking mode of
operation upon detecting the change in the trend of the sampled
error signal.
6. The PLL controller of claim 5, further comprising: a phase
frequency detector (PFD) configured to compare a frequency of the
reference input signal and a frequency of the output signal to
provide a frequency difference of the error signal in the frequency
tracking mode of operation and in the phase tracking mode of
operation.
7. The PLL controller of claim 6, further comprising: a
time-to-digital converter (TDC) configured to: compare a phase of
the reference input signal and a phase of the output signal to
provide a phase difference of the error signal in the phase
tracking mode of operation, and be disabled in the frequency
tracking mode of operation.
8. A method for operating a phase lock loop (PLL), the method
comprising: sampling an error signal from the PLL received in a
frequency tracking mode of operation, the error signal representing
a difference between a frequency of a reference input signal of the
PLL and a frequency of an output signal of the PLL; determining a
trend of the sampled error signal; initiating a change in a mode of
operation of the PLL from the frequency tracking mode of operation
to a phase tracking mode of operation upon detecting a change in
the trend of the sampled error signal from a previous trend of the
sampled error signal.
9. The method of claim 8, wherein the trend comprises: a positive
trend; a negative trend; or a flat trend.
10. The method of claim 8, further comprising: determining a trend
clocking signal based upon the reference input signal and the error
signal, and wherein the sampling comprises: sampling the error
signal in accordance with the trend clocking signal.
11. The method of claim 10, wherein the determining the trend
clocking signal comprises: providing the trend clocking signal at a
first logical value when the error signal is at a first digital
value, holding the trend clocking signal at the first logical level
until the error signal changes to a second digital value, and
switching the trend clocking signal from the first logical level to
the second logical level in response to the error signal changing
to the second digital value.
12. The method of claim 8, further comprising: adjusting a
frequency of the output signal to be proportional to a frequency of
the reference input signal in a frequency tracking mode of
operation; adjusting a phase of the output signal to match a phase
of the reference input signal in the phase tracking mode of
operation; and switching a mode of operation of the PLL among the
frequency tracking mode of operation and the phase tracking mode of
operation upon detecting the change in the trend of the sampled
error signal.
13. The method of claim 2, wherein the adjusting the frequency of
the output signal comprises: comparing a frequency of the reference
input signal and a frequency of the output signal to provide a
frequency difference of the error signal in the frequency tracking
mode of operation and in the phase tracking mode of operation.
14. The method of claim 13, wherein the adjusting the phase of the
output signal comprises: comparing a phase of the reference input
signal and a phase of the output signal to provide a phase
difference of the error signal in the phase tracking mode of
operation.
15. A controller for controlling a phase lock loop (PLL), the
controller comprising: means for sampling an error signal, the
error signal representing a difference between a reference input
signal of the PLL and an output signal of the PLL; means for
determining a trend of the sampled error signal; and means for
initiating a change in a mode of operation of the PLL upon
detecting a change in the trend of the sampled error signal from a
previous trend of the sampled error signal,
16. The PLL controller of claim 15, wherein the trend comprises:
means for determining a trend clocking signal based upon the
reference input signal and the error signal, wherein the means for
sampling is configured to sample the error signal in accordance
with the trend clocking signal.
17. The PLL controller of claim 16, wherein the means for
determining the trend clocking signal is further configured to:
provide the trend clocking signal at a first logical value when the
error signal is at a first digital value, hold the trend clocking
signal at the first logical level until error signal changes to a
second digital value, and switch the trend clocking signal from the
first logical level to the second logical level in response to the
error signal changing to the second digital value.
18. The PLL controller of claim 15, wherein the PLL is further
configured to adjust a frequency of the output signal to be
proportional to a frequency of the reference input signal in a
frequency tracking mode of operation, wherein the PLL is further
configured to adjust a phase of the output signal to match a phase
of the reference input signal in a phase tracking mode of
operation, and wherein the trend change detector is further
configured to switch a mode of operation of the PLL among the
frequency tracking mode of operation and the phase tracking mode of
operation upon detecting the change in the trend of the sampled
error signal.
19. The PLL controller of claim 18, further comprising: means to
compare a frequency of the reference input signal and a frequency
of the output signal to provide a frequency difference of the error
signal in the frequency tracking mode of operation and in the phase
tracking mode of operation.
20. The PLL controller of claim 19, further comprising: means to
compare a phase of the reference input signal and a phase of the
output signal to provide a phase difference of the error signal in
the phase tracking mode of operation.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a continuation of U.S. patent
application Ser. No. 15/845,193, filed Dec. 18, 2017, which is a
continuation of U.S. patent application Ser. No. 15/135,212, filed
Apr. 21, 2016, now U.S. Pat. No. 9,853,807, each of which is
incorporated herein by reference in its entirety.
BACKGROUND
[0002] Phase lock loops (PLLs) generate output signals whose phases
are related to the phases of the input signals. For example, a PLL
can be used to adjust an oscillator so that a frequency and phase
of a signal generated by the oscillator matches the frequency and
phase of a reference input signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion. In the drawings:
[0004] FIG. 1 is a block diagram of an exemplary ADPLL 100
according to an exemplary embodiment of the present disclosure;
[0005] FIG. 2 is a diagram illustrating trends of an error signal
in accordance with an embodiment of the present disclosure;
[0006] FIG. 3A is a timing diagram illustrating a change of
tracking mode based on a change in trend in accordance with an
embodiment of the present disclosure;
[0007] FIG. 3B is a flowchart illustrating a method of changing
tracking mode based on determining a change in the trend of the
error signal in accordance with an embodiment of the present
disclosure;
[0008] FIG. 4 is a block diagram illustrating an exemplary
implementation of a controller that can be implemented with the
ADPLL in accordance with an embodiment of the present disclosure;
and
[0009] FIG. 5 is a more detailed diagram illustrating an exemplary
implementation of the controller in accordance with an embodiment
of the present disclosure.
DETAILED DESCRIPTION
[0010] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0011] Overview
[0012] A phase lock loop (PLL), such as an all digital phase lock
loop (ADPLL) to provide an example, of the present disclosure can
be used to adjust its oscillator so that a frequency and/or a phase
of an output signal generated by the oscillator is proportional to
a frequency and/or a phase of a reference input signal. The PLL
includes a phase and/or frequency detector that provides an error
signal representing a difference, in frequency and/or phase,
between the output signal and the reference input signal. This
error signal can be measured to ensure that the frequency and/or
the phase of the output signal is proportional to the frequency
and/or the phase of the reference signal. For example, as the PLL
adjusts the oscillator, the frequency and/or the phase of the
output signal can gradually become closer to the frequency of the
reference input signal. When the frequency and the phase of the
output signal is proportional to the frequency and/or the phase of
the reference input signal, the PLL is said to be locked onto the
reference input signal. The time it takes for the frequency and/or
phase of the output signal to become proportional to the frequency
and/or the phase of the reference input signal can be referred to
as the locking time.
[0013] In an embodiment, the PLL operates in a frequency tracking
mode to adjust the frequency of the output signal to be
proportional to a frequency of the reference input signal, or, in a
phase tracking mode to adjust a phase of the output signal to match
any variations in the reference input signal. Often times, the
error signal includes a frequency component representing a
difference in frequency between the reference input signal and the
output signal and a phase component representing a difference in
phase between the reference input signal and the output signal. The
PLL adjusts a frequency of the output signal to minimize the
frequency component of the error signal when in the frequency
tracking mode. In this exemplary embodiment, when the frequency
component of the error signal has been minimized, the tracking mode
of the PLL can be switched from the frequency tracking mode to the
phase tracking mode. The PLL adjusts a phase of the output signal
to minimize the phase component of the error signal when in the
phase tracking mode while the oscillator is locked onto the
reference input signal.
[0014] Exemplary All Digital Phase Lock Loop (ADPLL)
[0015] FIG. 1 is a block diagram of an exemplary ADPLL 100
according to an exemplary embodiment of the present disclosure. A
digital reference input signal 150 represents a digital
representation of a first time-varying signal, such as a cosine
wave or a sine wave to provide some examples, having a frequency
f.sub.REF and a phase .PHI..sub.REF. Similarly, a digital output
signal 152 represents a digital representation of a second
time-varying signal having a frequency f.sub.OUT and a phase
.PHI..sub.OUT. Herein, the frequency f.sub.REF and the phase
.PHI..sub.REF of the first time-varying signal is referred to as
the f.sub.REF and the phase .PHI..sub.REF, respectively. Similarly,
the frequency f.sub.OUT and the phase .PHI..sub.OUT of the second
time-varying signal is referred to as the f.sub.OUT and the phase
.PHI..sub.OUT, respectively. An ADPLL 100 adjusts the digital
output signal 152 such that the frequency f.sub.OUT and/or the
phase .PHI..sub.OUT is proportional to the frequency f.sub.REF
and/or the phase .PHI..sub.REF. The ADPLL 100 can to operate in a
frequency tracking mode of operation to adjust the frequency
f.sub.OUT to be proportional to the frequency f.sub.REF or in a
phase tracking anode of operation to adjust the phase .PHI..sub.OUT
to match, or substantially match, the phase .PHI..sub.REF. The
ADPLL 100 can be implemented using a phase frequency detector (PFD)
102, a digital loop filter 104, a digital controlled oscillator
(DCO) 106, and a time-to-digital converter (TDC) 108, and a
controller 110. The PFD 102, the loop filter 104. the DCO 106, the
TDC 108, and the digital combination network 116 can be implemented
using digital components to form an all-digital PLL (ADPLL).
[0016] The PFD 102 compares the frequency f.sub.OUT and the
frequency f.sub.REF to provide an error signal 154. The error
signal 154 includes a frequency component representing a first
difference between the frequency f.sub.REF and the frequency
f.sub.OUT and a phase component representing a second difference
between the phase .PHI..sub.REF and the phase .PHI..sub.OUT. As
illustrated in FIG. 1, the PFD 102 includes a DCO accumulator 112,
a reference accumulator 114, and a digital combination network 116.
The DCO accumulator 112 accumulates the digital reference input
signal 150 and the digital output signal 152 to provide a digital
output value 156. The reference accumulator 114 accumulates the
digital reference input signal 150 and a digital data signal 166,
which is to be discussed in further detail below, to provide a
digital reference input value 158. The digital combination network
116 determines a difference between the digital output value 156
and the digital reference input value 158 to provide the frequency
component of the error signal 154 when the ADPLL 100 is operating
in the frequency tracking mode of operation and the phase tracking
mode of operation. Additionally, when the ADPLL 100 is operating
the phase tracking mode of operation, the digital combination
network 116 additionally combines a phase difference 160
representing the second difference between the phase .PHI..sub.REF
and the phase .PHI..sub.OUT, which is to be discussed in further
detail below, to provide the phase component of the error signal
154.
[0017] The digital loop filter 104 provides a fine digital tuning
word 162 in response to the error signal 154. In a similar manner
as the digital reference input signal 150 and/or the digital output
signal 152, the error signal 154 represents a digital
representation of a third time-varying signal. The digital loop
filter 104 suppresses high frequency components in the third
time-varying signal which are outside of its bandwidth to provide
samples of a direct current (DC), or near DC, component of the
third time-varying signal within its bandwidth as the fine digital
tuning word 162.
[0018] The DCO 106 adjusts the frequency f.sub.OUT and/or the phase
.PHI..sub.OUT in accordance with the fine digital tuning word 162
and the coarse tuning word 164. The coarse tuning word 164 coarsely
tunes the frequency f.sub.OUT to be within a locking range of the
ADPLL 100. The locking range of the ADPLL 100 represents a range of
the frequency f.sub.OUT that is sufficiently close to the frequency
f.sub.REF such that the ADPLL 100 can lock onto the digital
reference input signal 150 using the fine digital tuning word 162.
The fine digital tuning word 162 can be used by the DCO 106 to
adjust the frequency f.sub.OUT and the phase .PHI..sub.OUT to match
any variations in the frequency f.sub.REF and the phase
.PHI..sub.REF.
[0019] The TDC 108 determines various timing characteristics of the
digital reference input signal 150 and the digital output signal
152 to provide the phase difference 160 representing the second
difference between the phase REF and the phase .PHI..sub.OUT. For
example, the TDC 108 determines a first start time of the digital
reference input signal 150 and/or a first stop time of the digital
reference input signal 150. The TDC similarly determines a second
start time of the digital output signal 152 and/or a second stop
time of the digital output signal 152. Thereafter, the TDC compares
the first start time and the second start time and/or the first
stop time and the second stop time to determine the phase
difference 160. The TDC 108 can be disabled in the frequency
tracking mode by setting a TDC enable signal 166 to a first logical
level, such as a logical zero to provide an example, and/or can be
enabled in the phase tracking mode by setting the TDC enable signal
166 to a second logical level, such as a logical one to provide an
example.
[0020] The controller 110 controls the overall configuration and
operation of the ADPLL 100. The controller 110 configures the ADPLL
100 to operate in the frequency tracking mode of operation. In the
frequency tracking mode of operation, the controller 110 disables
the TDC 108 by setting the TDC enable signal 166 to the first
logical level. The DCO 106 adjusts the digital output signal 152 to
adjust the frequency for f.sub.OUT in the frequency tracking mode.
Thereafter, the controller 110 monitors the error signal 154 to
determine a trend, for example, a positive trend, a flat trend,
and/or a negative trend in the error signal 154. The positive trend
indicates a digital value of the error signal 154 is increasing
from a previous value of the error signal 154, the flat trend
indicates the digital value of the error signal 154 is
substantially unchanged from the previous value of the error signal
154, and the negative trend indicates the digital value of the
error signal 154 is decreasing from the previous value of the error
signal 154. Once the controller 110 detects a first change in the
trend of the error signal, for example, from the positive trend to
the flat trend or the negative trend to the flat trend, the
controller 110 configures the ADPLL 100 to operate in the phase
tracking mode of operation. The first change in the trend of the
error signal 154 indicates the frequency f.sub.REF is sufficiently
close to the frequency f.sub.OUT to allow the DCO 106 to lock onto
the reference input signal 150 in the phase tracking mode of
operation.
[0021] In the phase tracking mode of operation, the controller 110
enables the TDC 108 by setting the TDC enable signal 166 to the
second logical level. The DCO 106 adjusts the digital output signal
152 to adjust the phase .PHI..sub.OUT in the phase tracking mode.
When the phase component of the error signal 154 is minimized, the
phase .PHI..sub.OUT is sufficiently close to the phase
.PHI..sub.REF. In this situation, the DCO 106 is locked onto the
reference input signal 150 to match any variations in the frequency
f.sub.REF and the phase .PHI..sub.REF. Thereafter, the controller
110 continues to monitor the error signal 154 to determine the
trend. Once the controller 110 detects a second change in the trend
of the error signal, for example, from the flat trend to the
positive trend or the flat trend to the negative trend, the
controller 110 configures the ADPLL 100 to operate in the frequency
tracking mode of operation. The second change in the trend of the
error signal 154 indicates the frequency f.sub.REF is no longer
sufficiently close to the frequency f.sub.OUT to allow the DCO 106
to lock onto the reference input signal 150.
[0022] Additionally, the controller 110 provides the coarse tuning
word 164 to coarsely steer the frequency of the DCO 106. Typically,
the controller 110 can perform a calibration routine to determine
the coarse tuning word 164 corresponding to a desired frequency
f.sub.OUT. For example, the controller 110 may cycle through
different combinations of the coarse tuning word 164 using a
searching algorithm, such as a binary search tree algorithm, a
recursion algorithm, a Stern-Brocot algorithm and/or any other
suitable search that will be apparent to those skilled in the
relevant art(s) without departing from the spirit and scope of the
present disclosure to produce the desired frequency f.sub.OUT.
[0023] Further, the controller 110 provides the digital data signal
166 representing a digital representation of a fourth time-varying
signal having a frequency f.sub.DATA. The frequency f.sub.DATA is
approximately equal to the frequency f.sub.OUT. In an exemplary
embodiment, the digital data signal 166 represents information to
he modulated by the ADPLL 100 onto the digital output signal 152.
This allows the ADPLL 100 to lock onto the digital reference input
signal 150 when the frequency f.sub.OUT is an integer multiple of
the frequency f.sub.REF without using a digital divider to divide
the frequency f.sub.OUT.
[0024] Exemplary PLL Tracking Modes
[0025] FIG. 2 is a diagram illustrating trends of an error signal
accordance with an embodiment of the present disclosure. As
discussed above, the controller 110 monitors the error signal 154
to determine a trend, for example, a positive trend, a flat trend,
and/or a negative trend in the error signal 154. As the frequency
f.sub.OUT and the frequency f.sub.REF converge, the error signal
154 decreases, and the error signal 154 increases when the
frequency f.sub.OUT and the frequency f.sub.REF diverge. As shown
in FIG. 2, the error signal 154 can have a positive trend 202, for
example, as the frequency f.sub.OUT converges with the frequency
f.sub.REF. The error signal 154 can have a negative trend 204, for
example, as the frequency f.sub.OUT diverges from the frequency
f.sub.REF. The error signal 154 can have a flat trend 208, for
example, when the frequency f.sub.OUT is approximately proportional
to the frequency f.sub.REF. In accordance with an embodiment of the
present disclosure, when ADPLL 100 detects a change in trend (e.g.,
from the positive trend 202 to the flat trend 208), the controller
110 can initiate the change in the tracking mode.
[0026] Exemplary Operation of the Controller of the ADPLL
[0027] FIG. 3A is a timing diagram illustrating a change of
tracking mode based on a change in trend of the error signal, in
accordance with an embodiment of the present disclosure. As
discussed above, the controller 110 detects a change in the trend
of the error signal 154, for example, from the flat trend 208 to
the positive trend 202 or the flat trend 208 to the negative trend
204, and changes tracking mode from frequency tracking mode to
phase tracking mode based on the change.
[0028] FIG. 3B is a flowchart illustrating an exemplary operational
control flow of the controller 110 that detects a change in the
trend of error signal and changes tracking mode based on the
change. The controller 110 is not limited to this operational
control flow. Rather, it will be apparent to ordinary persons
skilled in the relevant art(s) that other operational control flows
are within the scope and spirit of the present disclosure.
[0029] At step 302 as illustrated in FIG. 3B, the operational
control flow monitors the error signal 154. In an exemplary
embodiment, the operational control flow collects one or more
samples, such as three samples D1 through D3 to provide an example
as illustrated in FIG. 3A, of the error signal 154.
[0030] At step 304 as illustrated in FIG. 3B, the operational
control flow determines the trend of the error signals 154 from the
one or more collected samples from step 302 to determine the trend
of the error signal 154. As illustrated in FIG. 3A, the one or more
collected samples from step 302 are increasing indicating the
frequency f.sub.OUT is converging with the frequency f.sub.REF
indicating the positive trend 202.
[0031] At step 306 as illustrated in FIG. 3B, the operational
control flow continues to monitor the error signal 154. In an
exemplary embodiment, the operational control flow collects one or
more additional samples, such as samples D.sub.N-1 and D.sub.N as
illustrated in FIG. 3A to provide an example, of the error signal
154. Thereafter, the operational control flow compares the one or
more collected additional samples with the trend of the error
signal 154 from step 304. The operational control flow determines
the trend of the error signal 154 has changed when the one or more
collected additional samples differ from the initial trend of the
error signal 154 from step 304. For example, as illustrated in FIG.
3A, the trend of the error signal 154 is the positive trend 202
indicated by the "plus" references corresponding to the three
samples D1 through D3. In this example, the operational control
flow collects the sample D.sub.N-1 and compares this sample to the
positive trend 202. Because the sample D.sub.N-1 continues with the
positive trend 202, namely greater than the last of the three
samples D1 through D3, no change in the trend of the error signal
154 is detected. The operational control flow remains in step 306
to collect the sample D.sub.N and compares this sample to the
positive trend 202. Because the sample D.sub.N does not continue
with the positive trend 202 as indicated by the "minus" reference
corresponding to the sample D.sub.N, the operational control flow
detects the change in the trend of the error signal 154 and
proceeds to step 308. The sample D.sub.N is less than the sample
D.sub.N-1 indicating the frequency f.sub.OUT is diverging from the
frequency f.sub.REF. The error signal 154 is trending from the
positive trend 202 to the negative trend 204 and/or the flat trend
208.
[0032] At step 308 as illustrated in FIG. 3B, the operational
control flow switches the mode of operation of the ADPLL 100 from
frequency tracking mode of operation to the phase tracking mode of
operation or from the phase tracking mode of operation to the
frequency tracking mode of operation in response to detecting the
change in the trend of the error signal 154 in step 306.
Additionally, the operational control flow provides a control
signal, such as the TDC enable signal 166 to provide an example, to
enable or disable the TDC 108. Thereafter, the operational control
flow reverts to step 306 to continue to monitor the error signal
154 for other changes in the trend of the error signal 154.
[0033] Exemplary Controller That Can Be Implemented Within the
ADPLL
[0034] FIG. 4 is a block diagram illustrating an exemplary
implementation of a controller that can be implemented with the
ADPLL in accordance with an embodiment of the present disclosure. A
controller 400 configures an ADPLL, such as the ADPLL 100 to
provide an example, to operate in the frequency tracking mode of
operation or the phase track mode of operation. The controller 400
can configure the ADPLL to switch among the frequency tracking mode
of operation or the phase track mode of operation in response to
detecting a change in a trend of the error signal 154. The
controller 400 includes a clock generator 402, a trend detector
404, and a trend change detector 406. The controller 400 can
represent an exemplary embodiment of the controller 100.
[0035] The clock generator 402 determines a trend clocking signal
450 based upon the digital reference input signal 150 and the error
signal 154. The trend clocking signal 450 is used to capture the
error signal 154 for use with the trend detector 404 and the trend
change detector 452. In an exemplary embodiment, the clock
generator 402 monitors the error signal 154 and switches the trend
clocking signal 450 between logical values when the error signal
154 changes in response to adjustment of the frequency f.sub.OUT
and/or the phase .PHI..sub.OUT. For example, the clock generator
402 causes the trend clocking signal 450 to be at a first logical
level when the error signal 154 is at a first digital value. The
clock generator 402 holds the trend clocking signal 450 at the
first logical level until the error signal 154 changes to a second
digital value, different from the first, whereby the clock
generator 402 switches the trend clocking signal 450 from the first
logical level to a second logical level. In another exemplary
embodiment, this change in logical levels of the trend clocking
signal 450 occurs during a rise edge or a falling edge of the first
time-varying signal of the digital reference input signal 150.
[0036] The trend detector 404 collects one or more samples, such as
three samples D1 through D3 to provide an example, of the error
signal 154 in accordance with the trend clocking signal 450 to
provide a trend indicator 452. The trend indicator 452 indicates
whether the collected one or more samples of the error signal 154
have a positive trend, a flat trend, and/or a negative trend.
[0037] The trend change detector 406 compares the trend indicator
452 with a previous trend indicator to determine whether the trend
of the error signal 154 has changed. The operational control flow
determines the trend of the error signal 154 has changed when the
trend indicator 452 differs from the previous trend indicator. In
response to this difference, the trend change detector 406 provides
a control signal, such as the TDC enable signal 166, to initiate a
change in the tracking mode, for example, from the frequency track
mode of operation to the phase tracking mode of operation.
[0038] FIG. 5 is a more detailed diagram illustrating an exemplary
implementation of the controller in accordance with an embodiment
of the present disclosure. As shown in FIG. 5, a controller 500
contains the clock generator 402, the trend detector 404, and the
trend change detector 406.
[0039] The clock generator 402 includes multiple logical gates,
such as flip flops, logical OR gates, and logical AND gates to
determine the trend clocking signal 450 based upon the digital
reference input signal 150 and the error signal 154 as discussed
above in FIG. 4. As illustrated in FIG. 5, the clock generator 402
includes flip flops 502A through 502C and a digital combination
network 503. The flip flops 502A and 502B, using input signal 150
as clocking signal, store samples of data received from the error
signal 154. The digital combination network 503 determines a
difference between the samples of data and forwards the determined
difference to the flip flop 502C through a series of logical OR and
logical AND gates. The flip flop 502C receives the determined
difference and using input signal 150 as clocking signal, generates
the trend clocking signal 450.
[0040] The trend detector 404, using the trend clocking signal 450,
can determine a trend between three samples of the error signal 154
(represented as INT_PHE1, INT_PHE2, and INT_PHE3, respectively, in
FIG. 5). As explained in details below, the trend detector 404
determines the difference between the samples of data (e.g.,
between INT_PHE1 and TNT_PHE2 and between INT_PHE2 and INT_PHE3)
using two digital combination networks and determines two
respective signs indicative of these differences. Based on these
determined signs, the trend detector 404 provides the trend
indicator 452.
[0041] As illustrated in FIG. 5, the trend detector 404 includes
logical OR gates, logical AND gates, flip flops 504A through 504D,
a trend code generator 505, multiplexers 506A through 506C and
digital combination networks 507A through 507B. The flip flops 504A
through 504C use the trend clocking signal 450 as a clocking signal
and store three samples of data from the error signal 154,
represented as INT_PHE1, INT_PHE2, and INT_PHE3, respectively. The
multiplexers 506A through 506C are respectively connected to flip
flops 504A through 504C, while the flip flop 504D is connected to
the output of flip flop 504C through a series of logical OR gates.
If the flip flop 504C has not received a sample of data, it sends
out an instruction signal through the flip flop 504D to
multiplexers 506A through 506C. Each multiplexer from among the
multiplexers 506A through 506C then forwards samples of data
through the chain of flip flops 504A through 504C, until INT_PHE1,
INTPHE2, and INT_PHE3 are stored in flip flops 504A through 504C
respectively. The digital combination network 507A receives
INT-PHE1 and INT_PHE2 from flip flop 504A and 504B respectively,
and generates a single bit output code Sign1 indicative of a sign
between samples of data INT-PHE1 and INT_PHE2. Similarly, the
digital combination network 507B generates a single bit output code
Sign2 indicative of a sign between samples of data INT-PHE2 and
INT_PHE3. The Sign1 and Sign2 forms a two-bit code indicating a
trend of the stored three samples of data. For example, a two-bit
code of 11 would indicate a positive trend, a two bit code of 00
would indicate a negative trend, while 01 or 10 would indicate a
flat trend. The trend code generator 505 receives the two bit code,
and using the connected logical AND gates and logical OR gate,
generates the trend indicator 452. The trend indicator 452 may be a
single bit code, indicating the trend of the stored three samples
of data. For example, a single bit of 1 would indicate a positive
or flat trend, while a single bit of 0 would indicate a negative
trend.
[0042] The trend change detector 406 uses the trend indicator 452
and the error signal 154 to determine when a change in trend has
occurred. For example, trend change detector 406 can determine when
the sign between adjacent data no longer matches the sign detected
by the trend detector 404. Similar to the operation of flip flops
504A and 504B and digital combination network 507A, flip flops 512A
and 512B receive and store two samples of data from the error
signal 154, and a digital combination network 510 further
determines a sign between the adjacent two samples of data. When
the determined sign is different from trend indicator 452, the
trend change detector 406 detects this change and a multiplexer 511
outputs the TDC enable signal 166 to initiate a change in tracking
mode. To prevent data glitch in the detector system and provide
more reliable detection in trend changes, the flip flops 512C and
512D may be used to further process the TDC enable signal 166, in
accordance with sonic embodiments. For example, the flip flop 512D
may be a D-type flip flop that is configured to receive and output
the TDC enable signal 166. The flip flop 512D may further comprise
a reset signal input for asynchronously clearing the output of the
flip flop 512D if its reset signal is set to 0. As shown in FIG. 5,
the reset signal input may be provided by the flip flop 504C of
trend detector 404, and the flip flop 512D would therefore be
enabled to output the TDC enable signal 166 only after samples of
data have been respectively stored in the flip flops 504A through
504C. The flip flop 512C and the connected logical OR gates are
configured to form a feedback loop and maintain the output of the
trend change detector 406 during operation.
CONCLUSION
[0043] The foregoing Detailed Description discloses a phase lock
loop (PLL) controller. The PLL controller includes a clock
generator that receives an error signal from a PLL, the error
signal representing a difference between a frequency or a phase of
a reference input signal of the PLL and a frequency or a phase of
an output signal of the PL and generates a clock signal based on
the error signal. The PLL controller additional includes a trend
detector that samples the error signal in accordance with the clock
signal and determines a trend of the sampled error signal. The PLL
controller further includes a trend change detector that compares
the trend of the sampled error signal to a previous trend of the
sampled error signal and initiates a change in a mode of operation
of the PLL upon detecting a change in the trend of the sampled
error signal.
[0044] The foregoing Detailed Description additional discloses an
all-digital phase lock loop (ADPLL). The ADPLL includes a phase
frequency detector (PFD) that compares a first frequency of a first
time-varying signal represented by a digital reference input signal
and a second frequency of a second time-varying signal represented
by a digital output signal to provide a frequency error component
of an error signal and a time-to-digital converter (TDC) configured
that compares a first phase of the first tune-varying signal and a
second phase of the second time-varying signal to provide a phase
error component of the error signal. The ADPLL additionally
includes a digital controlled oscillator (DCO) that adjusts the
second frequency and the second phase based upon the error signal
and a controller that monitors the error signal and disables or
enables the TDC upon detecting a change in the trend of the error
signal.
[0045] The foregoing Detailed Description further discloses a
method for operating a phase lock loop (PLL). The method includes
receiving an error signal from the PLL, the error signal
representing a difference between a frequency or a phase of a
reference input signal of the PLL and a frequency or a phase of an
output signal of the PLL, sampling the error signal, determining a
trend of the sampled error signal, comparing the trend of the
sampled error signal to a previous trend of the sampled error
signal, and initiating a change in a mode of operation of the PLL
upon detecting a change in the trend of the sampled error
signal.
[0046] The foregoing disclosure outlines features of several
embodiments so that those skilled in the art may better understand
the aspects of the present disclosure. Those skilled in the art
should appreciate that they may readily use the present disclosure
as a basis for designing or modifying other processes and
structures for carrying out the same purposes and/or achieving the
same advantages of the embodiments introduced herein. Those skilled
in the art should also realize that such equivalent constructions
do not depart from the spirit and scope of the present disclosure,
and that they may make various changes, substitutions, and
alterations herein without departing from the spirit and scope of
the present disclosure.
* * * * *