U.S. patent application number 15/691717 was filed with the patent office on 2019-02-14 for semiconductor device and method for fabricating the same.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to En-Chiuan Liou, Yu-Cheng Tung.
Application Number | 20190051731 15/691717 |
Document ID | / |
Family ID | 65241857 |
Filed Date | 2019-02-14 |
United States Patent
Application |
20190051731 |
Kind Code |
A1 |
Liou; En-Chiuan ; et
al. |
February 14, 2019 |
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Abstract
A method for fabricating a semiconductor structure is provided
in the present invention. The method includes the steps of forming
a plurality of fins in a first region, a second region and a dummy
region, forming a first solid-state dopant source layer and a first
insulating buffer layer in the first region, forming a second
solid-state dopant source layer and a second insulating buffer
layer in the second region and the dummy region, and performing an
etch process to cut the fin in the dummy region.
Inventors: |
Liou; En-Chiuan; (Tainan
City, TW) ; Tung; Yu-Cheng; (Kaohsiung City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
65241857 |
Appl. No.: |
15/691717 |
Filed: |
August 30, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/823828 20130101;
H01L 29/0649 20130101; H01L 29/66803 20130101; H01L 29/0847
20130101; H01L 21/823821 20130101; H01L 27/0924 20130101; H01L
29/6681 20130101; H01L 29/24 20130101; H01L 21/823878 20130101;
H01L 29/161 20130101; H01L 21/2255 20130101; H01L 21/02129
20130101; H01L 21/2256 20130101; H01L 21/823814 20130101; H01L
21/823807 20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 21/8238 20060101 H01L021/8238; H01L 21/225
20060101 H01L021/225; H01L 21/02 20060101 H01L021/02; H01L 27/092
20060101 H01L027/092; H01L 29/06 20060101 H01L029/06; H01L 29/161
20060101 H01L029/161; H01L 29/24 20060101 H01L029/24; H01L 29/08
20060101 H01L029/08 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 10, 2017 |
CN |
201710679485.5 |
Claims
1. A method for fabricating a semiconductor device, comprising:
providing a substrate having a first region, a second region and a
dummy region; forming a plurality of fins in the first region, the
second region and the dummy region; forming a first solid-state
dopant source layer in the first region; forming a first insulating
buffer layer on the first solid-state dopant source layer; forming
a second solid-state dopant source layer in the second region and
the dummy region; forming a second insulating buffer layer on the
second solid-state dopant source layer and on the first insulating
buffer layer; and performing an etch process to cut the fin in the
dummy region to form a dummy fin.
2. The method for fabricating a semiconductor device according to
claim 1, wherein forming a first solid-state dopant source layer in
the first region further comprises: masking the first region; and
removing the first solid-state dopant source layer and the first
insulating buffer layer from the second region, thereby exposing
the fins and the substrate in the second region.
3. The method for fabricating a semiconductor device according to
claim 1, wherein forming a second solid-state dopant source layer
in the second region and the dummy region further comprises:
forming the second solid-state dopant source layer on the first
region, the second region and the dummy region; masking the second
region and the dummy region; and removing the second solid-state
dopant source layer from the first region, thereby exposing the
first insulating buffer layer in the first region.
4. The method for fabricating a semiconductor device according to
claim 1, wherein before performing an etch process to cut the fin
in the dummy region, further comprising: forming a dielectric layer
on the first region, the second region and the dummy region;
etching the dielectric layer, the second insulating buffer layer,
the first insulating buffer layer, the first solid-state dopant
source layer and the second solid-state dopant source layer to a
level below a top surface of the fins, thereby exposing a
protruding portion of each of the fins; and diffusing dopants from
the first solid-state dopant source layers and second solid-state
dopant source layers into the fins respectively in the first region
and the second region.
5. The method for fabricating a semiconductor device according to
claim 4, further comprising: forming a metal gate traversing the
fins and covering the dummy region after cutting the fin; forming
source and drain regions in the protruding portions of each of the
fins on either side of the metal gate; and cutting the metal gate
into gate segments.
6. The method for fabricating a semiconductor device according to
claim 4, wherein the fin in the dummy region is cut down to a level
below the level of the dielectric layer, the second insulating
buffer layer, the first solid-state dopant source layer and the
second solid-state dopant source layer.
7. The method for fabricating a semiconductor device according to
claim 1, wherein the fin in the dummy region is completely cut and
removed.
8. The method for fabricating a semiconductor device according to
claim 1, wherein a top surface of the second insulating buffer
layer and a top surface of the second solid-state dopant source
layer at both sides of the dummy fins are recessed to a level
higher than the remaining dummy fin but lower than the dielectric
layer after the cutting, and the top surface of the second
insulating butter layer is lower than the top surface of the second
solid-state dopant source layer at both sides of the dummy fin
after the cutting.
9. The method for fabricating a semiconductor device according to
claim 1, wherein the second solid-state dopant source layer and the
second insulating buffer layer at both sides of the dummy fin are
completely removed after the cutting so that two grooves are formed
respectively between the remaining dummy fin and the dielectric
layer at both sides of the dummy fin.
10. A semiconductor device, comprising: a substrate having a first
region, a second region and a dummy region between the first region
and the second region; a plurality of fins in the first region and
the second region; at least one trench is provided in the dummy
region, wherein a width of the trench is same as a width of the
fin; at least one dummy fin in the trench of the dummy region; a
first solid-state dopant source layer in the first region, a first
insulating buffer layer on the first solid-state dopant source
layer; a second solid-state dopant source layer in the second
region and the dummy region; a second insulating buffer layer on
the second solid-state dopant source layer; and a dielectric layer
on the substrate; wherein a top surface of the dielectric layer,
the second insulating buffer layer, the first insulating buffer
layer, the first solid-state dopant source layer and the second
solid-state dopant source layer are lower than a top surface of the
fins, and a bottom surface of the trench in the dummy region is
lower than the dielectric layer.
11. (canceled)
12. The semiconductor device according to claim 10, wherein the top
surface of the second insulating butter buffer layer is lower than
the top surface of the second solid-state dopant source layer at
both sides of the dummy fin.
13. The semiconductor device according to claim 10, wherein a top
surface of the dummy fin is lower than the top surface of the
dielectric layer, the second insulating buffer layer, the first
insulating buffer layer, the first solid-state dopant source layer
and the second solid-state dopant source layer.
14. The semiconductor device according to claim 10, further
comprising two grooves respectively between the dummy fin and the
dielectric layer at both sides of the dummy fin.
15. The semiconductor device according to claim 10, wherein the
second insulating buffer layer covers on the first insulating
buffer layer in the first region.
16. The semiconductor device according to claim 10, further
comprising a metal gate traversing the fins and covering the dummy
region.
17. The semiconductor device according to claim 10, wherein the
first solid-state dopant source layer comprises a borosilicate
glass (BSG) layer.
18. The semiconductor device according to claim 10, wherein the
second solid-state dopant source layer comprises a phosphosilicate
glass (PSG) layer or an arsenic silicate glass (AsSG) layer.
19. The semiconductor device according to claim 10, wherein the
first insulating buffer layer and the second insulating buffer
layer comprise silicon nitride.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The present invention relates generally to a semiconductor
transistor device and a method of fabricating the same. More
particularly, the present invention relates to a semiconductor
transistor device using a solid state doping (SSD) technique to
form a doped layer in the lower half of a fin structure and a
method of fabricating the same.
2. Description of the Prior Art
[0002] In recent years, as the dimensions of key components
continue to shrink, the development of planar field effect
transistor elements has been faced with process limitations. In
order to overcome process limitations, it has become a mainstream
trend to replace planar transistor elements with non-planar
field-effect transistor elements, such as fin field effect
transistors (Fin FET) elements.
[0003] Because the three-dimensional structure of the fin field
effect transistor element can increase the contact area between the
gate electrode and the fin structure, the control of the gate
electrode to the carrier channel region can be further increased,
thereby reducing the drain induced barrier lowering (DIBL) effect
and suppressing the short-channel effect (SCE).
[0004] Moreover, because the fin field effect transistor element
has a wider channel width at the same gate electrode length, a
double of the drain drive current can be obtained. Even the
threshold voltage of the transistor element can be controlled by
adjusting the work function of the gate electrode.
[0005] The integrated microelectronic device having a FinFET
architecture may rely on solid-state diffusion sources where an
impurity source film is formed adjacent to a sidewall of a portion
of a sub-fin region proximate to substrate. Dopants are driven from
the impurity source film(s) into the portions of the sub-fin region
proximate to the source films.
[0006] However, there is still improvement required in the process
design of the fin structure, such as the removal of the unnecessary
dummy fins between active areas at post stage. Therefore, how to
improve the prior process of fin field effect transistor and
develop the process for post stage is an important issue today.
SUMMARY OF THE INVENTION
[0007] One objective of the present invention is to provide a
process for removing dummy fins at post solid-state doping (SSD)
stage.
[0008] To achieve the objective, the preferred embodiment of the
present invention provides a method for fabricating a semiconductor
device, which includes the steps of providing a substrate having a
first region, a second region and a dummy region, forming a
plurality of fins in the first region and the second region and a
dummy fin in the dummy region, forming a first solid-state dopant
source layer in the first region, forming a first insulating buffer
layer on the first solid-state dopant source layer, forming a
second solid-state dopant source layer in the second region and the
dummy region, forming a second insulating buffer layer on the
second solid-state dopant source layer and on the first insulating
buffer layer, and performing an etch process to cut the fin in the
dummy region.
[0009] The present invention also provides a semiconductor device
resulted from the method provided above, which includes a substrate
having a first region, a second region and a dummy region between
the first region and the second region, a plurality of fins in the
first region and the second region, at least one dummy fin in the
dummy region, a first solid-state dopant source layer in the first
region, a first insulating buffer layer on the first solid-state
dopant source layer, a second solid-state dopant source layer in
the second region and the dummy region, a second insulating buffer
layer on the second solid-state dopant source layer, and a
dielectric layer on the substrate, wherein a top surface of the
dielectric layer, the second insulating buffer layer, the first
insulating buffer layer, the first solid-state dopant source layer
and the second solid-state dopant source layer is lower than a top
surface of the fins, and a top surface of the dummy fin is lower
than the top surface of the dielectric layer, the second insulating
buffer layer, the first insulating buffer layer, the first
solid-state dopant source layer and the second solid-state dopant
source layer.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings are included to provide a further
understanding of the embodiments, and are incorporated in and
constitute apart of this specification. The drawings illustrate
some of the embodiments and, together with the description, serve
to explain their principles. In the drawings:
[0012] FIGS. 1-8 are cross-sectional views schematically
illustrating the process for fabricating the semiconductor
structure in accordance with one embodiment of the present
invention;
[0013] FIG. 9 is a cross-sectional view schematically illustrating
the semiconductor structure in accordance with another embodiment
of the present invention;
[0014] FIG. 10 is a cross-sectional view schematically illustrating
the semiconductor structure in accordance with still another
embodiment of the present invention;
[0015] FIG. 11 is a cross-sectional view schematically illustrating
the semiconductor structure in accordance with still another
embodiment of the present invention;
[0016] FIG. 12 is a cross-sectional view schematically illustrating
the semiconductor structure in accordance with still another
embodiment of the present invention;
[0017] FIG. 13 is a cross-sectional view schematically illustrating
a gate electrode formed on fins and dummy fins in accordance with
still another embodiment of the present invention; and
[0018] FIG. 14 is a cross-sectional view schematically illustrating
no gate electrode is formed on the dummy fin in accordance with
still another embodiment of the present invention.
[0019] It should be noted that all the figures are diagrammatic.
Relative dimensions and proportions of parts of the drawings have
been shown exaggerated or reduced in size, for the sake of clarity
and convenience in the drawings. The same reference signs are
generally used to refer to corresponding or similar features in
modified and different embodiments.
DETAILED DESCRIPTION
[0020] In the following detailed description of the invention,
reference is made to the accompanying drawings, which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention. Other embodiments may
be utilized and structural, logical and electrical changes may be
made without departing from the scope of the present invention. The
following detailed description is, therefore, not to be taken in a
limiting sense, and the scope of the present invention is defined
only by the appended claims, along with the full scope of
equivalents to which such claims are entitled.
[0021] Before describing the preferred embodiment, the following
description will be given for specific terms used throughout the
specification. The term "etch" or "etching" is used herein to
generally describe a fabrication process of patterning a material,
such that at least a portion of the material remains after the etch
is completed. For example, it should be understood that the process
of etching silicon involves the steps of patterning a photoresist
layer above the silicon, and then removing the areas of silicon no
longer protected by the photoresist layer. As such, the areas of
silicon protected by the photoresist layer would remain behind
after the etch process is complete. However, in another example,
etching may also refer to a process that does not use a photoresist
layer, but still leaves behind at least a portion of the material
after the etch process is complete.
[0022] The above description serves to distinguish the term
"etching" from "removing." When etching a material, at least a
portion of the material remains behind after the process is
completed. In contrast, when removing a material, substantially all
of the material is removed in the process. However, in some
embodiments, "removing" is considered to be a broad term that may
incorporate etching.
[0023] The term "substrate," "semiconductor substrate" or "wafer"
as described throughout, is most commonly a silicon substrate or a
silicon wafer. However, term "substrate" or "wafer" may also refer
to any semiconductor material such as germanium, gallium arsenide,
indium phosphide, and the like. In other embodiments, the term
"substrate" or "wafer" may be non-conductive, such as a glass or
sapphire wafer.
[0024] FIG. 1 to FIG. 8 are schematic cross-sectional views
illustrating an exemplary process of fabricating a semiconductor
transistor device in accordance with one embodiment of the
invention. First, as shown in FIG. 1, a semiconductor substrate 100
is provided. The semiconductor substrate 100 includes a first
region 100a, a second region 100b and a dummy region 100c between
the first region 100a and the second region 100b. For example, the
first region 100a may be a NMOS region and the second region 100b
may be a PMOS region. The first region 100a and the second region
100b do not overlap each other. Next, a plurality of fins 102 are
formed in the first region 100a, the second region 100b and the
dummy region 100c, respectively. In the embodiment, the dummy
region 100c is formed, but not limited, in the outer peripheral
area of the second region 100b. It may also be formed in the outer
peripheral areas of the first region 100a in other embodiments. The
process of forming the semiconductor fins on a semiconductor
substrate is well known and may include steps such as lithography
and etching, which are not described in any detail.
[0025] According to the embodiment of the invention, the top of
each fin 102 may be optionally provided with a pad oxide layer (not
shown), such as a silicon dioxide layer, and a hardmask layer (not
shown), such as a silicon nitride hardmask layer. Further, an oxide
layer (not shown) may be optionally formed on the fins, such as a
silicon oxide layer formed by in-situ steam generation (ISSG), but
is not limited thereto.
[0026] Next, as shown in FIG. 2, a first solid-state dopant source
layer 108 is formed in the first region 100a on the semiconductor
substrate 100, for example, by a chemical vapor deposition method.
The first solid-state dopant source layer 108 is deposited
conformally on the semiconductor substrate 100. According to the
embodiment of the present invention, the first solid-state dopant
source layer 108 may include p-type dopants, such as a borosilicate
glass (BSG) layer, but is not limited thereto. A first insulating
buffer layer 110 is then formed on the first solid-state dopant
source layer 108 in the first region 100a. The first insulating
buffer layer 110 may include silicon nitride, but is not limited
thereto. The first insulating buffer layer 110 may be formed by a
chemical vapor deposition method.
[0027] To be detailed, the first solid-state dopant source layer
108 and the first insulating buffer layer 110 may be formed first
on the entire substrate 100, an etching mask (not shown), such as a
photoresist, is then masked on the first region 100a without
masking the second region 100b and the dummy region 100c. An
etching process is then performed to remove the first solid-state
dopant source layer 108 and the first insulating buffer layer 110
not covered by the etching mask from the second region 100b and the
dummy region 100c, so that the first solid-state dopant source
layer 108 and the first insulating buffer layer 110 are formed only
covering the first region 100a. The etching mask is removed
subsequently after the etching process.
[0028] Next, as shown in FIG. 3, the second solid-state dopant
source layer 112 is deposited in the second region 100b on the
semiconductor substrate 100, for example, by a chemical vapor
deposition method. The second solid-state dopant source layer 112
is deposited conformally on the semiconductor substrate 100.
According to the embodiment of the present invention, the second
solid-state dopant source layer 112 may include n-type dopants,
such as a phosphosilicate glass (PSG) layer or an arsenic silicate
glass (AsSG) layer, but is not limited thereto.
[0029] To be detailed, the second solid-state dopant source layer
112 may be first formed on the entire substrate 100, an etching
mask (not shown), such as a photoresist, is then masked on the
second region 100b without masking the first region 100a. An
etching process is then performed to remove the second solid-state
dopant source layer 112 not covered by the etching mask in the
first region 100a, to thereby expose the first insulating buffer
layer 110 in the first region 100a, so that the second solid-state
dopant source layer 112 is formed only in the second region 100b
and the dummy region 100c. The etching mask is removed subsequently
after the etching process.
[0030] As shown in FIG. 4, a second insulating buffer layer 114 is
then formed on the first insulating buffer layer 110 in the first
region 100a and on the second solid-state dopant source layer 112
in the second region 100b. The second insulating buffer layer 114
may include silicon nitride, but is not limited thereto. The second
insulating buffer layer 114 may be formed by a chemical vapor
deposition method.
[0031] Next, as shown in FIG. 5, a dielectric layer 116, for
example, a silicon dioxide layer, is formed on the substrate 100
between the fins 102. According to the embodiment of the invention,
the dielectric layer 116 may be formed by a chemical vapor
deposition method, but is not limited thereto, to fill the recesses
between the semiconductor fins. Furthermore, a planarization
process such as chemical mechanical polishing (CMP) is then
performed to remove parts of the dielectric layer 116 and the fins
102 to a predetermined level. The top surfaces of the dielectric
layer 116, the fins 102, the first solid-state dopant source layer
108, the second solid-state dopant source layer 112, the first
insulating buffer layer 110 and the second insulating buffer layer
114 are flush after the planarization process.
[0032] Furthermore, after the above planarization process, a
thermal doping process is performed to drive dopants from the first
solid-state dopant source layer 108 and the second solid-state
dopant source layer 112 into the fins 102 in the first region 100a,
the second region 100b and the dummy region 100c, respectively. In
this way, the doped portions with different conductive type are
formed respectively in the fins 102 in the first region 100a and
the second region 100b, respectively. The doped portion may also be
formed extending into the substrate 100 with a predetermined
thickness in addition to the fins 102.
[0033] Subsequently, as shown in FIG. 6, the dielectric layer 116,
the second insulating buffer layer 114, the first insulating buffer
layer 110, the first solid-state dopant source layer 108 and the
second solid-state dopant source layer 112 are recessed to a
predetermined level below a top surface of the fins 102, to thereby
expose protruding portion 102a of each fin 102. The level to which
the first solid-state dopant source layer 108 and the second
solid-state dopant source layer 112 are recessed would determine
the channel portion in each fin 102.
[0034] Next, as shown in FIG. 7, the first region 100a and the
second region 100b are masked by an etching mask 118, such as a
photoresist. The etching mask 118 has opening 118a exposing only
the fin 102 in the dummy region 100c between the first region 100a
and the second region 100b.
[0035] After the etching mask 118 is formed, an anisotropic dry
etching process is then performed to etch the fin 102 exposed from
the opening 118a, so that the fin is cut to a level lower than the
top surface of the dielectric layer 116 and forms a dummy fin 119,
as shown in FIG. 8. Thereafter, the etching mask 118 is
removed.
[0036] The dummy fin 119 in this embodiment is provided with the
second solid-state dopant source layer 112 and the second
insulating buffer layer 114 at both sides, However, in other
embodiment, the dummy fin 119 may be provided with the second
solid-state dopant source layer 112 and the second insulating
buffer layer 114 at one side and the first solid-state dopant
source layer 108 and the second insulating buffer layer 110 at the
other side, depending on the predetermined region of the first
solid-state dopant source layer 108 and the second solid-state
dopant source layer 112 in the forming process.
[0037] In another embodiment of the present invention, as shown in
FIG. 9, the fin 102 may be completely removed to create a fin-free
dummy region 100c between the first region 100a and the second
region 100b. The trench 119a formed by the removal of the fin 102
may extend into the substrate 100 to a level lower than the doped
portion.
[0038] In still another embodiment of the present invention, the
cutting process may also recess the exposed second solid-state
dopant source layer 112 and the second insulating buffer layer 114
to a level lower than the top surface of the dielectric layer 116.
More specifically, the cutting process has different etching rates
for the second solid-state dopant source layer 112 and the second
insulating buffer layer 114, so that the top surface of the second
solid-state dopant source layer 112 would higher than the top
surface of the second insulating buffer layer 114 at both sides of
the dummy fin 119 as shown in FIG. 10, and the top surfaces of both
layer are both higher than the top surface of the dummy fin
119.
[0039] In still another embodiment of the present invention, the
cutting process may have quite larger etching rates for the second
solid-state dopant source layer 112 and the second insulating
buffer layer 114 rather than the fins 102, so that the second
solid-state dopant source layer 112 and the second insulating
buffer layer 114 would be completely removed by the cutting process
at both sides of the dummy fin 119 to form two grooves 120 between
the dummy fin 119 and the dielectric layer 116 as shown in FIG. 11.
The groove 120 may extend slightly into the doped portion in the
substrate 100.
[0040] In still another embodiment of the present invention, as
shown in FIG. 12, there may be more than one fin 102 been cut out
in the cutting process, depending on the area of the dummy region
100c. At least two trenches 119a are formed in the dummy region
100c.
[0041] Next, as shown in FIG. 13, a gate electrode 122 is formed on
the dielectric layer 116. The gate electrode 122 may traverse the
protruding portions 102a of each fin 102 and completely cover the
dummy region 100c. According to the embodiment of the invention,
the gate electrode 122 may include a metal gate, which may be
formed by a replacement metal gate process. For example, first
forming dummy gates and an interlayer dielectric on the substrate
and the fins, and the dummy gates are then removed and replaced
with metal material to form metal gate. Source and drain regions
(not shown) are then formed in the protruding portions 102a of each
fin 102, on two opposite sides of the gate electrode 122, and the
SiGe or SiP epitaxy may be subsequently formed in the source and
drain regions.
[0042] Finally, according to the embodiment of the invention as
shown in FIG. 13, there is further included a step of cutting the
gate electrode 122 into a plurality of gate segments 122a, 122b,
122c for different regions. Other conventional components, such as
high-k layer, work function layer, or low resistance layer, will
not be shown in FIG. 12 for the concise and simplicity of the
drawings.
[0043] In other embodiment, as shown in FIG. 14, the dummy region
100c and the dummy fin 119 may not be provided with gate electrode
122. The gate segment 122c once provided on the dummy fin 119 in
FIG. 13 is removed during the cutting of gate electrode 122.
[0044] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *