U.S. patent application number 15/698030 was filed with the patent office on 2019-01-31 for buried interconnect conductor.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Kuan-Lun Cheng, Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang.
Application Number | 20190035785 15/698030 |
Document ID | / |
Family ID | 65138339 |
Filed Date | 2019-01-31 |
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United States Patent
Application |
20190035785 |
Kind Code |
A1 |
Ching; Kuo-Cheng ; et
al. |
January 31, 2019 |
Buried Interconnect Conductor
Abstract
Various examples of a buried interconnect line are disclosed
herein. In an example, a device includes a fin disposed on a
substrate. The fin includes an active device. A plurality of
isolation features are disposed on the substrate and below the
active device. An interconnect is disposed on the substrate and
between the plurality of isolation features such that the
interconnect is below a topmost surface of the plurality of
isolation features. The interconnect is electrically coupled to the
active device. In some such examples, a gate stack of the active
device is disposed over a channel region of the active device and
is electrically coupled to the interconnect. In some such examples,
a source/drain contact is electrically coupled to a source/drain
region of the active device, and the source/drain contact is
electrically coupled to the interconnect.
Inventors: |
Ching; Kuo-Cheng; (Hsinchu
County, TW) ; Ju; Shi Ning; (Hsinchu City, TW)
; Pan; Kuan-Ting; (Hsinchu, TW) ; Cheng;
Kuan-Lun; (Hsin-Chu, TW) ; Wang; Chih-Hao;
(Hsinchu County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsinchu |
|
TW |
|
|
Family ID: |
65138339 |
Appl. No.: |
15/698030 |
Filed: |
September 7, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62537168 |
Jul 26, 2017 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/7851 20130101;
H01L 21/823437 20130101; H01L 21/76895 20130101; H01L 21/76802
20130101; H01L 29/0649 20130101; H01L 29/456 20130101; H01L
21/823475 20130101; H01L 29/41791 20130101; H01L 21/823481
20130101; H01L 23/528 20130101; H01L 29/7848 20130101; H01L 27/0886
20130101; H01L 21/74 20130101; H01L 21/76224 20130101; H01L
29/66545 20130101; H01L 21/3086 20130101; H01L 21/3065 20130101;
H01L 21/3081 20130101; H01L 21/823431 20130101; H01L 23/535
20130101; H01L 21/76877 20130101; H01L 21/743 20130101 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 29/78 20060101 H01L029/78; H01L 29/06 20060101
H01L029/06; H01L 23/528 20060101 H01L023/528; H01L 21/8234 20060101
H01L021/8234; H01L 21/308 20060101 H01L021/308; H01L 21/762
20060101 H01L021/762; H01L 29/66 20060101 H01L029/66 |
Claims
1. A device comprising: a fin disposed on a substrate, wherein the
fin includes an active device; a plurality of isolation features
disposed on the substrate and below the active device; an
interconnect disposed on the substrate and between the plurality of
isolation features such that a topmost surface of the interconnect
is below a topmost surface of the plurality of isolation features,
wherein the interconnect is electrically coupled to the active
device; and a dielectric feature disposed between the plurality of
isolation features and extending from the topmost surface of the
interconnect to a height above the topmost surface of the plurality
of isolation features.
2. The device of claim 1 further comprising: a gate stack of the
active device disposed over a channel region of the active device,
wherein the gate stack of the active device is electrically coupled
to the interconnect.
3. The device of claim 2, wherein the gate stack is directly
electrically coupled to the interconnect.
4. The device of claim 2, wherein a gate electrode of the gate
stack extends between the plurality of isolation features to
electrically couple to the interconnect.
5. The device of claim 1 further comprising: a source/drain contact
electrically coupled to a source/drain region of the active device,
wherein the source/drain contact is electrically coupled to the
interconnect.
6. The device of claim 5, wherein the source/drain contact is
directly electrically coupled to the interconnect.
7. The device of claim 1, wherein a horizontal width of the
interconnect is greater than a horizontal width of the fin.
8. The device of claim 1, wherein a ratio of width to height of the
interconnect is between about 1:4 and about 3:2.
9. The device of claim 1, wherein: a first side surface of the
interconnect is contacted in its entirety by the plurality of
isolation features; and a second side surface of the interconnect
that is opposite the first side surface is contacted in its
entirety by the plurality of isolation features.
10. The device of claim 1, wherein the interconnect is disposed
between the substrate and the dielectric feature.
11. A device comprising: a substrate; a plurality of FinFET devices
disposed on a plurality of fins extending from the substrate; a
plurality of isolation features disposed between the plurality of
fins; a conductive line disposed on and directly contacting the
substrate and between the plurality of isolation features such that
a topmost surface of the conductive line is below a topmost surface
of the plurality of isolation features and a bottommost surface of
the conductive line is above a bottommost surface of the plurality
of isolation features, wherein the conductive line is electrically
coupled to the plurality of FinFET devices; and a dielectric
disposed on the topmost surface of the conductive line between the
plurality of isolation features.
12. The device of claim 11 further comprising: a gate stack
disposed over channel regions of the plurality of FinFET devices,
wherein the gate stack is electrically coupled to the conductive
line.
13. The device of claim 12, wherein a gate electrode of the gate
stack extends between the plurality of isolation features to
electrically couple to the conductive line.
14. The device of claim 11 further comprising: a source/drain
contact disposed over source/drain features of the plurality of
FinFET devices, wherein the source/drain contact is electrically
coupled to the source/drain features and to the conductive
line.
15. The device of claim 14, wherein the source/drain contact
extends between the plurality of isolation features to electrically
couple to the conductive line.
16. The device of claim 11 further comprising: an inter-level
dielectric disposed over the isolation features, over the
conductive line, and between the plurality of FinFET devices.
17. The device of claim 11, wherein the conductive line has a
horizontal width that is greater than a horizontal width of each of
the plurality of fins.
18-20. (canceled)
21. A device comprising: a substrate; a plurality of fins extending
from the substrate, wherein each fin of the plurality of fins has
an active device formed thereupon; a plurality of isolation
features disposed on the substrate between the plurality of fins;
and a conductive feature disposed on a topmost surface of an
additional fin extending from the substrate and between a first
isolation feature and a second isolation feature of the plurality
of isolation features and disposed below the active devices of the
plurality of fins, wherein the conductive feature is electrically
coupled to a first active device of the active devices.
22. The device of claim 21, wherein a gate electrode of the first
active device physically and electrically couples to the conductive
feature.
23. The device of claim 21, wherein the conductive feature is below
a topmost surface of the plurality of isolation features.
Description
PRIORITY DATA
[0001] The present application claims the benefit of U.S.
Provisional Application No. 62/537,168, entitled "Buried
Interconnect Conductor," filed Jul. 26, 2017, herein incorporated
by reference in its entirety.
BACKGROUND
[0002] The semiconductor industry has progressed into nanometer
technology process nodes in pursuit of higher device density,
higher performance, and lower cost. Beyond merely shrinking
devices, circuit designers are looking to novel structures to
deliver even greater performance. One avenue of inquiry is the
development of three-dimensional designs, such as a fin-like field
effect transistor (FinFET). A FinFET may be envisioned as a typical
planar device extruded out of a substrate and into the gate. An
exemplary FinFET is fabricated with a thin "fin" (or fin structure)
extending up from a substrate. The channel region of the FET is
formed in this vertical fin, and a gate is provided over (e.g.,
wrapping around) the channel region of the fin. Wrapping the gate
around the fin increases the contact area between the channel
region and the gate and allows the gate to control the channel from
multiple sides. This can be leveraged in a number of way, and in
some applications, FinFETs provide reduced short channel effects,
reduced leakage, and higher current flow. In other words, they may
be faster, smaller, and more efficient than planar devices.
[0003] To electrically coupled the FinFETs and other devices, an
integrated circuit may include an interconnect structure with one
or more layers of conductive lines electrically coupled to the
devices. The overall circuit size and performance may depend on the
number and size of the conductive lines as well as the circuit
devices.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The present disclosure is best understood from the following
detailed description when read with the accompanying figures. It is
emphasized that, in accordance with the standard practice in the
industry, various features are not drawn to scale and are used for
illustration purposes only. In fact, the dimensions of the various
features may be arbitrarily increased or reduced for clarity of
discussion.
[0005] FIG. 1 is a perspective view of a portion of a workpiece
according to various aspects of the present disclosure.
[0006] FIGS. 2A and 2B are flow diagrams of a method of fabricating
a workpiece with a buried interconnect line according to various
aspects of the present disclosure.
[0007] FIG. 3A is a perspective view of the workpiece at a stage of
the method of fabricating the workpiece with a buried interconnect
line according to various aspects of the present disclosure.
[0008] FIGS. 3B and 4-11 are cross-sectional diagrams taken along a
channel region of the workpiece at various stages of the method of
fabricating the workpiece with a buried interconnect line according
to various aspects of the present disclosure.
[0009] FIG. 12 is a perspective view of the workpiece at a stage of
the method of fabricating the workpiece with a buried interconnect
line according to various aspects of the present disclosure.
[0010] FIGS. 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A are
cross-sectional diagrams taken along the channel region of the
workpiece at various stages of the method of fabricating the
workpiece with the buried interconnect line according to various
aspects of the present disclosure.
[0011] FIGS. 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, and 21B are
cross-sectional diagrams taken along a source/drain feature of the
workpiece at various stages of the method of fabricating the
workpiece with the buried interconnect line according to various
aspects of the present disclosure.
[0012] FIG. 17C is a perspective view of the workpiece at a stage
of the method of fabricating the workpiece with the buried
interconnect line according to various aspects of the present
disclosure
DETAILED DESCRIPTION
[0013] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the disclosure. Specific examples of components and arrangements
are described below to simplify the present disclosure. These are,
of course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
beyond the extent noted.
[0014] Moreover, the formation of a feature on, connected to,
and/or coupled to another feature in the present disclosure that
follows may include embodiments in which the features are formed in
direct contact, and may also include embodiments in which
additional features may be formed interposing the features, such
that the features may not be in direct contact. In addition,
spatially relative terms, for example, "lower," "upper,"
"horizontal," "vertical," "above," "over," "below," "beneath,"
"up," "down," "top," "bottom," etc. as well as derivatives thereof
(e.g., "horizontally," "downwardly," "upwardly," etc.) are used for
ease of the present disclosure of one features relationship to
another feature. The spatially relative terms are intended to cover
different orientations of the device including the features.
[0015] As device sizes continue to fall, a circuit may become
wire-bound. In other words, the circuit size may depend more on the
conductive lines in an interconnect structure that electrically
couples the circuit devices than on the sizes of the devices
themselves. While the thickness of the conductive lines may be
reduced to pack more lines in the interconnect, thinner lines have
a higher resistance, making them slower and more of a load on the
driving device. Likewise, reducing the spacing between lines
increases the risk of shorts, noise interference, and capacitive
coupling, which may increase the load on the driver. Additional
layers of conductive lines may be added to the interconnect
structure, but routing on these layers may take additional vias,
which have an associated resistance and pose inter-layer alignment
issues. Alignment errors tend to compound with each additional
interconnect layer, adding yield risk as the number of layers
grows.
[0016] As described below, the present disclosure provides a
technique to relieve some interconnect congestion by providing
conductive lines below the interconnect (e.g., the conductive lines
and vias above the circuit devices and the contacts that couple to
the devices). For example, in a FinFET circuit, an interconnect
line may be buried in a dummy fin among the device fins. The buried
interconnect line provides an additional routing resource for
coupling the FinFETs and other circuit device. Thus, some
embodiments of the present disclosure thereby provide additional
routing resources to relieve routing congestion in the interconnect
structure. However, unless otherwise noted, no embodiment is
required to provide any particular advantage.
[0017] FIG. 1 is a perspective view of a portion of a workpiece 100
according to various aspects of the present disclosure. FIG. 1 has
been simplified for the sake of clarity and to better illustrate
the concepts of the present disclosure. Additional features may be
incorporated into the workpiece 100, and some of the features
described below may be replaced or eliminated for other embodiments
of the workpiece 100.
[0018] The workpiece 100 includes a substrate 102 with one or more
device fins 104 formed upon it and separated by isolation features
106. The device fins 104 are representative of any raised feature,
and while the illustrated embodiments include FinFET device fins
104, further embodiments include other raised active and passive
devices formed upon the substrate 102. In some embodiments, the
FinFET device fins 104 include a pair of opposing source/drain
features 108 separated by a channel region 110. The flow of
carriers (electrons for an n-channel FinFET and holes for a
p-channel FinFET) through the channel region 110 is controlled by a
voltage applied to a gate stack 112 adjacent to and overwrapping
the channel region 110. The gate stack 112 is shown as translucent
to better illustrate the underlying channel region 110.
[0019] In the illustrated embodiment, the channel region 110 rises
above the plane of the substrate 102 upon which it is formed and
above the isolation features 106, and accordingly, circuit devices
formed on the device fins 104 may be referred to as a "nonplanar"
devices. The raised channel region 110 provides a larger surface
area proximate to the gate stack 112 than comparable planar
devices. This strengthens the electromagnetic field interactions
between the gate stack 112 and the channel region 110, which may
reduce leakage and short channel effects associated with smaller
devices. Thus in many embodiments, FinFETs, and other nonplanar
devices deliver better performance in a smaller footprint than
their planar counterparts.
[0020] The workpiece 100 may include a Multi-Layer Interconnect
(MLI) structure 114 to electrically couple the devices of the
device fins 104 and other circuit devices. Each layer of the MLI
structure 114 may include conductive elements (e.g., lines, vias,
contacts, gate stacks, etc.) disposed in an Inter-Level Dielectric
(ILD) 116 that supports and isolates these elements. The lower
layers of the MLI structure 114 may include the gate stack 112 and
source/drain contacts disposed in the ILD 116. In the upper layers,
MLI structure 114 may contain conductive lines and vias disposed in
the ILD. For clarity, in FIG. 1, only the lowest layer of the MLI
structure 114 is shown, and the ILD 116 is shown as translucent.
Latter figures illustrate additional layers of the MLI structure
114.
[0021] In some examples, the size and density of the workpiece 100
is limited by the density of the conductive lines within the MLI
structure 114. To address this, some of the fins (e.g., dummy fin
118) may include an interconnect line 120 buried below the top of
the isolation features 106. The buried interconnect line 120 may
relieve some of the routing congestion in the MLI structure 114,
and because it is proximate to the device fins 104, the buried
interconnect line 120 may be coupled directly to the source/drain
features 108 and/or the gate stacks 112 without any intervening
vias. As can be seen, the dummy fins 118 may be different in length
from the device fins 104. Selectively forming a dummy fins 118
where the buried interconnect line 120 is used to route a signal
and not extending the dummy fin 118 elsewhere may reduce the
capacitance associated with surplus conductive material.
[0022] The sides of the buried interconnect line 120 may be covered
and electrically isolated by the isolation features 106, and the
top of the interconnect line 120 may be covered and electrically
isolated by a dummy fin dielectric 122 disposed on the interconnect
line 120. In some examples, the dummy fin dielectric 122 extends
between the isolation features 106 to cover the top of the
interconnect line 120. The dummy fin dielectric 122 may be
patterned to expose the buried interconnect line 120 adjacent the
channel regions 110, the source/drain features 108, and/or
elsewhere to allow coupling to the interconnect line 120. In some
examples, the dummy fin dielectric 122 is patterned to allow a gate
stack 112 or a source/drain contact to electrically couple directly
to the interconnect line 120.
[0023] Exemplary methods of forming a workpiece with a buried
interconnect line 120, such as the workpiece 100 of FIG. 1, will
now be described with reference to FIGS. 2A-21B. Some of the
figures that follow refer to cross-sections taken through the
channel region 110 (e.g., along plane 124) and/or through the
source/drain features 108 (e.g., along plane 126) of the device
fins 104. For reference, these cross-sectional planes 124 and 126
are shown in FIG. 1.
[0024] FIGS. 2A and 2B are flow diagrams of a method 200 of
fabricating a workpiece 300 with a buried interconnect line
according to various aspects of the present disclosure. The
workpiece 300 may be substantially similar to the workpiece 100 of
FIG. 1 in many regards. Additional steps can be provided before,
during, and after the method 200, and some of the steps described
can be replaced or eliminated for other embodiments of the method
200. FIGS. 3A and 12 are perspective view diagrams of the workpiece
300 at various stages of the method 200 of fabricating a workpiece
300 with a buried interconnect line according to various aspects of
the present disclosure. FIGS. 3B, 4-11, 13A, 14A, 15A, 16A, 17A,
18A, 19A, 20A, and 21A are cross-sectional diagrams taken along a
channel region 110 of the workpiece 300 at various stages of the
method 200 of fabricating a workpiece 300 with a buried
interconnect line according to various aspects of the present
disclosure. Throughout the corresponding processes of blocks
202-220, the source/drain features 108 and the channel regions 110
may undergo substantially similar processes. To avoid unnecessary
duplication, the substantially similar cross-sectional views
showing a cross section taken along the source/drain features 108
are omitted. However, where the regions may differ, both channel
region 110 and source/drain feature 108 cross-sections are
provided. In that regard, FIGS. 13B, 14B, 15B, 16B, 17B, 18B, 19B,
20B, and 21B are cross-sectional diagrams of the workpiece 300
taken along a source/drain feature 108 at various stages of the
method 200 of fabricating a workpiece 300 with a buried
interconnect line according to various aspects of the present
disclosure. Additionally, FIG. 17C is a perspective view of the
workpiece 300 at a stage of the method 200 of fabricating a
workpiece 300 with a buried interconnect line according to various
aspects of the present disclosure.
[0025] Referring first to block 202 of FIG. 2A and to FIGS. 3A and
3B, a workpiece 300 is received that includes a substrate 102 upon
which fins are to be formed. In various examples, the substrate 102
includes an elementary (single element) semiconductor, such as
silicon or germanium in a crystalline structure; a compound
semiconductor, such as silicon germanium, silicon carbide, gallium
arsenic, gallium phosphide, indium phosphide, indium arsenide,
and/or indium antimonide; a non-semiconductor material, such as
soda-lime glass, fused silica, fused quartz, and/or calcium
fluoride (CaF.sub.2); and/or combinations thereof.
[0026] The substrate 102 may be uniform in composition or may
include various layers, some of which may be selectively etched to
form the fins. The layers may have similar or different
compositions, and in various embodiments, some substrate layers
have non-uniform compositions to induce device strain and thereby
tune device performance. Examples of layered substrates include
silicon-on-insulator (SOI) substrates 102. In some such examples, a
layer of the substrate 102 may include an insulator such as a
semiconductor oxide, a semiconductor nitride, a semiconductor
oxynitride, a semiconductor carbide, and/or other suitable
insulator materials.
[0027] Referring to block 204 of FIG. 2A and referring still to
FIGS. 3A and 3B, a first hard mask 302 is formed on the substrate
102 and patterned to define the device fins 104 and dummy fins 118
to be formed in subsequent processes. The first hard mask 302 may
include a dielectric such as a semiconductor oxide, a semiconductor
nitride, a semiconductor oxynitride, and/or a semiconductor
carbide, and in an exemplary embodiment, the first hard mask 302
includes silicon nitride. The first hard mask 302 may be formed to
any suitable thickness and by any suitable process including
thermal growth, chemical vapor deposition (CVD), high-density
plasma CVD (HDP-CVD), physical vapor deposition (PVD), atomic-layer
deposition (ALD), and/or other suitable deposition processes.
[0028] To pattern the first hard mask 302, a first photoresist 304
may be formed on the first hard mask 302. An exemplary first
photoresist 304 includes a photosensitive material sensitive to
radiation such as UV light, deep ultraviolet (DUV) radiation,
and/or EUV radiation. A lithographic exposure is performed on the
workpiece 300 that exposes selected regions of the first
photoresist 304 to radiation. The exposure causes a chemical
reaction to occur in the exposed regions of the first photoresist
304. After exposure, a developer is applied to the first
photoresist 304. The developer dissolves or otherwise removes
either the exposed regions in the case of a positive resist
development process or the unexposed regions in the case of a
negative resist development process. Suitable positive developers
include TMAH (tetramethyl ammonium hydroxide), KOH, and NaOH, and
suitable negative developers include solvents such as n-butyl
acetate, ethanol, hexane, benzene, and toluene.
[0029] After the first photoresist 304 is developed, the first hard
mask 302 may be patterned by an etching process that removes
portions of the first hard mask 302 exposed by the first
photoresist 304. In various examples, etching is performed by wet
etching, dry etching, Reactive Ion Etching (RIE), ashing, and/or
other etching methods using etchant chemistries such as carbon
tetrafluoride (CF.sub.4), difluoromethane (CH.sub.2F.sub.2),
trifluoromethane (CHF.sub.3), other suitable etchants, and/or
combinations thereof. After etching the first hard mask 302, the
first photoresist 304 may be removed.
[0030] In the illustrated examples, the first hard mask 302 defines
four device fins 104 and one dummy fin 118 of uniform width as
indicated by markers 306, although in further examples, the first
hard mask 302 may define any number of device fins 104 and dummy
fins 118 of any suitable width. The device fins 104 and the dummy
fins 118 may extend to any length 308, and in many examples, the
dummy fins 118 and the resulting buried interconnect are shorter in
length than the device fins 104. The spacing between fins may be
uniform or may vary, and in some embodiments, the dummy fin 118 has
additional spacing and subsequent processes enlarge the width of
the fin to lower the resistance of a buried interconnect line as
shown in blocks 206-208.
[0031] Referring to block 206 of FIG. 2A and to FIG. 4, a second
hard mask 402 is formed on at least the sidewalls of the first hard
mask 302. The second hard mask 402 may include any suitable
material (e.g., semiconductor, semiconductor oxide, semiconductor
nitride, semiconductor oxynitride, semiconductor carbide, etc.),
and may be selected to have a different etchant selectivity than
the first hard mask 302. In an example, the first hard mask 302
includes silicon nitride, and the second hard mask 402 includes
amorphous silicon.
[0032] The second hard mask 402 may be deposited by any suitable
process including CVD, HDP-CVD, ALD, PVD, and/or other suitable
deposition techniques. In some such embodiments, the material of
the second hard mask 402 is deposited conformally by CVD or ALD and
an anisotropic (directional) etching technique such, as an
anisotropic plasma etching, is performed to remove portions of the
second hard mask 402 deposited on horizontal surfaces of the
substrate 102. In this way, portions of the second hard mask 402
deposited on the vertical surfaces of the first hard mask 302
remain. In some examples, the second hard mask 402 remains on the
horizontal surfaces of the first hard mask 302. In further
examples, etching the second hard mask 402 from the horizontal
surfaces of the substrate 102 also removes the second hard mask 402
from the horizontal surfaces of the first hard mask 302.
[0033] The second hard mask 402 may be used to widen the dummy fin
118 relative to the device fins 104 by removing it from the device
fins 104. Referring to block 208 of FIG. 2A and to FIGS. 5 and 6,
the second hard mask 402 is selectively removed from portions of
the first hard mask 302 corresponding to device fins 104 while
being preserved on the portion of the first hard mask 302
corresponding to the dummy fin 118. In an example, a second
photoresist 502 is formed on the first hard mask 302 and the second
hard mask 402 as shown in FIG. 5. In many regards, the second
photoresist 502 may be substantially similar to the first
photoresist 304, and a similar lithographic exposure may be
performed on the workpiece 300 to expose selected regions of the
second photoresist 502 to radiation. After exposure, a developer is
applied to the second photoresist 502 to remove the second
photoresist 502 from over the first hard mask 302 features that
define device fins 104 while leaving the second photoresist 502
over the first hard mask 302 features that define the dummy fin
118.
[0034] Referring to FIG. 6, after the second photoresist 502 is
developed, the exposed portions of the second hard mask 402 may be
removed by an etching process, such as wet etching, dry etching,
Reactive Ion Etching (RIE), ashing, and/or other etching methods.
In an example, the etching process includes an ammonia dip to
remove amorphous silicon of the second hard mask 402. After
etching, the second photoresist 502 may be removed.
[0035] Referring to block 210 of FIG. 2A and to FIG. 7, the
substrate 102 is etched using the first hard mask 302 and the
second hard mask 402 to define the device fins 104 and the dummy
fin 118. The etching processes may include any suitable etching
technique such as wet etching, dry etching, RIE, ashing, and/or
other etching methods. In some embodiments, etching includes
multiple etching steps with different etching chemistries, each
targeting a particular material of the substrate 102 and each
selected to resist etching the first hard mask 302 and the second
hard mask 402. For example, in an embodiment, the substrate 102 is
etched by a dry etching process using a fluorine-based etchant
(e.g., CF.sub.4, CHF.sub.3, CH.sub.2F.sub.2, etc.).
[0036] The etching is configured to produce device fins 104 and
dummy fins 118 of any suitable height and width extending above the
reminder of the substrate 102. In some examples, the processes of
blocks 206-208 result in a dummy device fin 104 that is wider than
the device fins 104 as indicated by markers 702 and 704. The wider
dummy device fin 104 may produce a wider buried interconnect line
with lower resistance and reduced risk of discontinuities.
[0037] In addition to defining the device fins 104 and dummy fins
118, the etching of block 210 may also define one or more isolation
feature trenches 706 between the device fins 104 and dummy fins
118. Referring to block 212 of FIG. 2A and to FIG. 8, the isolation
feature trenches 706 are filled with a dielectric material to form
an isolation feature 106, such as a shallow trench isolation
feature (STI). Suitable dielectric materials for the isolation
features 106 include semiconductor oxides, semiconductor nitrides,
semiconductor carbides, FluoroSilicate Glass (FSG), low-K
dielectric materials, and/or other suitable dielectric materials.
The dielectric material may be deposited by any suitable technique
including thermal growth, CVD, HDP-CVD, PVD, ALD, and/or spin-on
techniques. In one such embodiment, a CVD process is used to
deposit a flowable dielectric material that includes both a
dielectric component and a solvent in a liquid or semiliquid state.
A curing process is used to drive off the solvent, leaving behind
the dielectric material of the isolation features 106 in its solid
state. Following the deposition, a Chemical Mechanical
Polishing/Planarization (CMP) process may be performed to remove
excess dielectric material.
[0038] Referring to block 214 of FIG. 2A and to FIG. 9, a portion
of the dummy fin 118 may be removed. This may create a recess
between the isolation features 106 for the buried interconnect
line. In some examples, the patterning of block 214 leaves a
portion of the substrate 102 remaining between the isolation
features 106 having any suitable height (as indicated by marker
902). However, in some examples, the patterning completely removes
the substrate 102 of the dummy fin 118 between the isolation
features 106.
[0039] The dummy fin 118 may be selectively removed using any
suitable technique. In an embodiment, a third photoresist 904 is
formed on the workpiece 300. In many regards, the third photoresist
904 may be substantially similar to the first photoresist 304
and/or the second photoresist 502, and a similar lithographic
exposure may be performed on the workpiece 300 to expose selected
regions of the third photoresist 904 to radiation. After exposure,
a developer is applied to the third photoresist 904 to remove the
third photoresist 904 from over the dummy fin 118. After the third
photoresist 904 is developed, exposed portions of the first hard
mask 302, second hard mask 402, and the substrate 102 may be
removed by an etching process, such as wet etching, dry etching,
RIE, ashing, and/or other etching methods. In some embodiments,
etching includes multiple etching steps with different etching
chemistries, each targeting a particular material of the first hard
mask 302, the second hard mask 402, and the substrate 102 while
resisting etching of the third photoresist 904 and the isolation
features 106. By selecting an etchant that resists etching the
isolation features, in some embodiments, portions of the isolation
features 106 adjacent to the dummy fin 118 are exposed without
consequence. This may increase the tolerance of the
photolithographic process. The third photoresist 904 may be removed
after the etching process completes.
[0040] Referring to block 216 of FIG. 2A and to FIG. 10, a
conductive material is deposited on the substrate 102 of the dummy
fin 118 between the isolation features 106 to form the buried
interconnect line 120. The buried interconnect line 120 may include
any suitable conductive material deposited by any suitable
technique such as CVD, HDP-CVD, PVD, ALD, and/or other suitable
techniques. In some examples, the buried interconnect line 120
includes tungsten, a tungsten alloy, ruthenium, RuO.sub.2, and/or
other ruthenium compounds deposited by CVD. Tungsten and ruthenium
may be used because of their resilience to diffusion during high
temperature processes. Other suitable materials for the buried
interconnect line 120 include Ti, TiN, polysilicon, and/or a
Cu-containing fill material with a tungsten-, titanium-, or
ruthenium-containing liner. The conductive material may be
deposited to any suitable thickness. In various examples, the
resulting interconnect line 120 has a height 1002 in a vertical
direction of between about 10 nm and about 30 nm, has a width 1004
in a horizontal direction of between about 8 nm and about 16 nm,
and the top of the interconnect line 120 is between about 10 nm and
about 30 nm below a top surface of the isolation features 106. In
such examples, the interconnect line 120 has an aspect ratio
(width:height) of between about 1:4 and about 3:2.
[0041] Referring to block 218 of FIG. 2A and to referring still to
FIG. 10, a dummy fin dielectric 122 may be deposited on the buried
interconnect line 120. The dummy fin dielectric 122 may include any
suitable dielectric material including a semiconductor oxide, a
semiconductor nitride, a semiconductor oxynitride, a semiconductor
carbide, and/or other suitable dielectric materials, and may be
deposited by any suitable deposition process including thermal
growth, CVD, HDP-CVD, PVD, ALD, and/or other suitable processes. In
an example, the dummy fin dielectric 122 includes silicon carbon
nitride (SiCN) deposited by CVD. Following the deposition, a CMP
process may be performed to remove excess dielectric material.
[0042] Referring to block 220 of FIG. 2A and referring to FIG. 11,
the isolation features 106 are recessed. Any suitable etching
technique may be used to recess the isolation features 106
including dry etching, wet etching, RIE, and/or other etching
methods, and in an exemplary embodiment, an anisotropic dry etching
is used to selectively remove the dielectric material of the
isolation features 106 without etching the substrate 102. The
remainder of the first hard mask 302 and the second hard mask 402
may also be removed before, during, and/or after the recessing of
the isolation features 106. In some examples, the first hard mask
302 and second hard mask 402 are removed by a CMP process performed
prior to the recessing of the isolation features 106. In some
examples, the first hard mask 302 and second hard mask 402 are
removed by an etchant used to recess the isolation features
106.
[0043] A dummy gate may then be formed over a channel region 110 of
the device fins 104. Referring to block 222 of FIG. 2B and
referring to FIG. 12, a dummy gate 1202 is formed on the channel
region 110. In FIG. 12, one dummy gate 1202 is shown as translucent
to better illustrate the underlying channel region 110. The dummy
gate 1202 may reserve an area for a metal gate stack and may
include a dummy gate layer 1204, a dummy gate hard mask 1206, gate
spacers 1208, and/or other components. Accordingly, in some
embodiments, forming the dummy gate 1202 includes depositing the
dummy gate layer 1204 containing polysilicon or other suitable
material and patterning the dummy gate layer 1204 in a lithographic
process. Thereafter, the dummy gate hard mask 1206 is formed on the
dummy gate layer 1204. The dummy gate hard mask 1206 may include
any suitable material, such as a semiconductor oxide, a
semiconductor nitride, a semiconductor carbide, a semiconductor
oxynitride, other suitable materials, and/or combinations
thereof.
[0044] In some embodiments, gate spacers 1208 are formed on each
side of the dummy gate (on the sidewalls of the dummy gate layer
1204 and/or dummy gate hard mask 1206). The gate spacers 1208 may
be used to offset the subsequently formed source/drain features and
may be used for designing or modifying the source/drain structure
(junction) profile. The gate spacers 1208 may include any suitable
dielectric material, such as a semiconductor oxide, a semiconductor
nitride, a semiconductor carbide, a semiconductor oxynitride, other
suitable materials, and/or combinations thereof.
[0045] Referring to block 224 of FIG. 2B and to FIGS. 13A and 13B,
an epitaxial process is performed to form source/drain features 108
on the substrate 102 in the source/drain regions of the device fins
104. The dummy gate and/or gate spacers 1208 limit the source/drain
features 108 to the source/drain regions. Suitable epitaxy
processes include CVD deposition techniques (e.g., vapor-phase
epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular
beam epitaxy, and/or other suitable processes. The epitaxy process
may use gaseous and/or liquid precursors, which interact with the
composition of the substrate 102.
[0046] The source/drain features 108 may be in-situ doped during
the epitaxy process by introducing doping species including: p-type
dopants, such as boron or BF.sub.2; n-type dopants, such as
phosphorus or arsenic; and/or other suitable dopants including
combinations thereof. If the source/drain features 108 are not
in-situ doped, an implantation process (i.e., a junction implant
process) is performed to dope the source/drain features 108. In an
exemplary embodiment, the source/drain features 108 in an NMOS
device include SiP, while those in a PMOS device include GeSnB (tin
may be used to tune the lattice constant) and/or SiGeSnB. One or
more annealing processes may be performed to activate the
source/drain features 108. Suitable annealing processes include
rapid thermal annealing (RTA) and/or laser annealing processes.
[0047] Referring to block 226 of FIG. 2B and to FIGS. 14A and 14B,
an Inter-Level Dielectric (ILD) 116 is formed on the source/drain
features 108 in the source/drain regions. The ILD 116 may be part
of an electrical MLI structure 114 that electrically interconnects
the devices of the workpiece including the FinFET devices formed on
the device fins 104. In such embodiments, the ILD 116 acts as an
insulator that supports and isolates conductive traces of the MLI
structure 114. The ILD 116 may comprise any suitable dielectric
material, such as a semiconductor oxide, a semiconductor nitride, a
semiconductor oxynitride, a semiconductor carbide, other suitable
materials, and/or combinations thereof.
[0048] The ILD 116 may surround the dummy gate 1202 allowing it to
be removed and a replacement gate to be formed in the resulting
cavity. Accordingly, in such embodiments, the dummy gate layer 1204
and dummy gate hard mask 1206 are removed after depositing the ILD
116 as shown in block 228 of FIG. 2B and FIGS. 15A and 15B.
[0049] A gate stack 112 is formed on the workpiece 100 wrapping
around the channel regions 110 of the device fins 104. Although it
is understood that the gate stack 112 may be any suitable gate
structure, in some embodiments, the gate stack 112 is a high-k
metal gate that includes an interfacial layer 1602, a gate
dielectric layer 1604, and a gate electrode 1802 that may each
comprise a number of sub-layers.
[0050] Referring to block 230 of FIG. 2B and to FIGS. 16A and 16B,
in some such embodiments, the interfacial layer 1602 is deposited
on the workpiece 300 and the gate dielectric layer 1604 is
deposited on the interfacial layer 1602. With respect to the
interfacial layer 1602, it may be deposited by any suitable
technique, such as ALD, CVD, ozone oxidation, etc. The interfacial
layer 1602 may include a metal silicate (e.g., HfSiO), a metal or
semiconductor oxide, a metal or semiconductor nitride, a metal or
semiconductor oxynitride, and/or other suitable material. Likewise,
the gate dielectric layer 1604 is deposited on the interfacial
layer 1602 by any suitable technique, such as ALD, CVD,
metal-organic CVD (MOCVD), PVD, thermal oxidation, combinations
thereof, and/or other suitable techniques. A high-k-type gate
dielectric layer 1604 may include a metal oxide (e.g., LaO, AlO,
ZrO, TiO, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, SrTiO.sub.3 (STO),
BaTiO.sub.3 (BTO), BaZrO, HfZrO, HfLaO, HfTaO, HfTiO,
(Ba,Sr)TiO.sub.3 (BST), Al.sub.2O.sub.3, etc.) a metal silicate
(e.g., HfSiO, LaSiO, AlSiO, etc.), a metal or semiconductor
nitride, a metal or semiconductor oxynitride, combinations thereof,
and/or other suitable materials.
[0051] Some gate stacks 112 may electrically couple directly to the
buried interconnect line 120. Referring to block 232 of FIG. 2B and
to FIGS. 17A, 17B, and 17C, the interfacial layer 1602, gate
dielectric layer 1604, and dummy fin dielectric 122 may be removed
to expose the buried interconnect line 120 in those locations on
the workpiece 300 where a gate stack 112 is to electrically couple
to the buried interconnect line 120. In an example, a fourth
photoresist 1702 is formed on the workpiece 300, and a lithographic
exposure is performed that exposes selected regions of the fourth
photoresist 1702 to radiation. After exposure, a developer is
applied to the fourth photoresist 1702 to remove the portions of
the fourth photoresist 1702 from over the dummy fin dielectric 122
in locations where a gate stack 112 is to couple to the buried
interconnect line 120. Referring to FIG. 17C, a recess in the
patterned fourth photoresist 1702 is indicated by marker 1704.
[0052] After the fourth photoresist 1702 is developed, exposed
portions of the interfacial layer 1602, gate dielectric layer 1604,
and the dummy fin dielectric 122 may be removed by an etching
process, such as wet etching, dry etching, RIE, ashing, and/or
other etching methods. In various examples, the etching process
includes one or more anisotropic (directional) etching processes
configured to etch faster in a vertical direction than a horizontal
direction using one or more etchants configured to selectively etch
the interfacial layer 1602, the gate dielectric layer 1604, and the
dummy fin dielectric 122. The fourth photoresist 1702 may be
removed after the etching process completes.
[0053] Referring to block 234 of FIG. 2B and to FIGS. 18A and 18B,
a gate electrode 1802 is deposited on the channel regions 110 of
the workpiece. In particular, the gate electrode 1802 may be
deposited on the interfacial layer 1602 and the gate dielectric
layer 1604 and may be electrically coupled to the buried
interconnect line 120 in regions where the interfacial layer 1602
and the gate dielectric layer 1604 have been removed. In various
examples, the gate electrode 1802 is formed by ALD, PVD, CVD, or
other suitable process, and may include a single layer or multiple
layers, such as a metal layer, a liner layer, a wetting layer,
and/or an adhesion layer. The gate electrode 1802 may include Ti,
Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN,
Cu, W, and/or any other suitable materials. In some embodiments,
different metal gate materials are used for nMOS and pMOS devices.
A CMP process may be performed to produce a substantially planar
top surface of the gate stack 112.
[0054] At any time before, during, or after forming the gate stacks
112, contacts and vias to the source/drain features 108 may be
formed. Some of the source/drain contacts may extend to and
electrically couple to the buried interconnect line 120. Referring
to block 236 of FIG. 2B and to FIGS. 19A and 19B, the ILD 116 and
dummy fin dielectric 122 may be removed to expose the buried
interconnect line 120 in those locations on the workpiece 300 where
a source/drain contact is to electrically couple to the buried
interconnect line 120. In an example, a fifth photoresist 1902 is
formed on the workpiece 300, and a lithographic exposure is
performed that exposes selected regions of the fifth photoresist
1902 to radiation. After exposure, a developer is applied to the
fifth photoresist 1902 to remove the portions of the fifth
photoresist 1902 from over the ILD 116 and the dummy fin dielectric
122 in locations where a source/drain contact is to couple to the
buried interconnect line 120. After the fifth photoresist 1902 is
developed, exposed portions of the ILD 116 and the dummy fin
dielectric 122 may be removed by an etching process, such as wet
etching, dry etching, RIE, ashing, and/or other etching methods. In
various examples, the etching process includes one or more
anisotropic (directional) etching processes configured to etch
faster in a vertical direction than a horizontal direction using
one or more etchants configured to selectively etch the ILD and the
dummy fin dielectric 122. The fifth photoresist 1902 may be removed
after the etching process completes.
[0055] The etching of block 236 exposes the source/drain features
108 of the device fins 104. Referring to block 238 of FIG. 2B and
to FIGS. 20A and 20B, a source/drain contact 2002 is deposited on
the source/drain features 108. The contact 2002 may electrically
couple the source/drain features 108 to the buried interconnect
line 120, and may include one or more layers of conductive
materials such as metals (e.g., W, Al, Ta, Ti, Ni, Cu, etc.), metal
oxides, metal nitrides, and/or combinations thereof. In some
examples, the contact 2002 contains a barrier layer that includes
W, Ti, TiN, Ru, and/or combinations thereof and contains a
Cu-containing fill material disposed on the barrier layer. In some
examples, the contact 2002 includes tungsten, which is deposited
with or without a barrier layer. In some examples, the contact
includes a cobalt contact material. The material(s) of the contact
2002 may be deposited by any suitable technique including PVD
(e.g., sputtering), CVD, PE CVD, ALD, PEALD, and/or combinations
thereof. A planarization process can be performed to remove
portions of the contact material that is above the ILD 116.
[0056] Referring to block 240 of FIG. 2B, and to FIGS. 21A and 21B,
the workpiece 300 is provided for further fabrication processes.
These processes may include forming additional layers of the MLI
structure 114. Each layer may include conductive features, such as
interconnect lines 2202 and vias 2204, disposed in additional
layers of the ILD 166. In various examples, the interconnect lines
2202 and vias 2204 include a conductive material such as copper,
aluminum, aluminum/silicon/copper alloy, titanium, titanium
nitride, tungsten nitride, metal silicide, non-metallic conductive
material, and/or combinations thereof. In some examples, the
interconnect lines 2202 and vias 2204 include a barrier layer, such
as a tungsten or tungsten nitride barrier layer, and a fill
material such as copper disposed on the barrier layer. The barrier
layer may be configured to prevent diffusion of the fill
material.
[0057] Thus, the present disclosure provides examples of a buried
interconnect line for integrated circuit fabrication. In some
examples, a device includes a fin disposed on a substrate, and the
fin includes an active device. A plurality of isolation features
are disposed on the substrate and below the active device. An
interconnect is disposed on the substrate and between the plurality
of isolation features such that the interconnect is below a topmost
surface of the plurality of isolation features. The interconnect is
electrically coupled to the active device. In some such examples, a
gate stack of the active device is disposed over a channel region
of the active device and is electrically coupled to the
interconnect. In some such examples, the gate stack is directly
electrically coupled to the interconnect. In some such examples, a
gate electrode of the gate stack extends between the plurality of
isolation features to electrically couple to the interconnect. In
some such examples, a source/drain contact is electrically coupled
to a source/drain region of the active device and is electrically
coupled to the interconnect. In some such examples, the
source/drain contact is directly electrically coupled to the
interconnect. In some such examples, a horizontal width of the
interconnect is greater than a horizontal width of the fin. In some
such examples, a ratio of width to height of the interconnect is
between about 1:4 and about 3:2. In some such examples, a first
side surface of the interconnect is contacted in its entirety by
the plurality of isolation features, and a second side surface of
the interconnect that is opposite the first side surface is
contacted in its entirety by the plurality of isolation features.
In some such examples, the interconnect is disposed between the
substrate and a dielectric that extends between the plurality of
isolation features. In some such examples, a dummy fin portion of
the substrate extends between the plurality of isolation features
and extends to the interconnect.
[0058] In further examples, a device includes a plurality of FinFET
devices disposed on a plurality of fins, a plurality of isolation
features disposed between the plurality of fins, a conductive line
disposed between the plurality of isolation features such that the
conductive line is below a topmost surface of the plurality of
isolation features and above a bottommost surface of the plurality
of isolation features, and a dielectric disposed on the conductive
line between the plurality of isolation features. The conductive
line is electrically coupled to the plurality of FinFET devices. In
some such examples, a gate stack is disposed over channel regions
of the plurality of FinFET devices and is electrically coupled to
the conductive line. In some such examples, a gate electrode of the
gate stack extends between the plurality of isolation features to
electrically couple to the conductive line. In some such examples,
a source/drain contact is disposed over source/drain features of
the plurality of FinFET devices and is electrically coupled to the
source/drain features and to the conductive line. In some such
examples, the source/drain contact extends between the plurality of
isolation features to electrically couple to the conductive line.
In some such examples, an inter-level dielectric is disposed over
the isolation features, over the conductive line, and between the
plurality of FinFET devices. In some such examples, the conductive
line has a horizontal width that is greater than a horizontal width
of each of the plurality of fins.
[0059] In yet further examples, a method includes receiving a
substrate; forming on the substrate: a plurality of device fins, a
dummy fin, and a plurality of isolation features disposed between
the plurality of device fins and the dummy fin; recessing the dummy
fin to a height below the plurality of isolation features; and
depositing a conductive material on the recessed dummy fin between
the plurality of isolation features. In some such examples, a
dielectric is deposited on the conductive material between the
plurality of isolation features; a portion of the dielectric
adjacent a channel region of the plurality of device fins is
recessed; and a gate stack is formed over the channel region. The
gate stack is electrically coupled to the conductive material. In
some such examples, a dielectric is deposited on the conductive
material between the plurality of isolation features; a portion of
the dielectric adjacent a source/drain feature of the plurality of
device fins is recessed; and a source/drain contact is formed on
the source/drain feature. The source/drain contact is electrically
coupled to the source/drain feature and to the conductive
material.
[0060] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *