U.S. patent application number 15/942705 was filed with the patent office on 2019-01-31 for high energy density capacitor system and method.
The applicant listed for this patent is Flash Power Capacitors, LLC. Invention is credited to Edward L. Davis.
Application Number | 20190035562 15/942705 |
Document ID | / |
Family ID | 65038200 |
Filed Date | 2019-01-31 |
United States Patent
Application |
20190035562 |
Kind Code |
A1 |
Davis; Edward L. |
January 31, 2019 |
HIGH ENERGY DENSITY CAPACITOR SYSTEM AND METHOD
Abstract
A high energy density capacitor comprising a substrate, a
positive electrode, a negative electrode, a plurality of
intermediate dielectric layers disposed between the positive
electrode and negative electrode, and a metal layer deposited on
each of the intermediate dielectric layers. Each intermediate
dielectric layer comprises sequential layers of a high surface area
dielectric material, an electrolyte and a polar organic solvent
deposited onto the substrate. The plurality of intermediate
dielectric layers and metal layers are arranged in series to form a
stack, and at least one an internal passivation layer is disposed
between each stack. The positive and negative electrodes extend
along a height of the capacitor and have poles in an alternating
arrangement around an edge thereof, wherein the positive and
negative electrodes are attached to periodic metal layers deposited
on each of the intermediate dielectric layers. Dipoles of the
intermediate dielectric layers are aligned in an opposite direction
of an electric field created between the positive and negative
electrodes while charging.
Inventors: |
Davis; Edward L.; (Estacada,
OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Flash Power Capacitors, LLC |
Las Vegas |
NV |
US |
|
|
Family ID: |
65038200 |
Appl. No.: |
15/942705 |
Filed: |
April 2, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62556640 |
Sep 11, 2017 |
|
|
|
62511727 |
May 26, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 51/05 20130101;
H01L 51/0007 20130101; H01G 11/86 20130101; H01G 11/22 20130101;
H01G 11/60 20130101; H01G 11/84 20130101; H01G 11/52 20130101; H01G
11/58 20130101 |
International
Class: |
H01G 11/60 20060101
H01G011/60; H01G 11/86 20060101 H01G011/86; H01G 11/22 20060101
H01G011/22 |
Claims
1. A high energy density capacitor, comprising: a substrate; a
positive electrode; a negative electrode; at least one intermediate
dielectric layer disposed between the positive electrode and
negative electrode, the at least one intermediate dielectric layer
comprised of a high surface area dielectric material, an
electrolyte and a polar organic solvent; and a metal layer
deposited on each of the at least one intermediate dielectric
layers.
2. The capacitor according to claim 1 wherein the high surface area
dielectric material has a dielectric constant in the range of about
10.sup.9 to about 10.sup.11.
3. The capacitor according to claim 1 wherein the polar organic
solvent is a polar protic solvent selected from the group
comprising NH.sub.3, (CH.sub.3).sub.3COH, C.sub.3H.sub.8O,
C.sub.2H.sub.6O, CH.sub.3OH, CH.sub.3COOH, and H.sub.2O.
4. The capacitor according to claim 1 wherein the polar organic
solvent is a polar aprotic solvent selected from the group
comprising C.sub.3H.sub.6O, (CH.sub.3).sub.2NCH, CH.sub.3CN,
C.sub.2H.sub.6OS, CH.sub.2Cl.sub.2, C.sub.4H.sub.8O, and
C.sub.4H.sub.8O.sub.2.
5. The capacitor according to claim 1 wherein the intermediate
dielectric layer is formed by depositing sequential layers of the
high surface area dielectric material, electrolyte and polar
organic solvent onto the substrate using semiconductor fabrication
techniques.
6. The capacitor according to claim 1 further comprising: a
plurality of intermediate dielectric layers and metal layers
arranged in series to form a stack; and at least one an internal
passivation layer disposed between each stack.
7. The capacitor according to claim 1 wherein the at least one
intermediate dielectric layer is comprised by molar percentage of
about 3% to about 20% electrolyte, about 3% to about 20% dielectric
material, and about 60% to about 94% polar organic solvent.
8. The capacitor according to claim 1 wherein dipoles of the at
least one intermediate dielectric layer align in an opposite
direction of an electric field created between the positive and
negative electrodes while charging.
9. The capacitor according to claim 1 wherein the positive and
negative electrodes extend along a height of the capacitor and have
poles in an alternating arrangement around an edge thereof, and
wherein the positive and negative electrodes are attached to
periodic metal layers deposited on each of the at least one
intermediate dielectric layers.
10. A method of forming a high energy density capacitor,
comprising: providing a substrate; providing a positive electrode
disposed on the substrate; providing a negative electrode opposite
the positive electrode; providing at least one intermediate
dielectric layer disposed between the positive electrode and
negative electrode, the at least one intermediate dielectric layer
comprised of a high surface area dielectric material, an
electrolyte and a polar organic solvent; and providing a metal
layer deposited on each of the at least one intermediate dielectric
layers.
11. The method according to claim 10 wherein the step of providing
at least one intermediate dielectric layer disposed between the
positive electrode and negative electrode further comprises:
depositing sequential layers of the high surface area dielectric
material, electrolyte and polar organic solvent onto the substrate
using semiconductor fabrication techniques.
12. The method according to claim 10 further comprising: providing
a plurality of intermediate dielectric layers and metal layers
arranged in series to form a stack; and providing at least one an
internal passivation layer disposed between each stack.
13. The method according to claim 10 further comprising: aligning
dipoles of the at least one intermediate dielectric layer such that
the polarized dielectric layer opposes an electric field created
between the positive and negative electrodes while charging.
14. The method according to claim 10 further comprising:
positioning the positive and negative electrodes to extend along a
height of the capacitor such that poles of the electrodes are in an
alternating arrangement around an edge thereof; and attaching the
positive and negative electrodes to periodic metal layers deposited
on each of the at least one intermediate dielectric layers.
15. The method according to claim 10 wherein the polar organic
solvent is a polar protic solvent selected from the group
comprising NH.sub.3, (CH.sub.3).sub.3COH, C.sub.3H.sub.8O,
C.sub.2H.sub.6O, CH.sub.3OH, CH.sub.3COOH, and H.sub.2O.
16. The method according to claim 10 wherein the polar organic
solvent is a polar aprotic solvent selected from the group
comprising C.sub.3H.sub.6O, (CH.sub.3).sub.2NCH, CH.sub.3CN,
C.sub.2H.sub.6OS, CH.sub.2Cl.sub.2, C.sub.4H.sub.8O, and
C.sub.4H.sub.8O.sub.2.
Description
RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Patent
Application No. 62/511,727 filed May 26, 2017, and U.S. Provisional
Patent Application No. 62/556,640 filed Sep. 11, 2017, the entire
disclosures of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] Embodiments of the present invention relate generally to
energy storage.
2. Description of Related Art
[0003] The potential energy in a capacitor is stored in an electric
field, whereas a battery stores its potential energy in a chemical
form. The technology for chemical storage currently yields greater
energy densities (capable of storing more energy per weight) than
capacitors, but batteries require much longer to charge.
[0004] Prior art ultra-capacitors have energy densities far below
comparably sized batteries of any modern chemistry on the market.
The highest energy density ultra-capacitor commercially available
today is Maxwell at 6 Wh/kg. Batteries like lithium ion are over
100 Wh/kg.
[0005] There is a significant need for high energy density
capacitors to replace batteries in many applications (e.g. electric
vehicles and other modes of transportation including planes or
trains, cell phones, backup storage for utilities, windmills, and
any other type of electrical facility) because capacitors can be
charged and discharged very rapidly and last for many thousands,
even millions of cycles. Whereas, batteries typically charge very
slowly and last only a couple thousand full cycles at most, and
much less if discharged more than fifty percent (50%) each cycle.
Further, capacitors are not hazardous and do not have any of the
safety issues typically associated with batteries.
SUMMARY OF THE INVENTION
[0006] Bearing in mind the problems and deficiencies of the prior
art, it is therefore an object of the present invention to provide
an improved capacitor having a higher energy density.
[0007] It is another object of the present invention to provide an
improved capacitor having a three-dimensional dielectric
surface.
[0008] A further object of the invention is to provide an improved
capacitor by substantially increasing the dielectric constant "k",
while shrinking the distance between the plates.
[0009] It is yet another object of the present invention to provide
an improved method of forming a capacitor utilizing standard
semiconductor fabrication techniques by adding a supplemental
apparatus to aid in polarization alignment.
[0010] Still other objects and advantages of the invention will in
part be obvious and will in part be apparent from the
specification.
[0011] The above and other objects, which will be apparent to those
skilled in the art, are achieved in the present invention which is
directed to a high energy density capacitor comprising a substrate
and at least one dielectric layer disposed between a positive
electrode and a negative electrode. A metal layer is deposited on
each of the dielectric layers for attachment to the poles of the
electrodes. The positive and negative electrodes extend along a
height of the capacitor and have poles in an alternating
arrangement around an edge thereof, such that the positive and
negative electrodes are attached to periodic metal layers deposited
on each of the intermediate dielectric layers. Each intermediate
dielectric layer is polarized such that its dipoles are aligned in
an opposite direction of an electric field created between the
positive and negative electrodes while charging.
[0012] In one or more embodiments, the capacitor of the present
invention is a multi-layer capacitor comprising internal
passivation layers disposed between each capacitor stack, wherein a
stack consists of a plurality of intermediate dielectric layers and
metal layers arranged in series.
[0013] Each intermediate dielectric layer is comprised of a high
surface area dielectric material, an electrolyte and a polar
organic solvent, and is formed by depositing sequential layers of
the high surface area dielectric material, the electrolyte and the
polar organic solvent onto the substrate using semiconductor
fabrication techniques. The high surface area dielectric material
has a dielectric constant in the range of about 10.sup.9 to about
10.sup.11.
[0014] In one or more embodiments, the polar organic solvent may be
a polar protic solvent selected from the group comprising NH.sub.3,
(CH.sub.3).sub.3COH, C.sub.3H.sub.8O, C.sub.2H.sub.6O, CH.sub.3OH,
CH.sub.3COOH, and H.sub.2O. In other embodiments, the polar organic
solvent may be a polar aprotic solvent selected from the group
comprising C.sub.3H.sub.6O, (CH.sub.3).sub.2NCH, CH.sub.3CN,
C.sub.2H.sub.6OS, CH.sub.2Cl.sub.2, C.sub.4H.sub.8O, and
C.sub.4H.sub.8O.sub.2. Each intermediate dielectric layer may be
comprised by molar percentage of about three percent (3%) to about
twenty percent (20%) electrolyte, about three percent (3%) to about
wenty percent (20%) dielectric material, and about sixty percent
(60%) to about ninety-four percent (94%) polar organic solvent.
[0015] In another aspect, the present invention is directed to a
method of forming a high energy density capacitor, comprising:
providing a substrate, providing a positive electrode disposed on
the substrate and a negative electrode opposite the positive
electrode, providing at least one intermediate dielectric layer
disposed between the positive electrode and negative electrode, and
providing a metal layer deposited on each of the at least one
intermediate dielectric layers. Each intermediate dielectric layer
is comprised of a high surface area dielectric material, an
electrolyte and a polar organic solvent, and is formed by
depositing sequential layers of the high surface area dielectric
material, the electrolyte and the polar organic solvent onto the
substrate using semiconductor fabrication techniques.
[0016] The method may comprise positioning the positive and
negative electrodes to extend along a height of the capacitor such
that the poles of the electrodes are in an alternating arrangement
around an edge thereof, and attaching the positive and negative
electrodes to periodic metal layers deposited on each of the at
least one intermediate dielectric layers. The dipoles of each
intermediate dielectric layer may be aligned such that the
polarized dielectric layer opposes an electric field created
between the positive and negative electrodes while charging.
[0017] In one or more embodiments, the method may include providing
a plurality of intermediate dielectric layers and metal layers
arranged in series to form a stack, and providing at least one an
internal passivation layer disposed between each stack.
[0018] In one or more embodiments, the polar organic solvent in the
intermediate dielectric layer may be a polar protic solvent
selected from the group comprising NH.sub.3, (CH.sub.3).sub.3COH,
C.sub.3H.sub.8O, C.sub.2H.sub.6O, CH.sub.3OH, CH.sub.3COOH, and
H.sub.2O. In other embodiments, the polar organic solvent may be a
polar aprotic solvent selected from the group comprising
C.sub.3H.sub.6O, (CH.sub.3).sub.2NCH, CH.sub.3CN, C.sub.2H.sub.6OS,
CH.sub.2Cl.sub.2, C.sub.4H.sub.8O, and C.sub.4H.sub.8O.sub.2.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The features of the invention believed to be novel and the
elements characteristic of the invention are set forth with
particularity in the appended claims. The figures are for
illustration purposes only and are not drawn to scale. The
invention itself, however, both as to organization and method of
operation, may best be understood by reference to the detailed
description which follows taken in conjunction with the
accompanying drawings in which:
[0020] FIG. 1 depicts a wafer or panel with layers of metal and
dielectric layers, in accordance with disclosed embodiments of the
present invention.
[0021] FIG. 2 depicts the capacitors of the present invention in
serial parallel arrays, in accordance with disclosed
embodiments.
[0022] FIG. 3 depicts the capacitors of the present invention
having an alternating anode and cathode pole arrangement around the
edge of the device in order to get the charge in and out quickly
with minimal effective series resistance (ESR).
[0023] FIG. 4 depicts the dielectric surface area of a capacitor in
accordance with embodiments of the present invention, wherein
surface area "A" is a three dimensional (3D) surface area, as
opposed to two dimensional (2D).
[0024] FIG. 5 depicts the capacitor layer anatomy of a capacitor in
accordance with disclosed embodiments of the present invention.
[0025] FIG. 6 depicts a deposition chamber used in an exemplary
process for forming a capacitor in accordance with embodiments of
the present invention.
[0026] FIG. 7 depicts a deposition chamber used in a second
exemplary process for forming a capacitor in accordance with
embodiments of the present invention.
DESCRIPTION OF THE EMBODIMENT(S)
[0027] In describing the embodiments of the present invention,
reference will be made herein to FIGS. 1-7 of the drawings in which
like numerals refer to like features of the invention.
[0028] The high energy density capacitor of the present invention
provides a solution for replacing slow charging, short-life
batteries with quick charging, long-life capacitors. The method of
forming the capacitor(s) of the present invention utilizes atomic
layer deposition (ALD), metal oxide chemical vapor deposition
(MOCVD), Electrospray, Sputtering, 3D printing and other
semiconducting fabrication equipment to produce sub-micron thin
layers and the capability for at least twelve (12) inch wafers
and/or rectangular substrates, like those used for LED panels,
which are available in a wide variety of generations and sizes.
Wafers may also be sawed into any shape or size and stacked to any
height.
[0029] The instant invention takes advantages of these advances by
utilizing a large array of ALD machines and other standard
semiconducting fabrication machinery, 3D printing and robotic
automation to apply up to thousands of layers per day to mass
produce the capacitors in any shape or size.
[0030] The primary advantage that batteries currently have over
prior art capacitors is energy density. The capacitor of the
present invention eliminates this barrier.
[0031] Certain terminology is used herein for convenience only and
is not to be taken as a limitation of the invention. For example,
words such as "upper," "lower," "left," "right," "horizontal,"
"vertical," "upward," and "downward" merely describe the
configuration shown in the drawings. For purposes of clarity, the
same reference numbers may be used in the drawings to identify
similar elements.
[0032] Additionally, in the subject description, the word
"exemplary" is used to mean serving as an example, instance or
illustration. Any aspect or design described herein as "exemplary"
is not necessarily intended to be construed as preferred or
advantageous over other aspects or design. Rather, the use of the
word "exemplary" is merely intended to present concepts in a
concrete fashion.
[0033] Referring now to FIG. 1, an exemplary high energy density
capacitor of the present invention is shown. The capacitor includes
a wafer or substrate upon which is deposited alternating layers of
metal and dielectric layers, and further includes a positive
electrode 100, a negative electrode 101, and a "stack" of five (5)
capacitors 102, which makes a 25 volt stack at one-fifth
(1/5.sup.th) the capacitance of a single instantiation, since the
five are in series. It should be understood by those skilled in the
art that a "stack" of five capacitors is being shown for exemplary
purposes only, and that any number of capacitors may be
implemented, in series, in order to achieve the desired voltage per
design requirements, as will be described below. A passivation
layer 103 or insulator isolates the "stacks" 102. A metal layer
104, an ultra-dielectric material (UDM) layer 105, and the
substrate or wafer 106 complete the assembly, in accordance with
disclosed embodiments of the present invention.
[0034] FIG. 2 depicts how a plurality of capacitors are organized
in serial parallel arrays, in accordance with disclosed
embodiments. Capacitor 201 is a single capacitor formed with UDM
and metal layers. Stack 202 depicts a stack of five (5) capacitors
in series. Putting capacitors in series lowers the capacitance, but
it is necessary to increase the voltage. By way of example herein,
each capacitor 201 is rated at 5 volts, therefore the stack 202 is
rated up to 25 volts, albeit at one-fifth (1/5.sup.th) the
capacitance of a single capacitor. The total capacitance is
increased by arranging an array of stacks in parallel, because
capacitors in parallel sum. Up to n stacks 203 may be created until
the desired level of energy storage is achieved.
[0035] Capacitance is defined as:
C=(k.epsilon..sub.0A)/d
where:
[0036] C=Capacitance (Farads)
[0037] k=Dielectric multiplier
[0038] .epsilon..sub.0=permittivity constant
[0039] A=Area of the plates (m.sup.2)
[0040] d=distance between plates (.mu.m)
[0041] The present invention produces a high capacitance EDLC-type
electrochemical capacitor by substantially increasing the
dielectric constant "k", while shrinking the distance between the
plates.
[0042] Referring now to FIG. 3, the capacitors' alternating anode
300 and cathode 301 pole arrangement around the edge of the
capacitor device is shown. Alternating poles in such a way allows
the charge in and out quickly with minimal effective series
resistance (ESR). In larger capacitors, additional positive and
negative electrodes may be dispersed intermittently in the interior
of the capacitor device, and may be arranged around the center of
the device. As shown in the side view of FIG. 3, the electrodes
extend along the full height of the capacitor array, even though
these poles only attach to the metal layers periodically. In one
embodiment, the electrodes 301 are attached to every fifth layer
(as depicted in FIG. 1), in order to achieve 25 volt stacks. The
unconnected layers may be masked to create a gap between the metal
layers 501 and the electrodes 300, 301.
[0043] FIG. 4 depicts the dielectric surface area of an embodiment
of a capacitor of the present invention. Of particular note is that
surface area "A" is a three dimensional (3D) surface area, not 2D.
The atomic layer of conducting atoms snuggle in around the
dielectric atoms, forming a three dimensional structure which
yields a much higher surface area than just the 2D. It's the 3D
surface area which in this case is the surface area for a bunch of
half spheres, i.e. 1/2*(4.pi.r.sup.2) multiplied by the number of
atoms or molecules in the length by width area.
[0044] FIG. 5 depicts the capacitor layer anatomy of one embodiment
of the capacitor of the present invention, comprising anode and
cathode metal layers 501, with layers of high surface area
dielectric material (such as silica) and positive and negative
atomic layers disposed therebetween. FIG. 5 illustrates how the
dipoles 502 in the dielectric layer 500 align with the electric
field 503 of the capacitor, but in the opposite direction, which
leads to a reduction in the total field, and an increase in the
total quantity of charge that the capacitor can hold for a given
voltage/applied field. As a result, more charge can build up on the
positive and negative electrodes 501. The "k" in physics is
determined by the degree of polarization that the dielectric layers
500 can undergo, in other words, how many dipoles 502 are available
inside the "N"-type and "P"-type atomic layers to reduce the
applied field across the capacitor, thereby allowing more charge to
be stored on the plates.
[0045] The metal atoms with their conduction band and free
electrons snuggle in around the hemispherical surfaces of the top
of the dielectric layer (FIG. 4). Using pairs of high voltage
plates to align the dipoles, as will be described in more detail
below, the dielectric layers become "electrets," equivalent to
magnets; however, instead of aligning magnetic domains, the high
energy density capacitor of the present invention comprises
aligning electric dipole domains.
[0046] The present invention optimizes energy density by maximizing
the operating voltage. Some polar organic solvents have breakdown
voltages three (3) to four (4) times higher than distilled water,
and some are in the 5V range at micron thicknesses. By contrast,
distilled water breakdown voltage limits the operating voltage to
0.8 to 1.2 volts per cell. The present invention also encompasses
replacing the polar protic solvents with electric dipole materials,
electrets, that are deposited and aligned to oppose the main
electric field created when the capacitor is charging.
[0047] One advantage of the present invention is that each
capacitor may have a thickness of much less than 1 micron (.mu.m)
to optimize energy density while increasing capacitance.
[0048] The ultra-dielectric materials (UDM) utilized in one
embodiment comprise a combination of a polar organic solvent from
Table 1 below, an electrolyte from Table 2 below, and a high
surface area dielectric material from Table 3 below. In an
embodiment, polar protic solvents are used for their high
dielectric constants and high dipole moments. In other embodiments,
polar aprotic solvents work well also, e.g. DMSO, KCl, and
SiO.sub.2 or DMSO, NaCl, and SiO.sub.2, and therefore it should be
understood by those skilled in the art that the present invention
encompasses such alternative compositions which include a polar
aprotic solvent in place of a polar protic solvent.
TABLE-US-00001 TABLE 1 Polar Protic/Aprotic Solvents Protic Break
or Dielectric Dipole Down Polar Solvents Aprotic Constant Moment
Volts.sup.1 Ammonia protic 25 1.40 D t-Butanol protic 12 1.70 D
n-Propanol protic 20 1.68 D Ethanol protic 25 1.69 D Methanol
protic 33 1.70 D Acetic Acid protic 6.2 1.74 D Water protic 80 1.85
D .8-1.2 Acetone aprotic 25 1.40 D Dimethylformamide (DMF) aprotic
12 1.70 D Acetonitrile (MeCN) aprotic 20 1.68 D Dimethyl Sulfoxide
(DMSO) aprotic 25 1.69 D Dichloromethane aprotic 9.1 1.60 D
Tetrahydrofuran (THF) aprotic 7.5 1.75 D Ethyl Acetate aprotic 6
1.78 D
TABLE-US-00002 TABLE 2 Electrolyte materials Electrolyte Materials
NaCL NH.sub.4CL KCl
TABLE-US-00003 TABLE 3 High Surface Area Dielectric materials High
Surface Area Dielectric Materials In situ k Pyrogenic Silica (Fumed
Silica) 10.sup.10 to 10.sup.11 Silicon Dioxide (SiO.sub.2)
~10.sup.10 Alumina 10.sup.9 to 10.sup.10
[0049] In one exemplary embodiment, ammonia (NH.sub.3) is used as
the polar protic solvent, NH.sub.4CL is the electrolyte, and
silicon dioxide is the high surface area dielectric material.
[0050] In an embodiment, these materials are each deposited in
sequential layers onto the wafer or substrate to build up a half
micron (0.5 .mu.m) layer of UDM material 105 using semiconductor
processing equipment and/or 3D printers. Then a quarter micron
(0.25 .mu.m) layer of metal 104 is deposited on top of the UDM
layer 105. This is repeated in an alternating process until five
(5) complete UDM/metal sandwich layers are completed, thereby
forming a 25 volt stack 102.
[0051] The three UDM compounds are built up sequentially in molar
percentages of about three percent (3%) to about twenty percent
(20%) electrolyte (Table 2), about three percent (3%) to about
twenty percent (20%) dielectric materials (Table 3), and about
sixty percent (60%) to about ninety-four percent (94%) polar
organic solvent (Table 1).
[0052] These UDM compounds yield dielectric k values in the
10.sup.8 to 10.sup.11 range.
[0053] Table 4 below reveals the high energy density of an
embodiment of the capacitor of the present invention using a six
(6) inch wafer and assuming k is at the median point of the range
of about 10.sup.10. The UDM dielectric layer thickness is 0.5 .mu.m
in this example. Stacks of five layers in series creates a 25 volt
capacitor. This embodiment yields 56.1 kWh of capacity with only
100 stacks.
TABLE-US-00004 TABLE 4 A six inch wafer at the median k range k
.epsilon..sub.0 A d F/lyr Lyrs F/stk Par Stks F Total J =
CV.sup.2/2 kWh 1.00E+10 8.85E-12 0.182415 5.00E-07 3.23E+04 5
6460.5 100 646,055 201,892,084 56.1
[0054] In one embodiment, the Fumed Silica utilized was 7 nm
Aldrich powder.
[0055] Capacitors made in accordance with the present invention may
have a life cycle of more than 1,000,000 cycles even at deep
discharge rates, e.g., eighty percent (80%) depth of discharge
("DoD"). The charge time for each capacitor may be about 30 seconds
for full recharge.
[0056] After the wafers or panels are processed, the capacitors may
be sawed in various shapes and sizes and placed into the final
packaging using activated carbon, graphene or other type
electrodes.
[0057] These capacitors may be used in electric vehicles (EVs) and
charged using a "Capacitive Wireless Charging System and Method,"
as described in patent application Ser. No. 62/511,754, filed May
26, 2017, by the same inventor, which may be easily installed in
existing service stations. Other applications for the improved high
energy density capacitor of the present invention include not only
vehicles, but other modes of transportation including planes or
trains, backup storage for utilities, windmills, and any other type
of electrical facilities.
[0058] In another embodiment, the wafers or substrates may be
twelve (12'') inch (.about.300 mm), but any size wafer or even
rectangular LED panels will work in ALD, MOCVD and other
semiconductor or 3D printing systems. Up to 370 mm.times.470 mm
panels may be used to make rectangular capacitors. It is further
contemplated by the present invention that larger panels may be
used as they become available in the future.
[0059] In one embodiment according to the present invention is a
two solvent mixture of ethylene glycol and a polar organic
cosolvent from Table 1. Boric acid is dissolved in this mixture
with a carboxylic acid.
[0060] A deposition chamber used in an exemplary solid state
process for forming a capacitor in accordance with embodiments of
the present invention is shown in FIG. 6. Dipoles structures in
each dielectric layer are fabricated by depositing a layer of
polarized dielectric material and aligning the dipoles using high
voltage plates. This process requires minimal layers per
capacitor.
[0061] Capacitive plates are placed above and below the deposition
chamber external to the chamber and a high voltage DC is applied.
One capacitive plate takes on a high positive Voltage and the other
a high negative Voltage, to ensure that the dipoles remain aligned
while applying each subsequent layer. During ion deposition, the
small dipoles in the Oxide layer align in the opposite direction of
the Electric Field. After each layer is completed, the dipoles will
remain aligned after the external Electric Field is removed.
Consequently, the dielectric k value increases by several orders of
magnitude and the breakdown voltages increase by an order of
magnitude or more over what is conventionally expected. An
advantage of this solid state deposition process is that many
layers may be built up to make very large capacitors.
[0062] Referring now to FIG. 7, an atomic layer deposition (ALD)
chamber used in a second, different solid state process for forming
a high energy density capacitor of the present invention is shown.
In this process, the dipole structures are fabricated in a sandwich
of alternating layers of ions and dielectric by first depositing a
layer of dielectric 605 disposed above the p-Electrode 606, then a
layer of n-ions 604, another layer of dielectric 603, a layer of
p-ions 602, and another layer of dielectric 601 to insulate the
p-ions from the n-Electrode 600. This process requires more layers
per capacitor.
[0063] As shown in FIG. 7, a wafer or substrate is placed at the
bottom of the deposition chamber, and aligned with the positive
electrode or p-Electrode. The first layer of ions is deposited by
filling the chamber with ionic gas and placing a High Voltage plate
inside the chamber beneath the substrate or wafer, as well as
placing a High Voltage plate having an opposite voltage above and
external to the chamber, to create a strong Electric Field by
applying a DC Voltage. The stronger the Electric field applied, the
more densely the layer of ions is able to be packed. Next, the
chamber is cleared, and a dielectric layer is applied to hold the
ions (up to five atomic layers may be required), before removing
the Electric field. The chamber is then flooded with a positive ion
gas and the voltage on the plates is reversed. As the Positive ions
get close to the dielectric layer, the Negative ions underneath the
dielectric layer attract the Positive ions and align them overhead,
creating smaller dipoles. On each successive layer, the process of
reversing the chamber plate Voltage is repeated, selecting the
other ionizing tip, as necessary. It is further contemplated by the
present invention that the positive and negative ions may instead
be replaced by a mixture of bare electrons and protons. In another
embodiment, electrospray may be used to deposit the ion layers.
[0064] It is contemplated that other low cost, high fidelity
methods may be used to deposit the dielectric layer. For example,
technologies that may be suitable for producing dielectric layers
of appropriate thickness include spin-coating, spray-coating, or
screen printing. Generally, roll-to-roll coating methods are
considered suitable.
[0065] Thus, the present invention achieves one or more of the
following advantages. The capacitor of the present invention
provides a solution for replacing slow charging, short-life
batteries with quick charging, long-life capacitors having a
significant higher energy density than prior art capacitors. The
method of forming the capacitor(s) of the present invention
utilizes atomic layer deposition (ALD), metal oxide chemical vapor
deposition (MOCVD), 3D printing and other semiconducting
fabrication equipment to produce sub-micron thin layers and the
capability for 12 inch wafers and/or rectangular substrates, like
those used for LED panels, which are available in a wide variety of
generations and sizes. Wafers may also be sawed into any shape or
size and stacked to any height. The instant invention takes
advantage of these advances by utilizing a large array of ALD
machines and other standard semiconducting fabrication machinery,
3D printing and robotic automation to apply up to thousands of
layers per day to mass produce the capacitors of the present
invention in any shape or size.
[0066] While the present invention has been particularly described,
in conjunction with specific embodiments, it is evident that many
alternatives, modifications and variations will be apparent to
those skilled in the art in light of the foregoing description. It
is therefore contemplated that the appended claims will embrace any
such alternatives, modifications and variations as falling within
the true scope and spirit of the present invention.
* * * * *