U.S. patent application number 15/994596 was filed with the patent office on 2019-01-10 for hdmi extender with bidirectional power over twisted pair.
The applicant listed for this patent is Shenzhen Hollyland Technology Co., Ltd., Vanco International, LLC. Invention is credited to O. Bradley Corbin, Dezhi Liu.
Application Number | 20190012275 15/994596 |
Document ID | / |
Family ID | 64903261 |
Filed Date | 2019-01-10 |
View All Diagrams
United States Patent
Application |
20190012275 |
Kind Code |
A1 |
Corbin; O. Bradley ; et
al. |
January 10, 2019 |
HDMI Extender with Bidirectional Power Over Twisted Pair
Abstract
Disclosed are various embodiments of transmit and receive
connectivity devices that include signal processing circuitry, an
HDMI port, and a multi-position multi-contact port. The signal
processing circuitry can transmit and receive signals over the
multi-position multi-contact port. The signals can include a
compressed video signal and a data signal. A power source can be
sent over a cable attached to the multi-position multi-contact
port.
Inventors: |
Corbin; O. Bradley; (Amelia
Island, FL) ; Liu; Dezhi; (Nanshan, CN) |
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Applicant: |
Name |
City |
State |
Country |
Type |
Vanco International, LLC
Shenzhen Hollyland Technology Co., Ltd. |
Batavia
Nanshan |
IL |
US
CN |
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|
Family ID: |
64903261 |
Appl. No.: |
15/994596 |
Filed: |
May 31, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15948171 |
Apr 9, 2018 |
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15994596 |
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15674614 |
Aug 11, 2017 |
9946663 |
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15948171 |
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15230703 |
Aug 8, 2016 |
9710038 |
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15674614 |
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15178876 |
Jun 10, 2016 |
9798681 |
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15230703 |
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15092714 |
Apr 7, 2016 |
9747236 |
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15178876 |
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62313305 |
Mar 25, 2016 |
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62143907 |
Apr 7, 2015 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 13/385 20130101;
H04L 9/14 20130101; H04L 9/12 20130101; H04L 69/16 20130101; H04N
21/43635 20130101; H04N 21/4408 20130101; H04N 21/43615 20130101;
H04N 21/4402 20130101; G06F 13/102 20130101; H04N 1/4486 20130101;
G06F 1/266 20130101; H04N 21/4405 20130101; G06F 13/4068
20130101 |
International
Class: |
G06F 13/10 20060101
G06F013/10; G06F 1/26 20060101 G06F001/26; H04N 21/4408 20060101
H04N021/4408; G06F 13/40 20060101 G06F013/40; H04L 29/06 20060101
H04L029/06; H04N 1/44 20060101 H04N001/44; H04N 21/4363 20060101
H04N021/4363; H04N 21/4402 20060101 H04N021/4402; H04N 21/4405
20060101 H04N021/4405; G06F 13/38 20060101 G06F013/38; H04L 9/12
20060101 H04L009/12; H04N 21/436 20060101 H04N021/436 |
Claims
1. A transmit connectivity device, comprising: a high definition
media interface (HDMI) port; a multi-position multi-contact port;
and signal processing circuitry coupled to the HDMI port and the
multi-position multi-contact port, the signal processing circuitry
being configured to at least: generate a plurality of compressed
signals by compressing a plurality of media signals from the HDMI
port; transmit the plurality of compressed signals over the
multi-position multi-contact port; transmit a data signal over the
multi-position multi-contact port; and transmit a power source over
the multi-position multi-contact port.
2. The transmit connectivity device of claim 1, wherein the signal
processing circuitry generates the plurality of compressed signals
by at least: generating a plurality of decrypted signals by
decrypting the plurality of media signals from the HDMI port; and
generating the plurality of compressed signals by compressing the
decrypted signals.
3. The transmit connectivity device of claim 1, wherein the signal
processing circuitry is further configured to at least receive
another data signal over the multi-position multi-contact port.
4. The transmit connectivity device of claim 3, wherein the other
data signal comprises data corresponds to an Infrared (IR)
signal.
5. The transmit connectivity device of claim 1, wherein the data
signal is based at least in part on signals received from a first
subset of pins on the HDMI port, and the plurality of media signals
are based at least in part on signals received from a second subset
of pins on the HDMI port.
6. The transmit connectivity device of claim 5, wherein the first
subset of pins and the second subset of pins are mutually
exclusive.
7. The transmit connectivity device of claim 1, wherein the
plurality of compressed signals are transmitted at a different
frequency than the data signal.
8. The transmit connectivity device of claim 1, wherein the signal
processing circuitry is further configured to at least drive the
plurality of compressed signals.
9. The transmit connectivity device of claim 1, wherein the data
signal comprises data corresponding to one or more of: an infrared
signal, a consumer electronics control (CEC) signal, a hot plug
detection (HPD) signal, and a display data channel (DDC)
signal.
10. A receive connectivity device, comprising: a high definition
media interface (HDMI) port; a multi-position multi-contact port;
and signal processing circuitry coupled to the HDMI port and the
multi-position multi-contact port, the signal processing circuitry
being configured to at least: receive a plurality of compressed
signals over the multi-position multi-contact port; receive a data
signal over the multi-position multi-contact port; receive a power
source over the multi-position multi-contact port; generating a
plurality of decompressed signals by decompressing the plurality of
compressed signals; and transmit the plurality of decompressed
signals and a plurality of other signals over the HDMI port, the
plurality of other signals being based at least in part on the data
signal.
11. The receive connectivity device of claim 10, wherein the signal
processing circuitry generates the plurality of decompressed
signals by at least: generating a plurality of decrypted
decompressed signals by decompressing the plurality of compressed
signals; and generate the plurality of decompressed signals by
encrypting the plurality of decrypted decompressed signals.
12. The receive connectivity device of claim 10, wherein the signal
processing circuitry is further configured to at least transmit
another data signal over the multi-position multi-contact port.
13. The receive connectivity device of claim 12, wherein the other
data signal comprises data corresponds to an Infrared (IR)
signal.
14. The receive connectivity device of claim 10, wherein the
plurality of compressed signals are received at a different
frequency than the data signal.
15. The receive connectivity device of claim 10, wherein the signal
processing circuitry is further configured to at least equalize the
plurality of compressed signals.
16. The receive connectivity device of claim 10, wherein the signal
processing circuitry is further configured to at least amplify the
plurality of compressed signals.
17. The receive connectivity device of claim 10, wherein the data
signal comprises data corresponding to one or more of: an infrared
signal, a consumer electronics control (CEC) signal, a hot plug
detection (HPD) signal, and a display data channel (DDC)
signal.
18. A transmit connectivity device, comprising: a high definition
media interface (HDMI) port; a multi-position multi-contact port;
and signal processing circuitry coupled to the HDMI port and the
multi-position multi-contact port, the signal processing circuitry
being configured to at least: generate a plurality of compressed
signals by compressing a plurality of first signals from the HDMI
port; transmit the plurality of compressed signals over the
multi-position multi-contact port; receive a data signal over the
multi-position multi-contact port; and transmit a power source over
the multi-position multi-contact port.
19. The transmit connectivity device of claim 18, wherein the data
signal comprises data corresponds to an Infrared (IR) signal.
20. The transmit connectivity device of claim 18, wherein the
signal processing circuitry is further configured to at least
transmit another data signal over the multi-position multi-contact
port.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of copending U.S.
patent application Ser. No. 15/948,171, entitled "HDMI EXTENDER
WITH BIDIRECTIONAL POWER OVER TWISTED PAIR, filed Apr. 9, 2018,
which claims priority to U.S. patent application Ser. No.
15/674,614, entitled "HDMI EXTENDER WITH BIDIRECTIONAL POWER OVER
TWISTED PAIR, filed Aug. 11, 2017, now U.S. Pat. No. 9,946,663,
which claims priority to U.S. patent application Ser. No.
15/230,703, entitled "HDMI EXTENDER WITH BIDIRECTIONAL POWER OVER
TWISTED PAIR," filed Aug. 8, 2016, now U.S. Pat. No. 9,710,038,
which claims priority to U.S. patent application Ser. No.
15/178,876, entitled "HDMI EXTENDER WITH BIDIRECTIONAL POWER OVER
TWISTED PAIR," filed on Jun. 10, 2016, now U.S. Pat. No. 9,798,681,
which claims priority to U.S. U.S. patent application Ser. No.
15/092,714, entitled "HDMI EXTENDER WITH BIDIRECTIONAL POWER OVER
TWISTED PAIR", filed Apr. 7, 2016, now U.S. Pat. No. 9,747,236,
which claims priority to Provisional Application No. 62/313,305
entitled "HDMI EXTENDER WITH BIDIRECTIONAL POWER OVER TWISTED
PAIR," filed on Mar. 25, 2016, and U.S. Provisional Application No.
62/143,907 entitled "TRANSMITTING ENCRYPTED MULTIMEDIA SIGNALS,"
filed on Apr. 7, 2015, both of which are hereby incorporated by
reference in their entirety.
BACKGROUND
[0002] High Definition Media Interface (HDMI) is transmission
interface defined by the HDMI Licensing, LLC Organization. HDMI is
a common audiovisual standard for the transmission of high
definition video, audio, and related media signals. In this
context, HDMI defines an interface for transferring uncompressed
video and compressed or uncompressed audio data from a source
device to a sink device. HDMI has generally been relied upon as a
digital replacement for conventional analog video standards.
[0003] The HDMI can simultaneously transmit uncompressed digital
video and audio data streams. Currently, HDMI may be the most
widely used audio and video transmission interface in consumer
electronics. HDMI is compatible with the HDCP (High-bandwidth
Digital Content Protection) digital rights management technology,
and provides an interface between any compatible digital source
device, such as a set-top box, a Blu-ray.RTM. digital-versatile
disc (DVD) player, an HD DVD player, a personal computer, or a
video game console, for example, and a compatible sink device, such
as a digital television, computer monitor, display, etc.
[0004] In the standard HDMI, a signal line for Transition Minimized
Differential Signaling (TMDS) can be used for transmitting audio
data, video data, and associated control information; a signal line
for Display Data Channel (DDC) can be used for transmitting the
Extended Display Identification Data (EDID) and the information
associated with the HDCP key; a signal line for Consumer Electronic
Control (CEC) can be used for transmitting the operation control
data between equipment; a signal line for Hot Plug Detect (HPD) can
be used for transmitting information associated with the
connectivity state of the equipment; and a 5 voltage power signal
line and a common ground signal line can be used for providing an
auxiliary power supply to the receiving device and providing a
unified reference ground level for all single-ended signals.
SUMMARY
[0005] These and other aspects, objects, features, and embodiments
will become apparent to a person of ordinary skill in the art upon
consideration of the following detailed description of illustrative
embodiments exemplifying the best mode as presently perceived.
[0006] For video sharing among multi-rooms in a family or in some
industrial applications, a technology for long-distance
transmitting a High Definition Media (HDM) signal may need to be
relatively convenient for wiring. CAT5e cable or CAT6 cable can be
used to extend the transmission of a HDM signals. In some
embodiments, preexisting CAT5e or CAT6 cables can be installed
within a connectivity environment. In contrast to the HDMI cable,
the CAT5e cable or CAT6 cable can provide advantages when
transmitting over long distance. For example, the CAT5e or CAT6
cable can provide lower cost or easier wiring. A CAT5E or CAT6
cable can also be shared with other services.
[0007] The standard CAT5e cable or CAT6 cable may contain four
twisted pair cables. According to one embodiment, extender devices
can use four twisted pair cables to transmit a TMDS signal. The
receive extender device can perform equalization, amplification, or
clock recovery on the TMDS signal, in such a way to improve the
TMDS transmission over a 50-meter distance. However, the operator
or designer may still need to consider how to transmit the DDC
signal, the CEC signal, and the HPD signal, how to implement the
HDCP copyright protection mechanisms, how to transmit
bi-directional infrared (IR) control signal between the transmitter
of the extend equipment and the receiver of the extend equipment
over a long distance between the transmitter and receiver, and so
on.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] For a more complete understanding of the embodiments and the
advantages thereof, reference is now made to the following
description, in conjunction with the accompanying figures briefly
described as follows.
[0009] FIG. 1 is a drawing that depicts a connectivity system
according to an example embodiment of the present disclosure.
[0010] FIG. 2 is a block diagram of a signal traveling through a
connectivity system according to an example of the present
disclosure.
[0011] FIGS. 3, 4A, 4B, 5A, and 5B are block diagrams for realizing
partial functions of connectivity system according to an example
embodiment of the present disclosure.
[0012] FIG. 6 is a drawing that depicts an example pinout of a high
definition media interface (HDMI) port.
[0013] FIG. 7 is a drawing that depicts an example pinout of a
multi-position multi-contact port.
[0014] FIG. 8 is a schematic view of a frame structure of a framed
low speed signal according to an example embodiment of the present
disclosure.
[0015] FIG. 9 is a schematic circuit of a common signal
driver/receiver circuit according to an example embodiment of the
present disclosure.
[0016] FIG. 10 is a schematic circuit of a differential and common
frequency division multiplexing network according to an example
embodiment of the present disclosure.
[0017] FIGS. 11A and 11B are example flowcharts of certain
functionality implemented by portions of connectivity system of
FIG. 1 according to various embodiments of the present disclosure;
and
[0018] FIG. 12 is a schematic block diagram that illustrates an
example computing environment employed in the connectivity system
of FIG. 1 according to various embodiments.
[0019] The drawings illustrate only example embodiments and are
therefore not to be considered limiting of the scope described
herein, as other equally effective embodiments are within the scope
and spirit of this disclosure. The elements and features shown in
the drawings are not necessarily drawn to scale, emphasis instead
being placed upon clearly illustrating the principles of the
embodiments. Additionally, certain dimensions may be exaggerated to
help visually convey certain principles. In the drawings, similar
reference numerals between figures designate like or corresponding,
but not necessarily the same, elements.
DETAILED DESCRIPTION
[0020] In the following paragraphs, the embodiments are described
in further detail by way of example with reference to the attached
drawings. In the description, well known components, methods,
and/or processing techniques are omitted or briefly described so as
not to obscure the embodiments. As used herein, the "present
invention" refers to any one of the embodiments of the invention
described herein and any equivalents. Furthermore, reference to
various feature(s) of the "present invention" is not to suggest
that all embodiments must include the referenced feature(s).
[0021] Among embodiments, some aspects of the present invention are
implemented by a computer program executed by one or more
processors, as described and illustrated. As would be apparent to
one having ordinary skill in the art, the present invention may be
implemented, at least in part, by computer-readable instructions in
various forms, and the present invention is not intended to be
limiting to a particular set or sequence of instructions executed
by the processor.
[0022] The embodiments described herein are not limited in
application to the details set forth in the following description
or illustrated in the drawings. The invention is capable of other
embodiments and of being practiced or carried out in various ways.
Also, the phraseology and terminology used herein is for the
purpose of description and should not be regarded as limiting. The
use of "including," "comprising," or "having" and variations
thereof herein is meant to encompass the items listed thereafter,
additional items, and equivalents thereof. The terms "connected"
and "coupled" are used broadly and encompass both direct and
indirect connections and couplings. In addition, the terms
"connected" and "coupled" are not limited to electrical, physical,
or mechanical connections or couplings. As used herein the terms
"machine," "computer," "server," and "work station" are not limited
to a device with a single processor, but may encompass multiple
devices (e.g., computers) linked in a system, devices with multiple
processors, special purpose devices, devices with various
peripherals and input and output devices, software acting as a
computer or server, and combinations of the above.
[0023] Turning now to the drawings, exemplary embodiments are
described in detail. With reference to FIG. 1, shown is an extender
system 100, including a media signal source device 110, a transmit
extender device 120, a receive extender device 130, a sink device
140, a first IR transmit module 162, a first IR receive module 163,
a second IR transmit module 164, and a second IR receive module
165. In some embodiments, the transmit extender device 120 and
receive extender device 130 can be the same device. As such, any
reference herein to a feature of transmit or receive extender
device 120 or 130 can be similarly implemented in the other device.
The first IR transmit module 162 and the first IR receive module
163 can be combined as a first IR transmit/receive module. The
second IR transmit module 164 and second IR receive module can be
combined as a second IR transmit/receive module.
[0024] The media signal source device 110 can be electrically
coupled to the transmit extender device 120 at a source port 121 by
way of a cable 113, such as an HDMI cable, a DVI cable, or other
transmission mediums. The media signal source device 110 can output
a media signal, such as an HDM signal, a digital video (DV) signal,
or other media signals. The media signal output by the media signal
source device 110 can be encrypted, for example, the media signal
may comply with the high-bandwidth digital content protection
(HDCP) specification. In one embodiment, the HDCP standard
encryption can be used in addition to another encryption method.
The media signal can be transmitted through one or more TMDS signal
lines of cable 113.
[0025] Beside the source port 121, the transmit extender device 120
further includes an IR transmit port 122, an IR receive port 123, a
power input connector 150, a video indicator light 132, a power
indicator 133, and a network port 124. The network port 124 can
include an RJ45 port having eight contacts, and the source port 121
can include an HDMI port having nineteen contacts, a DVI port, or
another interface. In other embodiments, the network port 125 and
the source port 121 can have greater or fewer contacts.
[0026] The first and second IR receive and transmit modules 162,
163, 164, and 165 can be configured to receive, transmit, and relay
(e.g., pass-through) IR control signals to and from IR remote
controls and other devices which include IR receivers and
transmitters for control. In other words, in addition to extending
media signals from the media signal source device 110 to the sink
device 140, the extender system 100 can also extend IR control
signals between the transmit extender device 120 and the receive
extender device 130.
[0027] The transmit extender device 120 can include transmit
processing circuitry 128. It should be appreciated that the
transmit processing circuitry 128 can include a combination of
different types of circuitry, including various types of integrated
processing circuits, driver circuits, memory, etc. Generally, any
combination of circuitry or logic suitable to achieve the media
signal conversion and HDMI extension features described herein may
be relied upon. The transmit processing circuitry 128 can include
power circuitry configured to receive an incoming power signal on
the power input connector 150 from a power supply. The transmit
processing circuitry 128 can provide a power signal to receive
extender device 130 via the network port 124 and the cable 154. In
some embodiments, the transmitter processing circuitry 128 can
include power circuitry configured to receive an incoming power
signal from receive extender device 130 through the network port
124 and the cable 154. The transmit processing circuitry 128 can
include encryption and decryption hardware.
[0028] The transmit processing circuitry 128 can be configured to
receive a media signal, such as one or more media signals from the
media signal source device 110. The transmit processing circuitry
128 can be configured to receive IR control signals from the first
IR receive/transmit module 162. The IR control signals can be
packet data from a computing device. The transmit processing
circuitry 128 can convert the media signals to a converged media
signal based on a converged signal specification. As an example,
the transmit processing circuitry 128 can include a computing
device, and the computing device can execute software to convert a
media signal to a converged media signal based on the converged
signal specification.
[0029] In some embodiments, the converted signal specification can
be one or more of TCP/IP or UDP/IP. In these embodiments, the one
or more media signals can be converted from 10 bit TMDS data
signals to 8 bit data packets by transmit processing circuitry 128
and transmitted through network port 125. For example, because TMDS
contains only 8 bits of media data within the 10 bit TMDS signal,
the transmit processing circuitry 128 can extract the 8 bits of
media data from the 10 bit TMDS signal and transmit the media data
in 8 bit TCP or UDP packets.
[0030] As another example, the transmit processing circuitry 128
can package the individual 10 bit TMDS data chunks into 16 bit
aligned data packets. In yet another example, the transmit
processing circuitry 128 can package multiple 10 bit TMDS data
chunks into multiple data packets without regard for bit alignment,
for example, placing eight 10 bit TMDS data chunks into ten 8 bit
data blocks and transmitting the data via TCP and/or UDP. In this
context, it should be appreciated that the converged media signal
can take on signal level, timing, and/or protocol characteristics
different from those of the original signals from the media signal
source device 110, the first IR receive/transmit module 162/163,
and/or the computing device, individually. Data describing the
characteristics, such as signal level, timing, and other protocol
characteristics, can be embedded in data packets transmitted over
cable 154. The data describing the characteristics can be used to
recreate a signal with the same signal level, timing, and protocol
characteristics, for example, by the receive processing circuitry
138.
[0031] In one embodiment, the transmit extender device 120 can be
configured to support the extended transmission of full
uncompressed high definition video, and audio, along with various
control signals such as CEC and IR.
[0032] The transmit extender device 120 can be coupled to the
receive extender device 130 by cable 154. The receive extender
device 130 can be referred to as a sink device when discussed in
relation to the transmit extender device 120. The transmit extender
device 120 can be referred to as a source device when discussed in
relation to the receive extender device 130. The cable 154 can be
embodied as a signal cable including four twisted pairs of
conductors, such as a category 5e, 6, 6a, or 7 cable, for example,
among other similar, suitable cables (e.g., "a twisted pair
cable"). The transmit extender device 120 can also transmit or
receive power via cable 154.
[0033] One of the four twisted pairs of conductors can be connected
to a power supply, and a second twisted pair can be connected to a
ground. For example, the power input connector 150 can be coupled
to power circuitry (not shown) configured to create a potential
difference between the twisted pair connected to pins 1 and 2 of
the network port 124 and the twisted pair connected to pins 7 and 8
of network port 124. The transmit extender device 120 can also
receive a power signal and ground from cable 154 on two twisted
pairs of conductors. When power and ground are supplied via the
cable 154, the transmit extender device 120 does not require a
power supply connected to power input connector 150. The voltage
across the twisted pairs of conductors can range from 10 to 20
volts. In one embodiment, the voltage is 12 volts.
[0034] The cables 113 and 142 can be embodied as an HDMI cable
compliant with at least one of the HDMI specifications (e.g.,
1.1-1.4 or after) or HDMI compliance testing specifications (e.g.,
1.1-1.4 or after) (i.e., "an HMDI cable"). Further, the cables 113
and 142 can be embodied as either a standard or category 1 cable or
a high speed category 2 cable. Cables 113 and 142 can include an
Ethernet channel and audio return channel. According to one
embodiment, depending upon the category or quality of the cables
113 and 142, the cables 113 and 142 can range up to about 150 feet
in length.
[0035] The sink device 140 can be electrically coupled to the
receive extender device 130 at a sink port 127 through a cable 142,
for example an HDMI cable. Beside the sink port 127, the receive
extender device 130 can further include an IR receive port 131, an
IR transmit port 129, a power status indicator 134, a video status
indicator 135, a power connection port 126, and a network port
141.
[0036] The receive extender device 130 can receive processing
circuitry 138. It should be appreciated that the receiver
processing circuitry 138 can include a combination of different
types of circuitry, including various types of integrated
processing circuits, driver circuits, memory, etc. Generally, any
combination of circuitry or logic suitable to achieve the media
signal conversion and HDMI extension features described herein can
be relied upon. The receiver processing circuitry 138 can include
power circuitry configured to receive an incoming power signal on
power input connector 151 from a power supply. The receive
processing circuitry 138 can provide a power signal to transmit
extender device 120 via network port 125 and cable 154. In some
embodiments, the receiver processing circuitry 138 can include
power circuitry configured to receive an incoming power signal from
transmit extender device 120 via network port 125 and cable
154.
[0037] The receive processing circuitry 138 can be configured to
receive a converged media signal over the network port 141 and to
convert the converged media signal to one or more media signals for
output to the sink device 140. The receive processing circuitry 138
can be configured to base the conversion of the converged media
signal to one or more media signals on a converged signal
specification. In some embodiments, the converted signal
specification can be one or more of TCP/IP or UDP/IP. In these
embodiments, the one or more media data packets can be received via
the network port 141 and converted from 8 bit data packets to 10
bit TMDS data signals by receive processing circuitry 138 and
output via the sink port 127. For example, because TMDS contains
only 8 bits of media data within the 10 bit TMDS signal, the
receive processing circuitry 138 can process the TCP and/or UDP
data packets by converting each 8 bit packet of media data into a
10 bit TMDS signal and output the TMDS signal via the sink port
127.
[0038] As another example, the receive processing circuitry 138 can
extract the individual 10 bit TMDS data chunks from 16 bit aligned
data packets. In yet another example, the receive processing
circuitry 138 can extract multiple 10 bit TMDS data chunks from
multiple data packets without regard for bit alignment, such as
mapping ten 8 bit data blocks to eight 10 bit TMDS data chunks. In
this context, it should be appreciated that the converged media
signal can have signal level, timing, and/or protocol
characteristics different from those of the media signals for
output. In one embodiment, the receive processing circuitry 138 can
extract data from the converged media signal, the data describing
the characteristics of an original media signal received by the
transmit processing circuitry 128. The receive processing circuitry
138 can utilize the data describing the characteristics to generate
the media signal with characteristics corresponding to the data. As
illustrated in FIG. 1, the network cable 154 can be coupled to both
the network port 124 of the transmit extender device 120 and the
network port 125 of the receive extender device 130.
[0039] The receive processing circuitry 138 can include a data
recovery circuit. According to one example, the data recovery
circuit can be a PS8401A available from the Parade Technologies,
Ltd. In one embodiment, data recovery circuit contains a clock and
data recovery phase locked-loop (CDR PLL). The data recovery
circuit can eliminate clock jitter or data jitter in long-distance
transmissions, and improve the signal quality of the TMDS signal
for outputting to encryption circuitry.
[0040] With reference to FIG. 2, shown is a block diagram 200 of a
signal traveling through a connectivity system according to an
example embodiment of the present disclosure. The block diagram 200
includes a media signal source device 110, a transmit extender
device 120, a receive extender device 130, and a sink device 140.
The transmit processing circuitry 128 can include decryption
circuitry 203. The receive processing circuitry 138 can include
encryption circuitry 206 and data recovery circuitry 209.
[0041] The media signal source device 110 can generate a media
signal and output the media signal to the source port 121 of the
transmit extender device 120. The media signal source device 110
can generate the media signal based on a content source, such as an
internet media stream, a television broadcast, a DVD, a Blu-ray, a
content server, or other media source. The generated media signal
can be an encrypted. An encrypted media signal can be encrypted to
comply with the HDCP specification.
[0042] The decryption circuitry 203 can receive the encrypted media
signal from the media signal source device 110 through the source
port 121. The decryption circuitry 203 can convert the encrypted
media signal into a decrypted media signal. In one embodiment, the
decryption circuitry 203 can be a hardware circuit configured to
decrypt an HDCP encrypted media signal. In another embodiment, the
decryption circuitry 203 can be a processor executing software
configured to decrypt an HDCP encrypted media signal.
[0043] The transmit processing circuitry 128 can transmit the
decrypted media signal to the receive processing circuitry 138
through the network port 124 and the network port 125. The data
recovery circuitry 209 can perform a data recovery process on the
decrypted media signal to generate a recovered media signal. An
output of the data recovery circuitry 209 can provide the recovered
media signal to an input of the encryption circuitry 206. The
encryption circuitry 206 can encrypt the recovered media signal to
generate a re-encrypted media signal. In some embodiments, the
re-encrypted media signal generated by the encryption circuitry 206
is substantially similar to the encrypted media signal generated by
the media signal source device 110. As an example, the encryption
circuitry 206 can generate a re-encrypted media signal using the
same, or substantially similar, algorithm used to encrypt the media
signal generated by the media signal source device 110.
[0044] In some embodiments, the encryption circuitry 206 can use
the same, or substantially similar, algorithm to generate a
re-encrypted media signal that differs from the media signal
generated by the media signal source device 110. As a non-limiting
example, a first key can be negotiated between the media signal
source device 110 and the decryption circuitry 203, and a second
key can be negotiated between the encryption circuitry 206 and the
sink device 140. In this example, the first key can be used to
encrypt communications between the media signal source device 110
and the decryption circuitry 203 while the second key can be used
to encrypt the communications between the encryption circuitry 206.
The encryption circuitry 206 can transmit the re-encrypted media
signal to the sink device 140 through the sink port 127.
[0045] As an example, the encrypted media signal can be an
encrypted TMDS signal using the HDCP technology. The decryption
circuitry 203 and/or the encryption circuitry 206 can be an IC
EP91A1K available from the Explore Microelectronics, Taiwan or
another integrated circuit. The decrypted circuitry 203 can decrypt
the encrypted TMDS signal. The decryption circuitry 203 can contain
a HDCP key complying with HDCP 2.0 specification. The decryption
circuitry 203 can decrypt the input HDCP-encrypted TMDS signal by
using the HDCP technology. The encryption circuitry 206 can encrypt
the un-encrypted TMDS signal by using the HDCP technology.
[0046] According to some embodiments, the transmit processing
circuitry 128 and the receive processing circuitry 138 each include
a computing device. In another embodiment, only one of the transmit
processing circuitry 128 and the receive processing circuitry 138
includes a computing device. The decryption circuitry 203 can
connect to the computing device in the transmit processing
circuitry 128 and the encryption circuitry 20 can connect to the
computing device in the receive processing circuitry 138. The
connections to the computing devices can be through an
inter-integrated circuit (I2C) bus. The computing device can
control the decryption or encryption process of the TMDS signal.
The computing device can perform framing operations on the low
speed signals received from the source port 121 or the sink port
127 through an I2C bus.
[0047] In one example, the data recovery circuitry 209 can be a
PS8401A available from the Parade Technologies, Ltd. The data
recovery circuitry 209 can contain a clock and data recovery phase
locked-loop (CDR PLL). The data recovery circuitry 209 can
eliminate the clock jitter or data jitter in long-distance
transmission. The data recovery circuitry 209 can improve the
signal quality of the TMDS signal for outputting to the encryption
circuitry 206.
[0048] The transmit processing circuitry 128 and the receive
processing circuitry 138 can include a transmission circuit.
According to one embodiment, the transmission circuit can be a
transmission circuit as described in US20120210385A1, which is
incorporated herein by reference in its entirety, or another
transmission circuit. The high definition media signals can be
extended from a source to a display over long distances using the
transmission circuit. The transmission circuit can transmit low
speed signals (framed low speed signals, power signals, etc) as
common mode signals. The transmission circuit can transmit the TMDS
signal as a differential mode signal.
[0049] High-frequency magnetic beads and center-tapped transformers
can be used to couple the common mode signal and the differential
mode signal for the transmission through the cable 154. Coupling
two signals with high frequency beads and a center-tapped
transformer may be not applicable in some applications, such as in
an application which has a high requirement for real-time
interaction of HDCP information, in which the common mode signal
may have a transmission rate of Mbps which may cause interference
between the common mode signal and the TMDS differential signal,
thereby raising the requirement further for the high-frequency
rejection of the high-frequency beads and center-tapped
transformers.
[0050] As an example, when the media signal, which has a low
resolution such as 480i, is input, the TMDS media signal can have a
rate of 270 Mbps and a clock frequency of 27 MHz. In this example,
the rate of the common mode signal in Mbps can near to the TMDS
clock frequency, which may cause more troublesome interference.
Thus, a high pass filter network including the center-tapped
transformer, high-frequency beads, and high-frequency capacitors
can require a high Q value, thereby making it difficult for
selection of device and cost saving.
[0051] FIG. 3 is a block diagram of for realizing partial functions
of the extender system 100 according to an example of the present
disclosure. The extender system 100 can transmit high speed
signals, such as a high speed media signal or a high speed clock
signal, and low speed signals, such a framing signal corresponding
to low speed signals.
[0052] The cable 154 can include a plurality of twisted pair
cables. The extender system 100 can transmit high and low speed
signals through the plurality of twisted pair cables. The high
speed signals are labeled as High Speed Inputs 1-8 and High Speed
Output 1-8. The high speed signals can include a media signal and a
clock signal which can both be transmitted in TMDS form. The media
signal can be transmitted by using three twisted pair cables. The
clock signal can be transmitted by using one twisted pair
cable.
[0053] The low speed signals are labeled as Low Speed Input 1, Low
Speed Input 2, Low Speed Output 1, and Low Speed Output 2. The low
speed signals can be control signals which are transmitted through
the source port 121 or the network port 124. The control signals
can be a DDC control signal. The low speed signals can be control
signals which are transmitted from an external device, such as an
infrared input signal or an infrared output signal. The low speed
signals can be received or transmitted through the IR transmit port
122, the IR receive port 123, the IR receive port 131, and the IR
transmit port 129.
[0054] The transmit extender device 120 and the receive extender
device 130 can respectively include a differential and common
frequency division multiplexing network 303, 309. In each twisted
pair cable, the differential and common frequency division
multiplexing network 303, 309 can form a differential mode channel
and a common mode channel. The DI channel1, DI channel2, DI
channel3, and DI channel4 can be the differential mode channels.
J1, J2, X1, and X2 can be the common mode channels, wherein the J1
and J2 common mode channels can be unidirectional channels.
[0055] A first unidirectional common mode channel J1 can be formed
on the first twisted pair cables which are labelled as DI Channel1.
A second unidirectional common mode channel J2 can be formed on the
second twisted pair cables which are labelled as DI Channel2. Each
of the differential mode channels can be used to transmit a pair of
high speed signal. The first unidirectional common mode channel J1
can be used to transmit a low speed signal from the transmit
extender device 120 to the receive extender device 130. The second
unidirectional common mode channel J2 can be used to transmit a low
speed signal from the receive extender device 130 to the transmit
extender device 120.
[0056] The transmit extender device 120 and the receive extender
device 130 can include a common signal driver/receiver circuit 306
and 312, respectively. The common signal driver/receiver circuit
306 and 312 can be used to conduct a first unidirectional common
mode channel J1 and a second unidirectional common mode channel J2,
respectively.
[0057] When a low speed signal is received by the transmit extender
device 120 via Low Speed Input 1, the common signal driver/receiver
circuit 306 can conduct the first unidirectional common mode
channel J1 such that the low speed signal can be transmitted from
the transmit extender device 120 to the receive extender device
130. When a low speed signal is to be sent out from the transmit
extender device 120 via Low Speed Output 1, the differential and
common frequency division multiplexing network 303 can conduct the
second unidirectional common mode channel J2 such that the transmit
extender device 120 can receive the low speed signal from the
receive extender device 130.
[0058] When a low speed signal is to be sent out from the receive
extender device 130 via Low speed Output2, the differential and
common frequency division multiplexing network 309 can conduct the
first unidirectional common mode channel J1 such that the receive
extender device 130 can receive the low speed signal from the
transmit extender device 120. When a low speed signal is received
by the receive extender device 130 via Low Speed Input2, the common
signal driver/receiver circuit 312 can conduct the second
unidirectional common mode channel J2 such that the low speed
signal can be transmitted from the receive extender device 130 to
the transmit extender device 120.
[0059] The low speed signal can include multiple signal types. For
example, the low speed signal can include an external bidirectional
broadband 20-60 KHz IR signal and a communication signalling
signal, or a low speed signal received from the source port 121 or
the sink port 127. The low speed signal can be a display data
channel (DDC) signal, a consumer electronic control (CEC) signal, a
hot plug detect (HPD) signal, or another signal.
[0060] In one embodiment, the high-bandwidth digital content
protection (HDCP) signal is not included in a display data channel
(DDC) signal transmitted from the receive extender device 130
through the cable 154. In this embodiment, the low speed signals
transmitted from the transmit extender device 120 to the receive
extender device 130 can include one or more of the following
signals: a CEC signal, an IR signal, a VCC signal, or a GND signal.
The low speed signals transmitted from the receive extender device
130 to the transmit extender device 120 can include one or more of
the following signals: a CEC signal, a HPD signal, a DDC signal, an
IR signal, a VCC signal, or a GND signal.
[0061] The low speed signals can include a VCC signal and a GND
signal. The differential and common frequency division multiplexing
network 303 and 309 can form a first bidirectional common mode
channel X1 on a third twisted pair cables labelled as DI Channel3
and form a second bidirectional common mode channel X2 on a fourth
twisted pair cables labelled as DI Channel4. The first
bidirectional common mode channel X1 and the second bidirectional
common mode channel X2 can be used to transmit the power signal and
the ground signal, respectively. The transmit extender device 120
can include some or all of the following modules: the source port
121, the decryption circuitry 203, the differential and common
frequency division multiplexing network 303, the common mode signal
driver/receiver circuit 306, the network port 124, or other
modules.
[0062] FIG. 4A is a block diagram for realizing partial functions
of the transmit extender device 120 of the extender system 100
according to an example of the present disclosure. The transmit
extender device 120 can include a high speed signal redriver 403
which is connected between the decryption circuitry 203 and the
differential and common frequency division multiplexing network
303. The high speed signal redriver 403 can be an integrated
circuit (IC) with a part number of MAX3814 provided by the Maxim
Integrated Circuits Inc. The high speed signal redriver 403 can be
used to reshape and amplify a TMDS signal for increasing the
driving capability on the cable 154.
[0063] When the transmit extender device 120 transmits the low
speed signals to the receive extender device 130, the transmit
extender device 120 can perform a framing operation of the low
speed signals to form a framed signal and transmit the framed
signal to the receive extender device 130. When the receive
extender device 130 receives the framed signal, the receive
extender device 130 can perform a de-framing operation of the
received framed signal to restore the low speed signals. The
process for transmitting low speed signals from the receive
extender device 130 to the transmit extender device 120 is similar
to the above descriptions. Thus, the transmit extender device 120
can include a computing device 406 to perform a framing operation
of the low speed signal to form a framed signal and transmit the
framed signal to the receive extender device 130 through the first
unidirectional common mode channel J1. The computing device 406 can
perform a de-framing operation of the received framed signal
transmitted from the second unidirectional common mode channel J2
so as to restore the low speed signals.
[0064] The functions of the computing device 406 can be implemented
by a MCU or other processors with computing power. The computing
device 406 can perform the framing operation by encoding control
signals of all type and perform the de-framing operation by
decoding the received framed signal. The frame can include a frame
header field, a frame type field, a data frame length field, a data
frame content field, and a CRC field. The frame type field is used
to indicate the frame is a control signal data frame or a
communication signalling frame. In the application, the control
signal data frame can be an EDID data frame, a CEC data frame, a
HPD notification frame, or an IR data frame. The communication
signalling frame can be an ACK frame, a NACK frame, a Heartbeat
frame, and a Data Request frame.
[0065] To ensure reliable communication and reduce frame
transmission processing delay, a short frame architecture can be
used. In one embodiment, the frame of the framed signal
corresponding to the low speed signals cannot exceed 16 bytes and
each frame can include a CRC field. The framed signal corresponding
to the low speed signals can be the half-duplex frame which can be
transmitted from the transmit extender device 120 to the receive
extender device 130 through the first unidirectional common mode
channel J1 or transmitted from the receive extender device 130 to
the transmit extender device 120 through the second unidirectional
common mode channel J2.
[0066] The transmit extender device 120 can receive TMDS signals
and low speed signals through the source port 121, wherein the low
speed signals are to be framed. The TMDS signals can include three
pairs of encrypted media signals TMDS D0, TMDS D1, and TMDS D2, and
one pair of clock signal TMDS CLK. The low speed signals can
include a CEC signal and an IR signal.
[0067] The decryption circuitry 203 can receive the TMDS signals,
and decrypt the received TMDS signals to generate a decrypted TMDS
signals, wherein the decryption process can be controlled by the
computing device 406. The high speed signal redriver 403 can
receive the three pairs of decrypted media signals TMDS D0_1, TMDS
D1_1, and TMDS D2_1 and one pair of clock signal TMDS CLK_1. The
high speed signal redriver 403 can reshape and amplify the received
signals to generate amplified signals TMDS D0_2, TMDS D1_2, TMDS
D2_2, and TMDS CLK_2. The high speed signal redriver 403 can output
the amplified signals to the differential and common frequency
division multiplexing network 303.
[0068] The low speed signals received by the computing device 406
can include a signal directly inputted to the computing device 406
without passing through the decryption circuitry 203, such as the
CEC signal. The low speed signals can further include a signal
received from an external device interface, such as the IR_TX1. The
computing device 406 can perform the framing operation of the low
speed signals according to the frame structure shown in FIG. 8, and
output the framed low speed signal MCU_TXD. The framed low speed
signal MCU_TXD can be inputted to the common signal driver/receiver
circuit 306. The common signal driver/receiver circuit 306 can
conduct the first unidirectional common mode channel J1 to output
the signal TXD_T to the differential and common frequency division
multiplexing network 303. The signal TXD_T can corresponding to the
framed low speed signal MCU_TXD.
[0069] The differential and common frequency division multiplexing
network 303 can multiplex the amplified signals TMDS D0_2, TMDS
D1_2, TMDS D2_2, and TMDS CLK_2 with the signal TXD_T. The
amplified signals TMDS D0_2, TMDS D1_2, TMDS D2_2, and TMDS CLK_2
can be output from the high speed signal redriver 403. The signal
TXD_T can be output from the common signal driver/receiver circuit
306. The low speed signals can include a power signal (VCC) and a
ground signal (GND) to be transmitted to the differential and
common frequency division multiplexing network 303. For the
multiplexed signals D0, D1, D2, and CLK, four pairs of the
differential signals (TMDS signals) can be transmitted to the
network port 124 through the differential mode channels. At least
one path of the common mode signal can be transmitted to the
network port 124 through at least one common mode channel.
[0070] The differential and common frequency division multiplexing
network 303 can receive a framed signal RXD_T corresponding to the
low speed signals through the second unidirectional common mode
channel J2. The framed signal RXD_T can be transmitted from the
receive extender device 130. The differential and common frequency
division multiplexing network 303 can transmit the framed signal
RXD_T to the common signal driver/receiver circuit 306. The common
signal driver/receiver circuit 306 can process the received framed
signal RXD_T to generate a framed signal MCU_RXD and transmit the
framed signal MCU_RXD to the computing device 406. The computing
device 406 can perform a de-framing operation of the framed signal
MCU_RXD to generate low speed signals. The generated low speed
signals can include a CEC signal, a HPD signal, a DDC signal, an IR
signals, and other signals. The generated low speed signals can be
transmitted through corresponding output interfaces. For example,
the IR_RX1 signal can be transmitted through the infrared
interface, the CEC signal can be transmitted through the CEC signal
line to the source port 121, and the EDID signal can be transmitted
through the DDC signal line to the source port 121.
[0071] FIG. 4B is another block diagram for realizing partial
functions of the transmit extender device 120b of the extender
system 100 according to an example of the present disclosure. The
transmit extender device 120b performs similarly to the transmit
extender device 120 except that the transmitter extender device
120b can provide increased bandwidth for video signals. The
transmit extender device 120b can perform the framing and deframing
operations similar to the transmit extender device 120. The
transmit extender device 120b can include a compression circuit
409. The compression circuit 409 can include a high speed signal
redriver similar to high speed signal redriver 403. The compression
circuit 409 can include logic to decrypt an HDMI signal similar to
decryption circuitry 203, such as, for example, to decrypt an HDCP
encryption of the HDMI TMDS signals. The compression circuit 409
can receive the TMDS signals from the source port 121. The
compression circuit 409 can be connected to the differential and
common frequency division multiplexing network 303. The compression
circuit 409 can be an integrated circuit (IC) with a part number of
BV6336E by Explore semiconductor. The compression circuit 409 can
perform VLC compression and decompression. In some embodiments, the
compression circuit 409 can achieve a maximum compression ratio of
three.
[0072] The compression circuit 409 can decrypt the signal from the
TMDS signals. Once decrypted, the compression circuit 409 can
compress the video signals. By compressing the video signals, the
transmit extender device 120b can provide increase bandwidth over
the sink port 127, which can facilitate increased video quality. In
some embodiments, the transmit extender device 120 can transmit
TMDS channels with 2 Gbps per channel including 4K content
(approximately 4000 pixels horizontally). The compression circuit
409 can be used to reshape and amplify a TMDS signal for increasing
the driving capability on the cable 154. As an example, the
compression circuit 409 can reshape and amplify the decrypted and
compressed video signals from the TMDS signals.
[0073] The transmit extender device 120b can receive TMDS signals
and low speed signals through the source port 121, wherein the low
speed signals are to be framed. The TMDS signals can include three
pairs of encrypted media signals TMDS D0, TMDS D1, and TMDS D2, and
one pair of clock signal TMDS CLK. The low speed signals can
include control signals, such as a CEC signal, an EDID signal, and
an IR signal.
[0074] The compression circuit 409 can receive the TMDS signals,
and decrypt the received TMDS signals to generate a decrypted TMDS
signals. In some embodiments, the decryption process can be
controlled by the computing device 406. The compression circuit 409
can compress the decrypted TMDS signals. The compression circuit
409 can reshape and amplify the received signals to generate
amplified, decrypted, and compressed signals TMDS D0_1, TMDS D1_1,
TMDS D2_1, and TMDS CLK_1. The compression circuit 409 can output
the amplified signals to the differential and common frequency
division multiplexing network 303.
[0075] The low speed signals received by the computing device 406
can include a signal directly inputted to the computing device 406
without passing through the compression circuit 409, such as the
CEC signal. The low speed signals can further include a signal
received from an external device interface, such as the IR_TX1. The
computing device 406 can perform the framing operation of the low
speed signals according to the frame structure shown in FIG. 8, and
output the framed low speed signal MCU_TXD. The framed low speed
signal MCU_TXD can be inputted to the common signal driver/receiver
circuit 306. The common signal driver/receiver circuit 306 can
conduct the first unidirectional common mode channel J1 to output
the signal TXD_T to the differential and common frequency division
multiplexing network 303. The signal TXD_T can corresponding to the
framed low speed signal MCU_TXD.
[0076] The differential and common frequency division multiplexing
network 303 can multiplex the amplified signals TMDS D0_1, TMDS
D1_1, TMDS D2_1, and TMDS CLK_1 with the signal TXD_T. The
amplified signals TMDS D0_1, TMDS D1_1, TMDS D2_1, and TMDS CLK_1
can be output from the compression circuit 409. The signal TXD_T
can be output from the common signal driver/receiver circuit 306.
The low speed signals can include a power signal (VCC) and a ground
signal (GND) to be transmitted to the differential and common
frequency division multiplexing network 303. For the multiplexed
signals D0, D1, D2, and CLK, four pairs of the differential signals
(TMDS signals) can be transmitted to the network port 124 through
the differential mode channels. At least one path of the common
mode signal can be transmitted to the network port 124 through at
least one common mode channel.
[0077] The differential and common frequency division multiplexing
network 303 can receive a framed signal RXD_T corresponding to the
low speed signals through the second unidirectional common mode
channel J2. The framed signal RXD_T can be transmitted from the
receive extender device 130. The differential and common frequency
division multiplexing network 303 can transmit the framed signal
RXD_T to the common signal driver/receiver circuit 306. The common
signal driver/receiver circuit 306 can process the received framed
signal RXD_T to generate a framed signal MCU_RXD and transmit the
framed signal MCU_RXD to the computing device 406. The computing
device 406 can perform a de-framing operation of the framed signal
MCU_RXD to generate low speed signals. The generated low speed
signals can include a CEC signal, a HPD signal, a DDC signal, an IR
signals, and other signals. The generated low speed signals can be
transmitted through corresponding output interfaces. For example,
the IR_RX1 signal can be transmitted through the infrared
interface, the CEC signal can be transmitted through the CEC signal
line to the source port 121, and the EDID signal can be transmitted
through the DDC signal line to the source port 121.
[0078] FIG. 5A is a block diagram for realizing partial functions
of a receive extender device 130 of the extender system 100
according to an example the present disclosure. The receive
extender device 130 can include a sink port 127, encryption
circuitry 206, a differential and common frequency division
multiplexing network 309, a common mode signal driver/receiver
circuit 312, and a sink port 127.
[0079] The receive extender device 130 can include a high speed
signal equalizer and amplifier 503. The high speed signal equalizer
and amplifier 503 can be connected between the data recovery
circuitry 209 and the differential and common frequency division
multiplexing network 309. The high speed signal equalizer and
amplifier 503 can be an integrated circuit (IC) with a part number
of MAX3815 or MAX3815A provided by the Maxim Integrated Circuits
Inc. The high speed signal equalizer and amplifier 503 can be used
to equalize and amplify TMDS signals for restoring the waveforms of
the TMDS signals transmitted through an extended long distance
cable. The high speed signal equalizer and amplifier 503 can
support an adaptive automatic equalization.
[0080] The receive extender device 130 can include a computing
device 506 to perform a de-framing operation of a framed low speed
signal received through the first unidirectional common mode
channel J1. The computing device 506 can perform a framing
operation of low speed signals received from the media sink 13 or
other external devices. The computing device 506 can transmit a
framed signal corresponding to the received low speed signals to
the second unidirectional common mode channel J2.
[0081] FIG. 5B is another block diagram for realizing partial
functions of a receive extender device 130b of the extender system
100 according to an example the present disclosure. The receive
extender device 130b performs similarly to the receive extender
device 130 except that the receive extender device 130b can provide
increased bandwidth for video signals. The receive extender device
130b can include a sink port 127, a high speed signal equalizer and
amplifier 503, a computing device 506, a decompression circuitry
509, a differential and common frequency division multiplexing
network 309, a common mode signal driver/receiver circuit 312, and
a sink port 127.
[0082] The receive extender device 130b can include a high speed
signal equalizer and amplifier 503. The high speed signal equalizer
and amplifier 503 can be connected between the decompression
circuitry 509 and the differential and common frequency division
multiplexing network 309. According to some embodiments, the high
speed signal equalizer and amplifier 503 can be an integrated
circuit (IC) with a part number of MAX3815A provided by the Maxim
Integrated Circuits Inc.
[0083] The receive extender device 130b can include a computing
device 506 to perform a de-framing operation of a framed low speed
signal received through the first unidirectional common mode
channel J1. The computing device 506 can perform a framing
operation of low speed signals received from the media sink 13 or
other external devices. The computing device 506 can transmit a
framed signal corresponding to the received low speed signals to
the second unidirectional common mode channel J2.
[0084] The differential and common frequency division multiplexing
network 309 can receive the signals D0, D1, D2, and CLK from the
network port 125. The differential and common frequency division
multiplexing network 309 can also transmit low speed signals on a
second unidirectional common mode channel J2. The differential and
common frequency division multiplexing network 309 can separate the
signals from the differential mode channels and the common mode
channels. The TMDS signals from the differential mode channels can
be output to the high speed signal equalizer and amplifier 503 as
TMDS_D10, TMDS_D11, TMDS_D12, and TMDS_CLK1. The high speed signal
equalizer and amplifier 503 can be used to equalize and amplify
TMDS signals for restoring the waveforms of the TMDS signals
transmitted through an extended long distance cable. The high speed
signal equalizer and amplifier 503 can support an adaptive
automatic equalization.
[0085] An output from the high speed signal equalizer and amplifier
503 can be provided to the decompression circuitry 509 as TMDS_D20,
TMDS_D21, TMDS_D22, and TMDS_CLK2. The decompression circuitry 509
can decompress and encrypt the TMDS signals. The decompression
circuitry 509 can reshape and amplify the TMDS signal to increase
the driving capability to the sink port 127. The decompression
circuitry 509 can output to the sink port 127 as TMDS_D0, TMDS_D1,
and TMDS_D2, TMDS_CLK. The computing device 506 can output control
signals, such as the CEC and HPD signals, to the sink port 127
based on data from the framed low speed signal. The computing
device 506 can output one or more controls signals via the
decompression circuitry 509. As an example, the computing device
506 can communicate data via an I.sup.2C connection or another
connection, and the decompression circuitry 509 can transmit the
signal corresponding to the data to a pin of the sink port 127.
[0086] Turning to FIG. 6, an example pinout of an HDMI port 600 is
illustrated. The HDMI port 600 can be relied upon in one or both of
the transmit extender device 120 and the receive extender device
130 at the source port 121 and the sink port 127. Generally, in the
transmit extender device 120 and receive extender device 130, the
HDMI port 600 can be relied upon for connections to HDMI cables
such as the cables 113 and 142. As illustrated in FIG. 6, the HDMI
port 600 includes nineteen contacts or port pins. In other
embodiments, the HDMI port 600 can include greater or fewer
contacts. Table 2, below, provides a listing of the nineteen
contacts or port pins in the HDMI port 600 and their corresponding
HDMI signal names or pin identities. In Table 2, it can be
appreciated that HDMI port 600 includes a plurality of contacts. A
subset of the contacts including four pair of differential
contacts, TMDS Data 0, 1, 2, and Clock.
TABLE-US-00001 TABLE 2 HDMI Jack Pinout HDMI Port Pin HDMI Signal
Identity 1 TMDS Data 2+ 2 TMDS Data 2 Shield- 3 TMDS Data 2- 4 TMDS
Data 1+ 5 TMDS Data 1 Shield 6 TMDS Data 1- 7 TMDS Data 0+ 8 TMDS
Data 0 Shield 9 TMDS Data 0- 10 TMDS Clock+ 11 TMDS Clock Shield 12
TMDS Clock- 13 CEC 14 Reserved 15 SCL 16 SDA 17 DDC/CEC Ground 18
+5 V Power 19 Hot Plug Detect
[0087] FIG. 7 illustrates an example pinout of a network port 700.
The network port 700 can be relied upon in one or both of the
transmit extender device 120 and the receive extender device 130 at
any or all of the network ports 124 and 125. Generally, in the
transmit and receive extender devices 120 and 130, the network port
700 can be relied upon for connections to twisted pair cables such
as the cable 154. As illustrated in FIG. 7, the network port 700
includes eight contacts or port pins. In other embodiments, the
network port 300 can include greater or fewer contacts. Table 3
below provide listings of the eight contacts or port pins in the
network port 700 and their corresponding signal names or pin
identities according to the present disclosure. In Table 3, it can
be appreciated that a network port 700 can include a plurality of
contacts and, in some embodiments, four pairs of differential
contacts, Diff Pair 0, 1, 2, and 3. It should be appreciated that
Table 3 shows one of many configurations. In other embodiments, the
positive voltage, transmit, receive, and ground can occupy any one
of the four differential pairs.
TABLE-US-00002 TABLE 3 Port Pinout Port Pin Conductor Identity
Signal Identity Pin Function 1 Green/White Diff Pair 0+ +12 Volts 2
Green Diff Pair 0- +12 Volts 3 Orange/White Diff Pair 1+ Transmit 4
Blue Diff Pair 2+ Transmit 5 Blue/White Diff Pair 2- Receive 6
Orange Diff Pair 1- Receive 7 Brown/White Diff Pair 3+ Ground 8
Brown Diff Pair 3- Ground
[0088] With reference to FIG. 8, shown is a schematic view of a
frame structure 800 of a framed message corresponding to the low
speed signals according to various embodiments. The frame structure
800 can include a frame header field 803, a frame type field 806, a
data frame length field 809, a data frame content field 812, and a
CRC field 815.
[0089] The frame type field 806 can be used to indicate a framed
message is a control signal data frame or a communication
signalling frame. The control signal data frame can be an EDID data
frame, a CEC data frame, a HPD notification frame, an IR data
frame, or another control signal frame. The communication signaling
frame can be an ACK frame, a NACK frame, a Heartbeat frame, a Data
Request frame, or other communication frame.
[0090] The frame message that complies with the frame structure 800
can be generated by the transmit processing circuitry 128 and the
receive processing circuitry 138. In some embodiments, the frame
message is generated in computing device 406 or 506.
[0091] With reference to FIG. 9, shown is schematic circuit of a
common signal driver/receiver circuit 306 and 312 according to the
present disclosure. As an example, according to the transmission of
high definition video signal disclosed in FIGS. 11A and 11B, (e.g.
the transmission of un-encrypted high definition video signal
through cable 154), the display data channel (DDC) signal
transmitted from the computing device 506 does not include a
high-bandwidth digital content protection (HDCP) signal. In one
embodiment, the display data channel (DDC) signal can only include
an EDID signal.
[0092] In another example, the DDC signal transmitted from the
computing device 506 can include a DDC signal of other types.
Without considering the transmission of the HDCP signal, the framed
signal corresponding to low speed signals can be a unidirectional
signal and the transmission rate of the framed signal may be not
greater than 100 kbps. The circuit of the common signal
driver/receiver circuit 306 can be the same as that of the common
signal driver/receiver circuit 312. The common signal
driver/receiver circuit 306/312 can include a first branch BR1 and
a second branch BR2.
[0093] When the common signal driver/receiver circuit 306 receives
a framed signal corresponding to low speed signals from the
computing device 406, the common signal driver/receiver circuit 306
can turn on the first branch BR1 in order to transmit the received
framed signal to the first unidirectional common mode channel J1.
When the common signal driver/receiver circuit 312 receives a
framed signal corresponding to low speed signals, the common signal
driver/receiver circuit 312 can transmit the received framed signal
through the second branch BR2 to the computing device 506 where a
de-framing operation may be performed to the framed signal.
[0094] When the common signal driver/receiver circuit 312 receives
a framed signal corresponding to control signals from the computing
device 506, the common signal driver/receiver circuit 312 can turn
on the first branch BR1 in order to transmit the framed signal to
the first unidirectional common mode channel J1. When the common
signal driver/receiver circuit 306 receives a framed signal
corresponding to low speed signals, the common signal
driver/receiver circuit 306 can transmit the received framed signal
through the second branch BR2 to the computing device 406 where the
computing device 406 can perform a de-framing operation to the
framed signal.
[0095] In an example, the first branch BR1 can include a first
resistor R1, a second resistor R2, a third resistor R3, a fourth
resistor R4, a first transistor Q1, a second transistor Q2, and a
first filter capacitor C1. In one embodiment, the first transistor
Q1 and the second transistor Q2 can be transistors with a part
number of 3904 NPN.
[0096] One end of the first resistor R1 can be connected to an
output end of the computing device 406 or an output end of the
computing device 506, the other end of the first resistor R1 can be
connected to one end of the second resistor R2 and a base B of the
first transistor Q1. The other end of the second resistor R2 can be
connected to the ground signal GND. An emitter E of the first
transistor Q1 can be connected to the ground signal, and a
collector C of the first transistor Q1 can be connected to one end
of the third resistor R3 and one end of the fourth resistor R4. The
other end of the third resistor R3 can be connected to a power
signal. In one embodiment, the power signal is 3.3V. The other end
of the fourth resistor R4 can be connected to one end of the first
filter capacitor C1 and a base B of the second transistor Q2. An
emitter E of the second transistor Q2 can be connected to the
ground signal GND and a collector C of the second transistor Q2 can
be connected to an input end of the differential and common
frequency division multiplexing network 303 or 309. The filter
capacitor C1 can be connected between the base B of the second
transistor Q2 and the ground.
[0097] According to one example, the second branch BR2 can include
a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an
eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an
eleventh resistor R11, a third transistor Q3, a fourth transistor
Q4, and a second filter capacitor C2. In this example, the third
transistor Q3 can be be the transistor with the part number of 3906
PNP, and the fourth transistor Q4 can be the transistor with the
part number of 3904 NPN.
[0098] One end of the fifth resistor R5 can be connected to the
differential and common frequency division multiplexing network 303
or 309 and one end of the sixth resistor R6. The other end of the
fifth resistor R5 can be connected to one end of the seventh
resistor R7, a base B of the third transistor Q3, and one end of
the second filter capacitor C2. The other end of the sixth resistor
R6 can be connected to the power signal 3.3V, the other end of the
seventh resistor R7, and an emitter E of the third transistor Q3.
The other end of the second filter capacitor C2 can be connected to
the ground signal. A collector of the transistor Q3 can be
connected to one end of the eighth resistor R8. The other end of
the eighth resistor R8 can be connected to one end of the ninth
resistor R9 and a base B of the fourth transistor Q4. The other end
of the ninth resistor R9 is connected to the ground signal GND. An
emitter E of the fourth transistor Q4 can be connected to the
ground signal GND. A collector C of the fourth transistor Q4 can be
connected to one end of the tenth resistor R10 and one end of the
eleventh resistor R11. The other end of the tenth resistor R10 can
be connected to the power signal 3.3V. The other end of the
eleventh resistor R11 can be connected to the computing device 406
or the computing device 506.
[0099] When the transmit extender device 120 transmits a framed
signal corresponding to low speed signals to the receive extender
device 130, in the transmit extender device 120, the framed signal
can be output by the computing device 406 to a voltage divider. The
voltage divider can include the first resistor R1 and the second
resistor R2. The output of the voltage divider can be amplified by
the first transistor Q1. The output signal of the first transistor
Q1 can be transmitted to the fourth resistor R4 and the first
filter capacitor C1 so as to filter out the noise. The filtered
signal can be transmitted to the second transistor Q2. The second
transistor Q2 can amplify the filtered signal and output the
amplified filtered signal to the differential and common frequency
division multiplexing network 303. In the receive extender device
130, the differential and common frequency division multiplexing
network 309 can receive the framed signal corresponding to low
speed signals and transmit the received framed signal to the second
branch BR2. The fifth resistor R5, the sixth resistor R6, and the
seventh resistor R7 can adjust the current of the received framed
signal to complete a conversion from a current signal to a voltage
signal. The fourth transistor Q4 can reshape the received signal
and transmit the reshaped signal to the the computing device 506
for performing a de-framing operation.
[0100] When the receive extender device 130 transmits a framed
signal corresponding to low speed signals to the transmit extender
device 120, the framed signal can be output by the computing device
506 to a voltage divider. The voltage divider can include the first
resistor R1 and the second resistor R2. The output of the voltage
divider can be amplified by the first transistor Q1. The output
signal of the first transistor Q1 can be transmitted to the fourth
resistor R4 and the first filter capacitor C1 to filter out the
noise. The filtered signal can be transmitted to the second
transistor Q2. The second transistor Q2 can amplify the filtered
signal and output the amplified filtered signal to the differential
and common frequency division multiplexing network 303.
[0101] The differential and common frequency division multiplexing
network 303 can receive the framed signal corresponding to low
speed signals and transmit the received framed signal to the second
branch BR2. The fifth resistor R5, the sixth resistor R6, and the
seventh resistor R7 can adjust the current of the received framed
signal to complete a conversion from a current signal to a voltage
signal. The fourth transistor Q4 can reshape the received signal
and transmit the reshaped signal to the the computing device 406
for performing a de-framing operation.
[0102] The fourth resistor R4 and the first filter capacitor C1 in
the first branch BR1 as well as the fifth resistor R5 and the
second filter capacitor C2 in the second branch BR2 can be RC
filters that can adjust the waveform of the framed signal. As a
result of the current-driven and current-reception, the circuit can
have a low sensitivity to the impedance variations of the
transmission line. The transistors can be an integrated circuit
with part numbers of 3904 and 3906, among other transistors.
[0103] Turning to FIG. 10, shown is a schematic circuit 1000 of a
differential and common frequency division multiplexing network 303
or 309 according to the present disclosure. In some embodiments,
the differential and common frequency division multiplexing network
303 and the differential and common frequency division multiplexing
network 309 have the same circuit structure. The differential and
common frequency division multiplexing network 303/309 can use a
high frequency magnetic bead and a high frequency capacitor to
implement the separation of the common mode signal and the TMDS
signals. As shown, in some embodiments the schematic circuit 1000
does not include a transformer, thus the cost can be reduced
dramatically.
[0104] Because the DDC signal cannot contain a HDCP signal, the
transmission rate of the framed signal corresponding to low speed
signals can be only few ten kbps. The bandwidth of the common mode
channel may only be 100 kbps and satisfy the requirements. The
transmission rate of the TMDS signals is not less than 270 Mbps.
Because the transmission rate of the common mode signals and the
transmission rate of the TMDS signals have a large difference, thus
the requirements for the high frequency bead and the high frequency
capacitor may be relaxed and the transmission quality of the TMDS
signals may be unaffected by the common mode signals.
[0105] The differential and common frequency division multiplexing
network 303/309 shown in FIG. 3 can include four twisted pair
cables 1003, 1006, 1009, and 1012. Each twisted pair cable can
include two capacitors, and each capacitor can be connected to one
of the wires of the twist pair cable. As shown in FIG. 10, the
capacitors C0+ and C0- are located at the first twisted pair cable
1003, the capacitors C1+ and C1- are located at the second twisted
pair cable 1006, and so on. The positive polar of the high speed
media signal can be transmitted to the conductor wire L0+ of the
twisted pair cable 1003 through the positive polar capacitor C0+,
and the negative polar of the high speed media signal can be
transmitted to the other conductor wire L0- of the twisted pair
cable 1003 through the negative polar capacitor C0-. Each capacitor
can be connected to high frequency beads in parallel to form a LC
multiplexing network.
[0106] The ends of the two high frequency beads on the positive and
negative wires are connected to form a single end in order to
receive the common mode signal. As shown in FIG. 10, two high
frequency beads can be connected in series to form a single high
frequency bead. That is, the high frequency beads F0- and F0_1- can
be connected in series to form a single high frequency bead, and
the high frequency beads F0+ and F0_1+ can be connected in series
to form a single high frequency bead. One end of the high frequency
bead F0_1+ and one end of the high frequency bead F0_1- can be
connected to form a single end in order to receive the common mode
signal TXD. The other twisted pair cables can have same structure
as the twisted pair cable 1003.
[0107] The transmit extender device 120 can use the first
unidirectional common mode channel J1 to transmit a framed signal
TXD corresponding to low speed signals to the receive extender
device 130. The first bidirectional common mode channel X1 and the
second bidirectional common mode channel X2 can be used to transmit
a power signal VCC and a ground signal GND, respectively. The
receive extender device 130 can use the second unidirectional
common mode channel J2 to transmit a framed signal RXD
corresponding to low speed signals to the transmit extender device
120. Four differential mode channels can be used to transmit three
pairs of high speed media signals TMDS D0_2, TMDS D1_2, and TMDS
D2_2, and one pair of high speed clock signal TMDS CLK_2.
[0108] In one embodiment, the transmission rate of the framed
signals RXD and TXD is less than or equal to 100 kbps. The framed
signals RXD and TXD can be multiplex into a high speed differential
mode channel. The high speed differential mode channel can be used
to transmit TMDS signals. The impedance values of the high
frequency beads F0+, F0-, F0_1+, F0_1-, F1+, F1-, F1_1+, and F1_1-
at 100 MHz can be 1K ohm to 2K ohm. In some embodiments, the
impedance values of the high frequency beads F0+, F0-, F0_1+,
F0_1-, F1+, F1-, F1_1+, and F1_1- at 1000 MHz can be over 300 ohm.
These impedance values can ensure the high frequency beads F0+,
F0-, F0_1+, F0_1-, F1+, F1-, F1_1+, and F1_1- represent high
impedance corresponding to the TMDS signals and represent low
impedance corresponding to the low speed signals.
[0109] The values of the capacitors C0+, C0-, C1+, and C1- can
range from 1000 pF to 10 nF. These values can ensure the capacitors
C0+, C0-, C1+, and C1- represent high impedance corresponding to
the low speed signals and represent low impedance corresponding to
the TMDS signals. The lowest transmission rate of the TMDS signals
can be 270 Mbps. The signal VCC can provide a power supply and the
GND signal can provide a common ground. The signals VCC and GND can
be multiplex into a high speed differential mode channel. The high
speed differential mode channel can be used to transmit TMDS
signals. In one embodiment, the signals VCC and GND can provide 12
volts of power. The loading current can achieve 200 mA to 300 mA of
current. The loading current can pass through the high frequency
beads F2+, F2-, F2_1+, F2_1-, F3+, F3-, F3_1+, and F3_1- with the
rated current being greater than 500 mA.
[0110] The high frequency beads can have an impedance of 50% in the
condition of current loading. The loading current can pass through
the high frequency beads F2+, F2-, F2_1+, F2_1-, F3+, F3-, F3_1+,
and F3_1- with the impedance value of 1K ohm at 100 MHz and the
impedance value of 300 ohm at 1000 MHz. The loading current can
also pass through the capacitor C2+ and C2- with the values in the
range of 20 nF to 100 nF and the capacitor C3+ and C3- with the
values being greater than 100 nF. In one embodiment, the upper
limit of voltage of the capacitors C3+ and C3- must exceed the
value of the power signal VCC.
[0111] As shown in FIG. 10, the power signal VCC can be multiplex
transmitted with the TMDS clock signal by the differential and
common frequency division multiplexing network 303/309 because of
the isolating functions provided by the high frequency beads and
capacitors included in the differential and common frequency
division multiplexing network 303/309. Similarly, the common ground
signal GND can be multiplex transmitted with the TMDS media signal
by the differential and common frequency division multiplexing
network 303/309. The frequency of the power signal VCC and the
common ground signal GND can have large differences from the
frequency of the TMDS signals. Thus the requirements of the high
frequency beads and capacitors can be relaxed. That is, any high
frequency beads and any capacitors can be applicable as long as the
rated current is in the design range and the impedance meets the
requirement to isolate the TMDS signals from the power signal and
the ground signal.
[0112] Before turning to the process flow diagrams of FIGS. 11A and
11B, it is noted that embodiments described herein may be practiced
using an alternative order of the steps illustrated in FIGS. 11A
and 11B. That is, the process flows illustrated in FIGS. 11A and
11B are provided as examples only, and the embodiments may be
practiced using process flows that differ from those illustrated.
Additionally, it is noted that not all steps are required in every
embodiment. In other words, one or more of the steps may be omitted
or replaced, without departing from the spirit and scope of the
embodiments. Further, steps can be performed in different orders,
in parallel with one another, or omitted entirely, and/or certain
additional steps may be performed without departing from the scope
and spirit of the embodiments. Although the flowcharts are
primarily discussed with reference to either transmit extender
device 120 or receive extender device 130, both the transmit
extender device 120 and receive extender device 130 can perform all
of the functionality described herein.
[0113] FIG. 11A is a flowchart of a method for receiving and
transmitting an media signal in a transmit extender device 120 or a
receive extender device 130 according to an example of the present
disclosure. At block 1103, the transmit extender device 120 or a
receive extender device 130 can receive an encrypted media signal.
The media signal source device 110 can transmit the encrypted media
signal to the transmit extender device 120 through the cable 113.
The encrypted media signal can be compliant with a high-bandwidth
digital content protection (HDCP) specification. The encrypted
media signal can also be encrypted with other encryption methods.
The encrypted media signal can enter into the transmit extender
device 120 through a TMDS signal line connected to the source port
121. The sink device 140 can transmit the encrypted media signal to
the receive extender device 130. The encrypted media signal can
also enter into the receive extender device 120 through a TMDS
signal line connected to the sink port 127.
[0114] At block 1106, the transmit extender device 120 or receive
extender device 130 can generate a decrypted media signal. As an
example, the transmit extender device 120 can decrypt the encrypted
media signal in the decryption circuitry 203 to generate a
decrypted media signal. According to one embodiment, the receive
extender device 130 includes decryption circuitry similar to
decryption circuitry 203. In this embodiment, the receive extender
device 130 can generate a decrypted media signal from the encrypted
media signal similar to the transmit extender device 120.
[0115] At block 1109, the transmit extender device 120 or receive
extender device 130 can transmit the decrypted media signal. The
transmit extender device 120 can transmit the decrypted media
signal through the cable 154 to the receive extender device 130 or
vice versa. The high speed signal redriver 403 can reshape and
amplify the decrypted media signal for increasing the driving
capability on the cable 154. The decrypted media signal can be
transmitted on the cable 154 over a bidirectional common mode
channel between the differential and common frequency division
multiplexing networks 303 and 309.
[0116] In transmission, problems such as jitter or packet loss can
exist on the cable 154. If the media signal transmitted in the
cable was encrypted, the receive extender device 130 can experience
errors decrypting an encrypted signal, resulting in image flash. If
the media signal transmitted in the cable 154 is not encrypted,
even if the jitter or packet loss occurs, only a few image pixels
may be affected. Besides, the receive extender device 130 can
performed a data recovery operation of the decrypted media signal
to restore the affected image pixels. Thus, image flicker can be
avoided.
[0117] In addition to a decrypted media signal, the cable 154 can
carry a power signal, a ground signal, and a framing signal. The
power signal, ground signal, and framing signal can be referred to
as low speed signals. The transmit extender device 120 can receive
and transmit low speed signals through network port 124 or other
interfaces such as an infrared interface, and so on. The receive
extender device 130 can output low speed signals to the sink device
140 or receive these low speed signals from an external device
through the sink port 127 or through other interfaces such as an
infrared interface or other peripheral interface, and so on.
[0118] The low speed signals that enter or exit through the source
port 121 or the network port 124 can include a DDC signal. The
signals transmitted over the cable 154 are un-encrypted signals,
and the transmit extender device 130 and the receive extender
device 130 can interact without a HDCP key information associated
with the decryption. The transmit extender device 120 can operate
without transmitting a DDC signal to the receive extender device
130, and the DDC signal transmitted from the receive extender
device 130 to the transmit extender device 120 can omit or exclude
HDCP key information.
[0119] Turning to FIG. 11B, shown is a flowchart of a method for
receiving and transmitting a media signal in a receive extender
device 130 or a transmit extender device 120 and output a media
signal to a sink device according to an example of the present
disclosure. At block 1112, the receive extender device 130 can
receive an unencrypted media signal. As an example, the receive
extender device 130 can receive the decrypted media signal
transmitted in block 1109 of FIG. 11A.
[0120] At block 1115, the receive extender device 130 can perform a
data recovery operation on the unencrypted media signal to generate
a recovered media signal. The recovered media signal can be output
by the data recovery circuitry 209. In one example, the signal
transmitted through the TDMS signal line can include a clock
signal. The clock signal can be transmitted through the cable 154
without being encrypted. After receiving the clock signal, the
receive extender device 130 can perform a data recovery operation
with the received clock signal. In one example, the data recovery
operation of the media signal or the clock signal can include a
jitter process or a packet loss process.
[0121] At block 1118, the receive extender device 130 can encrypt
the recovered media signal to generate an encrypted media signal,
which is referred to herein as a re-encrypted media signal. The
encryption circuitry 206 can receive the recovered media signal
from data recovery circuitry 209 and encrypt the recovered media
signal to generate the re-encrypted media signal. The re-encrypted
media signal can be HDCP compliant.
[0122] At block 1121, the receive extender device 130 can output
the re-encrypted media signal. As an example, the encryption
circuitry 206 can output the re-encrypted media signal to sink port
127. The re-encrypted media signal can travel through cable 142 to
the sink device 140. In one example, the sink device 140 can render
media corresponding to the re-encrypted media signal on a display
device. In this example, the rendered media can also correspond to
the encrypted media signal received in block 1103.
[0123] Turning to FIG. 12, an example hardware diagram of a
computing device 1200 is illustrated. Any of the computing device
406 or computing device 506 can be implemented, in part, using one
or more elements of the computing device 1200. The computing device
1200 includes a processor 1210, a Random Access Memory ("RAM")
1220, a Read Only Memory ("ROM") 1230, a memory device 1240, a
network interface 1250, and an Input Output ("I/O") interface 1260.
The elements of the computing device 1200 are communicatively
coupled via a bus 1202.
[0124] The processor 1210 comprises any well known general purpose
arithmetic processor or Application Specific Integrated Circuit
("ASIC"). The RAM and ROM 1220 and 1230 comprise any well known
random access or read only memory device that stores
computer-readable instructions to be executed by the processor
1210. The memory device 1240 stores computer-readable instructions
thereon that, when executed by the processor 1210, direct the
processor 1210 to execute various aspects of the present invention
described herein. When the processor 1210 comprises an ASIC, the
processes described herein may be executed by the ASIC according to
an embedded circuitry design of the ASIC, by firmware of the ASIC,
or both an embedded circuitry design and firmware of the ASIC. As a
non-limiting example group, the memory device 1240 comprises one or
more of an optical disc, a magnetic disc, a semiconductor memory
(i.e., a semiconductor, floating gate, or similar flash based
memory), a magnetic tape memory, a removable memory, combinations
thereof, or any other known memory means for storing
computer-readable instructions. The network interface 1250
comprises hardware interfaces to communicate over data networks.
The I/O interface 1260 comprises device input and output interfaces
such as keyboard, pointing device, display, communication, and
other interfaces. The bus 1202 electrically and communicatively
couples the processor 1210, the RAM 1220, the ROM 1230, the memory
device 1240, the network interface 1250, and the I/O interface
1260, so that data and instructions may be communicated among
them.
[0125] In operation, the processor 1210 is configured to retrieve
computer-readable instructions stored on the memory device 1240,
the RAM 1220, the ROM 1230, or another storage means, and copy the
computer-readable instructions to the RAM 1220 or the ROM 1230 for
execution, for example. The processor 1210 is further configured to
execute the computer-readable instructions to implement various
aspects and features of the present invention. For example, the
processor 1210 may be adapted and configured to execute the
processes described above with reference to FIG. 11, including the
processes described as being performed by the modules of the
transmit extender device 120 and receive extender device 130. Also,
the memory device 1240 may store data in a database either remotely
on locally on computing device 1200.
[0126] A phrase, such as "at least one of X, Y, or Z," unless
specifically stated otherwise, is to be understood with the context
as used in general to present that an item, term, etc., can be
either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or
Z). Similarly, "at least one of X, Y, and Z," unless specifically
stated otherwise, is to be understood to present that an item,
term, etc., can be either X, Y, and Z, or any combination thereof
(e.g., X, Y, and/or Z). Thus, as used herein, such phrases are not
generally intended to, and should not, imply that certain
embodiments require at least one of either X, Y, or Z to be
present, but not, for example, one X and one Y. Further, such
phrases should not imply that certain embodiments require each of
at least one of X, at least one of Y, and at least one of Z to be
present.
[0127] Although embodiments have been described herein in detail,
the descriptions are by way of example. The features of the
embodiments described herein are representative and, in alternative
embodiments, certain features and elements may be added or omitted.
Additionally, modifications to aspects of the embodiments described
herein may be made by those skilled in the art without departing
from the spirit and scope of the present invention defined in the
following claims, the scope of which are to be accorded the
broadest interpretation so as to encompass modifications and
equivalent structures.
* * * * *