U.S. patent application number 16/056275 was filed with the patent office on 2018-12-27 for transimpedance amplifier-based reduction of hall sensor parasitic impedance.
The applicant listed for this patent is TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Baher S. Haroun, Rajarshi Mukhopadhyay, Arup Polley, Srinath Ramaswamy.
Application Number | 20180372508 16/056275 |
Document ID | / |
Family ID | 60660113 |
Filed Date | 2018-12-27 |
View All Diagrams
United States Patent
Application |
20180372508 |
Kind Code |
A1 |
Polley; Arup ; et
al. |
December 27, 2018 |
TRANSIMPEDANCE AMPLIFIER-BASED REDUCTION OF HALL SENSOR PARASITIC
IMPEDANCE
Abstract
A first amplifier has an input to receive a Hall-signal output
current from a first Hall element and has an output to output
feedback current in response to the received Hall-signal output
current. The Hall-signal output current is impeded by an impedance
of the first Hall element. The feedback current is coupled to
counterpoise the Hall-signal output current at the input, and a
voltage at the output is an amplified Hall output signal. A second
amplifier generates a high-frequency portion output signal in
response to a difference between the amplified Hall output signal
and a Hall-signal output signal from a second Hall element. A
filter reduces high-frequency content of the high-frequency portion
output signal and generates an offset correction signal. A third
amplifier generates a corrected Hall signal in response to a
difference between the amplified Hall output signal and the offset
correction signal.
Inventors: |
Polley; Arup; (Richardson,
TX) ; Ramaswamy; Srinath; (Murphy, TX) ;
Haroun; Baher S.; (Allen, TX) ; Mukhopadhyay;
Rajarshi; (Allen, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TEXAS INSTRUMENTS INCORPORATED |
Dallas |
TX |
US |
|
|
Family ID: |
60660113 |
Appl. No.: |
16/056275 |
Filed: |
August 6, 2018 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
15186394 |
Jun 17, 2016 |
10041811 |
|
|
16056275 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G01D 5/145 20130101;
G01D 3/0365 20130101; G01D 5/142 20130101 |
International
Class: |
G01D 5/14 20060101
G01D005/14; G01D 3/036 20060101 G01D003/036 |
Claims
1. A circuit, comprising: a first amplifier having an input to
receive a Hall-signal output current of a first polarity from a
first Hall element and having an output to output feedback current
of a second polarity opposite the first polarity in response to the
received Hall-signal output current, the Hall-signal output current
being impeded by an impedance of the first Hall element, the
feedback current being coupled to counterpoise the Hall-signal
output current at the input, and a voltage at the output being an
amplified Hall output signal; a second amplifier to generate a
high-frequency portion output signal in response to a difference
between the amplified Hall output signal and a Hall-signal output
signal from a second Hall element, wherein the amplified Hall
output signal includes higher frequencies than frequencies included
by the Hall-signal output signal; a filter to reduce high-frequency
content of the high-frequency portion output signal and to generate
an offset correction signal; and a third amplifier to generate a
corrected Hall signal in response to a difference between the
amplified Hall output signal and the offset correction signal.
2. The circuit of claim 1, wherein the feedback current is coupled
to counterpoise the Hall-signal output current at the input, such
that an effect of the impedance of the first Hall element on a
voltage associated with the Hall-signal output current is
suppressed at the input.
3. The circuit of claim 2, wherein the Hall-signal output current
is generated by the first Hall element in response to an
electromagnetic field affecting the first Hall element and in
response to a bias current applied to the first Hall element.
4. The circuit of claim 2, wherein: the input is a first input; the
first amplifier has a second input to receive an inverse
Hall-signal output current; and the impedance of the first Hall
element includes parasitic capacitance distributed between a first
polarity output and a second polarity output of the Hall-signal
output current and the inverse Hall-signal output current
respectively.
5. The circuit of claim 2, wherein: the input is a first input; the
first amplifier is coupled to output the feedback current in
response to an inverse Hall-signal output current, such that a
voltage at the first input is limited to a voltage associated with
a voltage at a second input of the first amplifier; and the
impedance of the first Hall element includes parasitic capacitance
distributed between a first polarity output and a second polarity
output of the Hall-signal output current and the inverse
Hall-signal output current respectively.
6. The circuit of claim 5, wherein the first amplifier has an
operating bandwidth determined in accordance with one or more
impedance elements coupled between the output and the first
input.
7. The circuit of claim 6, wherein values of the one or more
impedance elements coupled between the output and the first input
are selectable by a designer.
8. The circuit of claim 6, wherein values of the one or more
impedance elements coupled between the output and the first input
are selectable during operation of the first amplifier.
9. The circuit of claim 1, wherein: the input is a first input; the
output is a first output; the feedback current is a first feedback
current; the first amplifier has a second input coupled to receive
an inverse Hall-signal output current; the first amplifier has a
second output to output a second feedback current of a polarity
opposite the first feedback current; the inverse Hall-signal output
current is impeded by the impedance of the first Hall element; and
the impedance of the first Hall element includes parasitic
capacitance distributed between a first polarity output and a
second polarity output of the Hall-signal output current and the
inverse Hall-signal output current respectively.
10. The circuit of claim 9, wherein an operating bandwidth of the
first amplifier is determined in accordance with one or more
impedance elements coupled between the second output and the second
input of the first amplifier.
11. The circuit of claim 9, wherein the second feedback current is
coupled to counterpoise the inverse Hall-signal output current at
the second input, such that an effect of the impedance of the first
Hall element on a voltage associated with the inverse Hall-signal
output current is suppressed at the second input.
12. A circuit, comprising: a first amplifier having an input to
receive a Hall-signal output current of a first polarity from a
first Hall element and having an output to output a feedback
current of a second polarity opposite the first polarity in
response to the received Hall-signal output current, the
Hall-signal output current being impeded by an impedance of the
first Hall element, and the feedback current being coupled to
counterpoise the Hall-signal output current at the input; a second
amplifier to generate an amplified Hall output signal in response
to a second Hall element sensing output signal; a third amplifier
to generate a subtracted output signal in response to: the
amplified Hall output signal; and a second Hall output signal from
the first amplifier, the second Hall output signal being generated
by the first amplifier in response to the Hall-signal output
current; a filter to generate an offset correction signal in
response to the subtracted output signal; and a fourth amplifier to
generate a corrected Hall signal in response to: the offset
correction signal; and the second Hall output signal.
13. The circuit of claim 12, wherein a bandwidth of the subtracted
output signal is higher than a bandwidth of the Hall-signal output
current.
14. A system, comprising: a first Hall element to generate a
Hall-signal output current impeded by an impedance of the first
Hall element; a first amplifier having an input to receive the
Hall-signal output current of a first polarity and having an output
to output a feedback current of a second polarity opposite the
first polarity in response to the received Hall-signal output
current, the feedback current being coupled to counterpoise the
Hall-signal output current at the input, and a voltage at the
output being an amplified Hall output signal; a second Hall element
to generate a Hall-signal output signal; a second amplifier to
generate a high-frequency portion output signal in response to a
difference between the amplified Hall output signal and the
Hall-signal output signal, wherein the amplified Hall output signal
includes higher frequencies than frequencies included by the
Hall-signal output signal; a filter to reduce high-frequency
content of the high-frequency portion output signal and to generate
an offset correction signal; and a third amplifier to generate a
corrected Hall signal in response to a difference between the
amplified Hall output signal and the offset correction signal.
15. The system of claim 14, comprising one or more impedance
components to couple the feedback current from the output of the
first amplifier to the input of the first amplifier.
16. The system of claim 15, comprising a processor to execute
special-purpose instructions for selectively coupling the impedance
components to programmably select an operating bandwidth of the
first amplifier.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. patent
application Ser. No. 15/186,394 filed Jun. 17, 2016, which is fully
incorporated herein by reference.
BACKGROUND
[0002] Many applications of integrated circuits require acquisition
of sensor information derived from sensing events related to
physical objects or phenomena that are external to the integrated
circuits of the applications. The sensor information relating to
events being sensed may include sensor quantities such as
positioning (including positioning and orientation of a physical
object) and detection (including measurement of, e.g., a current
pulse). Often, such applications require relatively accurate sensor
information of events such physical objects and phenomenon that
changes relatively quickly with respect to one or more reference
values. However, when a physical object moves (and/or the detected
phenomenon changes) relatively quickly, the ability of various
sensors to accurately to detect and provide (e.g., relatively)
instantaneous sensor information typically decreases. Likewise,
providing accurate sensor information at increased resolution
typically decreases, for example, the rates at which sensor
quantities can be determined from the provided sensor
information.
SUMMARY
[0003] A first amplifier has an input to receive a Hall-signal
output current from a first Hall element and has an output to
output feedback current in response to the received Hall-signal
output current. The Hall-signal output current is impeded by an
impedance of the first Hall element. The feedback current is
coupled to counterpoise the Hall-signal output current at the
input, and a voltage at the output is an amplified Hall output
signal. A second amplifier generates a high-frequency portion
output signal in response to a difference between the amplified
Hall output signal and a Hall-signal output signal from a second
Hall element. A filter reduces high-frequency content of the
high-frequency portion output signal and generates an offset
correction signal. A third amplifier generates a corrected Hall
signal in response to a difference between the amplified Hall
output signal and the offset correction signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 shows a computing system in accordance with example
embodiments.
[0005] FIG. 2 is a schematic of a six-resistor bridge illustrating
various causes of offset in Hall elements.
[0006] FIG. 3 is a schematic illustrating offset compensation
through orthogonally coupled Hall elements of Hall sensors.
[0007] FIG. 4 is a schematic illustrating offset compensation
through application of current spinning techniques to Hall elements
of Hall sensors.
[0008] FIG. 5 is a schematic of high bandwidth Hall-effect circuit
in accordance with embodiments.
[0009] FIG. 6 is a schematic of a schematic of a switched
capacitor, high bandwidth Hall-effect circuit including a switched
capacitor circuit for offset correction and gain compensation in
accordance with embodiments.
[0010] FIG. 7 is a schematic of typical Hall elements for
Hall-effect sensors.
[0011] FIG. 8 is a layout diagram of layout patterns for Hall
sensor arrays where each pattern includes a single Hall element for
coupling to the high bandwidth front end of a high bandwidth, low
offset Hall-effect sensor in accordance with embodiments.
[0012] FIG. 9 is a layout diagram of layout patterns for Hall
sensor arrays where each pattern includes multiple Hall elements
for coupling to the high bandwidth front end of a high bandwidth,
low offset Hall-effect sensor in accordance with embodiments.
[0013] FIG. 10 is a block diagram of a Hall-effect sensor having a
digital output in accordance with embodiments.
[0014] FIG. 11 is a layout diagram of a Hall-effect sensor.
[0015] FIG. 12 is a schematic diagram of models of Hall
sensors.
[0016] FIG. 13 is a schematic diagram of models of current sensing
amplifier coupled to a Hall element in accordance with
embodiments.
[0017] FIG. 14 is a simulation diagram of a Hall sensor coupled to
an ideal voltage.
[0018] FIG. 15 is a simulation diagram of a Hall sensor coupled to
a transimpedance amplifier in accordance with embodiments.
[0019] FIG. 16 is a simulation diagram of a Hall sensor coupled to
a variable transimpedance amplifier in accordance with
embodiments.
[0020] FIG. 17 is another layout diagram of layout patterns for
Hall sensor arrays where each pattern includes multiple Hall
elements for coupling to the high bandwidth front end of a high
bandwidth, low offset Hall-effect sensor in accordance with
embodiments.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0021] In this description, the terms "coupled to" or "couples
with" (and the like) describe either an indirect or direct
electrical connection. Thus, if a first device couples to a second
device, that connection can be made through a direct electrical
connection, or through an indirect electrical connection via other
devices and connections. The term "portion" can mean an entire
portion or a portion that is less than the entire portion. The term
"input" can mean either a source or a drain (or even a control
input such as a gate where context indicates) of a PMOS (p-type
metal oxide semiconductor) or NMOS (n-type metal oxide
semiconductor) transistor. The term "mode" can mean a particular
architecture, configuration (including electronically configured
configurations), arrangement, application, and the like, for
accomplishing a purpose. The term "processor" can mean a circuit
for processing, a state machine and the like for execution of
programmed instructions for transforming the processor into a
special-purpose machine, circuit resources used for the processing,
and combinations thereof. The term "sensor" can mean one or more
sensors provide one or more signals for conveying positioning
information, including circuitry for driving the sensor and
extracting positioning information from a signal provided by the
sensor. Where multiple sensors mutually function as (for example)
an enhanced unified sensor, each of the multiple sensors can be
referred to as an "element."
[0022] FIG. 1 shows a computing system 100 in accordance with
example embodiments. For example, the computing system 100 is, or
is incorporated into, an electronic system 129, such as a computer,
electronics control "box" or display, communications equipment
(including transmitters), or any other type of electronic system
arranged to generate electrical signals.
[0023] In some embodiments, the computing system 100 comprises a
megacell or a system-on-chip (SoC) which includes control logic
such as a CPU 112 (central processing unit), a storage 114 (e.g.,
random access memory (RAM)) and a power supply 110. The CPU 112 can
be, for example, a CISC-type (complex instruction set computer)
CPU, RISC-type CPU (reduced instruction set computer), MCU-type
(microcontroller unit), or a digital signal processor (DSP). The
storage 114 (which can be memory such as on-processor cache,
off-processor cache, RAM, flash memory, or disk storage) stores
instructions for one or more software applications 130 (e.g.,
embedded applications) that, when executed by the CPU 112, perform
any suitable function associated with the computing system 100.
[0024] The CPU 112 comprises memory and logic circuits that store
information frequently accessed from the storage 114. The computing
system 100 is often controlled by a user using a UI (user
interface) 116, which provides output to and receives input from
the user during the execution the software application 130. The
output is provided using the display 118, indicator lights, a
speaker, vibrations, and the like. The input is received using
audio and/or video inputs (using, for example, voice or image
recognition), and electrical and/or mechanical devices such as
keypads, switches, proximity detectors (including sensors), gyros,
accelerometers, and the like. The CPU 112 is coupled to I/O
(Input-Output) port 128, which provides an interface for receiving
input from (and/or provide output to) networked devices 131. The
networked devices 131 can include any device capable of
point-to-point and/or networked communications with the computing
system 100. The computing system 100 can also be coupled to
peripherals and/or computing devices, including tangible,
non-transitory media (such as flash memory) and/or cabled or
wireless media. These and other input and output devices are
selectively coupled to the computing system 100 by external devices
using wireless or cabled connections. The storage 114 can be
accessed by, for example, by the networked devices 131.
[0025] The CPU 112 is coupled to I/O (Input-Output) port 128, which
provides an interface for receiving input from (and/or provide
output to) peripherals and/or computing devices 131, including
tangible (e.g., "non-transitory") media (such as flash memory)
and/or cabled or wireless media (such as a Joint Test Action Group
(JTAG) interface). These and other input and output devices are
selectively coupled to the computing system 100 by external devices
using or cabled connections. The CPU 112, storage 114, and power
supply 110 can be coupled to an external power supply (not shown)
or coupled to a local power source (such as a battery, solar cell,
alternator, inductive field, fuel cell, charged capacitor, and the
like).
[0026] The computing system 100 includes a high bandwidth Hall
sensor 138 for providing accurate positioning information at high
bandwidths (e.g., high speeds). As described below, the high
bandwidth Hall sensor 138 usually includes multiple sensors
mutually arranged as an enhanced Hall-effect sensor. The high
bandwidth Hall sensor architectures disclosed herein are capable of
providing accurate position information using bandwidths that, for
example, are greater than around 200 MHz (see FIG. 15, for
example).
[0027] The bandwidth of a system that includes Hall sensors is
indirectly limited by offset cancellation techniques for reducing
the offset(s) of the Hall sensor(s). The offset of a Hall sensor is
the voltage output (e.g., Hall output signal) of the Hall sensor
when no magnetic field B (where "B" is the Systeme International
d'Unites magnetic induction symbol expressed in units of Tesla) is
present (e.g., when the magnetic field B has a value of 0 T). The
voltage offset of a Hall element is an inherent quality (e.g.,
having a voltage otherwise associated with a magnetic field
strength of around an order of magnitude around 100 mT) and, for a
single Hall element, is normally sufficiently large to obscure the
change in the voltage of a Hall element output signal that occurs
in response to a typically applied magnetic field.
[0028] When orthogonal coupling (where OC is a first conventional
offset reduction technique) is applied to multiple Hall elements
(by arranging the multiple Hall elements in an orthogonally coupled
configuration), the offset of the multiple Hall elements is usually
reduced to a residual offset having a voltage otherwise associated
with a magnetic field of around (e.g., an order of magnitude of) 10
mT. When spinning current techniques (where SCT is a second
conventional offset reduction technique) are applied to the
orthogonally coupled Hall sensor, the further-reduced offset is
further reduced to a residual offset indicative of a magnetic field
of around 10 through 100 .mu.T (microtesla) with bandwidth limited
to a (e.g., reduced) maximum frequency of around 100 through 200
kHz (kilohertz).
[0029] Accordingly, Hall sensors usually have a relatively large
offset, where the uncompensated offset of a Hall sensor usually
greatly exceeds the magnitude of a typical signal output by the
Hall sensor. For example, an uncompensated offset in a Hall output
signal of a typical Hall sensor is a voltage that would indicate
the presence of a magnetic field of around 10 through 50 mT
(millitesla). In contrast, the Hall signal output by the typical
Hall sensor is capable of indicating (e.g., changes in) quantities
from around 1 .mu.T (microtesla) through 10 mT (millitesla).
[0030] The offset of Hall sensors can be reduced using the
above-described offset compensation techniques. The offset
compensation techniques include techniques such as orthogonal
coupling (OC) and spinning current techniques (SCT). Conventional
offset compensation techniques are described below with reference
to (at least) FIG. 2, FIG. 3, and FIG. 4.
[0031] FIG. 2 is a schematic of a six-resistor bridge illustrating
various causes of offset in Hall elements. Bridge 210 is an
idealized bridge illustrating effective resistances between (e.g.,
contacts of) terminal pairs (e.g., combinations of two terminals)
of the four terminals of a Hall element of a Hall sensor. For
example, the resistance R.sub.A illustrates the effective
resistance between adjacent pairs (NW, NE, SW, and SE) of the
terminals N, S, E, and W (north, south, east, and west), whereas
the resistance R.sub.O illustrates the effective resistance between
opposing pairs (NS and EW) of the four terminals. (Accordingly, the
terminology corresponds, for example, with relative locations of
physical terminals arranged in a semiconductor substrate.) The
effective resistance between a pair of terminals is, for example,
the impedance developed by a conduction channel established between
each terminal pair.
[0032] However, differences exist between the resistances between
the various terminal pairs of real-world Hall-effect sensors (where
such differences are sources of offset). The differences can result
from, for example, shear stress, vertical mismatches, horizontal
mismatches, and compression stress. Each of the four causes can
result in a (e.g., nonlinear) change in the effective resistance,
where the change in the effective resistance caused by each such
cause is respectively referred to as terms .delta.R.sub.1,
.delta.R.sub.2, .delta.R.sub.3, and .delta.R.sub.4. Accordingly,
the effective resistance of each terminal pair can be expressed
as:
R.sub.NW=R.sub.A+.delta.R.sub.1+.delta.R.sub.2+.delta.R.sub.3
R.sub.NE=R.sub.A-.delta.R.sub.1+.delta.R.sub.2-.delta.R.sub.3
R.sub.SW=R.sub.A-.delta.R.sub.1-.delta.R.sub.2+.delta.R.sub.3
R.sub.SE=R.sub.A+.delta.R.sub.1-.delta.R.sub.2-.delta.R.sub.3
R.sub.NS=R.sub.O+.delta.R.sub.4
R.sub.EW=R.sub.O-.delta.R.sub.4 (1)
[0033] The terms .delta.R.sub.1, .delta.R.sub.2, .delta.R.sub.3,
and .delta.R.sub.4 are integrated as an integration function of the
length of the conduction channels to simplify modeling (e.g., of
causes of offset in a Hall-effect bridge, or "cross"), where each
such integration respectively produces a value for the terms
.delta.L.sub.1, .delta.L.sub.2, .delta.L.sub.3, and .delta.L.sub.4.
The effects (.delta.R.sub.1) of shear stress on the ideal bridge
210 is illustrated by bridge 220. The effects (.delta.R.sub.2) of
vertical mismatches (e.g., of mismatches resulting from
misalignments and doping gradients in the N-well of a Hall-effect
sensor cross) on the ideal bridge 210 is illustrated by bridge 240.
The effect (.delta.R.sub.3) of horizontal mismatches (e.g., of
mismatches also resulting from misalignments and doping gradients
in the N-well of a Hall-effect sensor cross) on the ideal bridge
210 is illustrated by bridge 250. The effect (.delta.R.sub.4) of
compression on the ideal bridge 210 is illustrated by bridge 230.
Accordingly, .delta.R.sub.2 and .delta.R.sub.3 are used to model
offsets caused by asymmetries in a manufactured Hall-effect cross,
and .delta.R.sub.4 is used to model an impedance anisotropy of the
bridge induced by a compression stress.
[0034] FIG. 3 is a schematic illustrating offset compensation
through orthogonally coupled Hall elements of Hall sensors. The
Hall sensor circuit 200 includes orthogonally coupled elements such
a Hall sensor 310 and Hall sensor 320. Hall sensor 310 and Hall
sensor 320 are selected (and/or designed) such that the "plate"
(e.g., electrically active portion) of a first Hall sensor has
characteristics similar to a second (and optionally, third and
fourth) Hall sensor. Substantially similar plates of Hall-effect
sensors have, for example, offsets that are substantially and
mutually offset by operation of orthogonal coupling of a magnetic
field (e.g., such that direct current gains of each sensor are
substantially equal). In the ideal case where the offsets each
plate are equal, the offsets (e.g., theoretically) are cancelled in
(e.g., ideally) orthogonally coupled plates.
[0035] Hall sensor 310 and Hall sensor 320 are orthogonally coupled
such that "orthogonal" terminals are respectively coupled. For
example, the north terminal of Hall sensor 310 and the west
terminal of Hall sensor 320 are connected, the east terminal of
Hall sensor 310 and the north terminal of Hall sensor 320 are
connected, the south terminal of Hall sensor 310 and the east
terminal of Hall sensor 320 are connected, and the west terminal of
Hall sensor 310 and the south terminal of Hall sensor 320 are
connected.
[0036] In operation, a voltage source (V.sub.BIAS) includes a
positive terminal for applying a bias voltage to the north terminal
of Hall sensor 310 and the west terminal of Hall sensor 320. The
voltage source includes a negative terminal for receiving a bias
current from the south terminal of Hall sensor 310 and the east
terminal of Hall sensor 320 (e.g., such the bias current is
generated in response to the applied bias voltage V.sub.BIAS). In
response to the applied bias voltage and an applied magnetic field,
Hall sensor 310 and Hall sensor 320 each generate a Hall-effect
voltage in response to respective orthogonal portions of the
magnetic field. Accordingly, a combined Hall-effect output voltage
(V.sub.H) is generated having a reduced offset with respect to an
individual offset of a single Hall sensor.
[0037] FIG. 4 is a schematic illustrating offset compensation
through application of current spinning techniques to Hall elements
of Hall sensors. The Hall sensor circuit 400 includes switch 410.
The switch 410 is controlled by control logic such as CPU 112. The
switch 410 is, for example, a (e.g., virtual) rotary switching
matrix having four inputs, four poles, and four outputs. The switch
410 simultaneously cycles each of four inputs to a respective
physical terminal of a Hall cross in accordance with a switching
phase of the poles. For example, at phase .phi.=0 (e.g., radians),
I.sub.BIAS is coupled to a north-positioned terminal, V- is coupled
to an east-positioned terminal, I.sub.RET is coupled to a
south-positioned terminal, and V+ is coupled to a west-positioned
terminal. When the phase is at .phi.=.pi./2, I.sub.BIAS is coupled
to a east-positioned terminal, V- is coupled to an south-positioned
terminal, I.sub.RET is coupled to a west-positioned terminal, and
V+ is coupled to a north-positioned terminal. When the phase is at
.phi.=.pi., I.sub.BIAS is coupled to a south-positioned terminal,
V- is coupled to an west-positioned terminal, I.sub.RET is coupled
to a north-positioned terminal, and V+ is coupled to an
east-positioned terminal. When the phase is at .phi.=3.pi./2,
I.sub.BIAS is coupled to a west-positioned terminal, V- is coupled
to an north-positioned terminal, I.sub.RET is coupled to an
east-positioned terminal, and V+ is coupled to a south-positioned
terminal.
[0038] The cycling of each of four inputs to a respective physical
terminal of a Hall cross in accordance with a switching phase is
illustrated using bridges 420, 430, 440, and 450. Bridge 420
illustrates the coupling of the input signals to a physical bridge
at phase .phi.=0. Bridge 430 illustrates the coupling of the input
signals to a physical bridge at phase .phi.=.pi./2. Bridge 440
illustrates the coupling of the input signals to a physical bridge
at phase .phi.=.pi.. Bridge 450 illustrates the coupling of the
input signals to a physical bridge at phase .phi.=3.pi./2.
[0039] The offset voltages of bridges 420, 430, 440, and 450 are
given respectively as:
V offset ( .PHI. = 0 ) = I BIAS R 2 R 3 - R 1 R 4 R 1 + R 2 + R 3 +
R 4 V offset ( .PHI. = .pi. 2 ) = I BIAS R 1 R 4 - R 2 R 3 R 1 + R
2 + R 3 + R 4 = - V offset ( .PHI. = 0 ) V offset ( .PHI. = .pi. )
= I BIAS R 2 R 3 - R 1 R 4 R 1 + R 2 + R 3 + R 4 = V offset ( .PHI.
= 0 ) V offset ( .PHI. = 3 .pi. 2 ) = I BIAS R 1 R 4 - R 2 R 3 R 1
+ R 2 + R 3 + R 4 = - V offset ( .PHI. = 0 ) ( 2 ) ##EQU00001##
Theoretically, orthogonal switching eliminates offsets by combining
outputs having a phase difference of (e.g., plus or minus) .pi./2
radians. However, manufacturing limitations usually results in
asymmetries in bridges such that the voltage offset is not
eliminated simply by combining outputs of phases that differ by
.pi./2 radians.
[0040] The voltage offset can be further reduced by using current
spinning techniques. For example, current spinning techniques are
used in determining a residual voltage offset by calculating an
average voltage using voltage outputs of mutually orthogonal
phases. (Although four outputs are shown in the example, other
bridges having a number of outputs that are higher powers of two
can be used: see, for example, FIG. 7 below, which illustrates a
bridge having eight outputs.)
[0041] However, the use of current spinning techniques
substantially limit the bandwidth of a signal for providing the
residual voltage. The bandwidth is limited by factors such as the
time required for bias current settling after the poles of the
switch is advanced in each phase, the clock speed of sample and
hold times required for sampling bridge outputs, and the time used
to determine a compensated output (e.g., which includes a residual
offset) after 2.pi. radians of phase switching. The time used to
determine a compensated output can be, for example, the time used
to accumulate four samples and calculate the average value of the
samples. (Each determined output can be output as a value after the
conclusion of complete cycle--e.g., 2.pi. radians--of phase
switching such that a compensated output signal is generated.)
[0042] FIG. 5 is a schematic of high bandwidth Hall-effect circuit
500 in accordance with embodiments. The high bandwidth Hall-effect
circuit 500 includes sensors 510 and 520, amplifiers 530 and 540,
differential amplifier 550, filter 560, and differential amplifier
570. The high bandwidth Hall-effect circuit 500 is arranged having
a low bandwidth path (which includes components 510, 530, 550, and
560) and a high bandwidth path (which includes components 520 and
540). As disclosed herein, the relatively high offset of the high
bandwidth path is substantially determined (e.g., estimated) in
response to a relatively low offset generated by the low bandwidth
path. The relatively high offset of the high bandwidth path is
substantially reduced by combining the output of the high bandwidth
path with the output of the low bandwidth path to generate a high
bandwidth, low offset output. The low bandwidth path usually
includes signals having a maximum frequency of f.sub.1, whereas the
high bandwidth path usually includes signals having a maximum
frequency of f.sub.2 (e.g., where f.sub.1<<f.sub.2).
[0043] Sensor 510 is a sensor, which includes a set of (e.g., two
or more) Hall elements. A Hall element can be a square (e.g., see
310), a cross (e.g., a Van der Paw structure such as 710), an
octagon (e.g., see 730) or any other suitable shape. Usually, the
geometry of each Hall element is ideally identical to other Hall
elements used in a sensor 510. The set of Hall elements for sensor
510 is arranged to generate a first Hall sensor output signal such
that such that the signal includes a first offset (Off.sub.1) that
is lower than a second offset (Off.sub.2, described below, of a
second Hall sensor signal). For example, the Hall elements of
sensor 510 are orthogonally coupled and spinning current techniques
applied such that a low offset signal is generated. As described
above, lowering the offset normally results in a lower bandwidth of
the Hall sensor output signal. The (e.g., relatively robust OC and
SCT) offset reduction techniques used to reduce the voltage offset
of the sensor 510 to a voltage indicative of a 1 .mu.T field
correspondingly reduce the maximum bandwidth of the Hall sensor
output signal to around (e.g., only) 5 kHz. Accordingly, the first
Hall sensor output signal is associated with a low-bandwidth path
and a (e.g., reduced) residual offset such that, for example, the
sensor 510 generates a Hall sensor output signal having an enhanced
sensitivity to effects on the sensor 510 by a change in a magnetic
field.
[0044] A nominally equal bias current IBIAS (described above with
respect to FIG. 4) is usually applied to each element of sensor 510
such that the resulting sensitivities are substantially equal. As
described further below, sensor 510 has a sensitivity S.sub.1
(e.g., in Volts per Tesla) to an applied magnetic field B.sub.in
wherein the sensitivity can be controlled during manufacture, for
example, by adjusting the dopant level of the regions of the
conductive channels of the Hall elements for sensor 510. The dopant
levels of the regions of the conductive channels of the Hall
elements for sensor 510 are usually applied equally such that the
sensitivities/impedances of each of the various conductive channels
are substantially equal.
[0045] Amplifier 530 is an analog front-end amplifier. The (one or
more terminals of the) input of amplifier 530 is coupled to the
(one or more terminals of the) output of sensor 510, such that
amplifier 530 has a gain G.sub.1. The amplifier 530 amplifies the
first Hall sensor output signal (received from the sensor 510) to
generate an output signal (Out.sub.1). Accordingly, the output
signal Out.sub.1 can be characterized in accordance with
Out.sub.1=G.sub.1S.sub.1B.sub.in(0-f.sub.1)+Off.sub.1, where the
range "0-f.sub.1" indicates that the term Out.sub.1 corresponds
roughly to a frequency band B.sub.in spanning 0 Hertz to f.sub.1
Hertz of the input magnetic field.
[0046] Sensor 520 is a sensor, which includes a set of (e.g., one
or more) Hall elements. The set of Hall elements for sensor 520 is
arranged to generate a second Hall sensor output signal such that
the second Hall sensor output signal (e.g., as compared with the
first Hall output signal generated by sensor 510) includes an
offset (Off.sub.2) that is higher than the offset (Off.sub.1) of
the first Hall sensor output signal (output by sensor 510).
Accordingly, the bandwidth of the second Hall sensor output signal
is higher than the bandwidth of the first Hall output signal.
[0047] For example, because spinning current techniques (SCT)
reduce the bandwidth of a Hall sensor output signal, spinning
current techniques are not necessarily applied to the Hall elements
of sensor 520. Not applying SCT to the Hall sensor output signal
helps ensure the generated Hall sensor output signal is a high
bandwidth output signal (albeit having a substantially higher
offset, where Off.sub.1<<Off.sub.2). (Optionally, multiple
Hall elements are orthogonally coupled such that the sensor 520 has
a reduced residual offset.) A nominally equal bias current IBIAS is
usually applied to each element such that the resulting sensitivity
of each element is substantially equal. The sensor 520 has a
sensitivity S.sub.2 to the applied magnetic field B.sub.in, wherein
the sensitivity is controlled during design and manufacture, for
example, such that the sensitivity S.sub.1 for sensor 510 is
substantially equal to the sensitivity for S.sub.2 sensor 520.
Sensor 510 and sensor 520 are usually formed having similar design
features (and the IBIAS current applied) such that the Hall-effect
sensitivity of each of the sensors to a common external event is
substantially similar (e.g., equal, proportional, and/or a having a
mathematical relationship such that the response of one of the
sensors 510 and 520 can be accurately derived from the other of the
sensors 510 and 520). Accordingly, the "innate" (e.g., as formed in
a substrate and assuming common inputs and exposure to the same
magnetic field) response of the sensors 510 and 520 is such that
the sensors 510 and 520 generate similar waveforms in response to a
common (e.g., the same, external to the substrate in which the
sensors 510 and 520 lie) event (e.g., a change in a magnetic field
applied to both sensors 510 and 520). Accordingly, both sensor
paths usually have same sensitivity and gain such that each path
produces the same change in DC output when a DC magnetic field is
applied (however, the waveform responses of the two sensor paths
could be different because the bandwidth of each of the two sensor
paths is different).
[0048] Amplifier 540 is an analog front-end amplifier. The input of
amplifier 540 is coupled to the output of sensor 520 such that
amplifier 540 has a gain G.sub.2. The gain G.sub.2 of the amplifier
540 is selected such that the gain G.sub.2 is substantially equal
to the gain G.sub.1 of amplifier 520. The amplifier 540 amplifies
the second Hall sensor output signal received from the sensor 520
to generate an output signal (Out.sub.2). Accordingly, the output
signal Out.sub.2 can be characterized in accordance with
Out.sub.2=G.sub.1S.sub.1B.sub.in(0-f.sub.2)+Off.sub.2, where
f.sub.2 is the upper limit of the bandwidth B.sub.in, and where
f.sub.2>f.sub.1 (such that Out2 is the high bandwidth path).
[0049] Amplifier 550 generates a high-frequency portion output
signal (Out) in response to the output signal Out.sub.1 being
coupled to an inverting input of amplifier 550 and in response to
the output signal Out.sub.2 being coupled to a noninverting input
of amplifier 550. For example, amplifier 550 is a differential
amplifier for generating a difference signal (e.g., in response to
subtracting Out.sub.1 from Out.sub.2). Assuming G1=G2=G and
S1=S2=S, the output signal Out can be characterized in accordance
with Out=-GSB.sub.in(f.sub.1-f.sub.2)+Off.sub.2-Off.sub.1. Further,
the output signal (Out) primarily includes the high frequency
portion (from f.sub.1 to f.sub.2) of the input magnetic field. In a
subsequent processing step in which the high frequency content of
the output signal (Out) is low-pass filtered, the filtered output
becomes independent of the input magnetic field, for example, such
that the filtered output (e.g., "offset correction signal") is now
largely a function of the residual offset).
[0050] Filter 560 generates an offset correction signal (Off) in
response to the output signal Out received from amplifier 550. For
example, the filter 560 is a low pass filter (LPF) for low pass
filtering the signal Out (from amplifier 550) such that the signal
Off can be characterized in accordance with
Off=Off.sub.2-Off.sub.1. Because the offset Off.sub.1 is measured
more accurately than the measurement of the offset Off.sub.2 (e.g.,
when using SCT and OC techniques), the signal Off is used (for
example) to generate an accurate estimation of the offset
Off.sub.2. As described below, the less accurate offset Off.sub.2
is effectively replaced by the more accurate offset Off.sub.1 by
combining the offset correction signal Off with the signal
Out.sub.2 such that the bandwidth of signal Out.sub.2 substantially
remains the same (e.g., is not substantially reduced).
[0051] In an embodiment, the filter 560 is a low pass filter
characterized by an offset drift bandwidth. The offset estimate Off
may drift over time depending on temperature, packaging stress and
other ambient conditions. Accordingly, the offset bandwidth is
usually selected to be sufficiently wide such that the offset
bandwidth is sufficient to accurately respond to changes in offset.
Usually, offset bandwidth is much smaller compared to signal
bandwidth. However, allowing more offset bandwidth tends to enhance
low frequency noise in the signal path.
[0052] The offset correction signal Off (e.g., which contains the
offsets Off.sub.2 and Off.sub.1) is subject to offset changes
(e.g., changes due to changing operating conditions), which are
sensed (e.g., tracked) at a rate up to and including the cutoff
frequency (e.g., specified using a 3 dB cutoff point) of the filter
560 (f.sub.lpf). The cutoff frequency f.sub.lpf is usually selected
to be substantially (e.g., much) lower than frequency f.sub.1
(e.g., the maximum frequency of the low bandwidth path) to avoid
errors that might occur when cutoff frequency f.sub.lpf is higher
than (e.g., around) the frequency f.sub.1.
[0053] Amplifier 570 generates a combined output signal
(Out.sub.final) in response to the offset correction signal Off
(received from filter 560 at an inverting input of amplifier 570)
and in response to the output signal Out.sub.2 (received from
amplifier 540 at a noninverting input of amplifier 570). For
example, amplifier 570 is a differential amplifier for generating a
corrected Hall signal (e.g., by subtracting the offset correction
signal Off from signal Out.sub.2) such that the output signal
Out.sub.final can be characterized in accordance with
Out.sub.final=G.sub.1S.sub.1B.sub.in(0-f.sub.2)+Off.sub.1.
Accordingly, the low offset, high bandwidth signal Out.sub.final is
generated, which differs from the high offset, high bandwidth
signal Out.sub.2 in that, for example, the high offset term
Off.sub.2 is replaced by the low offset term Off.sub.1.
[0054] FIG. 6 is a schematic of a switched capacitor, high
bandwidth Hall-effect circuit 600 including a switched capacitor
circuit for offset correction and gain compensation in accordance
with embodiments. The high bandwidth Hall-effect circuit 600
includes sensors 510 and 520, amplifiers 530 and 640, differential
amplifier 550, filter 560, and differential amplifier 570. The high
bandwidth Hall-effect circuit 600 also includes a switched
capacitor circuit 680, which includes capacitors C.sub.offset and
C.sub.offset.sub._.sub.sample and switch 682.
[0055] The high bandwidth Hall-effect circuit 600 is arranged
having a low bandwidth path (which includes components 510, 530,
550, and 560) and a high bandwidth path (which includes components
520 and 640). In a similar manner as described above (e.g., with
respect to FIG. 5), the relatively high offset of the high
bandwidth path is substantially reduced in response to a relatively
low offset determined by the low bandwidth path. The relatively
high offset of the high bandwidth path is substantially reduced by
the switched capacitor circuit 680, which (for example) combines
the output of the high bandwidth path with the output of the low
bandwidth path to generate a high bandwidth, low offset output.
[0056] The switched capacitor circuit includes the switch 682,
which operates (for example) under the control of control logic
such as CPU 112. The switch operates at a sampling frequency
usually selected to greater than the cutoff frequency f.sub.lpf.
For example, the switch 682 samples the offset correction signal
Off from filter 560, stores the sample in capacitor
C.sub.offset.sub._.sub.sample, and transfers the sample to the
capacitor C.sub.offset such that the inverting input of amplifier
640 is biased in accordance with the offset correction signal Off.
Additionally, the (e.g., offset tracking ability of the)
accumulated charge of capacitor C.sub.offset helps to prevent
amplifier saturation, which in turn allows higher gain amplifiers
to be used as amplifier 640.
[0057] Amplifier 640 is an analog front-end amplifier. The input of
amplifier 540 is coupled to the output of sensor 520 and the
switched capacitor circuit 680 such that amplifier 640 has a gain
G.sub.2. The gain G.sub.2 of the amplifier 640 is selected such
that the gain G.sub.2 is substantially equal to the gain G.sub.1 of
amplifier 520. In a similar manner as described for amplifier 540
(which generates the output signal Out.sub.2 in accordance with
Out.sub.2=G.sub.1S.sub.1B.sub.in(0-f.sub.2)+Off.sub.2), the
amplifier 640 receives the signal Off (which can be characterized
in accordance with Off=Off.sub.2-Off.sub.1). The amplifier 640 is a
differential amplifier for generating a corrected Hall signal
(e.g., by subtracting the offset correction signal Off from the
high bandwidth, low offset signal received from the sensor 520
similarly to amplifier 570 described above). Accordingly, the
output of amplifier 640 is the output signal Out.sub.final, which
can be characterized in accordance with
Out.sub.final=G.sub.1S.sub.1B.sub.in(0-f.sub.2)+Off.sub.1. (By
inspection, it can be seen in the equation for Out.sub.final that
the high offset term Off.sub.2 has been replaced by the low offset
term Off.sub.1.) In an embodiment, the amplifier 640 can combine
selected components of both amplifiers 540 and 570 (as taught with
respect to FIG. 5, for example, such that both the amplifiers form
a unitary differential amplifier as in amplifier 640).
[0058] FIG. 7 is a schematic of typical Hall elements for
Hall-effect sensors. Symbol 710 is a schematic symbol of a Hall
element such as a square or a cross. Accordingly, the shape of
symbol 710 (and symbol 730, described below) is suggestive of a
specific Hall type but is not necessarily limited to a specific
Hall element type (for example, symbol 710 can also represent an
eight-contact element, unless the context of the detailed
description clearly teaches otherwise). The current used to bias
the Hall element (e.g., that is represented by the symbol 710) is
illustrated as current 711. Hall element 720 (which is represented
by symbol 710) includes contacts 722, 724, 726, 728. The overall
shape of Hall element 720 and the placement of the contacts 722,
724, 726, 728 within the Hall element 720 are illustrated as being
generally symmetrical, and arranged during manufacture such that
electrical characteristics of the Hall element (e.g., whether
operated at 0, 90, 180, and 270 degrees during current spinning)
are substantially equal. For example, the impedance presented to
the bias current 721 is substantially similar regardless whether
the bias current 721 flows from contact 722 to contact 724, from
contact 726 to contact 728, from contact 724 to contact 722, or
from contact 728 to contact 726.
[0059] Symbol 730 is a schematic symbol of a Hall element such
having the shape of an octagon (other shapes having an
evenly-divisible-by-two number of sides such as a hexadecagon are
possible). The current used to bias the Hall element (e.g., that is
represented by the symbol 730) is illustrated as current 731. Hall
element 740 (which is represented by symbol 730) includes eight
contacts such as contact 742, 744, 746, and 748. The overall shape
of Hall element 740 and the placement of the contacts within the
Hall element 740 are illustrated as being generally symmetrical,
and arranged during manufacture such that electrical
characteristics of the Hall element (e.g., whether operated at 0,
45, 90, 135, 180, 225, 270, and 315 degrees during current
spinning) are substantially equal. A disclosed arrangement of such
Hall elements (e.g., Hall elements 720 and 740) in a high
bandwidth, low offset Hall-effect sensor is described with
reference to, at least, FIG. 8 and FIG. 9.
[0060] FIG. 8 is a layout diagram of layout patterns for Hall
sensor arrays where each pattern includes a central Hall element
for coupling to the high bandwidth front end of a high bandwidth,
low offset Hall-effect sensor in accordance with embodiments. Hall
sensor array 810 includes a central Hall element 812 (e.g., used
for the Hall sensor for a high bandwidth front-end such as Hall
sensor 520), which defines a centroid about which the orthogonally
coupled Hall elements 814 are arranged. The arrangement of the Hall
elements 814 is, for example, substantially symmetrical such that a
portion of the central Hall element 812 substantially lies within
or intersects an (e.g., notional) area or line defined by the
centers of the adjacent Hall elements 814. Accordingly, the central
Hall element 812 is substantially centrally located and/or
surrounded (including discontinuously surrounded) by the adjacent
Hall elements 814 such that the average of the sensitivity of the
adjacent Hall elements 814 is substantially similar to the
sensitivity of the (e.g., average of one of more of the) central
Hall element 812.
[0061] The single Hall element 812 and each of the orthogonally
coupled Hall elements 814 usually have similar form (e.g., a
symmetrical cross), composition, and function with respect to their
own symmetry and with respect to the symmetry of other elements of
the Hall sensor array 810. The elements are each placed in a
symmetrical arrangement such that, for example, the effects of a
magnetic field simultaneously applied to each element of the Hall
sensor array 810 is substantially similar to the respective effects
upon the other elements of the Hall sensor array (e.g., regardless
of whether a particular element is orthogonally coupled with other
elements). The orientation (e.g., a particular direction) of the
switched (e.g., "spinned") bias currents of the orthogonally
coupled Hall elements 814 is illustrated for a single switching
phase, such as .phi.=0.
[0062] In operation, the single Hall element 812 generates a high
bandwidth Hall-effect voltage in response to a magnetic field. For
example, the single Hall element 812 generates a high bandwidth
Hall-effect voltage in response to a magnetic field because the
single Hall element 812 is not biased using a spinning current
technique. In contrast, the adjacent (e.g., peripherally arranged)
orthogonally coupled Hall elements 814 are biased using a spinning
current technique wherein the bias currents of the orthogonally
coupled Hall elements 814 are switched in each of four directions
(e.g., such that current flows northward, eastward, southward, and
westward). The bias currents of the orthogonally coupled Hall
sensors 814 are switched such that the directions of the bias
currents have an equal number of currents (e.g., two currents) in
each of the directions regardless of the changes in direction of
the bias currents in response to the changing of the switching
phase.
[0063] Hall sensor array 820 includes a single (e.g., central) Hall
element 822 (e.g., used for the Hall sensor for a high bandwidth
front-end such as Hall sensor 520), which defines a centroid about
which the orthogonally coupled Hall elements 824 are arranged. The
single Hall element 822 and each of the orthogonally coupled Hall
elements 824 usually have similar form (e.g., an octagon),
composition, and function with respect to their own symmetry and
with respect to the symmetry of other elements of the Hall sensor
array 820. The elements are each placed in a symmetrical
arrangement such that, for example, the effects of a magnetic field
upon each element of the Hall sensor array 820 is substantially
similar to the respective effects upon each of the other elements
of the Hall sensor array. The orientation of the switched bias
currents of the orthogonally coupled Hall elements 824 is
illustrated for a single switching phase, such as .phi.=0.
[0064] In operation, the single Hall element 822 generates a high
bandwidth Hall-effect voltage in response to a magnetic field. For
example, the single Hall element 822 generates a high bandwidth
Hall-effect voltage in response to a magnetic field because the
single Hall element 822 is not biased using a spinning current
technique. In contrast, the adjacent (e.g., peripherally arranged)
orthogonally coupled Hall elements 824 are biased using a spinning
current technique wherein the bias currents of the orthogonally
coupled Hall elements 824 are switched in each of four directions
(e.g., such that current flows northward, eastward, southward, and
westward). The bias currents of the orthogonally coupled Hall
sensors 824 are switched such that the directions of the bias
currents have an equal number of currents (e.g., one current) in
each of the directions regardless of the of the changes in
direction of the bias currents in response to the changing of the
switching phase.
[0065] Hall sensor array 830 includes a single (e.g., central) Hall
element 832 (e.g., used for the Hall sensor for a high bandwidth
front-end such as Hall sensor 520), which defines a centroid about
which the orthogonally coupled Hall elements 834 are arranged. The
single Hall element 832 and each of the orthogonally coupled Hall
elements 834 usually have similar form (e.g., an octagon),
composition, and function with respect to their own symmetry and
with respect to the symmetry of other elements of the Hall sensor
array 830. The elements are each placed in a symmetrical
arrangement such that, for example, the effects of a magnetic field
upon each element of the Hall sensor array 830 is substantially
similar to the respective effects upon each of the other elements
of the Hall sensor array. The orientation of the switched bias
currents of the orthogonally coupled Hall elements 834 is
illustrated for a single switching phase, such as .phi.=0.
[0066] In operation, the single Hall element 832 generates a high
bandwidth Hall-effect voltage in response to a magnetic field. For
example, the single Hall element 832 generates a high bandwidth
Hall-effect voltage in response to a magnetic field because the
single Hall element 832 is not biased using a spinning current
technique. In contrast, the adjacent (e.g., peripherally arranged)
orthogonally coupled Hall elements 834 are biased using a spinning
current technique wherein the bias currents of the orthogonally
coupled Hall elements 834 are switched in each of eight directions
(e.g., such that current flows northward, northeastward, eastward,
southeastward, southward, southwestward, westward, and
northwestward). The bias currents of the orthogonally coupled Hall
sensors 834 are switched such that the directions of the bias
currents have an equal number of currents (e.g., one current) in
each of the directions regardless of the of the changes in
direction of the bias currents in response to the changing of the
switching phase.
[0067] FIG. 9 is a layout diagram of layout patterns for Hall
sensor arrays where each pattern includes multiple Hall elements
for coupling to the high bandwidth front end of a high bandwidth,
low offset Hall-effect sensor in accordance with embodiments. Hall
sensor array 910 includes multiple Hall elements 918 (e.g., used
for the Hall sensor of a high bandwidth front-end such as Hall
sensor 520) and multiple Hall elements 916 (e.g., used for the Hall
sensor for a low bandwidth front-end such as Hall sensor 510). The
multiple Hall elements 916 are optionally orthogonally coupled
(e.g., which reduces offset), whereas the multiple Hall elements
916 are usually both orthogonally coupled and arranged to use
spinning current techniques (e.g., which reduces both offset and
available bandwidth).
[0068] The Hall elements 916 and 918 are symmetrically arranged
around either or both a horizontal axis of reflection 914 and a
vertical axis of reflection 912, with the Hall elements 916 being
adjacently positioned and mutually reflected across the horizontal
axis of reflection. For example, a first Hall element 916 is
positioned such that the placement first Hall element 916 is
reflected by an axis of reflection in the placement such that a
corresponding second Hall element 916 appears as a notional mirror
image of the first Hall element 916.
[0069] The Hall sensor array 910 includes multiple (e.g., two) Hall
elements 918 and multiple (e.g., four) Hall elements 916, which
usually have similar form (e.g., a symmetrical cross), composition,
and function with respect to their own symmetry and with respect to
the symmetry of other elements of the Hall sensor array 910. The
elements are each placed in a symmetrical arrangement such that,
for example, the effects of a (e.g., applied) magnetic field upon
each element of the Hall sensor array 910 is substantially similar
to the respective effects upon each of the other elements of the
Hall sensor array. The orientation of the switched bias currents of
the Hall elements 916 is illustrated using a fixed switching phase,
such as .phi.=0.
[0070] In operation, the multiple Hall elements 918 generate a high
bandwidth Hall-effect voltage in response to a magnetic field. For
example, the multiple Hall elements 918 generate a high bandwidth
Hall-effect voltage where the generate Hall-effect voltage has a
reduced offset when the multiple Hall elements 918 are orthogonally
coupled. In contrast, the adjacent (e.g., symmetrically arranged)
orthogonally coupled Hall elements 916 have a further-reduced
offset and a reduced available bandwidth as result of being biased
using a spinning current technique (wherein the bias currents of
the orthogonally coupled Hall elements 916 are switched in each of
four directions through four switching phases). The bias currents
of the orthogonally coupled Hall sensors 916 are switched such that
the directions of the bias currents in a single phase have an equal
number of currents (e.g., one current) in each of the directions
regardless of the changes in direction of the bias currents in
response to the changing of the switching phase.
[0071] The Hall sensor array 920 includes multiple Hall elements
926 (e.g., used for the Hall sensor of a high bandwidth front-end
such as Hall sensor 520) and multiple Hall elements 928 (e.g., used
for the Hall sensor for a low bandwidth front-end such as Hall
sensor 510). The multiple Hall elements 926 are optionally
orthogonally coupled whereas the multiple Hall elements 928 are
usually both orthogonally coupled and arranged to use spinning
current techniques.
[0072] The Hall elements 926 and 928 are symmetrically arranged
around both a horizontal axis of reflection 924 and a vertical axis
of reflection 922, with the Hall elements 926 and 928 being
adjacently positioned and mutually reflected across each of the
horizontal axis of reflection 924 and the vertical axis of
reflection 922. For example, a first Hall element 926 is positioned
such that the placement first Hall element 926 is reflected by an
axis of reflection in the placement such that a corresponding
second Hall element 926 appears as a mirror image of the first Hall
element 926.
[0073] The Hall sensor array 920 includes multiple (e.g., two) Hall
elements 926 and multiple (e.g., four) Hall elements 928, which
usually have similar form (e.g., a symmetrical cross), composition,
and function with respect to their own symmetry and with respect to
the symmetry of other elements of the Hall sensor array 920. The
elements are each placed in a symmetrical arrangement such that,
for example, the effects of a (e.g., applied) magnetic field upon
each element of the Hall sensor array 920 is substantially similar
to the respective effects upon each of the other elements of the
Hall sensor array. The orientation of the switched bias currents of
the orthogonally coupled Hall elements 928 is illustrated for a
single switching phase, such as .phi.=0.
[0074] In operation, the multiple Hall elements 926 generate a high
bandwidth Hall-effect voltage in response to a magnetic field. For
example, the multiple Hall elements 926 generate a high bandwidth
Hall-effect voltage where the generate Hall-effect voltage has a
reduced offset when the multiple Hall elements 926 are orthogonally
coupled. In contrast, the adjacent (e.g., symmetrically arranged)
orthogonally coupled Hall elements 928 have a further-reduced
offset and a reduced available bandwidth as result of being biased
using a spinning current technique. The bias currents of the
orthogonally coupled Hall sensors 928 are switched such that the
directions of the bias currents in a single phase have an equal
number of currents (e.g., one current) in each of the directions
regardless of the changes in direction of the bias currents in
response to the changing of the switching phase.
[0075] The Hall sensor array 930 includes multiple Hall elements
938 (e.g., used for the Hall sensor of a high bandwidth front-end
such as Hall sensor 520) and multiple Hall elements 936 (e.g., used
for the Hall sensor for a low bandwidth front-end such as Hall
sensor 510). The multiple Hall elements 936 and 938 are apportioned
in accordance with a ratio of four Hall elements 936 for each Hall
element 938. The multiple Hall elements 938 are optionally
orthogonally coupled whereas the multiple Hall elements 936 are
usually both orthogonally coupled and arranged to use spinning
current techniques.
[0076] The Hall elements 936 and 938 are symmetrically arranged
around both a horizontal axis of reflection 934 and a vertical axis
of reflection 932, with the Hall elements 936 and 938 being
adjacently positioned and mutually reflected across each of the
horizontal axis of reflection 934 and the vertical axis of
reflection 932. For example, a first Hall element 936 is positioned
such that the placement first Hall element 936 is reflected by an
axis of reflection in the placement such that a corresponding
second Hall element 936 appears as a mirror image of the first Hall
element 936.
[0077] The Hall sensor array 930 includes multiple (e.g., four)
Hall elements 938 and multiple (e.g., 16) Hall elements 936, which
usually have similar form (e.g., a symmetrical cross), composition,
and function with respect to their own symmetry and with respect to
the symmetry of other elements of the Hall sensor array 930. The
elements are each placed in a symmetrical arrangement such that,
for example, the effects of a (e.g., applied) magnetic field upon
each element of the Hall sensor array 930 is substantially similar
to the respective effects upon each of the other elements of the
Hall sensor array. The orientation of the switched bias currents of
the orthogonally coupled Hall elements 936 is illustrated for a
single switching phase, such as .phi.=0.
[0078] In operation, the multiple Hall elements 938 generate a high
bandwidth Hall-effect voltage in response to a magnetic field. For
example, the multiple Hall elements 938 generate a high bandwidth
Hall-effect voltage where the generate Hall-effect voltage has a
reduced offset when the multiple Hall elements 938 are orthogonally
coupled. In contrast, the adjacent (e.g., symmetrically arranged)
orthogonally coupled Hall elements 936 have a further-reduced
offset and a reduced available bandwidth as result of being biased
using a spinning current technique. The bias currents of the
orthogonally coupled Hall sensors 936 are switched such that the
directions of the bias currents in a single phase have an equal
number of currents (e.g., four currents) in each of the directions
regardless of the direction of the bias currents.
[0079] FIG. 10 is a block diagram of a Hall-effect sensor having a
digital output in accordance with embodiments. Hall-effect sensor
1000 includes Hall sensor array 1010, amplifier 1040, delta-sigma
(.DELTA..SIGMA.) modulator 1060, and decimation counter 1070. The
Hall-effect sensor 1010 detects (e.g., including quantifying)
disturbances in magnetic field 1002 and to generate a signal for
indicating the detected disturbances (e.g., generated by moving
magnets, objects moving within a magnetic field, and the like).
[0080] The Hall-effect sensor 1000 is selected to operate in
accordance with an operating mode. For example, a first operating
mode is a low-bandwidth-derived offset-reduction signal mode (such
as described with respect to the operation of Hall-effect circuit
500). The low-bandwidth-derived offset-reduction signal mode can be
selected (for example) by activating circuitry to separately (e.g.,
high- from low-bandwidth) process outputs of Hall elements.
[0081] Additionally, a second operating mode is a transimpedance
mode (such as described below with respect to the operation of
Hall-effect circuit 1310 and 1320). The low-bandwidth-derived
offset-reduction signal mode can be selected (for example) by
activating switches to selectively couple feedback components,
where the frequency response can be selected by setting a feedback
resistance (by selectively coupling one or more feedback resistors)
and by setting a feedback capacitance (by selectively coupling one
or more feedback capacitors). The low-bandwidth-derived
offset-reduction signal mode and the transimpedance mode can be
used singly or in combination to reduce offset of Hall
elements.
[0082] The signal generated by the Hall-effect sensor 1010 is
coupled to a processor (e.g., CPU 112) for taking an action in
response to the signal generated by the Hall-effect sensor 1010.
The action can include activating a user-interface "button," (e.g.,
in response to a user pointing at a displayed menu option),
providing visual and/or aural feedback, adjusting engine control
parameters in response to a degree of rotation of a rotating shaft,
and the like.
[0083] Hall sensor array 1010 includes Hall elements such as (e.g.,
low bandwidth) Hall elements 1012, 1014, 1016, and 1018. The Hall
elements 1012, 1014, 1016, and 1018 can be orthogonally coupled and
have spinning current techniques applied to reduce the offset of
the Hall elements 1012, 1014, 1016, and 1018. In response to the
(e.g., disturbances in the) magnetic field 1002, the Hall sensor
array 1010 outputs Hall voltage signals VH1A and VH1B.
[0084] The Hall element 1011 generates (e.g., high bandwidth)
bandwidth reference Hall voltage signals VH2A and VH2B. As
described above with reference to FIG. 5 and FIG. 6 (for example),
the Hall voltage signals VH2A and VH2B are processed by the
amplifier 1040 (in the low-bandwidth-derived offset-reduction
signal mode) to reduce to offset of the Hall voltage signals VH1A
and VH1B.
[0085] In the transimpedance mode, the amplifier 1040 includes a
transimpedance amplifier circuit (e.g., instead of a conventional
voltage amplifier) to extract more bandwidth from a given
combination of Hall elements. Accordingly, the transimpedance
amplifier circuit of the amplifier 1040 can be a circuit such as
model 1320, described below.
[0086] The delta-sigma modulator 1060 receives the output of the
amplifier 1040 and converts the received output to a bit stream by
performing (for example) first order delta-sigma modulation. The
decimation counter 1070 is (for example) an up-down counter for
receiving the bit stream from the delta-sigma modulator 1060 and
for decimating the received bit stream for output as a signal for
further processing by a processor (such as CPU 112, as described
above). In various embodiments, the delta-sigma modulator 1060 can
be replace by various kinds of ADCs (analog-to-digital converters).
Further, analog-based systems can use an analog output signal such
that an ADC can be bypassed and/or not used.
[0087] FIG. 11 is a layout diagram of a Hall-effect sensor. Hall
element 1110 is a cross-shaped (e.g., Van der Paw structure) Hall
element and is illustrated in plan view. Hall element 1110 includes
contacts 1112, 1114, 1116, and 1118. A bias current 1111 is carried
from contact 1112 to contact 1114 such that a Hall voltage (VHall)
is generated (e.g., in the presence of a magnetic field) with
respect to the contacts within 1116 and 1118.
[0088] Hall element 1120 is illustrated as a cross-section (View A)
along section A of Hall element 1110. The Hall element 1120 is
formed in P-type substrate 1122 in which an N-well 1124 is formed.
The contacts 1112 and 1114 are formed in N-well 1124 through which
the bias current 1111 flows. The conduction channel in the N-well
1124 in which the bias current 1111 flows in accordance with an
impedance, which in turn can be modeled in accordance with
transmission line (e.g., which includes parasitic elements in
series such as resistors and elements in parallel such as
capacitors) theory. Accordingly, the intrinsic bandwidth of Hall
sensors (such as those including structures such as Hall element
1120) is limited by the distributed RC (resistance and capacitance)
impedance where the channel resistance is denoted by R and the
junction (e.g., the PN junction formed between the in P-type
substrate 1122 in which an N-well 1124) capacitance is denoted by
C.
[0089] FIG. 12 is a schematic diagram of models of Hall sensors.
Model 1210 is a schematic of a Hall element including voltage
source V.sub.H (e.g., where the voltage of the voltage source
V.sub.H is induced by a magnetic field in accordance with a Hall
effect). The Hall voltage V.sub.H is impeded by the series
resistance R.sub.H of the conductance channel and the parallel
capacitance C.sub.H of the PN junction of the Hall element.
[0090] As design rules for new manufacturing technologies allow
Hall elements having increasingly small areas, the sensitivity of
Hall elements (e.g., that have the same shape and/or aspect ratio)
with smaller areas ideally remains similar to the larger elements.
For example, when die sizes are "shrunk" (e.g., made smaller in
both horizontal and vertical directions), the impedance R.sub.H
generally remains the same while the impedance C.sub.H usually
decreases. Distributed sheet resistance (resistance/unit square)
and sheet capacitance (capacitance/unit square) remains same as die
sizes are made smaller such that the overall resistance remains the
same in accordance with the geometry (aspect ratio) of the device
remaining the same. However, the total capacitance reduces as
device area decreases. As disclosed herein, the Hall sensor
bandwidth of conventional Hall sensors is effectively limited by
the RC-based parasitic elements when coupled to conventional
voltage sensing frontend amplifiers.
[0091] Model 1220 is a schematic of a Hall element coupled to a
voltage sensing amplifier frontend. The model 1220 includes
voltage-sensing amplifier 1222, which has a gain function of
G.sub.VFE (frontend gain of voltage sensing amplifier). The
bandwidth of the Hall sensor frontend can be expressed as:
Bandwidth f 3 d B = 1 2 .pi. R H C H ( 3 ) ##EQU00002##
Accordingly, the bandwidth f.sub.3dB increases as the size of
(e.g., a fixed aspect ratio) Hall element decreases.
[0092] Model 1230 is a schematic of a noise model of a Hall element
coupled to a voltage sensing amplifier frontend. The model 1230
includes a differential voltage sensing amplifier 1232, which
includes a non-inverting input coupled to a first noise source
V.sub.n1 (e.g., for modeling the noise of the Hall-effect sensor),
and which includes an inverting input coupled to a second noise
source V.sub.n2 (e.g., for modeling the input voltage noise of the
amplifier). The model 1230 has a gain function of G.sub.VFE. The
total noise referred to the Hall sensor frontend input can be
expressed as:
.sigma..sub.n,tot=.sigma..sub.n1.sym..sigma..sub.n2 (4)
such that
.sigma..sub.n,tot= {square root over
(4kTR.sub.H)}.sym..sigma..sub.n2 (5)
where .sigma..sub.n,tot is the noise total, k is Boltzmann's
constant, T is the noise temperature, .sigma..sub.n1 is a noise
source associated with a first output (e.g., positive terminal) of
a Hall element, the .sym. operator is the square root of the sum of
the squares operator, and .sigma..sub.n2 is a noise source
associated with a second output (e.g., ground terminal) of a Hall
element.
[0093] In accordance with example embodiments, the operating
bandwidth of Hall sensors can be increased using a current-sensing
amplifier frontend.
[0094] FIG. 13 is a schematic diagram of models of current sensing
amplifier coupled to a Hall element in accordance with embodiments.
Model 1310 is a schematic of a current-sensing amplifier 1314
coupled to a Hall sensor 1312. As disclosed herein, the operating
bandwidth of Hall sensors can be increased by coupling a Hall
sensor to a current-sensing amplifier frontend (e.g., amplifier
1020). The Hall sensor 1312 produces a Hall-signal output current
across east and west terminals in response to a bias current (e.g.,
source) I.sub.HI coupled to the north terminal of the Hall sensor
1312 and a bias current (e.g., sink) I.sub.LO coupled to the south
terminal of the Hall sensor 1312. The Hall sensor 1312 can be a
Hall element array upon which spin current techniques are
optionally used to reduce the offset of the one or more Hall
elements of the Hall sensor 1312. When more than one Hall element
is used as Hall sensor 1312, the plurality of such elements are
usually orthogonally coupled.
[0095] The current-sensing amplifier 1314 includes a non-inverting
input coupled to the east terminal (of a first polarity) of the
Hall element 1312 and to a first terminal of a "top" feedback
resistor R.sub.FBTOP (where the "top" feedback resistor R.sub.FBTOP
illustrates impedances such as resistance and capacitance). The
second terminal of the feedback resistor R.sub.FBTOP is coupled to
the non-inverting output of the current sensing amplifier 1314 such
that a top feedback current is generated in response to the
Hall-effect voltage generated at the west terminal.
[0096] In a similar (but having opposing polarities, for example)
manner, the sensing amplifier 1314 includes an inverting input
coupled to the west terminal (of a polarity inverse to the first
polarity) of the Hall element 1312 and to a first terminal of a
"bottom" feedback resistor R.sub.FBBOTTOM (where the "bottom"
feedback resistor R.sub.FBBOTTOM illustrates impedances, such as
resistance and capacitance). The second terminal of the feedback
resistor R.sub.FBBOTTOM is coupled to the non-inverting output of
the current sensing amplifier 1314 such that a bottom feedback
current is generated in response to the Hall-effect voltage
generated at the east terminal. The top feedback current is applied
(e.g., coupled) to a first opposing Hall terminal (e.g., the west
terminal, and the bottom feedback current is applied to a second
opposing Hall terminal (e.g., the east terminal), such that the
Hall-effect voltage is amplified by the current sensing amplifier
1314.
[0097] Accordingly, the current sensing amplifier 1314 generates a
differential output (e.g., voltage) in response to voltages
developed in response to the applied Hall-effect voltage (e.g.,
where opposing terminals of a Hall element respectively source and
sink the current) and in response to the current limited by each
feedback resistor. The differential voltage developed at each of
the inputs of the current sensing amplifier 1314 is respectively
amplified by the current sensing amplifier 1314 in accordance with
principles of negative feedback.
[0098] Model 1320 is a (e.g., theoretically) equivalent circuit of
the model 1310 (e.g., such that model 1320 is a simplified
embodiment of the current sensing amplifier 1314 coupled to the
Hall sensor 1312 described above). The model 1320 includes the Hall
sensor modeling devices V.sub.H, R.sub.H, and C.sub.H and a voltage
amplifier A, to which the feedback capacitor C.sub.F and feedback
resistor R.sub.F are coupled.
[0099] In operation, the generated Hall voltage V.sub.H (e.g.,
which models the output of a Hall sensor) is developed by a
Hall-signal output current where the Hall-output current is impeded
by the series resistance R.sub.H of the conductance channel and the
parallel capacitance C.sub.H of the PN junction of the Hall element
such that a (e.g., low-pass filtered) voltage is applied to the
node V.sub.1. The node V.sub.1 is coupled to the inverting input of
amplifier A of model 1320 (which is a high impedance input, such
that the impedance of the input does not directly affect the
voltage level of the node V.sub.1. The output of the model 1320
amplifier A generates a feedback current in accordance with the
feedback capacitor C.sub.F and feedback resistor R.sub.F, both of
which are coupled in parallel between the output of the model 1320
amplifier A and the inverting input of the model 1320 amplifier A.
The feedback current is opposite in direction (e.g., polarity) from
the direction of the Hall-signal output current. Accordingly, the
output V.sub.0 of the model 1320 amplifier A is regulated in
accordance with the values of the feedback capacitor C.sub.F and
feedback resistor R.sub.F and the voltage (e.g., otherwise)
developed in response to the Hall-signal input at the inverting
input is suppressed.
[0100] The operation of the model 1320 amplifier A is illustrative
of a transimpedance amplifier where V.sub.1 is held at the virtual
ground and, accordingly, the Hall-signal output is conveyed as a
current, such that the Hall-signal is (e.g., instead) converted to
voltage across R.sub.F. For example, the voltage V.sub.1 developed
at the first (e.g., inverting) input is limited to a voltage
associated with a voltage developed at the second (e.g.,
non-inverting) input of the model 1320 amplifier A. Because V.sub.1
is held at a virtual ground by the feedback current counterpoising
(e.g., having an opposing and balancing effect upon the Hall-signal
output current), the effect of C.sub.H is minimized (e.g., by
suppressing the voltage that otherwise would be developed but for
the counterpoising feedback current).
[0101] As disclosed herein, the operating bandwidth of the (e.g.,
amplified) Hall voltage V.sub.H is controlled (e.g., limited) by
the values (e.g., chosen by a designer) of the feedback capacitor
C.sub.F and feedback resistor R.sub.F. Accordingly, the operating
bandwidth of the Hall voltage V.sub.H no longer need be limited by
the strengths of the parasitic elements (e.g., R.sub.H, and
C.sub.H) of the Hall sensor.
[0102] The operation of model 1320 can be described in accordance
with the following. The gain function of G.sub.FE (frontend gain of
current sensing amplifier) can be expressed as:
G FE ( s ) = - A A + 1 R F R H 1 [ R F R H ( 1 + sR H C H ) 1 + A +
( 1 + sR F C F ) ] ( 6 ) ##EQU00003##
where s is the complex number frequency parameter associated with
Laplace transform and A is the open-loop gain of the amplifier.
[0103] Eq. (6), when simplified (e.g., to provide a result
substantially similar to a result calculated in accordance with Eq.
(6)), demonstrates a G (s) of approximately:
G FE ( s ) .apprxeq. - R F R H 1 1 + sR F C F ( 7 )
##EQU00004##
[0104] Accordingly, the operating bandwidth of the Hall sensor
frontend can be expressed as:
Bandwidth f 3 d B = 1 2 .pi. R F C F ( 8 ) ##EQU00005##
It can be seen by inspection of Eq. (8) that the operating
bandwidth is a function of the feedback components R.sub.F and
C.sub.F (e.g., which can be components selected by a designer
during design or selected during operation as described below with
reference to FIG. 16). In contrast, conventional solutions have
bandwidths in accordance with Eq. (3), in which the bandwidth is a
function of R.sub.H and C.sub.H (e.g., which are parasitic
components of a Hall element that designers cannot eliminate and/or
fully control during design).
[0105] Model 1330 is a schematic of a noise model of a Hall element
coupled to a current sensing amplifier frontend. The model 1330
includes a differential voltage amplifier 1332. The differential
voltage amplifier 1332 includes a non-inverting input coupled to a
first noise source V.sub.n1 (e.g., for modeling the noise of the
Hall-effect sensor), an inverting input coupled to a second noise
source V.sub.n2 (e.g., for modeling the input referred voltage
noise of the amplifier), and an inverting input coupled to a third
noise source V.sub.n3 (e.g., for modeling the thermal noise of the
feedback resistor). The model 1330 has a gain function of G.sub.FE.
The noise referred to the Hall sensor frontend can be expressed
as:
.sigma. n , tot = .sigma. n 1 .sym. .sigma. n 2 .sym. .sigma. n 3 (
R F / R H ) ( 9 ) ##EQU00006## such that
.sigma..sub.n,tot= {square root over
(4kTR.sub.H)}.sym..sigma..sub.n2.sym.R.sub.H {square root over
(4kT/R.sub.F)} (10)
where .sigma..sub.n,tot is the noise total, k is Boltzmann's
constant, T is the noise temperature, .sigma..sub.n1 is a noise
source associated with a first output (e.g., positive terminal) of
a Hall element, .sigma..sub.n2 is a noise source associated with
input referred noise of the amplifier, and element, .sigma..sub.n3
is a noise source associated with the thermal noise of the feedback
resistor. Accordingly, Eq. (10) demonstrates the noise tradeoff of
the instant current sensing scheme (as compared with Eq. (5), for
example, which demonstrates the noise tradeoff of a voltage-sensing
scheme).
[0106] FIG. 14 is a simulation diagram of a Hall sensor coupled to
an ideal voltage amplifier. Model 1410 is a schematic for
simulating selected characteristics of Hall sensor 1412 such that
an output of the Hall sensor 1412 is coupled to an input of the
ideal voltage amplifier 1418. Model 1410 includes a substrate 1414,
which is biased with a DC voltage provided by voltage source 1416
and is coupled to a ground (e.g., signal "gnd!"). The Hall sensor
1412 is arranged (e.g., virtually) in the substrate 1414 and
generates a Hall voltage across east (Vh_out1) and west terminals
(Vh_out2) in response to a Hall sensor bias current generated by
current source J2. The Hall sensor bias current is sourced via the
north terminal of the Hall sensor 1412 and is sunk (e.g., shunted
to ground) via the south terminal of the Hall sensor 1412. For
purposes of, for example, comparison of simulation results of the
disclosed model 1500 described below, the Hall sensor 1412 is a
Hall element array upon which spin current techniques are not used
to reduce the offset of the one or more Hall elements of the Hall
sensor 1412.
[0107] An (e.g., positive Hall-effect) output of the Hall sensor
1412 is coupled to an input of the unity gain voltage sense
amplifier 1418. The amplifier is a unity gain voltage sense
amplifier having a gain function such as described above in Eq.
(3). In contrast with the disclosed transimpedance amplifier 1518,
the unity gain voltage sense amplifier 1418 does not include a
feedback path, and is bandwidth-limited in accordance with the
source impedance (e.g., parasitic resistance and capacitance) of
the Hall sensor 1412.
[0108] Frequency response diagram 1420 includes a response curve
1422, which illustrates voltage in decibels (dB) as a function of
frequency (e.g., using logarithmic scaling). The response curve
1422 includes points 1424 and 1426, which illustrate a bandwidth
demonstrated by a simulation of model 1410. For example, point 1424
illustrates a lower frequency point having a magnitude of around
-30 dB at a frequency of around 76 Hz. Point 1426 illustrates a
higher frequency point having a magnitude of around -33 dB at a
frequency of around 214 MHz. A bandwidth of around 214 MHz over a 3
dB decline in gain is demonstrated during simulation.
[0109] FIG. 15 is a simulation diagram of a Hall sensor coupled to
a transimpedance amplifier in accordance with embodiments. Model
1510 is a schematic for simulating selected characteristics of Hall
sensor 1512 such that an output of the Hall sensor 1512 is coupled
to an input of a transimpedance amplifier 1518. The input magnetic
field is modeled by voltage source 1516 and the Hall sensor 1512
and generates a Hall voltage across east (Vh_out1) and west
terminals (Vh_out2) in response to a Hall sensor bias current
generated by current source J2 and magnetic field input 1516. The
Hall sensor bias current is sourced via the north terminal of the
Hall sensor 1512 and is sunk (e.g., shunted to ground) via the
south terminal of the Hall sensor 1512. For purposes of, for
example, comparison of simulation results of the model 1400, the
Hall sensor 1512 is a Hall element array upon which spin current
techniques are not used to reduce the offset of the one or more
Hall elements of the Hall sensor 1512.
[0110] An (e.g., positive Hall-effect) output of the Hall sensor
1512 is coupled to an input of the transimpedance amplifier 1518.
The transimpedance amplifier is a transimpedance amplifier having a
gain function such as described above in Eq. (6) and Eq. (7), an
input bandwidth a gain function such as described in Eq. (8), and a
noise model such as described in Eq. (9) and Eq. (10). In an
embodiment, the transimpedance amplifier 1518 includes a feedback
path, which includes feedback components such as capacitor C.sub.f
and resistor R.sub.f of model 1510. As described above, the
bandwidth of the (e.g., amplified) Hall voltage V.sub.H is
controlled by the values selected for the (e.g., non-parasitic)
feedback capacitor C.sub.f and the (e.g., non-parasitic) feedback
resistor R.sub.f.
[0111] The frequency response diagram 1520 includes a response
curve 1522, which illustrates voltage in decibels (dB) as a
function of frequency (e.g., using logarithmic scaling). The
response curve 1522 includes points 1524 and 1526, which illustrate
an operating bandwidth demonstrated by a simulation of model 1510.
For example, point 1524 illustrates a lower frequency point having
a magnitude of around 1 dB at a frequency of around 1.5 kHz. Point
1526 illustrates a higher frequency point having a magnitude of
around -2 dB at a frequency of around 1.39 GHz. In an embodiment,
an operating bandwidth of around 1.39 GHz over a 3 dB decline in
gain is demonstrated during simulation.
[0112] The model 1510 and model 1610 (described below) are
transimpedance amplifiers and, as disclosed herein, can be used in
place of amplifier 530 and/or 540 such that (for example) the
corrected offset signal (derived in response to outputs of
amplifiers 530 and 540) is more accurate. The corrected offset
signal is more accurate (e.g., than the corrected offset signal
derived only from the teachings of FIG. 5) because the offset
correction techniques (e.g., of FIG. 5 and FIG. 6) and the
transimpedance amplifiers (e.g., of FIG. 15 and FIG. 16) are used
together.
[0113] FIG. 16 is a simulation diagram of a Hall sensor coupled to
a variable transimpedance amplifier in accordance with embodiments.
Model 1610 is a schematic for simulating selected characteristics
of Hall sensor 1612 such that an output of the Hall sensor 1612 is
coupled to an input of a transimpedance amplifier 1618. Model 1610
includes a Hall sensor 1612, a substrate 1614, a voltage source
1616, and a transimpedance amplifier 1618. The Hall-effect voltage
of the Hall sensor 1612 is coupled to an input of the
transimpedance amplifier 1618.
[0114] In an embodiment, the transimpedance amplifier 1618 includes
a variable impedance feedback path, which includes feedback
components such as capacitor C.sub.f and resistor R.sub.f of model
1610. As described above, the bandwidth of the (e.g., amplified)
Hall voltage V.sub.H is selectively controlled by the values
selected for the (e.g., non-parasitic) feedback capacitor C.sub.f
and the (e.g., non-parasitic) feedback resistor R.sub.f. The values
can be programmably selected, for example, during operation and/or
calibration (e.g., under control of a processor such as CPU 112
executing special-purpose instructions) by iteratively closing
switches for selectively coupling (and decoupling) the feedback
components and measuring responses for a given feedback impedance
such that an optimum feedback impedance is selected. The
calibration routine can be run intermittently during operation such
that optimum feedback impedance is selected in view of changes in
operating conditions (such as changes in temperature). The optimum
feedback impedance can accordingly be selected to maximize an
operating bandwidth of the transimpedance amplifiers 1618.
[0115] FIG. 17 is a layout diagram of layout patterns for Hall
sensor arrays where each pattern includes multiple Hall elements
for coupling to the high bandwidth front end of a high bandwidth,
low offset Hall-effect sensor in accordance with embodiments. Hall
sensor array 1710 includes multiple Hall elements 1718 (e.g., used
for the Hall sensor of a high bandwidth front-end such as Hall
sensor 520) and multiple Hall elements 1716 (e.g., used for the
Hall sensor for a low bandwidth front-end such as Hall sensor 510).
The multiple Hall elements 1716 are optionally orthogonally coupled
(e.g., which reduces offset), whereas the multiple Hall elements
1716 are usually both orthogonally coupled and arranged to use
spinning current techniques (e.g., which reduces both offset and
available bandwidth). As illustrated, the multiple Hall elements
1716 include elements S1 through S4 (with each element having
positions 1 through 8), while the Hall elements 1718 include
element F1 through F5 (with each element having positions 1 through
8).
[0116] The Hall elements 1716 and 1718 are symmetrically arranged
around either or both a horizontal axis of reflection 1714 and a
vertical axis of reflection 1712, with the Hall elements 1716 being
adjacently positioned and mutually reflected across the horizontal
axis of reflection. For example, a first Hall element 1716 is
positioned such that the placement first Hall element 1716 is
reflected by an axis of reflection in the placement such that a
corresponding second Hall element 1716 appears as a notional mirror
image of the first Hall element 1716.
[0117] The Hall sensor array 1710 includes multiple (e.g., five)
Hall elements 1718 and multiple (e.g., four) Hall elements 1716,
which usually have similar form (e.g., a symmetrical cross),
composition, and function with respect to their own symmetry and
with respect to the symmetry of other elements of the Hall sensor
array 1710. The elements are each placed in a symmetrical
arrangement such that, for example, the effects of a (e.g.,
applied) magnetic field upon each element of the Hall sensor array
1710 is substantially similar to the respective effects upon each
of the other elements of the Hall sensor array. The orientation of
the switched bias currents of the Hall elements 1716 is illustrated
using a fixed switching phase, such as .phi.=0.
[0118] In operation, the multiple Hall elements 1718 generate a
high bandwidth Hall-effect voltage in response to a magnetic field.
For example, the multiple Hall elements generate a high bandwidth
Hall-effect voltage where the generate Hall-effect voltage has a
reduced offset when the multiple Hall elements 1718 are
orthogonally coupled. In contrast, the adjacent (e.g.,
symmetrically arranged) orthogonally coupled Hall elements 1716
have a further-reduced offset and a reduced available bandwidth as
result of being biased using a spinning current technique (wherein
the bias currents of the orthogonally coupled Hall elements 1716
are switched in each of eight directions through eight switching
phases). The bias currents of the orthogonally coupled Hall sensors
1716 are switched such that the directions of the bias currents in
a single phase have an equal number of currents (e.g., one current)
in each of the directions regardless of the changes in direction of
the bias currents in response to the changing of the switching
phase. For example, at switching phase .phi.=0, a first
low-bandwidth, orthogonally coupled Hall element 1716 is biased
from position (e.g., terminal) S1_1 to position S1_5 (from N to S),
a second low-bandwidth, orthogonally coupled Hall element 1716 is
biased from position S2_3 to position S2_7 (from E to W), a third
low-bandwidth, orthogonally coupled Hall element 1716 is biased
from position S3_5 to position S3_1 (from S to N), and a fourth
low-bandwidth, orthogonally coupled Hall element 1716 is biased
from position S4_7 to position S4_3 (from W to E).
[0119] Modifications are possible in the described embodiments, and
other embodiments are possible, within the scope of the claims.
* * * * *