U.S. patent application number 15/024711 was filed with the patent office on 2018-12-20 for mems components and method of wafer-level manufacturing thereof.
The applicant listed for this patent is MOTION ENGINE INC.. Invention is credited to Robert Mark Boysel.
Application Number | 20180362330 15/024711 |
Document ID | / |
Family ID | 52741674 |
Filed Date | 2018-12-20 |
United States Patent
Application |
20180362330 |
Kind Code |
A9 |
Boysel; Robert Mark |
December 20, 2018 |
MEMS COMPONENTS AND METHOD OF WAFER-LEVEL MANUFACTURING THEREOF
Abstract
A MEMS and a method of manufacturing MEMS components are
provided. The method includes providing a MEMS wafer stack
including a top cap wafer, a MEMS wafer and optionally a bottom cap
wafer. The MEMS wafer has MEMS structures patterned therein. The
MEMS wafer and the cap wafers include insulated conducting channels
forming insulated conducting pathways extending within the wafer
stack. The wafer stack is bonded to an integrated circuit wafer
having electrical contacts on its top side, such that the insulated
conducting pathways extend from the integrated circuit wafer to the
outer side of the top cap wafer. Electrical contacts on the outer
side of the top cap wafer are formed and are electrically connected
to the respective insulated conducting channels of the top cap
wafer. The MEMS wafer stack and the integrated circuit wafer are
then diced into components having respective sealed chambers and
MEMS structures housed therein.
Inventors: |
Boysel; Robert Mark;
(Honeoye n Falls, NY) |
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Applicant: |
Name |
City |
State |
Country |
Type |
MOTION ENGINE INC. |
Montreal |
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CA |
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Prior
Publication: |
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Document Identifier |
Publication Date |
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US 20160229685 A1 |
August 11, 2016 |
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Family ID: |
52741674 |
Appl. No.: |
15/024711 |
Filed: |
September 19, 2014 |
PCT Filed: |
September 19, 2014 |
PCT NO: |
PCT/CA2014/050902 PCKC 00 |
371 Date: |
March 24, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14622619 |
Feb 13, 2015 |
9309106 |
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15024711 |
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PCT/CA2014/050635 |
Jul 4, 2014 |
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14622619 |
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61881592 |
Sep 24, 2013 |
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61843598 |
Jul 8, 2013 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
B81B 2207/095 20130101;
B81B 2201/0235 20130101; B81C 2201/013 20130101; B81B 2207/012
20130101; B81B 2201/0264 20130101; B81C 2203/0792 20130101; B81B
2201/0242 20130101; B81B 2207/07 20130101; B81B 2207/015 20130101;
B81C 1/00238 20130101; B81B 7/007 20130101 |
International
Class: |
B81B 7/00 20060101
B81B007/00; B81C 1/00 20060101 B81C001/00 |
Claims
1. A method of manufacturing MEMS components, comprising the steps
of: bonding a MEMS wafer stack to an integrated circuit wafer, the
MEMS wafer stack having an inner side and an outer side, the MEMS
wafer stack comprising a top cap wafer and a MEMS wafer, the top
cap wafer having opposed inner and outer sides and insulated
conducting channels extending through the top cap wafer between the
inner side and the outer sides; the MEMS wafer having opposed first
and second sides and insulated conducting channels extending
through the MEMS wafer between the first side and the second side
of the MEMS wafer, the MEMS wafer also including MEMS structures
patterned therein, the top cap wafer and the MEMS wafer providing
respective top and side walls for defining at least part of
hermetically sealed chambers housing the corresponding MEMS
structures, the inner side of the top cap wafer facing the first
side of the MEMS wafer and the insulated conducting channels of the
top cap wafer and of the MEMS wafer being aligned to form insulated
conducting pathways; integrated circuit wafer has an inner side
with electrical contacts, such that the inner side of the MEMS
wafer stack is bonded to the inner side of the integrated circuit
wafer such that the insulated conducting pathways extend from the
electrical contacts of the integrated circuit wafer, through the
MEMS wafer, through the top cap wafer, to the outer side of the
MEMS wafer stack; forming electrical contacts on the outer side of
the top cap wafer, the electrical contacts being respectively
connected to the insulated conducting channels of the top cap
wafer; and dicing the MEMS wafer stack and the integrated circuit
wafer into MEMS components such that the MEMS components comprise
the hermetically sealed chambers and MEMS structures.
2. The method according to claim 1, wherein step a) comprises:
patterning the insulated conducting channels on the inner side of
the top cap wafer such that the insulated conducting channels
extend from the inner side of the top cap wafer and partially
through the top cap wafer; bonding the first side of the MEMS wafer
to the inner side of the top cap wafer; and patterning the
insulated conducting channels, the MEMS structures and the
sidewalls of the sealed chambers on the second side of the MEMS
wafer and through the MEMS wafer.
3. The method according to claim 2, comprising a step of removing a
portion of the outer side of the top cap wafer so as to isolate the
insulated conducting channels, said step being performed after the
step of patterning the insulated conducting channels or after the
step of bonding the MEMS wafer to the integrated circuit wafer.
4. The method according to claim 1 wherein the wafer stack further
includes a bottom cap wafer having opposed inner and outer sides
and insulated conducting channels extending through the bottom cap
wafer between the inner side and the outer side, the inner side of
the bottom cap wafer facing the second side of the MEMS wafer, the
insulated conducting channels of the bottom cap wafer being
respectively aligned with the insulated conducting channels of the
MEMS wafer and forming part of the insulated conducting pathways,
and wherein the bonding step further comprises bonding the outer
side of the bottom cap wafer to the inner side of the integrated
circuit wafer, the outer side of bottom cap wafer corresponding to
the outer side of wafer stack.
5. The method according to claim 4, wherein step a) comprises the
sub-steps of: patterning the insulated conducting channels of the
top cap wafer on the inner side of the top cap wafer such that the
insulated conducting channels extend from the inner side of the top
cap wafer and partially through the top cap wafer, and patterning
the insulated conducting channels of the bottom cap wafer on the
inner side thereof such that the insulated conducting channels
extend from the inner side of the bottom cap wafer and partially
through the bottom cap wafer; bonding the first side of the MEMS
wafer to the inner side of the top cap wafer; patterning the
insulated conducting channels, the MEMS structures and the
sidewalls of the sealed chambers on the second side of the MEMS
wafer and through the MEMS wafer; and bonding the second side of
the MEMS wafer to the inner side of the bottom cap wafer.
6. The method according to claim 5, comprising a step of removing a
portion of the outer side of the bottom and top cap wafers so as to
isolate their respective insulated conducting channels, said step
being performed after the step of bonding the second side of the
MEMS wafer step.
7. The method according to claim 4, wherein step of forming
electrical contacts comprises forming electrical contacts on the
outer side of the bottom cap wafer, the electrical contacts of the
bottom cap wafer being respectively connected to the insulated
conducting pathways.
8. The method according to claim 7, wherein step of bonding the
MEMS wafer stack is performed by solder-bonding the electrical
contacts of the bottom cap wafer to electrical contacts of the
integrated circuit wafer.
9. The method according to claim 1, comprising a step of bonding
one of the MEMS components obtained from dicing of the MEMS wafer
stack to a printed circuit board (PCB).
10. The method according to claim 1, wherein, the insulated
conducting channels of the top cap wafer and of the MEMS wafer are
fabricated using a trench fill process.
11. The method according to claim 1, wherein the top and bottom cap
wafers are made of a silicon material, and the insulated conducting
channels of the top cap wafer and of the MEMS wafer are fabricated
by etching trenches around a conductive plug of the silicon
material, and by filling the trenches of the top cap wafer with an
insulating material.
12. The method according to claim 1, wherein the insulated
conducting channels of at least one of the top cap wafer and the
MEMS wafer is fabricated by etching channels into the corresponding
top cap wafer or the MEMS wafer, lining the channels with an
insulating material and filling the channels with a conductive
material.
13. A MEMS (microelectromechanical system) component, comprising: a
top cap wafer having an inner side and an outer side and insulated
conducting channels extending between the inner side and the outer
side through a thickness of the top cap wafer, the outer side being
provided with electrical contacts connected to the insulated
conducting channels; a MEMS wafer having a first side and a second
side and insulated conducting channels extending between the first
side and the second side through a thickness of the MEMS wafer, the
MEMS wafer including a MEMS structure patterned therein, the inner
side of the top cap wafer and the first side of the MEMS wafer
being bonded with respective insulated conducting channels aligned
to form insulated conducting pathways; and an integrated circuit
wafer having an inner side and an outer side, the inner side of the
integrated circuit wafer including electrical contacts, the inner
side of the integrated circuit wafer facing the second side of the
MEMS wafer such that electrical contacts of the integrated circuit
wafer are electrically connected to the electrical contacts of the
top cap wafer with the insulated conducting pathways, the top cap
wafer and the MEMS wafer providing a top cap wafer side wall and a
MEMS wafer side wall defining at least part of a hermetically
sealed chamber that houses the MEMS structure.
14. The MEMS component according to claim 13, wherein the top cap
wafer and the MEMS wafer comprise a silicon material and the
integrated circuit wafer is a CMOS wafer.
15. The MEMS component according to claim 13, wherein conducting
portions of the insulated conducting channels of the top cap wafer
include filled trenches.
16. The MEMS component according to claim 13, wherein the insulated
conducting channels of the top cap wafer and of the MEMS wafer
comprise a conductive plug of a silicon material surrounded by
insulating material and/or by an air gap.
17. The MEMS component according to claim 13, wherein the insulated
conducting channels of the top cap wafer and/or of the MEMS wafer
comprise etched channels lined with an insulating material and
filled with a conductive material.
18. The MEMS component according to claim 13, comprising a bottom
cap wafer having an inner side and an outer side and insulated
conducting channels extending through the bottom cap wafer between
the inner side and the outer side, the inner side of the bottom cap
wafer being bonded to the second side of the MEMS wafer, the
insulated conducting channels of the bottom cap wafer being
respectively aligned with the insulated conducting channels of the
MEMS wafer and forming part of the insulated conducting pathways,
the outer side of the bottom cap wafer being bonded to the
integrated circuit wafer, the insulated conducting pathways
extending from the electrical contacts of the integrated circuit
wafer and successively through the bottom cap wafer, the MEMS wafer
and the top cap wafer to the electrical contacts of the top cap
wafer.
19. The MEMS component according to claim 13, comprising at least
one of an inertial sensor, an accelerometer, a gyroscope and a
pressure sensor.
20. The MEMS component according to claim 18, wherein at least one
of the top cap wafer and the bottom cap wafer comprises: additional
electrical contacts on the outer side of said at least one of the
top cap wafer and the bottom cap wafer, said additional electrical
contacts being electrically connected to integrated circuits of the
integrated circuit wafer; and electrodes operatively coupled to the
MEMS structure and to the additional electrical contacts,
respectively.
Description
RELATED PATENT APPLICATION
[0001] This patent application incorporates by reference, in its
entirety, and claims priority to U.S. Provisional Patent
Application No. 61/881,592, filed Sep. 24, 2013.
TECHNICAL FIELD
[0002] The general technical field relates to
micro-electro-mechanical systems (MEMS) and to methods for
manufacturing MEMS, and more particularly to a method of
integrating and packaging a MEMS device with an integrated circuit
(IC) at the wafer level.
BACKGROUND
[0003] MicroElectroMechanical Systems, referred to as MEMS, are an
enabling technology. Generally speaking, MEMS devices are
integrated circuits containing tiny mechanical, optical, magnetic,
electrical, chemical, biological, or other, transducers or
actuators. They are manufactured using high-volume silicon wafer
fabrication techniques developed over the last 50 years for the
microelectronics industry. Their resulting small size and low cost
make them attractive for use in an increasing number of
applications in consumer, automotive, medical, aerospace/defense,
green energy, industrial, and other markets.
[0004] In general, a MEMS device must interact with a particular
aspect of its environment while being protected from damage from
the surroundings. For example, a micro mirror has to interact with
light and with an electrical addressing signal while being
protected from moisture and mechanical damage. An accelerometer has
to be free to move in response to accelerated motion, but be
protected from dirt and moisture, and perhaps also be kept under
vacuum or low pressure to minimize air damping. In almost every
application an electrical connection must be made between the MEMS
transducer or actuator and an external Integrated Circuit, also
referred to as IC, IC chip or microchip, in order to read the
transducer signal or to address the actuator.
[0005] In an effort to drive down final device costs, there has
been a push to eliminate much of the packaging and wire bonding by
moving to wafer-scale packaging processes in which the MEMS and IC
wafers are combined at the wafer level. There are basically two
approaches to wafer-level integration of MEMS and IC. In one
approach, the wafer containing the MEMS sensor element is bonded
directly to a substrate wafer and covered with a non-functional lid
wafer, such as described in U.S. Pat. No. 8,069,726 or U.S. Pat.
No. 8,486,744. This approach requires modifying the IC wafer to
accommodate the MEMS layout, leading to inefficiencies in the IC
layout. Additionally, in order to electrically access the IC
input/output signals (IC I/O), which are trapped between the MEMS
device and the IC, it is necessary to mechanically trim the MEMS
chips and caps after wafer-scale bonding to expose the bond pads.
Wire bonding and packaging are still required, and therefore this
approach is not truly wafer-level packaging.
[0006] Through-Silicon Vias (TSVs) have been proposed as a means of
electrically connecting the MEMS and IC, either in the MEMS cap, as
in U.S. Pat. No. 8,084,332 or in the IC, as in U.S. Pat. No.
8,486,744. The use of TSVs requires that the silicon being
penetrated be limited in thickness to 100-200 microns. Using TSVs
restricts devices to small vertical dimensions, placing limits on
design and performance.
[0007] In the second approach to MEMS/IC wafer-level integration,
the MEMS wafer fabrication is completed and the MEMS wafer is
hermetically sealed separately from the IC wafer. This permits more
flexibility in the design, fabrication, and bonding of both the
MEMS and IC. Conducting TSVs or regions of silicon defined by
insulating TSVs are used to provide electrical paths through one of
the caps, and the MEMS and IC can be solder bonded together at the
wafer level without using bond wires.
[0008] However, this still leaves the IC electrical connections
trapped between the MEMS and the IC.
[0009] In order to bring the signals from the MEMS/IC interface to
the outside, it has been proposed that TSVs be put in the IC wafer,
prior to wafer-level bonding to the MEMS wafer. The backside of the
IC wafer is then thinned and metalized. In this way the electrical
signals can be routed between the MEMS and IC where necessary and
out the back for IC I/O. This approach enables true wafer-scale
MEMS/IC integration and packaging since the bonded wafers can be
diced directly into chips that can be solder-bonded to a PC board
without any additional wire bonding or packaging.
[0010] However, in order to put TSVs in an IC wafer, the IC design
and process flow must be drastically modified to accommodate them.
The TSV process involves etching holes or trenches into the IC
wafer, coating the trench surface with an insulator, and filling
the trench with a conductor such as polysilicon or metal. The TSVs
are large (5-30 microns wide and up to 100-200 microns deep)
compared to typically sub-micron IC feature sizes. Consequently
large areas of the IC area must be reserved for the TSVs, resulting
in less area-efficient and cost-efficient IC designs. Additionally,
the TSV and IC processes are incompatible. IC transistors are
fabricated in the top few microns of the wafer, while the TSV must
penetrate through or nearly through the IC wafer. The additional
TSV processes require additional non-IC fabrication tools such Deep
Silicon Reactive Ion Etchers (DRIE) and electroplating. If the TSV
fill is polysilicon, the TSVs must be placed in the IC wafer at the
beginning of the IC process to avoid thermally affecting the IC
implants during polysilicon deposition. If the TSVs are added at
the end of the IC process, they must be filled with metal, such as
electroplated Cu. Finally, an additional grind and polish step must
be added to thin the IC wafer in order to make electrical contact
to the TSVs. All these considerations add cost, either through
additional process steps, inefficient use of IC silicon active
area, or a limited choice of IC fabrication plants capable of
performing the TSV steps.
[0011] What is needed then is a low cost wafer-scale MEMS/IC
integration and packaging method that provides a hermetic MEMS/IC
component requiring no additional bond wires or external packaging
for attachment to a board, and that is applicable to a wide variety
of MEMS devices.
SUMMARY
[0012] In accordance with an aspect of the invention, there is
provided a method of manufacturing MEMS components.
[0013] In some embodiments, the method includes the steps of
providing a MEMS wafer stack having an inner side and an outer
side, the MEMS wafer stack comprising a top cap wafer and a MEMS
wafer, the top cap wafer having opposed inner and outer sides and
insulated conducting channels extending through the top cap wafer
between the inner and outer sides. The MEMS wafer has opposed first
and second sides and insulated conducting channels extending
through the MEMS wafer between the first and second sides. The MEMS
wafer also includes MEMS structures patterned therein, the top cap
wafer and the MEMS wafer providing respective top and side walls
for defining at least part of hermetically sealed chambers housing
the corresponding MEMS structures. The inner side of the top cap
wafer faces the first side of the MEMS wafer and the insulated
conducting channels of the top cap wafer and of the MEMS wafer are
aligned to form insulated conducting pathways. The method also
includes a step of providing an integrated circuit wafer having an
inner side with electrical contacts, and bonding the inner side of
the MEMS wafer stack to the inner side of the integrated circuit
wafer such that the insulated conducting pathways extend from the
electrical contacts of the integrated circuit wafer, through the
MEMS wafer, through the top cap wafer, to the outer side of the
MEMS wafer stack. The method also includes a step of forming
electrical contacts on the outer side of the top cap wafer, the
electrical contacts being respectively connected to the insulated
conducting channels of the top cap wafer. Finally, the method
includes a step of dicing the MEMS wafer stack and the integrated
circuit wafer into MEMS components such that the MEMS components
respectively comprise the hermetically sealed chambers and MEMS
structures.
[0014] In some embodiments, step a) includes the sub-steps of:
[0015] i) patterning the insulated conducting channels on the inner
side of the top cap wafer such that the insulated conducting
channels extend from the inner side and partially through the top
cap wafer; [0016] ii) bonding the first side of the MEMS wafer to
the inner side of the top cap wafer; and [0017] iii) patterning the
insulated conducting channels, the MEMS structures and the
sidewalls of the sealed chambers on the second side of the MEMS
wafer and through the MEMS wafer.
[0018] In some embodiments, the method includes removing a portion
of the outer side of the top cap wafer so as to isolate the
insulated conducting channels, said step being performed after step
iii) or after step b).
[0019] In some embodiments of the method, in step a), the wafer
stack further includes a bottom cap wafer having opposed inner and
outer side and insulated conducting channels extending through the
bottom cap wafer between the inner and outer sides. The inner side
of the bottom cap wafer faces the second side of the MEMS wafer.
The insulated conducting channels of the bottom cap wafer are
respectively aligned with the insulated conducting channels of the
MEMS wafer and form part of the insulated conducting pathways. Step
b) comprises bonding the outer side of the bottom cap wafer to the
inner side of the integrated circuit wafer, the outer side of
bottom cap wafer corresponding to the outer side of wafer
stack.
[0020] In some embodiments, step a) comprises the sub-steps of:
[0021] i) patterning the insulated conducting channels of the top
cap wafer on the inner side thereof such that the insulated
conducting channels extend from the inner side of the top cap wafer
and partially through the top cap wafer. Patterning the insulated
conducting channels of the bottom cap wafer on the inner side
thereof such that the insulated conducting channels extend from the
inner side of the bottom cap wafer and partially through the bottom
cap wafer; [0022] ii) bonding the first side of the MEMS wafer to
the inner side of the top cap wafer; [0023] iii) patterning the
insulated conducting channels, the MEMS structures and the
sidewalls of the sealed chambers on the second side of the MEMS
wafer and through the MEMS wafer; and [0024] iv) bonding the second
side of the MEMS wafer to the inner side of the bottom cap
wafer.
[0025] Preferably, the step of patterning consists in etched
trenches.
[0026] In some embodiments, the method comprises a step of removing
a portion of the outer side of the bottom and top cap wafers so as
to isolate their respective insulated conducting channels, this
step being performed after step iv).
[0027] In some embodiments, step c) includes forming electrical
contacts (43), such as bond pads, on the outer side of the bottom
cap wafer, the electrical contacts of the bottom cap wafer being
respectively connected to the insulated conducting pathways.
[0028] In some embodiments, step b) is performed by solder-bonding
the electrical contacts of the bottom cap wafer to electrical
contacts of the integrated circuit wafer.
[0029] In some embodiments, the method comprises a step of bonding
one of the MEMS components obtained in step d) to a printed circuit
board (PCB).
[0030] In some embodiments, in step a), the insulated conducting
channels of the top cap wafer, the bottom cap wafer and/or of the
MEMS wafer are fabricated using a trench fill process.
[0031] In some embodiments of the method, the top and bottom cap
wafers are made of a silicon-based material, and in step a), the
insulated conducting channels of the top cap wafer and of the MEMS
wafer are fabricated by etching trenches around a conductive plug
of the silicon-based material, and by filling the trenches of the
top cap wafer with an insulating material.
[0032] In yet other embodiments, the insulated conducting channels
of at least one of the top cap wafer and the MEMS wafer is
fabricated by etching channels into the corresponding top cap wafer
or the MEMS wafer, lining the channels with an insulating material
and filling the channels with a conductive material.
[0033] In accordance with another aspect of the invention, a MEMS
(microelectromechanical system) component is provided. The
component comprises a top cap wafer having opposed inner and outer
sides and insulated conducting channels extending between the inner
side and the outer side through an entire thickness of the top cap
wafer, the outer side being provided with electrical contacts
connected to the insulated conducting channels. The component also
includes a MEMS wafer having opposed first and second sides and
insulated conducting channels extending between the first and
second sides through an entire thickness of the MEMS wafer, the
MEMS wafer including a MEMS structure patterned therein. The inner
side of the top cap wafer and the first side of the MEMS wafer is
bonded with their respective insulated conducting channels aligned
to form insulated conducting pathways. The component also includes
an integrated circuit wafer having opposed inner and outer sides,
the inner side of the integrated circuit wafer including electrical
contacts, such as bond pads. The inner side of the integrated
circuit wafer faces the second side of the MEMS wafer so that
electrical contacts of the integrated circuit wafer are
electrically connected to the electrical contacts of the top cap
wafer via the insulated conducting pathways, the top cap wafer and
the MEMS wafer providing respective top and side walls defining at
least part of a hermetically sealed chamber for housing the MEMS
structure.
[0034] In some embodiments, the top cap wafer and the MEMS wafer
are silicon-based and the integrated circuit wafer is a CMOS
wafer.
[0035] In some embodiments, conducting portions of the respective
insulated conducting channels of the top and/or bottom cap wafer
are delimited by filled trenches.
[0036] In some embodiments, the insulated conducting channels of
the top cap wafer and of the MEMS wafer comprise a conductive plug
of silicon-based material surrounded by insulating material and/or
by an air gap.
[0037] In some embodiments, the insulated conducting channels of
the top cap wafer and/or of the MEMS wafer comprise etched channels
lined with an insulating material and filled with a conductive
material.
[0038] In some embodiments, the MEMS component includes a bottom
cap wafer having opposed inner and outer sides and insulated
conducting channels extending through the bottom cap wafer between
the inner and outer sides. The inner side of the bottom cap wafer
are bonded to the second side of the MEMS wafer. The insulated
conducting channels of the bottom cap wafer are respectively
aligned with the insulated conducting channels of the MEMS wafer
and form part of the insulated conducting pathways. The outer side
of the bottom cap wafer is bonded to the integrated circuit wafer.
The insulated conducting pathways extend from the electrical
contacts of the integrated circuit wafer and successively through
the bottom cap wafer, the MEMS wafer and the top cap wafer to the
electrical contacts of the top cap wafer.
[0039] In some embodiments, the MEMS component comprises at least
one of an inertial sensor, an accelerometer, a gyroscope and a
pressure sensor.
[0040] In some embodiments, at least one of the top and bottom cap
wafers includes additional electrical contacts on its outer side.
These additional electrical contacts are electrically connected to
integrated circuits of the integrated circuit wafer. The top and/or
bottom cap wafers also include electrodes operatively coupled to
the MEMS structure, some of which are connected to the additional
electric contacts of the IC wafer.
[0041] Other features and advantages of the embodiments of the
present invention will be better understood upon reading of
preferred embodiments thereof with reference to the appended
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0042] FIG. 1A is a schematic exploded perspective view of a MEMS
component, in accordance with an exemplary embodiment. FIG. 1B is a
schematic cross-sectional view of the MEMS component of FIG. 1A.
FIG. 1C is an enlarged view of a portion of FIG. 1B. FIG. 1D shows
another possible variant of an insulated conducting channel in the
top cap wafer.
[0043] FIG. 2A is a schematic exploded perspective view of a MEMS
component, in accordance with another exemplary embodiment. FIG. 2B
is a schematic cross-sectional view of the MEMS component of FIG.
2A.
[0044] FIG. 3A shows the MEMS component for a sealed MEMS device,
formed from a three layer wafer stack and bonded to an IC wafer,
according to an exemplary embodiment. FIG. 3B (PRIOR ART) shows a
conventional sealed MEMS device bonded to an IC.
[0045] FIG. 4A shows a MEMS component with a MEMS device wafer
bonded directly to an IC wafer, without a bottom cap wafer,
according to a possible embodiment of the invention. FIG. 4B (PRIOR
ART) shows an existing MEMS bonded directly to an IC wafer.
[0046] FIG. 5 is a schematic partial top view of a top cap wafer,
according to a possible embodiment. FIG. 5A is a schematic partial
cross-sectional view of the top cap wafer of FIG. 5, showing the
patterning of trenches for forming insulated conducting channels.
FIGS. 5B and 5C show steps for lining and filling of the patterned
trenches, according to a possible embodiment. FIG. 5D shows a
possible variant of an insulated conducting channel in the top cap
wafer. FIG. 5E is an enlarged view of FIG. 5C.
[0047] FIG. 6A is a schematic partial cross-sectional view of a
bottom cap wafer, according to a possible embodiment.
[0048] FIG. 7 is a partial top view of a MEMS wafer bonded to a top
cap wafer, according to a possible embodiment. FIG. 7A is a
schematic partial cross-sectional view of the MEMS wafer bonded to
the top cap wafer. FIG. 7B is schematic perspective view of
portions of a MEMS wafer and of a top cap wafer.
[0049] FIG. 8A is a schematic partial cross-sectional view of the
bottom cap wafer bonded to the MEMS wafer, according to a possible
embodiment. FIG. 8B is a schematic exploded perspective view of a
section of a bottom cap wafer, and of a section of the MEMS wafer
bonded to the top cap wafer.
[0050] FIG. 9A is a schematic partial cross-sectional view of a
MEMS wafer stack bonded to an IC wafer, wherein the MEMS wafer
stack that does not include a bottom cap wafer. FIG. 9B is a
schematic exploded perspective view of the sections of the IC wafer
and of the MEMS wafer stack shown in FIG. 9A.
[0051] FIG. 10 is a partial cross-sectional view a MEMS wafer stack
being completed, according to a possible embodiment, showing the
thinning of the top and bottom cap wafers to isolate the insulated
conducting channels. FIG. 10 also shows the deposition of an
insulating cap layer.
[0052] FIG. 11 is a partial cross-sectional view of the MEMS wafer
stack of FIG. 10, showing the bond pad metallization on the top and
bottom cap wafers, according to a possible embodiment.
[0053] FIG. 12 is a schematic cross-sectional view of an IC wafer
bonded to a MEMS wafer stack for forming several MEMS components,
before wafer dicing, according to a possible embodiment.
[0054] FIG. 13 is a schematic cross-sectional view of one of the
MEMS components of FIG. 12, flip chip bonded via the electrical
contacts of its top cap to a PC board, according to a possible
embodiment.
[0055] FIG. 14 is a schematic cross-sectional view of an IC wafer
bonded to a MEMS wafer stack for forming several MEMS components,
before wafer dicing, according to another possible embodiment.
[0056] It should be noted that the appended drawings illustrate
only exemplary embodiments of the invention, and are therefore not
to be construed as limiting of its scope, for the invention may
admit to other equally effective embodiments.
DETAILED DESCRIPTION
[0057] In the following description, similar features in the
drawings have been given similar reference numerals, and, in order
to not unduly encumber the figures, some elements may not be
indicated on some figures if they were already identified in
preceding figures. It should also be understood that the elements
of the drawings are not necessarily depicted to scale, since
emphasis is placed upon clearly illustrating the elements and
structures of the present embodiments.
[0058] The present description generally relates to a
Micro-Electro-Mechanical System component, or MEMS component,
including a MEMS device packaged with an IC chip. The description
also relates to the wafer level bonding of a MEMS wafer stack to an
integrated circuit wafer, also referred to as an IC wafer, and the
dicing of the wafer stack and IC wafer to form several MEMS
components. Each MEMS component obtained by this method includes
one or several MEMS structures, hermetically sealed within the
component. Each MEMS component also includes insulated conducting
pathways extending vertically though its thickness, such that
electrical signals from the IC chip can be routed through the MEMS
device and accessed via electrical contacts on the top or outer
face of the MEMS device. Advantageously, the use of TSVs within the
IC wafer can be avoided, as well as wire-bonding.
[0059] Throughout the description, the term MEMS encompasses
devices such as, but not limited to, accelerometer, gyroscope,
pressure sensors, magnetometers, actuators, transducers,
micro-fluidic, micro-optic devices and the likes. The MEMS wafer
may also include microelectronic circuits such as power amplifiers,
detection circuitry, GPS, microprocessors, and the likes.
[0060] It will be understood that throughout the present
description, and unless stated otherwise, positional descriptors
such as "top" and "bottom" should be taken in the context of the
figures and should not be considered as being limitative. In
particular, the terms "top" and "bottom" are used to facilitate
reading of the description, and those skilled in the art of MEMS
will readily recognize that, when in use, MEMS devices can be
placed in different orientations such that the "top" and "bottom"
cap wafers and the "top" and "bottom" sides of the wafers may be
positioned upside down in certain configurations. In the following
description, the convention is taken that "top" refers to the
direction opposite the IC wafer.
[0061] According to an aspect of the invention, the MEMS components
are provided with an architecture that enables the routing of
electrical signals via insulated conducting pathways (such as
feedthroughs and electrical leads) in the MEMS device. The MEMS
device comprises at least a MEMS wafer and a top cap wafer. The
MEMS wafer is typically the wafer or stack of wafers which includes
a sensing and/or moving structure. The MEMS device can also
optionally comprise a bottom cap wafer. An IC chip is bonded to the
MEMS device and provides an electrical interface between the
singulated MEMS and IC wafers which requires no bond wires.
Furthermore, the MEMS device can act as an interposer to route I/O
signals from the IC chip back through the MEMS device to electrical
contacts (typically bond pads) on the MEMS cap (e.g., the top cap)
which is opposite to the IC chip. The need for additional
processing of the IC wafer for wafer thinning and addition of IC
TSVs is thereby eliminated. While the IC wafer is typically a
complementary metal-oxide-semiconductor (CMOS) wafer, other types
of integrated circuits can also be considered, such as Bipolar-CMOS
(BiCMOS), Silicon Carbide ICs, and Gallium-Arsenide ICs.
[0062] Different embodiments are possible. For example, the MEMS
portion of the component can include a MEMS wafer and a first or
top cap wafer, such as shown in FIGS. 1A, 1B and 4A. Alternatively,
the MEMS portion of the component can further comprise a second or
bottom cap wafer, as in FIGS. 2A, 2B and 3A. When manufacturing the
MEMS components, the IC wafer can be bonded to the MEMS wafer
directly, or to the second or bottom cap wafer. In the disclosed
MEMS packaging architecture, the MEMS portion of the component
includes electrically isolated "Three Dimensional Through-Chip
Vias" (3DTCVs) to route signals from/to the top cap wafer, through
the MEMS wafer and optionally through the bottom cap wafer to
electrical contacts located on the bottom side of the MEMS device,
at the interface with the IC chip. The bonded MEMS and IC wafers
are diced (or singulated) into MEMS components (or chips) and the
top cap can be flip-chip bonded to a PC board.
Examples of Possible Embodiments of MEMS Components
[0063] Referring to FIGS. 1A and 1B, there are shown a schematic
perspective view and a schematic cross-sectional view,
respectively, of a MEMS component 8, according to a possible
embodiment. In this embodiment, the MEMS component 8 includes a top
cap wafer 12, a MEMS wafer 16 and an IC wafer 44. The top cap wafer
12 has opposed inner and outer sides 121, 122 and insulated
conducting channels 123 extending between the inner side 121 and
the outer side 122 through an entire thickness of the top cap wafer
12. The outer side 122 is provided with electrical contacts 42,
such as bond pads, which are connected to the insulated conducting
channels 123, respectively. The top cap wafer 12 is typically an
electrically conductive silicon-based wafer, although other types
of wafers can be considered. Insulated conducting channels are
electrically conducting segments extending within a layer of the
MEMS device 10 (or MEMS portion of the component 8). The insulated
conducting channels are electrically isolated from other components
or features of the layer. Insulated conducting channels can have
different configurations, as will be explained in greater detail
below.
[0064] The MEMS wafer 16 has opposed first and second sides 161,
162 and insulated conducting channels 163 extending between the
first and second sides 161, 162, through the entire thickness of
the MEMS wafer 16. The MEMS wafer 16 can consist of a standard
electrically conductive silicon-based wafer or of multiple
silicon-based wafers bonded together.
[0065] The MEMS wafer 16 includes a MEMS structure 17 patterned
therein. The MEMS structure 17 can include or be embodied by any
sensing element or combination of sensing elements such as, but not
limited to, membranes, diaphragms, proof masses, comb sensors,
actuators, transducers, micro-valves, micro-pumps, and the
like.
[0066] The inner side 121 of the top cap wafer 12 and the first
side 161 of the MEMS wafer are bonded with their respective
insulated conducting channels 123, 163 aligned to form insulated
conducting pathways 33. Insulated conducting pathways, which can
also be referred to as Three-Dimensional Through-Chip Vias
(3DTCVs), are electrically conducting pathways surrounded by
insulating material and extend through the entire thickness of the
MEMS device 10, in this case formed by the top cap wafer 12 and the
MEMS wafer 16.
[0067] The insulated conducting channels 123, 163 can include a
conductive plug 26 (or conductive pad) of a silicon-based material,
in this case corresponding to a portion of the wafers. As best
shown in enlarged FIG. 1C, the insulated channels 123 in the top
cap wafer comprises a silicon wafer plug 26 surrounded by a trench.
The trench is lined by an insulating material 30, preferably a
dielectric such as silicon dioxide, and the trench is filled with a
conductive material 32, such as metal, silicon or polysilicon. In
the MEMS wafer, the conductive plug 26 can simply be surrounded by
an air gap. Alternatively, the insulated conducting channels 123
and/or 163 can be formed as etched channels, or holes, filled with
an insulating material 30, such as shown in FIG. 1D.
[0068] Referring back to FIGS. 1A and 1B, the IC wafer 44 has
opposed inner and outer sides 441, 442. The IC wafer 44 includes
several electronic circuits 62 which can be operatively connected
to the MEMS structure 17 and/or electrodes 13 of the MEMS wafer
stack 10. The IC wafer 44 is typically a CMOS wafer, although other
types of ICs can be used. The inner side 441 of the IC wafer 44
includes electrical contacts 48, such as bond pads. The inner side
441 of the IC wafer 44 faces the second side 162 of the MEMS wafer
16. In the present case, the inner side 441 of the integrated
circuit wafer faces directly the second side 162 of the MEMS wafer
16, but other arrangements are possible, as discussed below.
[0069] The electrical contacts 48 of the integrated circuit wafer
44 are electrically connected to the electrical contacts 42 of the
top cap wafer 12 via the insulated conducting pathways 33. In this
embodiment, electrical contacts 43 are also provided on the outer
side 162 of the MEMS wafer, and the contacts 43 from the MEMS wafer
14 and the contacts 48 (such as bond pads) from the IC wafer 44 can
be solder-bonded, or bump-bonded, with solder bumps. The top cap
wafer 12 and the MEMS wafer 16 provide respective top and side
walls 124, 164 which define, at least partially, the hermetically
sealed chamber 31 for housing the MEMS structure 17, such as comb
sensors for example. In this embodiment, the bottom sidewall is
formed by the IC wafer 44, but other arrangements are possible, an
example of which is provided in FIGS. 2A and 2B. Insulating and/or
metallization layers 40, 41 are typically applied and patterned on
the outer sides of the MEMS device 10.
[0070] Additional structures and/or features can be provided in the
top cap wafer 12 and/or MEMS wafer 16, such as electrodes 13 and
leads. The MEMS device 10 can advantageously act as an interposer,
with the insulated conducting pathways 33 used as vertical
feedthroughs extending from the IC wafer 44 up to electrical
contacts 42 on the top/outer side 122 of the MEMS device 10.
Integrated circuits 62 of the IC wafer 44 can thus be accessed from
the top side of the MEMS component 8. The micro-circuits 62 can
also be electrically coupled to the various electrodes and MEMS
structures 17, to read and/or transmit signals from/to the
electrodes 13 and/or other structures. Additional electrical
contacts on the outer sides of the MEMS wafer stack 10 can be
provided, with additional insulated conducting pathways being
operatively connected to these additional contacts and to the
electrodes and/or structures and/or micro-circuits 62.
[0071] Referring to FIGS. 2A and 2B, there are shown a schematic
perspective view and a schematic cross-sectional view,
respectively, of a MEMS component 80, according to another possible
embodiment.
[0072] The MEMS component 80 includes a top cap wafer 12, a MEMS
wafer 16 and an integrated circuit wafer 44, similar to those
described in reference to FIGS. 1A and 1B. However in this case,
the component 80 also comprises a bottom cap wafer 14. The bottom
cap wafer 14 is typically an electrically conducting silicon-based
wafer, although other types of wafer can be considered. The bottom
cap wafer 14 has opposed inner and outer sides 141, 142 and
insulated conducting channels 143 extending through the bottom cap
wafer 14, between its inner and outer sides 141, 142. The inner
side 141 of the bottom cap wafer 14 is bonded to the second side
162 of the MEMS wafer 16, with the insulated conducting channels
143 of the bottom cap wafer 14 respectively aligned with the
insulated conducting channels 163 of the MEMS wafer 16. The
insulated conducting channels 143 thus form part of the insulated
conducting pathways 33. The outer side 142 of the bottom cap wafer
14 is bonded to the integrated circuit wafer 44. Accordingly, the
insulated conducting pathways 33 extend from the electrical
contacts 48 of the integrated circuit wafer 44 and successively
through the bottom cap wafer 14, the MEMS wafer 16 and the top cap
wafer 12 to the electrical contacts 42 of the top cap wafer 12. As
in the embodiment of FIGS. 1A and 1B, the inner side 441 of the
integrated circuit wafer 44 faces the second side 162 of the MEMS
wafer 16, but this time indirectly since a bottom cap wafer 124 is
provided between the MEMS wafer 16 and the integrated circuit wafer
44.
[0073] Similarly to the embodiment of FIGS. 1A and 1B, the MEMS
component 80 of FIGS. 2A and 2B can include any type of MEMS, such
as for example an inertial sensor, an accelerometer, a gyroscope
and a pressure sensor. The MEMS component 80 also preferably has at
least one of the top and bottom cap wafers 12, 14 comprising
additional electrical contacts 47 on its outer side. These
additional electrical contacts 47 are connected to integrated
circuits 62 of the integrated circuit wafer 44 at one end, and to
electrodes 13 or 15 and/or the MEMS structure 17 of the MEMS device
10 at an opposed end. Electrical signals can thus be routed from/to
integrated circuit wafer 44 to MEMS features (leads, feedthroughs,
electrodes, sensing elements) of the MEMS device 10 via additional
insulated conducting pathways. An underfill 66 can be added between
the bottom cap wafer 14 and the IC wafer 44.
[0074] It will noted here that although the terms "top cap wafer",
"MEMS wafer", "bottom cap wafer" and "IC wafer" are used for
describing the different layers of the MEMS components 8, 80, these
terms refers to the diced portion or section of larger wafers.
During the manufacturing, as will described in more detail with
reference to FIGS. 5A to 13, entire top 120, MEMS 160, bottom 140
and IC 440 wafers are patterned, processed and bonded, and the MEMS
components 8, 80 are obtained after dicing the bonded wafers into
singulated or individual components.
[0075] Referring now to FIGS. 3A and 3B, and 4A and 4B, schematic
cross-sectional views of different MEMS architectures are shown.
FIGS. 3A and 4A are possible embodiments of MEMS components
according to the present invention, and for comparison, FIGS. 3B
and 4B are schematic representation of existing MEMS designs and
MEMS bonded directly to the IC wafer, respectively. In these prior
art implementations, the cap 2 is an inert structure used to
protect and seal the MEMS. Once the MEMS and IC wafers are bonded
together, the IC inputs/outputs (I/O) 4 are trapped between the
MEMS and the IC and are no longer electrically accessible. Other
wafer-scale packaging approaches rely on the use of TSVs through
the IC wafer to access signals. In such approaches, using TSVs
involves redesigning the IC wafer to isolate areas for the large
TSVs; then adding the TSVs post-ICs; and then thinning the IC wafer
to provide access to the TSVs. These processes add cost and limit
IC wafer source options. As can be appreciated, and as shown in
FIGS. 3A and 4A, signals from the IC wafer 44 can be routed to the
top/outer side of the MEMS components 8, 80, without requiring any
wire-bonding or TSVs in the IC wafer. The components 8, 80 can be
flip chip bonded directly to a Printed Circuit Board (PCB).
Method of Manufacturing MEMS Component
[0076] In accordance with another aspect, there is provided a
method for manufacturing MEMS components using wafer-scale
integration and packaging.
[0077] Broadly described, the method comprises the steps of
providing a MEMS wafer stack including at least a top cap wafer and
a MEMS wafer. The MEMS wafer stack is patterned with insulated
conducting pathways. An IC wafer is also provided. The IC wafer is
bonded to the MEMS wafer stack, the MEMS wafer stack and the IC
wafer are then diced into individual MEMS components, with MEMS
structure(s) being hermetically sealed in chambers formed either
between the MEMS wafer stack and the IC wafer, or entirely within
the MEMS wafer stack.
[0078] The method for manufacturing the MEMS components will be
described with reference to FIGS. 5A to 14, which schematically
illustrate steps and possible sub-steps of an exemplary embodiment
of the method. It will be noted that the method described is a
wafer level packaging method, and therefore entire wafers or large
portions of wafers are used in the steps occurring before the
dicing/singulating step. However, for clarity, in FIGS. 5A to 11,
only the portion of the wafer corresponding to a single MEMS
component is shown, although a plurality of such MEMS components
are manufactured on each wafer. As such, one skilled in the art
will understand that the portion of the wafer shown in FIGS. 5A to
11 is repeated on the area of the corresponding wafers. In other
words, the different steps of the method (such as the patterning,
lining, depositing, grinding, passivating, bonding and dicing) are
performed on the entire surface of the wafers (or at least on a
substantial section of the wafers), at the "wafer-scale", in order
to fabricate a plurality of preferably identical MEMS components.
For clarity, the perspective and top views show only portions of
the wafers associated to one of the many MEMS components fabricated
from entire wafers.
[0079] Referring to FIGS. 5A to 5E, at the start of the fabrication
of the MEMS packaging architecture, a wafer 120, preferably an
electrically conducting silicon-based wafer, is provided. The top
cap wafer 120 is patterned with predetermined patterns by etching
trenches 28 into the silicon 26 and filling the trenches 28 with
either an insulating material 30, or an insulating layer 30
followed by a conductive fill 32, as shown in FIGS. 5D and 5E,
respectively. Numerous trench fill processes are available at
different MEMS fabrication facilities and the insulating and
conducting materials vary between them. The details of the trench
fill process are not critical. Preferably, trenches 28 are etched
to form islands or plugs of silicon, which may eventually become
electrodes and feedthroughs, are surrounded by insulating barriers.
The trenches 28 are patterned into the silicon 26 at a sufficient
depth, which is at least slightly greater than the final desired
final cap thickness. The insulated conducting channels 123 to be
formed are patterned on the inner side 121 of the top cap wafer 120
such that the insulated conducting channels 123 extend from the
inner side 121 and partially through the top cap wafer 120. The top
wall 124 of the chamber is also preferably patterned, and also
preferably the electrodes 13.
[0080] For embodiments of the method in which a bottom cap wafer is
used, the same steps as described above are performed on another
silicon wafer 140, as shown in FIG. 6A. The bottom cap wafer 140 is
patterned with trenches 28 to form insulated conducting channels
143, from the inner side 141 and partially through the bottom cap
wafer 140. The bottom wall 144 of the chamber is also preferably
patterned during this step, and also preferably electrodes 15.
[0081] Referring to FIGS. 7, 7A and 7B, a MEMS wafer 160 is
provided. A first side 161 of the MEMS wafer 160 is bonded to the
inner side 121 of the top cap wafer 120. The MEMS wafer 160 also
typically consists of a silicon-based wafer, and can be a single
wafer or multi-stack wafer. During this step, the MEMS wafer 160 is
aligned and bonded to the top cap wafer 120, with the inner side
121 of the top cap wafer 120 facing the first side 161 of the MEMS
wafer 160. The wafer bonding process used is typically one that
provides a conductive bond, such as fusion bonding, gold
thermocompression bonding, or gold-silicon eutectic bonding.
Insulated conducting channels 163, MEMS structures 17, and the
sidewalls 164 of the cavities which will form part of the sealed
chambers are patterned on the second side 162 of the MEMS wafer 16
and through the MEMS wafer 16. The partial insulated conducting
channels 123 of the top cap wafer 120 and the insulated conducting
channels 163 of the MEMS wafer 16 are aligned to form the future
insulated conducting pathways 33. The desired MEMS patterns can
include electrodes, leads, and feedthroughs, delimited by trenches
28 in the MEMS wafer 160. The silicon plugs 26 on the MEMS wafer
160 are aligned to the corresponding plugs 26 on the top cap wafer
120 and electrodes 13 on the top cap wafer 120 are aligned to the
relevant electrodes and structure 17, 19 of the MEMS wafer 160. If
no bottom wafer is used, then the MEMS wafer stack 100 only
includes the top cap wafer 120 and the MEMS wafer 160.
[0082] As explained previously, the insulated conducting channels
123 of the cap wafers 120, 140 and of the MEMS wafer 160 are
preferably fabricated by etching trenches around conductive plugs
26 of the silicon-based wafer. For the top and/or bottom cap wafers
120, 140, the trenches are lined with an insulating material 30 and
the lined trenches are filled with a conductive material 32. The
insulated conducting channels of the MEMS wafer 160 can be
fabricated the same way, or alternatively, the trenches 28 can be
left unfilled; in this case the air surrounding the silicon plugs
26 acts as an insulator. Yet another alternative consists in
filling the trenches with an insulating material 30. The channels
123, 143 or 163 can also be fabricated using a TSV process.
[0083] Referring to FIGS. 8A and 8B, in embodiments of the method
where a bottom cap wafer 140 is used as part of the MEMS wafer
stack 100, the second side 162 of the MEMS wafer 16 is bonded to
the inner side 141 of the bottom cap wafer 14. A wafer bonding
method such as fusion bonding, gold thermocompression bonding, or
gold-silicon eutectic bonding can be used to provide electrical
contact between the conducting channels 163 of the MEMS wafer, and
the conducting channels 143 of the bottom cap wafer 140. Conducting
pathways 33, such as feedthroughs, thus extend from the bottom cap
140 to the top cap 120. Additional pathways can also be formed and
connected to the MEMS structure 17 and/or electrodes 13, 15, 19 in
the bottom, top and/or MEMS wafers 120, 140, 160. At this point,
the MEMS structure 17 of each of the future MEMS components is
hermetically sealed in a corresponding chamber 31 between the cap
wafers 120, 140. The conducting channels 123, 163, 143 are aligned
to form what will become insulated conducting pathways 33.
Electrodes 13, 15, 19 of the top, MEMS and bottom wafers are also
aligned. Since the conducting channels 123, 163, 143 do not fully
penetrate the cap wafers 120, 140, the pathways 33 and the
electrodes 13, 15 on each cap are shorted together through the
remaining silicon.
[0084] Referring to FIGS. 9A and 9B, in an alternative embodiment,
a bottom cap wafer is not used and the MEMS wafer stack 100, formed
by the MEMS wafer 160 and top cap wafer 120, are bonded directly to
a pre-patterned integrated wafer 440, preferably using a eutectic
solder bond. The bonding of the MEMS wafer directly to the CMOS
wafer is typically a metal bond, such as eutectic solder or
compression bond. The bond metal has two functions: a general
mechanical bond to provide a hermetic chamber and electrical
contacts where required. Preferably, both the MEMS and IC wafers
have pre-existing metal pads and the solder attaches them. In order
to insulate the pathways and electrodes 33, 13 from one another, to
form a component such as shown in FIG. 4A, a portion of the outer
side 122 of the top cap wafer 12 then needs to be removed. The
insulated conducting channels 123 are isolated after the top cap
wafer 120 has been thinned, such as by grinding. The step of
removing or thinning the outer side 122 of the top cap wafer 120
can be performed after the step of bonding of the integrated
circuit wafer 440 to the MEMS wafer stack 100.
[0085] The possible sub-steps for forming electrical contacts on
the outer side of the cap wafers will be explained with reference
to FIGS. 10 and 11. Of course, for embodiments in which a single
cap wafer is used, the process of forming electrical contacts only
occurs on this cap, and electrical contacts are also formed on the
side of the MEMS wafer facing the IC wafer.
[0086] Referring to FIG. 10, a portion of the outer side 122, 142
of the bottom and top cap wafers 120, 140 is removed so as to
isolate their respective insulated conducting channels 123, 143.
More specifically, both cap wafers 120, 140 are ground and polished
to expose the insulating channels 123, 143, so as to form the
insulated conducting pathways 33. The electrodes 13, 15 are also
electrically isolated and connected to additional conducting
pathways and/or electrical contacts 47, opening on the top and/or
bottom cap wafers 120, 140. The outer surfaces 122, 142 can be
passivated with an insulating oxide layer 40 to protect them.
[0087] Referring to FIG. 11, electrical contacts 42 on the outer
side 122 of the top cap wafer 120 are formed. The electrical
contacts 42 are respectively connected to the insulated conducting
channels 123 of the top cap wafer 120. In this variant of the
process, electrical contacts 43 on the outer side 142 of the bottom
cap wafer 14 are also formed, the electrical contacts 43 being
respectively connected to the insulated conducting channels 143,
and thus to the pathways 33 as well. More specifically, the
openings are made in the cap insulating layer 40, over or in-line
with the insulated conducting pathways 33 extending from the top to
the bottom cap wafers 120, 140. Then, bond pad metallization 45 is
applied. Electrical contacts 43 from the bottom cap wafer 140 are
electrically connected to the contacts 32 of the top cap wafer 120,
and are thus accessible from the top, such as for wafer bonding.
Additional contacts 47 can also be formed, and connected to the
electrodes 13, 15 and/or the MEMS structure 17.
[0088] Referring to FIG. 12, an IC wafer 440 having an inner side
441 with electrical contacts 48 is provided. The inner side 101 of
the MEMS wafer stack 100 is bonded to the inner side 441 of the
integrated circuit wafer 440 such that the insulated conducting
pathways 33 extend from the electrical contacts 48 of the IC wafer
440, through the MEMS wafer 160, through the top cap wafer 120, to
the outer side 102 of the MEMS wafer stack 100. This step can be
made by solder-bonding the electrical contacts 43 of the bottom cap
wafer 140 to electrical contacts 48 of the IC wafer 440. As can be
appreciated, an entire IC wafer 440 is solder bonded to bottom cap
wafer 140 of a wafer stack 100 at the wafer level. Preferably, a
patterned polymeric underfill 66 is used, to protect the interface,
as is known in the industry. The bonded stack formed by the MEMS
stack 100 and the IC wafer 440 can then be diced into individual
MEMS components or chips 80, along cutting lines 81. The MEMS
components 88 need no additional packaging or wire bonding, and can
be flip chip bonded directly to a PCB 46, as shown in FIG. 13.
[0089] Referring to FIG. 14, for MEMS components 8 for which no
bottom cap wafer is used, the bonding and dicing process is
similar, except that the MEMS wafer 160 is provided with electrical
contacts 43, such as bond pads, which are solder-bonded to the
contacts 48 of the IC wafer 440. The dicing or singulating step is
also conducted along predetermined cut lines 81 such that each MEMS
component 8 has a hermetically sealed cavity 31 with a MEMS
structure 17 housed therein.
[0090] Of course, other processing steps may be performed prior,
during or after the above described steps. Also, the order of the
steps may also differ, and some of the steps may be combined or
omitted. The figures illustrate only exemplary embodiments of the
invention and are, therefore, not to be considered limiting of its
scope, for the invention may admit to other equally effective
embodiments. The scope of the claims should not be limited by the
preferred embodiments set forth in the examples, but should be
given the broadest interpretation consistent with the description
as a whole.
* * * * *