U.S. patent application number 16/108054 was filed with the patent office on 2018-12-13 for method for reviewing defects.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Jun-Ming Chen, Sheng-Chieh Chen, Chung-Chih Hung, Hung-Chin Lin, Chia-Chen Sun, Yung-Teng Tsai, Chih-Yu Wu.
Application Number | 20180356347 16/108054 |
Document ID | / |
Family ID | 62712277 |
Filed Date | 2018-12-13 |
United States Patent
Application |
20180356347 |
Kind Code |
A1 |
Tsai; Yung-Teng ; et
al. |
December 13, 2018 |
METHOD FOR REVIEWING DEFECTS
Abstract
A semiconductor structure includes a wafer comprising a
plurality of viewing fields defined thereon, a plurality of dies
defined by a scribe line formed in each viewing field, a plurality
of mark patterns formed in the scribe line, and a plurality of
anchor pattern respectively formed in the review fields, the anchor
patterns being different from the mark patterns.
Inventors: |
Tsai; Yung-Teng; (Tainan
City, TW) ; Lin; Hung-Chin; (Tainan City, TW)
; Sun; Chia-Chen; (Kaohsiung City, TW) ; Wu;
Chih-Yu; (Tainan City, TW) ; Chen; Jun-Ming;
(Hsinchu City, TW) ; Hung; Chung-Chih; (Kaohsiung
City, TW) ; Chen; Sheng-Chieh; (Tainan City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
62712277 |
Appl. No.: |
16/108054 |
Filed: |
August 21, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15396805 |
Jan 2, 2017 |
10082471 |
|
|
16108054 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 22/12 20130101;
H01L 2223/54426 20130101; H01L 23/544 20130101; H01L 2223/5446
20130101 |
International
Class: |
G01N 21/93 20060101
G01N021/93; H01L 23/544 20060101 H01L023/544; H01L 21/66 20060101
H01L021/66; G01N 21/95 20060101 G01N021/95 |
Claims
1. A method for reviewing defects, comprising: receiving a
semiconductor structure and sets of coordinates locating a
plurality of defects formed thereon in a defect review apparatus;
identifying a plurality of viewing fields on the semiconductor
structure and recognizing a plurality of origin points respectively
in the viewing fields in the defect review apparatus, and each
viewing field comprising a plurality of dies formed therein;
performing a first review step to review a plurality of anchor
patterns in the viewing fields; performing an offset correction
after the first review step to re-locating the plurality of
defects; and performing a second review step to review the defects
after the offset correction.
2. The method for reviewing the defects according to claim 1,
wherein the sets of the coordinates are derived from a defect
inspection apparatus.
3. The method for reviewing the defects according to claim 1,
wherein the anchor patterns are formed at corners of the dies
located at corners of the viewing fields.
4. The method for reviewing the defects according to claim 3,
wherein the offset correction is performed to calculate a deviation
between the anchor pattern and the origin point in the viewing
fields.
5. The method for reviewing the defects according to claim 1,
wherein the anchor patterns are formed at corners of the dies not
located at corners of the viewing fields.
6. The method for reviewing the defects according to claim 5,
wherein the offset correction is performed to calculate a deviation
between the sets of coordinates and the anchor patterns.
7. The method for reviewing the defects according to claim 1,
wherein the anchor patterns comprise a plurality of sub-patterns
arranged within, and at least a programmed defect is formed in one
of the sub-patterns.
8. The method for reviewing the defects according to claim 7,
wherein the programmed defect comprises a gap defect, a short-end
defect, or a bridge defect.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of and claims
the benefit of U.S. patent application Ser. No. 15/396,805, filed
Jan. 2, 2017.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] The present invention relates to a semiconductor structure
and a method for reviewing defects, and more particularly, to a
semiconductor structure involved in the method for reviewing
defects in manufactured semiconductor substrates.
2. Description of the Prior Art
[0003] A semiconductor device is formed after a semiconductor
substrate undergoes a plurality of manufacturing steps of
oxidization, film deposition, lithography, etching, etc. In the
semiconductor manufacturing, it is important to find defects
appearing during a manufacturing step in early phases and take
measures against the defects in order to ensure yield enhancement.
And thus defect inspection systems and defect review systems are
required.
[0004] Defect inspection detects particles, pattern anomalies, and
process-induced anomalies on wafers and reticles. The inspection
process typically only involves detecting defects on the
wafer/substrate and providing limited information such coordinates
indicating defect locations, number of defects, and sometimes
defect size. And typically detection results from the inspection
systems are fed to defect review systems. As the dimensions of
semiconductor devices decrease, detection of defects has become
necessary since even relatively small defects may cause unwanted
aberrations in the semiconductor devices.
[0005] Defect review is often used to provide more information
about individual defects than that which can be from the inspection
results. For instance, a defect review may be used to revisit the
defects detected on the wafer/substrate and to examine the defects
further. Defect review typically involves generating more detailed
information about the defects at a higher resolution.
[0006] It is concluded that defect inspection and defect review
systems are two significant means for semiconductor yield
management. Conventionally, as the defect locations is detected and
the coordinates of these defects are fed to the defect review
system, the substrate/wafer is aligned on the stage of the review
system and the coordinates are used by the defect review system to
find the defects. Therefore, alignments between the defect
inspection system and defect review system are important.
SUMMARY OF THE INVENTION
[0007] According to an aspect of the present invention, a
semiconductor structure is provided. The semiconductor structure
includes a wafer comprising a plurality of viewing fields defined
thereon, a plurality of dies defined by a scribe line formed in
each viewing field, a plurality of mark patterns formed in the
scribe line, and a plurality of anchor patterns respectively formed
in the review fields. More important, the anchor patterns are
different from the mark patterns.
[0008] According to an aspect of the present invention, a method
for reviewing defects is provided. The method for reviewing defects
includes following steps. A wafer and sets of coordinates locating
a plurality of defects formed on the wafer are received in a defect
review apparatus. Next, a plurality of viewing fields on the wafer
are identified and a plurality of origin points respectively in the
viewing fields are recognized in the defect review apparatus. And
each viewing field includes a plurality of dies formed therein.
Thereafter, a first review step is performed to review a plurality
of anchor patterns in the viewing fields, and followed by
performing an offset correction after the first review step to
re-locate the defects. Then a second review step is performed to
review the defects after the offset correction.
[0009] According to the semiconductor structure provided by the
present invention, the anchor patterns that are different from the
mark patterns are formed in the viewing fields and thus the first
reviewing step is performed to review the anchor patterns. The
offset correction therefore can be easily achieved to re-locate the
defects because the deviation between the origin points and the
anchor patterns or the deviation between the coordinates locating
the defects and the anchor patterns is easily obtained.
Accordingly, the second reviewing step is performed to review the
real defects with accurate and precise coordinates. And thus the
method for reviewing defects provided by the present invention
provides high working efficiency and an improved reliability.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a schematic drawing illustrating a semiconductor
structure provided by a preferred embodiment of the invention.
[0012] FIG. 2 is a schematic drawings illustrating a semiconductor
structure provided by another preferred embodiment of the
invention.
[0013] FIG. 3 is a schematic drawing illustrating the anchor
pattern provided by the preferred embodiments of the present
invention.
[0014] FIGS. 4-6 respectively illustrate SEM pictures of the
programmed defect formed in the anchor pattern.
[0015] FIG. 7 is a flow chart illustrating the method for reviewing
defects provided by a preferred embodiment of the present
invention.
[0016] FIG. 8 is a schematic drawing illustrating a step of the
method for reviewing defects provided by the preferred embodiment
of the present invention.
[0017] FIGS. 9-10 are schematic drawings respectively illustrating
a step subsequent to FIG. 8 according to different preferred
embodiments of the present invention.
DETAILED DESCRIPTION
[0018] In the following description, numerous specific details are
set forth, such as particular structures, components, materials,
dimensions, processing steps and techniques, in order to provide a
thorough understanding of the present invention. However, it will
be appreciated by one of ordinary skill in the art that the
invention may be practiced without these specific details. In other
instances, well-known structures or processing steps have been
described in detail in order to avoid obscuring the invention.
[0019] It will be understood that when an element is referred to as
being "formed" on another element, it can be directly or
indirectly, formed on the given element by growth, deposition,
etch, attach, connect, or couple. And it will be understood that
when an elements or a layer is referred to as being "on",
"connected to", or "coupled to" another element or layer, it can be
directly on, connected or coupled to the other element or layer or
intervening elements or layers may be present.
[0020] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements,
components, regions, layers and/or sections, these elements,
components, regions, layers and/or sections should not be limited
by these terms. These terms are only used to distinguish one
element, component, region, layer and/or section from another.
Thus, a first element, component, region, layer or section
discussed below could be termed a second element, component,
region, layer or section without departing from the teachings of
the disclosure.
[0021] Spatially relative terms, such as "beneath", "below",
"lower", "above", "upper", "in", "on" and the like, may be used
herein for ease of description to describe one element or feature's
relationship to another element (s) or feature (s) as illustrated
in the figures. It will be understood that spatially relative terms
are intended to encompass different orientations of the device in
use or operation in addition to the orientations depicted in the
figures. For example, if the device in the figures in turned over,
elements described as "below" or "beneath" can encompass both an
orientation of above and below. The device may be otherwise
oriented (rotated 90 degrees or at other orientations) and the
spatially relative descriptors used herein interpreted
accordingly.
[0022] The terminology used herein is for the purpose of describing
particular embodiments and is not intended to be limiting of the
inventions. As used herein, the singular form "a", "an" and "the"
are intended to include the plural forms as well, unless the
context clearly indicates otherwise.
[0023] Please refer to FIG. 1, which is a schematic drawing
illustrating a semiconductor structure provided by a first
preferred embodiment of the invention. According to the preferred
embodiment, a semiconductor structure 100 is provided. The
semiconductor structure 100 includes a wafer 102 and a plurality of
dies 104 defined by a scribe line 106. According to the preferred
embodiment, the wafer 102 generally refers to a substrate formed of
semiconductor material, non-semiconductor material, or any base
material on which processing is conducted to produce layers of
material, pattern features, and/or integrated circuits. The wafer
102 may include one or more layers formed thereon. For example but
not limited to, the layer may include a resist, a dielectric
material, a conductive material, or a semiconductor material. It
some embodiments of the present invention, the wafer 102 is
intended to encompass a wafer including all types such layer.
Furthermore, the layer(s) formed on the wafer 102 may be patterned
and thus patterned features are formed. Therefore the wafer 102 may
include the plurality of dies 104 defined by the scribe line 106,
and each die 104 includes the patterned features constructing
different types of devices. In some embodiments of the present
invention, the wafer 102 is intended to encompass a wafer on which
any type of device known in the art is being fabricated.
[0024] Please refer to the right side of FIG. 1, which includes an
enlarged view of the wafer 102. As shown in the right side of FIG.
1, the dies 104 are defined by the scribe line 106, and a plurality
of mark patterns 108 are formed in the scribe line 106. It is
noteworthy that the mark patterns 108 are immediately adjacent to
corners of the dies 104 as shown in FIG. 1. The mark patterns 108
are provided to mark the edge of the dies. Furthermore, the mark
patterns 108 can include alignment mark pattern in the
manufacturing processes. More important, the semiconductor
structure 100 includes a plurality of anchor patterns 110 formed in
the scribe line 106, and the anchor patterns 110 are different from
the mark patterns 108. As shown in FIG. 1, the anchor patterns 110
are formed in the scribe line 106 at a corner of the dies 104,
respectively. Typically, the mark patterns 108, the anchor patterns
110 and material patterns formed in the dies 104 are formed by
transferring patterns from a photomask in the photolithography
technology. Moreover, this process of transferring a pattern to the
wafer is repeated many times on different areas (referred to as
"shots" or "fields") of the wafer 102 during a mass production
process of, for example, manufacturing semiconductor chips. In some
embodiments of the preset invention, the anchor patterns 110 are
respectively formed at the corner of a die 104 located at a corner
of a shot/field, which will be identified as a viewing field by a
defect review apparatus and will be described in the following
description.
[0025] Please refer to FIG. 2, which is a schematic drawing
illustrating a semiconductor structure provided by a second
preferred embodiment of the invention. It is noteworthy that
elements the same in the first and second preferred embodiments are
designated by the same numerals, and details of those same elements
are omitted in the interest of brevity. The difference between the
first and second preferred embodiments is: the anchor patterns 110'
are respectively formed at the corner of a die 104 not located at a
corner of shot/field, which will be identified as a viewing field
by a defect review apparatus and will be described in the following
description.
[0026] Please refer to FIG. 3, which is a schematic drawing
illustrating the anchor pattern provided by the preferred
embodiments of the present invention. The anchor pattern 110/110'
can include a plurality of sub-patterns 112 arranged therein. As
mentioned above, there are many types of layers formed and
patterned on the wafer, and the layers are patterned to form the
sub-patterns 112 to construct the anchor pattern 110/110'. In some
embodiments of the present invention, the sub-patterns 112
respectively is a cell pattern including a plurality of insulating
patterns, a plurality of semiconductor patterns such as fin
patterns or gate line pattern, and/or a plurality of metal patterns
such wiring patterns. It is noteworthy that the aforementioned
patterns can be formed concurrently with those patterns formed
within the dies 104. More important, the anchor pattern 110/110'
includes at least a programmed defect 114a, 114b, 114c artificially
formed in one of the sub-patterns 112.
[0027] Please refer to FIGS. 4-6, which respectively illustrate a
scanning electron microscope (hereinafter abbreviated as SEM)
picture of the programmed defect formed in the anchor pattern. As
shown in FIG. 4, the programed defect can include a gap defect 114a
formed in the one of the sub-patterns 112. As shown in FIG. 5, the
programmed defect can include a short-end defect 114b formed in the
one of the sub-patterns 112. As shown in FIG. 6, the programmed
defect can include a bridge defect 114c formed in the one of the
sub-patterns 112. However, those skilled in the art would easily
realize that any types of defects can be artificially formed in the
sub-patterns 112.
[0028] It should be easily realized that in some embodiments of the
present invention, the mark patterns 108 and the anchor patterns
110/110' can include the same shape, and the difference between the
mark patterns 108 and the anchor patterns 110/110' is: the anchor
patterns 110/110' include the programmed defects 114a, 114b, or
114c while the mark patterns 108 include no programmed defects.
However, in still other embodiments of the present invention, the
anchor patterns 110/110' and mark patterns 108 can include
different shapes and/or different sizes.
[0029] Please refer to FIG. 7, which is a flowchart illustrating
the method for reviewing defects provided by a preferred embodiment
of the present invention. According to the method for reviewing
defects 20 provided by the preferred embodiment, a STEP 200 is
performed:
[0030] STEP 200: Receiving a semiconductor structure and sets of
coordinates locating a plurality of defects formed thereon in a
defect review apparatus
[0031] According to the preferred embodiment, a semiconductor
structure 100 as mentioned above is inspected using any suitable
defect inspection apparatus. The semiconductor structure 100 is
inspected in a defect inspection apparatus and thus a plurality of
defects may be detected and sets of coordinates locating those
defects are derived from the defect inspection apparatus. As
mentioned above, the semiconductor structure 100 includes the wafer
102, the plurality of dies 104 formed on the wafer 102 and defined
by the scribe line 106, the plurality of mark patterns 108, and the
plurality of anchor patterns 110/110'. More important, the anchor
patterns 110/110' respectively include at least a programmed defect
114a, 114b and/or 114c formed therein, therefore the set of
coordinates are derived to locate not only the real defect(s) in
the dies 104 but also to locate the programmed defects 114a, 114b
and/or 114c in the anchor patterns 110/110'. In other words, since
the anchor patterns 110/110' include the programmed defects 114a,
114b and/or 114c, it will be always detected and recognized in the
defect inspection apparatus.
[0032] The semiconductor structure 100/the wafer 102 is then
transferred to a defect review apparatus. In some embodiments of
the present invention, the defect review apparatus is preferably a
scanning electron microscope (SEM)-based defect review apparatus,
but not limited to this. The defect review apparatus receives the
semiconductor structure 100 and the set of coordinates locating the
defects from the defect inspection apparatus.
[0033] Please refer to FIG. 7 again. According to the method for
reviewing defects 20 provided by the preferred embodiment, a STEP
210 is performed:
[0034] STEP 210: Identifying a plurality of viewing fields on the
semiconductor structure and recognizing a plurality of origin
points respectively in the viewing fields in the defect review
apparatus, and each viewing field comprising a plurality of dies
formed therein
[0035] Please also refer to FIG. 8, which is a schematic drawing
illustrating the STEP 210 according to the first preferred
embodiment. As shown in FIG. 8, after receiving the semiconductor
structure 100 and the sets of coordinates locating the defects, a
plurality of viewing fields 120 are identified by the defect review
apparatus. As mentioned above, the viewing fields 120 are those
areas referred to as shots or fields defined in the
photolithography process. More important, the viewing fields 120
are areas/units that will be reviewed one by one in the defect
review apparatus. As shown in FIG. 8, each viewing field 120
includes a plurality of dies 104 formed therein. Furthermore, a
plurality of origin points 122 are recognized by the defect review
apparatus. In some embodiments of the present invention, the origin
points 122 can be the mark patterns 108. It should be understood
that the origin points 122 serves as alignment marks in both of the
defect inspection apparatus and the defect review apparatus such
alignment between the defect inspection apparatus and the defect
review apparatus is achieved and thus the coordinates locating the
defects are meaningful.
[0036] Please refer to FIG. 7 again. According to the method for
reviewing defects 20 provided by the preferred embodiment, a STEP
220 is performed:
[0037] STEP 220: Performing a first review step to review a
plurality of anchor patterns in the viewing fields
[0038] Please refer to FIGS. 9 and 10. According to the method for
reviewing 20 provided by the present invention, the first review
step is performed to review a plurality of anchor patterns
110/110'. In some embodiments of the present invention, the anchor
patterns 110 are formed at corners of the dies 104 located at
corners of the viewing fields 120. Preferably, in some embodiments
of the present invention, the anchor patterns 110 are formed at the
origin points as shown in FIG. 9. In those embodiments, the anchor
patterns 110 can be reviewed immediately after recognizing the
origin points 122. Still in some embodiments of the present
invention, the anchor patterns 110' are formed at corners of the
dies 104 not located at corners of the viewing fields 120 as shown
in FIG. 10. In those embodiments, the anchor patterns 110' can be
reviewed according to the coordinates locating the programmed
defects transferred from the defect inspection apparatus.
[0039] Please refer to FIG. 7 again. According to the method for
reviewing defects 20 provided by the preferred embodiment, a STEP
230 is performed:
[0040] STEP 230: Performing an offset correction after the first
review step to re-locating the plurality of defects
[0041] Please refer to FIGS. 9 and 10 again. According to the
method for reviewing 20 provided by the present invention, an
offset correction is performed after the first review step. As
mentioned above, in some embodiments of the present invention that
the anchor patterns 110 are formed at the origin points as shown in
FIG. 9. The offset correction is performed to calculate a deviation
between the anchor pattern 110 and the origin point 122 in the
viewing fields 120. The offset correction is easily accomplished
because the deviation between the origin points 122 and the anchor
patterns 110 can be easily obtained. Also as mentioned above, in
some embodiments of the present invention that the anchor patterns
120 are formed at corners of the dies 104 not located at corners of
the viewing fields 120 as shown in FIG. 10. The offset correction
is performed to calculate a deviation between the sets of
coordinates locating the programmed defects and the anchor patterns
110'. The offset correction is also easily accomplished because the
deviation between the anchor patterns 110' and the coordinates
locating the programmed defects can be easily obtained.
Accordingly, the defects are re-located according to the offset
correction.
[0042] It should be noted that in the conventional defect review
method, user's skill based on the user experience are always
required because deviation between the defects in the viewing
fields of the defect review apparatus and the coordinates locating
the defects transferred from the defect inspection apparatus may be
too large to accurately address the defects and thus user needs to
find some of the defects manually. And the offset correction cannot
be performed until at least some of the defects are found. The most
common problem for the aforementioned user-required procedure is
time consuming.
[0043] According to the method for review defect provided by the
present invention, the offset correction can be easily performed by
introducing the anchor patterns 110/110' including the programmed
defects 112: Since the anchor patterns 110/110' are formed at the
origin points or formed within the viewings, the deviation between
the anchor patterns 120 and the origin points 120 are easily
obtained. Or, the deviation between the anchor patterns 120 and the
coordinates derived from the inspection apparatus is easily
obtained. Thus, the time-consuming defect finding procedure is no
longer required. Furthermore, by introducing the anchor patterns
110/110', the offset correction can even be automatically performed
by the defect view apparatus without user.
[0044] Please refer to FIG. 7 again. According to the method for
reviewing defects 20 provided by the preferred embodiment, a STEP
240 is performed:
[0045] STEP 240: Performing a second review step to review the
defects after the offset correction
[0046] As mentioned above, the offset correction is performed to
re-locate the defects, and thereafter a second review steps is
performed in the defect review apparatus. Since the real defects
detected by the defect inspection apparatus are re-located
according to STEP 230 as mentioned above, the second review step is
performed easily to find out where the real defects are and they
are reviewed and analyzed to obtain greater details.
[0047] According to the semiconductor structure provided by the
present invention, the anchor patterns that are different from the
mark patterns are formed in the viewing fields and thus the first
reviewing step is performed to review the anchor patterns. The
offset correction can be easily achieved to re-locate the defects
because the deviation between the origin points and the anchor
patterns or the deviation between the coordinates locating the
defects and the anchor patterns is easily obtained. Therefore the
second reviewing step is performed to review the real defects with
accurate and precise coordinates. And thus the method for reviewing
defects provided by the present invention includes a high working
efficiency and an improved reliability.
[0048] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *