U.S. patent application number 15/606778 was filed with the patent office on 2018-11-29 for transistors with dissimilar square waffle gate patterns.
The applicant listed for this patent is STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.. Invention is credited to Vlastimil Kote, Adam Kubacak, Milan Lzicar, Milos Vacula, Patrik Vacula.
Application Number | 20180342594 15/606778 |
Document ID | / |
Family ID | 64401754 |
Filed Date | 2018-11-29 |
United States Patent
Application |
20180342594 |
Kind Code |
A1 |
Vacula; Patrik ; et
al. |
November 29, 2018 |
TRANSISTORS WITH DISSIMILAR SQUARE WAFFLE GATE PATTERNS
Abstract
The present disclosure is directed to a plurality of waffle gate
parallel transistors having a shared gate on a surface of a
semiconductor substrate. The shared gate has connected channels
that form a plurality of squares, lines of each of the squares over
the perimeter of a respective source or drain region of the
plurality of waffle gate parallel transistors. The shared gate
includes squares of a first size and shape and a second size and
shape. The squares having the first size and shape are each over a
respective source region and the squares having the second size and
shape are each over a respective drain region. Each of the squares
having a first size and shape share at least one side with one of
the squares having the second size and shape.
Inventors: |
Vacula; Patrik; (Prague,
CZ) ; Vacula; Milos; (Humenne, SK) ; Kote;
Vlastimil; (Bechlin, CZ) ; Kubacak; Adam;
(Prague, CZ) ; Lzicar; Milan; (Jinocany,
CZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. |
Prague |
|
CZ |
|
|
Family ID: |
64401754 |
Appl. No.: |
15/606778 |
Filed: |
May 26, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/41766 20130101;
H01L 29/78 20130101; H01L 29/66462 20130101; H01L 29/41758
20130101; H01L 29/42316 20130101; H01L 21/823418 20130101; H01L
29/4238 20130101; H01L 27/088 20130101; H01L 29/66477 20130101;
H01L 29/7786 20130101; H01L 29/0696 20130101; H01L 21/823456
20130101 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 27/088 20060101 H01L027/088; H01L 29/06 20060101
H01L029/06; H01L 29/40 20060101 H01L029/40; H01L 29/66 20060101
H01L029/66; H01L 29/778 20060101 H01L029/778 |
Claims
1. A device, comprising: a semiconductor layer having a first side;
a first source region and a first drain region in the semiconductor
layer and adjacent to the first side; and a gate over the first
side of the semiconductor layer, the gate including a first frame
on the first side at lateral boundaries of the first source region
and a second frame on the first side at lateral boundaries of the
first drain region, the first frame having a first opening directly
over the first source region, the first opening having a first area
on the first side, and the second frame having a second opening
directly over the first drain region, the second opening having a
second area on the first side, the first area being a different
size than the second area, wherein a first channel path in the
semiconductor layer selectively couples the first source region to
the first drain region and wherein a length of the first channel
path equals the sum of a first length in the first source region, a
second length in the first drain region, and a third length between
the first source region and the first drain region, the first
length being less than the third length, and the third length being
less than the second length.
2. The device of claim 1 wherein the gate includes a line that
forms at least a portion of one side of the first frame and at
least a portion of one side of the second frame.
3. The device of claim 1 wherein the first area is smaller than the
second area.
4. The device of claim 1, further comprising: a second source
region and a second drain region in the semiconductor layer and
adjacent to the first side, the gate including a third frame on the
first side at lateral boundaries of the second source region and a
fourth frame on the first side at lateral boundaries of the second
drain region, the third frame having a third opening directly over
the second source region, the third opening having a third area on
the first side, and the fourth frame having a fourth opening
directly over the second drain region, the fourth opening having a
fourth area on the first side, the third area being a different
size than the fourth area.
5. The device of claim 4 wherein the first area is the same size as
the third area and the second area is the same size as the fourth
area.
6. The device of claim 4 wherein the gate includes: a first line
that forms at least a portion of a first side of the first frame
and at least a portion of a first side of the second frame; a
second line that forms at least a portion of a second side of the
first frame and at least a portion of a first side of the fourth
frame; and a third line that forms at least a portion of a second
side of the second frame and at least a portion of a first side of
the third frame.
7. The device of claim 4, further comprising: a first interconnect
and a second interconnect, the first interconnect electrically
coupling the first source region to the second source region, and
the second interconnect electrically coupling the first drain
region to the second drain region.
8. The device of claim 1 wherein the semiconductor layer has a
second side orthogonal to the first side and a third side
orthogonal to the first side and the second side, a normal vector
from the first frame not being parallel with a normal vector from
the second or third sides of the semiconductor layer.
9.-10. (canceled)
11. The device of claim 1, further comprising: a second source
region in the semiconductor layer and adjacent to the first side,
the gate including a third frame on the first side at lateral
boundaries of the second source region, the third frame having a
third opening directly over the second source region, the third
opening having a third area on the first side, and a second channel
path selectively couples the second source region and the first
drain region.
12. A system, comprising: a semiconductor layer having a first
side; a first transistor including a first source region, a first
drain region, and a first gate portion of a gate, the first gate
portion extending lengthwise in a first direction, the first source
and first drain regions being formed in the semiconductor layer,
and the gate being formed adjacent to the first side of the
semiconductor layer; a second transistor including a second source
region, a second drain region, and a second gate portion of the
gate, the second source and second drain regions being formed in
the semiconductor layer, the second gate portion extending
lengthwise in the first direction and being aligned with the first
gate portion; a third transistor including the first source region,
the second drain region, and a third gate portion of the gate, the
third gate portion extending lengthwise in a second direction
transverse to the first direction; and a fourth transistor
including the second source region, the first drain region, and a
third gate portion of the gate, the fourth gate portion extending
lengthwise in a third direction transverse to the first direction
and parallel to, and not aligned with, the second direction the
first and second source regions each have a first area on the first
side and the first and second drain regions each have a second area
on the first side, the first area being not equal to the second
area.
13. The system of claim 12 wherein the first area is smaller than
the second area.
14. The system of claim 13 wherein the first source region has
dimensions and the second source region has dimensions equal to the
dimensions of the first source region and the first drain region
has dimensions and the second drain region has dimensions equal to
the dimensions of the first drain region.
15. The system of claim 12 wherein the first source region is
electrically coupled to the second source region and the first
drain region is electrically coupled to second drain region.
16. The system of claim 15, further comprising: a first set of
interconnects, one of the first set of interconnects being coupled
to the first source region at a center of the first source region
and one of the first set of interconnects being coupled to the
second source region at a center of the second source region; and a
second set of interconnects, one of the second set of interconnects
being coupled to the first drain region at a center of the first
drain region and one of the second set of interconnects being
coupled to the second drain region at a center of the second drain
region.
17.-20. (canceled)
21. The device of claim 7 wherein the source interconnect is
parallel to the drain interconnect and extends in a straight line
from a first source terminal to a second source terminal.
22. The device of claim 7 wherein the first interconnect has a
first terminal, a second terminal, a first line, and a second line,
the first line coupled between the first terminal and the second
line, the second line coupled between the first line and the second
terminal, the first line being orthogonal to the second line, and
wherein the second interconnect has a third terminal, a fourth
terminal, a third line, and a fourth line, the third line coupled
between the third terminal and the fourth line, the fourth line
coupled between the third line and the fourth terminal, the third
line being orthogonal to the fourth line.
23. The device of claim 9 wherein the first area is less than a
quarter of the second area.
24. The device of claim 1 wherein the first frame and the second
frame each have a rhombus shape.
25. The device of claim 1 wherein the gate and the semiconductor
layer are components of a metal-oxide-semiconductor
field-effect-transistor.
26. A transistor device, comprising: a substrate; a semiconductor
layer on the substrate; a plurality of source regions and a
plurality of drain regions in the semiconductor layer, each one of
the plurality of source regions being a different size than each
one of the plurality of drain regions; and a gate on the
semiconductor layer, the gate being adjacent to portions of the
semiconductor layer at lateral boundaries of each one of the
plurality of source regions and each one of the plurality of drain
regions, wherein: the plurality of source regions includes a first
source region having first and second sides that are opposite sides
of the first source region, the plurality of drain regions includes
a first drain region and a second drain region, the first drain
region is part of a first transistor that includes the first source
region and a first channel region extending between the first drain
region and the first side of the first source region, the second
drain region is part of a second transistor that includes the first
source region and a second channel region extending between the
second drain region and the second side of the first source region,
and the first and second drain regions are staggered with respect
to a center of the first source region.
27. The transistor device of claim 26, wherein each one of the
plurality of source regions is smaller than each one of the
plurality of drain regions.
28. The transistor device of claim 27, wherein each one of the
plurality of source regions is adjacent to four drain regions of
the plurality of drain regions, and each one of the plurality of
drain regions is adjacent to four source regions of the plurality
of source regions.
29. The transistor of device claim 26, further comprising: a first
plurality of interconnections and a second plurality of
interconnections, the first plurality of interconnections
electrically coupling each one of the plurality of source regions
together and the second plurality of interconnections electrically
coupling each one of the plurality of drain regions together.
30. The transistor device of claim 26, wherein: the plurality of
source regions includes a second source region; the first drain
region has first and second sides that are opposite sides of the
first drain region; the first side of the first drain region is
immediately adjacent to the first channel region of the first
transistor; the second source region is part of a third transistor
that includes the first drain region and a third channel region
extending between the second source region and the second side of
the first drain region, and the first and second source regions are
staggered with respect to a center of the first drain region.
31. The system of claim 12, wherein a first channel path in the
semiconductor layer selectively couples the first source region to
the first drain region and wherein a length of the first channel
path equals the sum of a first length in the first source region, a
second length in the first drain region, and a third length between
the first source region and the first drain region, the first
length being less than the third length, and the third length being
less than the second length
Description
BACKGROUND
Technical Field
[0001] The present disclosure is directed to a plurality of
transistors adjacent to one another with a shared gate and, in
particular, to gate patterns for shared gate transistors.
Description of the Related Art
[0002] When activated, a transistor has a non-zero resistance
(R.sub.DSon) measured across the source and drain terminals. This
causes power to be lost across the transistor when it is
conducting, potentially leading to overheating or corrupting the
signal from the signal being attenuated in the transistor. Thus a
transistor may be limited to handling lower voltages or low signal
quality applications due to a high value of R.sub.DSon. The
transistor layout can be modified to decrease R.sub.DSon to improve
transistor performance, such as by creating source/drain asymmetry.
For example, R.sub.DSon can be decreased by increasing a length of
a drain region that charge carriers flow through to be greater than
a length of a source region that charge carriers flow through.
[0003] Parallel transistor layouts can also be used to decrease
R.sub.DSon for activated transistors and to increase power capacity
of a transistor with a fixed footprint. In a parallel transistor
layout, the source, gate, and drain of each transistor are
electrically coupled to the respective source, gate, and drain of
the remaining transistors in a group of parallel transistors. With
parallel transistors, each of the transistors is performance
matched to the other transistors because the system is limited by
the lowest performing transistor. The parallel transistors can be
isolated from one another in adjacent substrates or formed in a
common substrate without any isolation. One solution in which the
parallel transistors are not isolated from each other is with
standard gate parallel transistors having finger interconnects.
[0004] FIG. 1 is a perspective cut away view of a high electron
mobility transistor (HEMT) device that includes a plurality of
standard gate parallel transistors 100. A substrate 102 is covered
with a first layer 104, which is covered with a second layer 106.
In an example of an HEMT device, the substrate 102 is a
semiconductor substrate, such as an aluminum-gallium nitride
(AlGaN), or an insulating substrate, such as sapphire
(Al.sub.2O.sub.3) or diamond (C), the first layer 104 is a
semiconductor layer of gallium nitride (GaN), and the second layer
106 is a semiconductor layer of aluminum gallium nitride (AlGaN).
The first and second layers 104, 106 are of different materials
having different band gaps, thereby forming a heterojunction in
which majority charge carriers accumulate in the first layer 104
adjacent to the second layer 106.
[0005] A source region 108 is formed in the first layer 104 with a
source interconnect finger 110 coupled to the source region 108 by
a conductive via 112. One end of the conductive via 112 is embedded
in the first layer 104 at the source region 108, extends through
the second layer 106, and connects to the source interconnect
finger 110 at a via terminal 114, which is an enlarged portion of
the source interconnect finger 110. The source interconnect finger
110 couples the source region 108 with other source regions in the
plurality of standard gate parallel transistors 100.
[0006] Adjacent to the source region 108 is a drain region 116
formed in the first layer 104. A drain interconnect finger 118 is
coupled to the drain region 116 by a conductive via 120. One end of
the conductive via 120 is embedded in the first layer 104 at the
drain region 116, extends through the second layer 106, and
connects to the drain interconnect finger 118. The drain
interconnect finger 118 couples the drain region 116 with other
drain regions in the plurality of standard gate parallel
transistors 100. The drain interconnect finger 118 extends in a
parallel direction to the source interconnect finger 110.
[0007] On the second layer 106, between the source region 108 and
the drain region 116, is a gate 122. In the standard gate parallel
transistors 100, the gate 122 extends in a parallel direction to
the source interconnect finger 110 and the drain interconnect
finger 118. To improve R.sub.DSon, a portion of the gate 122
between the source region 108 and the drain region 116 is
positioned closer to the conductive via 112 in the source region
108 than the conductive via 120 in the drain region 116.
[0008] The gate 122 controls the conductivity of the first layer
104 from the source region 108 to the drain region 116 by applying
a voltage potential to the gate 122. A first channel is activated
by a voltage greater than a threshold voltage being applied to the
gate 122. When activated, the first channel forms between the
source region 108 and the drain region 116, permitting charge
carriers to flow between the source region 108 and the drain region
116.
[0009] Adjacent to the source region 108 is a drain region 124
formed in the first layer 104. A drain interconnect finger 126 is
coupled to the drain region 124 by a conductive via 128. One end of
the conductive via 128 is embedded in the first layer 104 at the
drain region 124, extends through the second layer 106, and
connects to the drain interconnect finger 126. The drain
interconnect finger 126 couples the drain region 124 with other
drain regions in the plurality of standard gate parallel
transistors 100, including the drain region 116. The drain
interconnect finger 126 extends in a parallel direction to the
source interconnect finger 110.
[0010] On the second layer 106 between the source region 108 and
the drain region 124 is a continuation of the gate 122. The
continuation of the gate 122 extends in a parallel direction to the
source interconnect finger 110 and the drain interconnect finger
126. To improve R.sub.DSon, a portion of the gate 122 between the
source region 108 and the drain region 124 is positioned closer to
the conductive via 112 in the source region 108 than the conductive
via 128 in the drain region 324.
[0011] The gate 122 controls the conductivity of the first layer
104 from the source region 108 to the drain region 124 by applying
the voltage potential to the gate 122. A second channel is
activated by a voltage greater than a threshold voltage being
applied to the gate 122. When activated, the second channel forms
from the source region 108 to the drain region 116, permitting
charge carriers to flow between the source region 108 and the drain
region 116.
[0012] Although not shown, the source interconnect finger 110 can
be coupled to one or more other source interconnect fingers by a
source master interconnect. Additionally, the drain interconnect
finger 118 and the drain interconnect finger 126 can be coupled to
each other or to one or more other drain interconnect fingers by a
drain master interconnect, also not shown.
[0013] A first transistor of the plurality of standard gate
parallel transistors 100 includes the source region 108, the drain
region 116, and the gate 122. A second transistor of the plurality
of standard gate parallel transistors 100 includes the source
region 108, the drain region 124, and the gate 122. The first and
second transistors are mirror images along the source region 108.
Additional transistors are formed adjacent to the first transistor
using the same source interconnect finger 110, drain interconnect
finger 118, and gate 122, but with different conductive vias to the
first layer 104. Additional transistors are formed adjacent to the
second transistor using the same source interconnect finger 110,
drain interconnect finger 126, and gate 122, but with different
conductive vias to the first layer 104.
[0014] FIG. 2 is a top cut away view of the standard gate parallel
transistors 100 of FIG. 1. Depicted are six parallel transistors.
Each conductive via in the source interconnect finger 110 is
coupled to a source region that is shared between two transistors.
One transistor extends to the left of the source region to couple
to a drain region at a conductive via from the drain interconnect
finger 118. The other transistor of the shared source extends to
the right of the source region to couple to a drain region at a
conductive via from the drain interconnect finger 126. There are
three rows of drain-source-drain regions marked by the three rows
of conductive vias from the top of the figure to the bottom of the
figure. Three rows of pairs of transistors equal six transistors.
The pattern repeats, as can be appreciated from the additional rows
of gates in which additional transistors can be formed using the
drain regions as shared drain regions similar to the source regions
depicted.
[0015] FIG. 3 is a perspective cut away view of an HEMT device that
includes a plurality of square waffle gate parallel transistors
300. A substrate 302 is covered with a first layer 304, which is
covered with a second layer 306. A source region 308 is formed in
the first layer 304 with a source interconnect finger 310 coupled
to the source region 308 by a conductive via 312. One end of the
conductive via 312 is embedded in the first layer 304 at the source
region 308, extends through the second layer 306, and connects to
the source interconnect finger 310 at a via terminal 314, an
enlarged portion of the source interconnect finger 310. The source
interconnect finger 310 couples the source region 308 with other
source regions in the plurality of square waffle gate parallel
transistors 300.
[0016] Adjacent to the source region 308 is a drain region 316
formed in the first layer 304. A drain interconnect finger 318 is
coupled to the drain region 316 by a conductive via 320. One end of
the conductive via 320 is embedded in the first layer 304 at the
drain region 316, extends through the second layer 306, and
connects to the drain interconnect finger 318. The drain
interconnect finger 318 couples the drain region 316 with other
drain regions in the plurality of square waffle gate parallel
transistors 300. The drain interconnect finger 318 extends in a
parallel direction to the source interconnect finger 310.
[0017] On the second layer 306 between the source region 308 and
the drain region 316 is a gate 322. In the square waffle gate
parallel transistors 300, the gate 322 extends in a crisscrossing
pattern with lines perpendicular to each other and at 45 degrees
off of the source interconnect finger 310 and the drain
interconnect finger 318. The gate 322 is spaced an equal distance
from the conductive via 312 in the source region 308 and the
conductive via 320 in the drain region 316, forming equally sized
squares around the source region 308 and the drain region 316.
[0018] Adjacent to the source region 308 is a drain region 324
formed in the first layer 304. A drain interconnect finger 326 is
coupled to the drain region 324 by a conductive via 328. One end of
the conductive via 328 is embedded in the first layer 304 at the
drain region 324, extends through the second layer 306, and
connects to the drain interconnect finger 326. The drain
interconnect finger 326 couples the drain region 324 with other
drain regions in the plurality of square waffle gate parallel
transistors 300, including the drain region 316. The drain
interconnect finger 326 extends in a parallel direction to the
source interconnect finger 310.
[0019] On the second layer 306 between the source region 308 and
the drain region 324 is a continuation of the crisscrossing pattern
of the gate 322. The gate 322 is spaced an equal distance from the
conductive via 312 in the source region 308 and the conductive via
328 in the drain region 324, forming equally sized squares around
the source region 308 and the drain region 324.
[0020] The source interconnect finger 310 can be coupled to one or
more other source interconnect fingers by a source master
interconnect 332. Additionally, the drain interconnect finger 318
and the drain interconnect finger 326 can be coupled to each other
or to one or more other drain interconnect fingers by a drain
master interconnect 330.
[0021] A first transistor of the plurality of square waffle gate
parallel transistors 300 includes the source region 308, the drain
region 316, and the gate 322. A second transistor of the plurality
of square waffle gate parallel transistors 300 includes the source
region 308, the drain region 324, and the gate 322. The first and
second transistors are mirror images along the source region 308.
Additional transistors are formed diagonal to the first transistor
using the same source interconnect finger 310, drain interconnect
finger 318, and gate 322, but with different conductive vias to the
first layer 304. Additional transistors are formed diagonal to the
second transistor using the same source interconnect finger 310,
drain interconnect finger 326, and gate 322, but with different
conductive vias to the first layer 304.
[0022] FIG. 4 is a top view of the square waffle gate parallel
transistors 300 of FIG. 3, with FIG. 3 showing the cut away at the
cross section line AA of FIG. 4. Depicted in FIG. 4 are twenty-four
parallel transistors. Each conductive via is coupled to a shared
source region or a shared drain region. The shared source regions
and the shared drain regions may be shared with two or more
transistors. As discussed above, the first transistor of the
plurality of square waffle gate parallel transistors 300 includes
the source region 308, the drain region 316, and the gate 322 and
the second transistor of the plurality of square waffle gate
parallel transistors 300 includes the source region 308, the drain
region 324, and the gate 322, with the first and second transistors
sharing the source region 308. The source region 308 is also shared
with a third transistor of the plurality of square waffle gate
parallel transistors 300 that includes the source region 308, a
drain region 402, and the gate 322. Thus the source region 308 is
shared between the first, second, and third transistors of the
plurality of square waffle gate parallel transistors 300.
Similarly, the drain region 324 is a shared drain region. The drain
region 324 is one terminal of the second transistor of the
plurality of square waffle gate parallel transistors 300, and also
is shared with a fourth transistor that includes a source region
404, the drain region 324, and the gate 322. The pattern continues
throughout so that there are three transistors per row and three
transistors per column in plurality of square waffle gate parallel
transistors 300.
[0023] FIG. 5 is a side cut away view of the square waffle gate
parallel transistors 300 of FIG. 3, taken at the cross section line
AA of FIG. 4. FIG. 5 depicts the first and second transistors as
discussed above. In addition, FIG. 5 depicts a top surface of the
second layer 306 covered by an encapsulant 502 that provides
electrical insulation between the components. The encapsulant 502
covers the gate 322, the conductive vias 312, 320, 328, the source
and drain interconnect fingers 310, 318, 326, and the source and
drain master interconnects 330, 332.
[0024] The gate 322 controls the conductivity of the first layer
304 from the source region 308 to the drain region 316 by applying
a voltage potential to the gate 322. A first channel 504 is
activated by a voltage greater than a threshold voltage being
applied to the gate 322. When activated, the first channel 504
forms from the source region 308 to the drain region 316,
permitting charge carriers to flow between the source region 308
and the drain region 316.
[0025] The gate 322 also controls the conductivity of the first
layer 304 from the source region 308 to the drain region 324 by
applying the voltage potential to the gate 322. A second channel
506 is activated by a voltage greater than a threshold voltage
being applied to the gate 322. When activated, the second channel
506 forms from the source region 308 to the drain region 324,
permitting charge carriers to flow between the source region 308
and the drain region 324.
[0026] Unlike the plurality of standard gate parallel transistors
100, the square waffle gate parallel transistors 300 have channels
with the gate spaced equally between the respective source and the
drain regions. With the square waffle gate parallel transistors
300, it is not possible to move a conductive via to change a
channel length uniformly for all transistors. Movement of the
conductive vias in one direction causes movement in an opposite
direction for adjacent transistors. This causes a performance
imbalance in the parallel transistors, limiting performance of the
square waffle gate parallel transistors 300. Because of the
symmetry of the plurality of square waffle gate parallel
transistors 300, these devices are typically unsuitable for high
voltage devices, such as those higher than 3 volts, for example.
Thus, what is needed is a device that allows for matched parallel
transistors with non-uniform sized source and drain regions.
BRIEF SUMMARY
[0027] The present disclosure is directed to a gate pattern for a
plurality of adjacent parallel transistors with unequal source and
drain areas. Each transistor of the plurality of adjacent parallel
transistors has a gate that has a first frame which extends over a
perimeter around lateral edges of a source region and a second
frame that extends over a perimeter of lateral edges of a drain
region. The area of the source region is a different size than the
area of the drain region, forming a dissimilar square waffle gate
pattern. A system including the discussed devices and a method of
forming a final package is also disclosed.
[0028] In some embodiments, a first transistor of the plurality of
adjacent parallel transistors is adjacent to the second transistor
of the plurality of adjacent parallel transistors. The first and
second transistors have gates that are electrically coupled
together. Furthermore, the first transistor has a portion of the
gate around the source region shared with a portion of the gate
around the drain region of the second transistor. In some
embodiments, the first transistor also has a portion of the gate
around the drain region shared with a portion of the gate around
the source region of the second transistor.
[0029] In some embodiments, a portion of the first frame is common
with a portion of the second frame. The common portion of the first
and second frames is a portion of the gate that controls a
semiconductor channel from the source to drain region of the first
transistor.
[0030] In some embodiments, one source region in the plurality of
adjacent parallel transistors is shared between a first group of
four transistors and one drain region in the plurality of adjacent
parallel transistors is shared between a second group of four
transistors, with one transistor in the first and second groups. In
an alternate embodiment, a group of four transistors includes a
first source region shared by a first transistor and a second
transistor, a first drain region shared by the first transistor and
a third transistor, a second source region shared by the third
transistor and a fourth transistor, and a second drain region
shared by the second transistor and the fourth transistor.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0031] FIG. 1 is a perspective cut away view of a high electron
mobility transistor (HEMT) device that includes a plurality of
standard gate parallel transistors 100.
[0032] FIG. 2 is a top cut away view of the standard gate parallel
transistors 100 of FIG. 1.
[0033] FIG. 3 is a perspective cut away view of an HEMT device that
includes a plurality of square waffle gate parallel transistors
300.
[0034] FIG. 4 is a top view of the square waffle gate parallel
transistors 300 of FIG. 3, with FIG. 3 showing the cut away at the
cross section line AA of FIG. 4.
[0035] FIG. 5 is a side cut away view of the square waffle gate
parallel transistors 300 of FIG. 3, taken at the cross section line
AA of FIG. 4.
[0036] FIG. 6 is a perspective cut away view of an HEMT device that
includes a plurality of dissimilar square waffle gate parallel
transistors 600.
[0037] FIG. 7 is a top view of the plurality of dissimilar square
waffle gate parallel transistors 600 of FIG. 6.
[0038] FIG. 8 is a side cut away view of the plurality of
dissimilar square waffle gate parallel transistors 600 of FIG. 6,
taken at the cross section line BB of FIG. 7.
[0039] FIG. 9 is a top view of the plurality of dissimilar square
waffle gate parallel transistors 600 having an alternate
interconnect finger pattern.
[0040] FIG. 10 is a top view of an alternate embodiment of the gate
pattern with a different position and ratio of source to drain
areas.
[0041] FIG. 11 is a top view of an alternate embodiment of the gate
pattern with non-square frames.
[0042] FIG. 12 is a top view of a plurality of dissimilar square
waffle gate parallel transistors, showing the dimension variables
of the gate pattern frames.
[0043] FIGS. 13A-13G are various embodiments showing different
source to gate to drain ratios.
[0044] FIG. 14 is an alternate embodiment of the plurality of
dissimilar square waffle gate parallel transistors, showing a cross
section of a device with MOSFET based transistors.
DETAILED DESCRIPTION
[0045] In the following description, certain specific details are
set forth in order to provide a thorough understanding of various
embodiments of the disclosure. However, one skilled in the art will
understand that the disclosure may be practiced without these
specific details. In other instances, well-known structures
associated with electronic components and fabrication techniques
have not been described in detail to avoid unnecessarily obscuring
the descriptions of the embodiments of the present disclosure.
[0046] Unless the context requires otherwise, throughout the
specification and claims that follow, the word "comprise" and
variations thereof, such as "comprises" and "comprising," are to be
construed in an open, inclusive sense; that is, as "including, but
not limited to."
[0047] Reference throughout this specification to "one embodiment"
or "an embodiment" means that a particular feature, structure or
characteristic described in connection with the embodiment is
included in at least one embodiment. Thus, the appearances of the
phrases "in one embodiment" or "in an embodiment" in various places
throughout this specification are not necessarily all referring to
the same embodiment. Furthermore, the particular features,
structures, or characteristics may be combined in any suitable
manner in one or more embodiments.
[0048] As used in this specification and the appended claims, the
singular forms "a," "an," and "the" include plural referents unless
the content clearly dictates otherwise. It should also be noted
that the term "or" is generally employed in its sense including
"and/or" unless the content clearly dictates otherwise.
[0049] As used in the specification and appended claims, the use of
"correspond," "corresponds," and "corresponding" is intended to
describe a ratio of or a similarity between referenced objects. The
use of "correspond" or one of its forms should not be construed to
mean the exact shape or size.
[0050] Throughout the specification, the term "layer" is used in
its broadest sense to include a thin film, a cap, or the like, and
one layer may be composed of multiple sub-layers.
[0051] Specific embodiments of transistors with a dissimilar square
waffle gate pattern are described herein; however, the present
disclosure and the reference to certain materials, dimensions, and
the details and ordering of processing steps are exemplary and
should not be limited to those shown.
[0052] The present disclosure is generally directed to transistor
gate layouts, such as those shown in the perspective cut away view
of FIG. 6. Dissimilar square waffle gate parallel transistors have
a gate above a semiconductor layer. The gate forms a plurality of
first frames having a first size and a plurality of second frames
having a second size. The first and second frames are formed above
the semiconductor layer and the lines of the frames define
boundaries in source and drain regions in the semiconductor
layer.
[0053] FIG. 6 is a perspective cut away view of a high electron
mobility (HEMT) device that includes a plurality of dissimilar
square waffle gate parallel transistors 600. A substrate 602 is
covered with a first layer 604, which is covered with a second
layer 606. In some embodiments, the substrate 602 and the layers
604, 606 are part of an HEMT. In one of these embodiments, the
substrate 602 is aluminum gallium nitride (AlGaN), sapphire
(Al.sub.2O.sub.3) or diamond (C), the first layer 604 is gallium
nitride (GaN), and the second layer 606 is AlGaN. The first and
second layers 604, 606 are of different materials having different
band gaps, thereby forming a heterojunction in which majority
charge carriers accumulate in the first layer 604 adjacent to the
second layer 606. Other embodiments include other transistor types.
Other transistor types may follow the same three layer structure as
discussed above or may have a different number or type of
layers.
[0054] A source region 608 is formed in the first layer 604. The
source region 608 is one terminal of one of the plurality of
dissimilar square waffle gate parallel transistors 600. In some
embodiments, the source region 608 is defined by a frame 609 around
the source region 608.
[0055] Coupled to the source region 608 is a source interconnect
finger 610 coupled to the source region 608 by a conductive via
612. The conductive via 612 passes through the second layer 606 and
terminates at a first end in the first layer 604. In other
embodiments other connectors are used in place of the conductive
via 612, such as a contact pad. The conductive via 612 terminates
at a second end in the source interconnect finger 610 at a via
terminal 614. The via terminal 614 is an enlarged portion of the
source interconnect finger 610 that couples the source interconnect
finger 610 to the conductive via 612. The source interconnect
finger 610 is a conductive line connecting source regions in the
plurality of dissimilar square waffle gate parallel transistors 600
together with respective conductive vias and via terminals.
[0056] Adjacent to the source region 608 is a drain region 616
formed in the first layer 604. The drain region 616 is a second
terminal of one of the plurality of dissimilar square waffle gate
parallel transistors 600. In some embodiments, the drain region 616
is defined by a frame 617 around the drain region 616.
[0057] Coupled to the drain region 616 is a drain interconnect
finger 618 coupled to the drain region 616 by a conductive via 620.
The conductive via 620 passes through the second layer 606 and
terminates at a first end in the first layer 604. In other
embodiments other connectors are used in place of the conductive
via 620, such as a contact pad. The conductive via 620 terminates
at a second end in the drain interconnect finger 618 at a via
terminal. The via terminal is an enlarged portion of the drain
interconnect finger 618 that couples the drain interconnect finger
618 to the conductive via 620. The drain interconnect finger 618 is
a conductive line connecting drain regions in the plurality of
dissimilar square waffle gate parallel transistors 600 together
with respective conductive vias and via terminals. In one
embodiment the drain interconnect finger 618 extends in a parallel
direction to the source interconnect finger 610.
[0058] On the second layer 606 between the source region 608 and
the drain region 616 is a gate 622. In the plurality of dissimilar
square waffle gate parallel transistors 600, the gate 622 extends
across the second layer 606 in a repeating pattern with lines 623a,
623b forming small frames 630 around the source regions and large
frames 632 around the drain regions. In an alternative embodiment,
the repeating pattern forms small frames around the drain regions
and large frames around the source regions. In one embodiment the
frames 630, 632 are on the second layer 606 at lateral boundaries
of the source region 608 and the drain region 616, with an opening
directly over the source region 608 and the drain region 616. Each
one of the small frames 630 are adjacent to four large frames 632
and each one of the large frames 632 are adjacent to four small
frames 630, except at the perimeter of the pattern in which one or
more sides of each frame are not adjacent to another frame. Due to
the size disparity of the frames, each large frame 632 is also
adjacent to four other large frames 632, except at the perimeter of
the pattern in which one or more sides of each frame are not
adjacent to another frame.
[0059] In some embodiments, each of the frames 630, 632 is
rectangular such that each line of the line 623a, 623b of the gate
622 is parallel or perpendicular to every other one of lines 623a,
623b. In an alternate embodiment, each of the frames 630, 632 is a
parallelogram such that each line of the gate 622 is parallel to a
first group of lines 623a or a second group of lines 623b, the
first group of lines 623a not parallel or perpendicular to the
second group of lines 623b. In yet another embodiment, each line of
the gate 622 is parallel to one of the lines 623a, 623b of the gate
622 and not parallel to one of the lines 623a, 623b of the gate
622.
[0060] The source interconnect finger 610 and the drain
interconnect finger 618 are in a first plane parallel to a second
plane in which the gate 622 resides. The source interconnect finger
610 and the drain interconnect finger 618 extend at a different
angle within the first plane than the angle of each line of the
gate 622 within the second plane, the angles measured around an
axis tangent to the planes. In an alternate embodiment, the source
interconnect finger 610 and the drain interconnect finger 618 are
at the same angle within the first plane as the angle of the first
group of lines 632a of the gate 622 in the second plane. In some
embodiments the source interconnect finger 610 and the drain
interconnect finger 618 are in different planes parallel to each
other. And in some embodiments portions of the source interconnect
finger 610 and the drain interconnect finger 618 are in the first
plane, and portions of the source interconnect finger 610 and the
drain interconnect finger 618 are in a third plane parallel to the
first plane. In some embodiments, the source interconnect finger
610 and the drain interconnect finger 618 are parallel to an edge
of the die. In some embodiments, at least one of the lines 623a,
623b of the gate 622 is parallel to an edge of the die.
[0061] In the embodiment shown in FIG. 6 the gate 622 is not spaced
an equal distance from the conductive via 612 in the source region
608 as the conductive via 620 in the drain region 616. Due to
source/drain asymmetry, R.sub.DSon for the plurality of dissimilar
square waffle gate parallel transistors 600 is lower than the
plurality of standard gate parallel transistors 100 with an
equivalent die footprint and is also lower than the plurality of
square waffle gate parallel transistors 300 with an equivalent die
footprint.
[0062] Alternatively, for a fixed R.sub.DSon, the plurality of
dissimilar square waffle gate parallel transistors 600 has a
smaller die footprint than the plurality of standard gate parallel
transistors 100 and also has a smaller die footprint than the
plurality of square waffle gate parallel transistors 300.
[0063] In some embodiments, the source/drain asymmetry also
provides for a higher voltage tolerance by the plurality of
dissimilar square waffle gate parallel transistors 600 compared to
the plurality of standard gate parallel transistors 100 and the
plurality of square waffle gate parallel transistors 300. For
example, the plurality of dissimilar square waffle gate parallel
transistors 600 may be suitable for applications up to 20 volts to
1000 volts, depending on the transistor technology.
[0064] Adjacent to the source region 608 on a side opposite from
the drain region 616 is a drain region 624 formed in the first
layer 604. The drain region 624 is a second terminal of one of the
plurality of dissimilar square waffle gate parallel transistors
600. The drain region 624 is defined by doping levels of the first
layer 604 in some embodiments. In other embodiments, the drain
region 624 is defined by a frame 625 around the drain region
624.
[0065] Coupled to the drain region 624 is a drain interconnect
finger 626 coupled to the drain region 624 by a conductive via 628.
The conductive via 628 passes through the second layer 606 and
terminates at a first end in the first layer 604. In other
embodiments other connectors are used in place of the conductive
via 628, such as a contact pad. The conductive via 628 terminates
at a second end in the drain interconnect finger 626 at a via
terminal. The via terminal is an enlarged portion of the drain
interconnect finger 626 that couples the drain interconnect finger
626 to the conductive via 628. The drain interconnect finger 626
extends linearly, connecting to other drain regions in the
plurality of dissimilar square waffle gate parallel transistors 600
with respective conductive vias and via terminals. In one
embodiment the drain interconnect finger 626 extends in a parallel
direction to the source interconnect finger 610 and the drain
interconnect finger 618.
[0066] On the second layer 606 between the source region 608 and
the drain region 624 is the gate 622. The repeating pattern, with
the lines 623a, 623b forming the small frames 630 around the source
regions and the large frames 632 around the drain regions, extends
around the drain region 624. In one embodiment, each of the frames
630, 632 is rectangular such that each line of the gate 622 is
parallel or perpendicular to every other line. In an alternate
embodiment, each of the frames 630, 632 is a parallelogram such
that each line of the gate 622 is parallel to the first group of
lines 623a or the second group of lines 623b, the first group of
lines 623a not parallel or perpendicular to the second group of
lines 623b. In yet another embodiment, each line of the gate 622 is
parallel to one of more than two lines of the gate 622 that are not
parallel to each other.
[0067] The drain interconnect finger 626 is in the first plane with
the source interconnect finger 610 and the drain interconnect
finger 618, parallel to the second plane in which the gate 622
resides. The source interconnect finger 610, the drain interconnect
finger 618, and the drain interconnect finger 626 extend at a
different angle within the first plane than the angle of each line
of the gate 622 within the second plane, the angles measured around
an axis tangent to the planes. In an alternate embodiment, the
source interconnect finger 610, the drain interconnect finger 618,
and the drain interconnect finger 626 are at the same angle within
the first plane as the angle of the first group of lines 623a of
the gate 622 in the second plane. In some embodiments the source
interconnect finger 610, the drain interconnect finger 618, and the
drain interconnect finger 626 are in different planes parallel to
each other. And in some embodiments portions of the source
interconnect finger 610, the drain interconnect finger 618, and the
drain interconnect finger 626 are in the first plane, and portions
of the source interconnect finger 610, the drain interconnect
finger 618, and the drain interconnect finger 626 are in the third
plane parallel to the first plane. In some embodiments, the source
interconnect finger 610, the drain interconnect finger 618, and the
drain interconnect finger 626 are parallel to an edge of the die.
And in some embodiments, at least one of the lines 623a, 623b of
the gate 622 is parallel to an edge of the die.
[0068] FIG. 7 is a top view of the plurality of dissimilar square
waffle gate parallel transistors 600 of FIG. 6. Depicted in FIG. 7
are 24 parallel transistors. Each conductive via is coupled to a
shared source region or a shared drain region. The shared source
regions and the shared drain regions may be shared with two or more
transistors.
[0069] A first transistor of the plurality of dissimilar square
waffle gate parallel transistors 600 includes the source region
608, the drain region 616, and the gate 622. A second transistor of
the plurality of dissimilar square waffle gate parallel transistors
600 includes the source region 608, the drain region 624, and the
gate 622. The first and second transistors are similarly sized and
positioned but 180 degrees out of rotation from each other. The
source region 608 is also shared with a third transistor of the
plurality of dissimilar square waffle gate parallel transistors 600
that includes the source region 608, a drain region 702, and the
gate 622. Thus the source region 608 is shared between the first,
second, and third transistors of the plurality of dissimilar square
waffle gate parallel transistors 600. Similarly, the drain region
616 is a shared drain region. The drain region 616 is one terminal
of the second transistor of the plurality of dissimilar square
waffle gate parallel transistors 600, and also is shared with a
fourth transistor that includes a source region 704, the drain
region 616, and the gate 622. The pattern continues throughout so
that each source and drain region is a terminal of at least two
transistors of the plurality of dissimilar square waffle gate
parallel transistors 600.
[0070] Additional transistors are formed diagonal to the first
transistor using the same source interconnect finger 610, drain
interconnect finger 618, and gate 622, but with different
conductive vias to the first layer 604. Additional transistors are
formed diagonal to the second transistor using the same source
interconnect finger 610, drain interconnect finger 626, and gate
622, but with different conductive vias to the first layer 604,
such as a fifth transistor that includes the source region 704, the
drain region 702, and the gate 622. In addition, in some
embodiments, the source interconnect finger 610 is coupled to other
source interconnect fingers by a source master interconnect 700,
and the drain interconnect finger 618 is coupled to the drain
interconnect finger 626 and to other drain interconnect fingers by
a drain master interconnect 701.
[0071] FIG. 8 is a side cut away view of the plurality of
dissimilar square waffle gate parallel transistors 600 of FIG. 6,
taken at the cross section line BB of FIG. 7. FIG. 8 depicts the
first and second transistors as discussed above. In addition, FIG.
8 depicts a top surface of the second layer 606 covered by an
encapsulant 802 that provides electrical insulation between the
components. The encapsulant 802 covers the gate 622, the conductive
vias 612, 620, 628, the source and drain interconnect fingers 610,
618, 626, and the source and drain master interconnects 700, 701.
The encapsulant is a molding compound in one embodiment and any
other insulator in other embodiments.
[0072] Also shown in FIG. 8 are lateral boundaries of the source
and drain regions. For example, the source region 608 has lateral
boundaries 808 defined by the lines of the gate 622. Additionally,
the drain region 616 has lateral boundaries 810 and the drain
region 624 has lateral boundaries 812 defined by the lines of the
gate 622. The lateral boundaries 808, 810, 812 may be reflected
only in the footprint of the gate 622. In other embodiments,
changes in doping or changes in materials may mark the lateral
boundaries 808, 810, 812.
[0073] The gate 622 controls the conductivity of the first layer
604 from the source region 608 to the drain region 616 by applying
a voltage potential to the gate 622. A first channel 804 is
activated by alternating between a voltage greater than a threshold
voltage and a voltage less than a threshold voltage applied to the
gate 622. When activated, the first channel 804 forms from the
source region 608 to the drain region 616, permitting charge
carriers to flow between the source region 608 and the drain region
616.
[0074] The gate 622 also controls the conductivity of the first
layer 604 from the source region 608 to the drain region 624 by
applying the voltage potential to the gate 622. A second channel
806 is activated by alternating between a voltage greater than a
threshold voltage and a voltage less than a threshold voltage
applied to the gate 622. When activated, the second channel 806
forms from the source region 608 to the drain region 624,
permitting charge carriers to flow between the source region 608
and the drain region 624.
[0075] Unlike the square waffle gate parallel transistors 300, the
plurality of dissimilar square waffle gate parallel transistors 600
has the gate 622 spaced different distances from the centers of
respective source and drain regions. The gate layout of the
plurality of dissimilar square waffle gate parallel transistors 600
permits each of the transistors to be shifted to have a longer
length in the drain region than in the source region or a longer
length in the source region than in the drain region.
[0076] FIG. 9 is a top view of the plurality of dissimilar square
waffle gate parallel transistors 600 having an alternate
interconnect finger pattern. Like FIG. 7, the embodiment depicted
in FIG. 9 includes 24 parallel transistors, each with a conductive
via coupled to a shared source region or a shared drain region. The
shared source regions and the shared drain regions are shared with
two or more transistors.
[0077] Coupled to the source region 608 is a source interconnect
finger 902 coupled to the source region 608 by the conductive via
612. The conductive via 612 passes through the second layer 606 and
terminates at the first end in the first layer 604. In other
embodiments other connectors are used in place of the conductive
via 612, such as a contact pad. The conductive via 612 terminates
at the second end in the source interconnect finger 902 at a via
terminal 904. The via terminal 904 is an enlarged portion of the
source interconnect finger 902 that couples the source interconnect
finger 902 to the conductive via 612. The source interconnect
finger 902 connects to other source regions in the plurality of
dissimilar square waffle gate parallel transistors 600, but only
uses lines parallel to lines of the gate 622, stepping between via
terminals with 90 degree corners.
[0078] Coupled to the drain region 616 is a drain interconnect
finger 906 coupled to the drain region 616 by the conductive via
620. The conductive via 620 passes through the second layer 606 and
terminates at the first end in the first layer 604. In other
embodiments other connectors are used in place of the conductive
via 620, such as a contact pad. The conductive via 620 terminates
at the second end in the drain interconnect finger 906 at a via
terminal. The drain interconnect finger 906 connects to other drain
regions in the plurality of dissimilar square waffle gate parallel
transistors 600, but only uses lines parallel to lines of the gate
622, stepping between via terminals with 90 degree corners.
[0079] Similarly, coupled to the drain region 624 is a drain
interconnect finger 908 coupled to the drain region 624 by the
conductive via 628. The conductive via 628 passes through the
second layer 606 and terminates at the first end in the first layer
604. In other embodiments other connectors are used in place of the
conductive via 628, such as a contact pad. The conductive via 628
terminates at the second end in the drain interconnect finger 908
at a via terminal. The drain interconnect finger 908 connects to
other drain regions in the plurality of dissimilar square waffle
gate parallel transistors 600, but only uses lines parallel to
lines of the gate 622, stepping between via terminals with 90
degree corners.
[0080] In some embodiments, the source interconnect finger 902 is
coupled to other source interconnect fingers by a source master
interconnect 910, and the drain interconnect finger 906 is coupled
to the drain interconnect finger 908 and to other drain
interconnect fingers by a drain master interconnect 912. The
embodiment shown in FIG. 9 includes interconnect fingers and master
interconnects with only right angle connections, meeting possible
design or manufacturing constraints.
[0081] FIG. 10 is a top view of an alternate embodiment of the gate
pattern with a different position and ratio of source to drain
areas. Depicted is a plurality of dissimilar square waffle gate
parallel transistors 1000. FIG. 10 depicts an HEMT type transistor;
however, any one of a number of transistor layer technologies can
be used. A source region 1004 is at or below the second layer 1002.
The source region 1004 is one terminal of one of the plurality of
dissimilar square waffle gate parallel transistors 1000. A drain
region 1008 is at or below the second layer 1002 and is adjacent to
the source region 1004. A drain region 1014 is at or below the
second layer 1002 and is adjacent to the source region 1004 on a
side opposite from the drain region 1008.
[0082] Although not shown, in some embodiments the source regions
are coupled together by a network of source interconnect fingers
and a source master interconnect. The drain regions are coupled
together by a network of drain interconnect fingers and a drain
master interconnect. Coupled between one of the source interconnect
fingers and the source region 1004 is a conductive via 1006.
Coupled between one of the drain interconnect fingers and the drain
region 1008 is a conductive via 1010. Coupled between one of the
drain interconnect fingers and the drain region 1014 is a
conductive via 1016.
[0083] On the second layer 1002 between the source region 1004 and
the drain region 1008 is a gate 1012. In the plurality of
dissimilar square waffle gate parallel transistors 1000, the gate
1012 extends in a repeating pattern with a first group of lines
1018a intersecting a second group of lines 1018b to form small
frames 1020 around the source regions and large frames 1022 around
the drain regions. In an alternative embodiment, the repeating
pattern forms small frames around the drain regions and large
frames around the source regions. Each one of the small frames 1020
are adjacent to four large frames 1022 and each one of the large
frames 1022 are adjacent to four small frames 1020, except at the
perimeter of the pattern in which one or more sides of each frame
are not adjacent to another frame. Due to the size disparity of the
frames, each large frame 1022 is also adjacent to four large frames
1022, except at the perimeter of the pattern in which one or more
sides of each frame are not adjacent to another frame.
[0084] In contrast to FIG. 7, a frame 1024 around the source region
1004 is positioned adjacent to a bottom portion of a right side of
a frame 1026 around the drain region 1008 and is positioned
adjacent to a top portion of a left side of a frame 1028 around the
drain region 1014. Also in contrast to FIG. 7, the size disparity
between the source regions, the gate width, and the drain regions
is increased.
[0085] FIG. 11 is a top view of an alternate embodiment of the gate
pattern with non-square frames. Depicted is a plurality of
dissimilar parallelogram waffle gate parallel transistors 1100.
FIG. 11 depicts an HEMT type transistor; however, any one of a
number of transistor layer technologies can be used. A source
region 1104 is at or below the second layer 1102. The source region
1104 is one terminal of one of the plurality of dissimilar
parallelogram waffle gate parallel transistors 1100. A drain region
1108 is at or below the second layer 1102 and is adjacent to the
source region 1104. A drain region 1114 is at or below the second
layer 1102 and is adjacent to the source region 1104 on a side
opposite from the drain region 1108.
[0086] Although not shown, in some embodiments the source regions
are coupled together by a network of source interconnect fingers
and a source master interconnect. The drain regions are coupled
together by a network of drain interconnect fingers and a drain
master interconnect. Coupled between one of the source interconnect
fingers and the source region 1104 is a conductive via 1106.
Coupled between one of the drain interconnect fingers and the drain
region 1108 is a conductive via 1110. Coupled between one of the
drain interconnect fingers and the drain region 1114 is a
conductive via 1116.
[0087] On the second layer 1102 between the source region 1104 and
the drain region 1108 is a gate 1112. In the plurality of
dissimilar parallelogram waffle gate parallel transistors 1100, the
gate 1112 extends in a repeating pattern with a first group of
lines 1118a intersecting a second group of lines 1118b to form
small frames 1120 around the source regions and large frames 1122
around the drain regions. In an alternative embodiment, the
repeating pattern forms small frames around the drain regions and
large frames around the source regions. Each one of the small
frames 1120 are adjacent to four large frames 1122 and each one of
the large frames 1122 are adjacent to four small frames 1120,
except at the perimeter of the in which one or more sides of each
frame are not adjacent to another frame. Due to the size disparity
of the frames, each large frame 1122 is also adjacent to four large
frames 1122, except at the perimeter of the pattern in which one or
more sides of each frame are not adjacent to another frame.
[0088] In contrast to FIG. 7, a frame 1124 around the source region
1104 is positioned adjacent to a bottom portion of a right side of
a frame 1126 around the drain region 1108 and is positioned
adjacent to a top portion of a left side of a frame 1128 around the
drain region 1114. Also in contrast to FIG. 7, each of the frames
is a parallelogram, but not a square. In some embodiments, the
parallelogram frames are rhombuses. In some embodiments, each of
the frames around the source regions are parallelograms of a first
size and each of the frames around the drain regions are
parallelograms of a second size. In one embodiment, the
parallelograms of the first size and the parallelograms of the
second size have the same interior angles. In other embodiments,
the parallelograms of the first size and the parallelograms of the
second size have different interior angles. In one embodiment, the
gate 1112 has a non-uniform width across each of the lines 1118a,
1118b.
[0089] FIG. 12 is a top view of a plurality of dissimilar square
waffle gate parallel transistors, showing the dimension variables
of the gate pattern frames. A plurality of dissimilar square waffle
gate parallel transistors 1200 includes a transistor having a
source region 1202, a drain region 1206, and a gate 1204 between
the source region 1202 and the drain region 1206. The gate 1204
surrounds the source region 1202 and the drain region 1206.
[0090] In the embodiment shown in FIG. 12, the gate 1202 is not
spaced an equal distance from a conductive via in the source region
1202 as a conductive via in the drain region 1206. Due to
source/drain asymmetry, R.sub.DSon for the plurality of dissimilar
square waffle gate parallel transistors 1200 is lower than the
plurality of standard gate parallel transistors 100 with an
equivalent die footprint and is also lower than the plurality of
square waffle gate parallel transistors 300 with an equivalent die
footprint. To optimize R.sub.DSon, in one embodiment, the below
equation is satisfied:
d 1 d 5 < 2.22369 - 4.34287 ( d 6 d 1 ) + 4.6647 ( d 6 d 1 ) 2 -
2.36499 ( d 6 d 1 ) 3 + 0.444144 ( d 6 d 1 ) 4 ##EQU00001##
In the above equation, d1 equals a width of the gate 1204, d5
equals a width of the source region 1202, and d6 equals a width of
a drain extension. The width of the drain extension is computed by
taking a width of the drain region 1206 minus d5 and divided by
two.
[0091] Alternatively, for a fixed R.sub.DSon, the plurality of
dissimilar square waffle gate parallel transistors 1200 has a
smaller die footprint than the plurality of standard gate parallel
transistors 100 and also has a smaller die footprint than the
plurality of square waffle gate parallel transistors 300. In one
embodiment, the reduction in area can be determined using the
equation below:
AreaIncrement SQR , FING = A SQR - A FING A FING = A SQR ( W L )
SQR .times. ( W L ) FING A FING - 1 ##EQU00002##
In the above equation, A.sub.SQR is a total area of a single
transistor of the plurality of dissimilar square waffle gate
parallel transistors 1200, A.sub.FING is a total area of a single
transistor of the plurality of standard gate parallel transistors
100, (W/L).sub.SQR is a width to length ratio of a single
transistor of the plurality of dissimilar square waffle gate
parallel transistors 1200, and (W/L).sub.FING is a width to length
ratio of a single transistor of the plurality of standard gate
parallel transistors 100. The width to length ratios are, in one
embodiment, calculated using finite elements method. Thus,
AreaIncrement.sub.SQR,FING is the ratio of area reduction based on
the difference between topologies of a dissimilar square waffle
gate parallel transistors and standard gate parallel
transistors.
[0092] FIGS. 13A-13G are various embodiments of different source to
gate to drain ratios for dissimilar square waffle gate parallel
transistors. The ratios are exemplary ratios showing relative
sizing of one dimension of frames of the transistors, such as
width. The ratios shown are exemplary ratios, and other larger or
smaller ratios are also within the scope of the disclosure.
[0093] FIG. 13A depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1302, a drain region 1306, and a gate 1304 between the
source region 1302 and the drain region 1306. In this embodiment,
the ratio of the drain region 1306 to the source region 1302 is
1.2:1 and the ratio of the gate 1304 to the source region 1302 is
0.5:1.
[0094] FIG. 13B depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1312, a drain region 1316, and a gate 1314 between the
source region 1312 and the drain region 1316. In this embodiment,
the ratio of the drain region 1316 to the source region 1312 is 2:1
and the ratio of the gate 1314 to the source region 1312 is
0.5:1.
[0095] FIG. 13C depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1322, a drain region 1326, and a gate 1324 between the
source region 1322 and the drain region 1326. In this embodiment,
the ratio of the drain region 1326 to the source region 1322 is 3:1
and the ratio of the gate 1324 to the source region 1322 is
0.5:1.
[0096] FIG. 13D depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1332, a drain region 1336, and a gate 1334 between the
source region 1332 and the drain region 1336. In this embodiment,
the ratio of the drain region 1336 to the source region 1332 is 5:1
and the ratio of the gate 1334 to the source region 1332 is
0.5:1.
[0097] FIG. 13E depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1342, a drain region 1346, and a gate 1344 between the
source region 1342 and the drain region 1346. In this embodiment,
the ratio of the drain region 1346 to the source region 1342 is 2:1
and the ratio of the gate 1344 to the source region 1342 is
0.2:1.
[0098] FIG. 13F depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1352, a drain region 1356, and a gate 1354 between the
source region 1352 and the drain region 1356. In this embodiment,
the ratio of the drain region 1356 to the source region 1352 is 2:1
and the ratio of the gate 1354 to the source region 1352 is
1:1.
[0099] FIG. 13G depicts a plurality of dissimilar square waffle
gate parallel transistors including a transistor having a source
region 1362, a drain region 1366, and a gate 1364 between the
source region 1362 and the drain region 1366. In this embodiment,
the ratio of the drain region 1366 to the source region 1362 is 2:1
and the ratio of the gate 1364 to the source region 1362 is
2:1.
[0100] FIG. 14 is an alternate embodiment of the plurality of
dissimilar square waffle gate parallel transistors, showing a cross
section of a device with MOSFET based transistors. FIG. 14 depicts
parallel metal-oxide-semiconductor field effect transistors
(MOSFET) with a dissimilar square waffle gate. In one embodiment, a
substrate 1402 is intrinsic silicon, a semiconductor layer 1404 is
a semiconductor, such as doped silicon, and the insulator 1406 is
an insulating material, such as silicon dioxide or silicon nitride.
In some embodiments with MOSFET transistors, the insulator 1406 on
the semiconductor layer 1404 does not extend over a majority of the
area of the semiconductor layer 1404.
[0101] Like the dissimilar square waffle gate parallel transistors
600, the dissimilar square waffle gate parallel transistors 1400
includes source and drain regions; however, in this embodiment the
regions are defined by doping of the semiconductor layer 1404. For
example, the source region 1408 is a doped region of the
semiconductor layer 1404, with the doping extending to the lateral
boundaries 1410. A conductive via 1412 couples to the source region
1408. The drain region 1414 is a doped region of the semiconductor
layer 1404, with the doping extending to the lateral boundaries
1416. A conductive via 1418 couples to the drain region 1414. In
one embodiment, the doping of the source region 1408 is similar to
the doping of the drain region 1414. In other embodiment, the
doping of the source region 1408 is dissimilar or opposite to the
doping of the drain region 1414. In some embodiments the
semiconductor layer 1404 is also doped.
[0102] A gate 1420 operates similarly to the gate 622, with an
electric potential causing a channel 1422 to activate in the
semiconductor layer 1404 between the source region 1408 and the
drain region 1414 that allows electric charge to be carried by
charge carriers between the source region 1408 and the drain region
1414. The electric potential required at the gate 1422 is dependent
on the materials and the doping of the various materials used in
the dissimilar square waffle gate parallel transistors 1400.
[0103] Similarly, the drain region 1424 is a doped region of the
semiconductor layer 1404, with the doping extending to the lateral
boundaries 1426. A conductive via 1428 couples to the drain region
1424. In one embodiment, the doping of the source region 1408 is
similar to the doping of the drain region 1424. In other
embodiment, the doping of the source region 1408 is dissimilar or
opposite to the doping of the drain region 1424. In some
embodiments the semiconductor layer 1404 is also doped.
[0104] The gate 1420 operates similarly to the gate 622, with an
electric potential causing a channel 1430 to activate in the
semiconductor layer 1404 between the source region 1408 and the
drain region 1424 that allows electric charge to be carried by
charge carriers between the source region 1408 and the drain region
1424. The electric potential required at the gate 1430 is dependent
on the materials and the doping of the various materials used in
the dissimilar square waffle gate parallel transistors 1400.
[0105] In other embodiments, other transistor types may be used
with the different gate layouts discussed above. For example, in
one embodiment, a plurality of dissimilar square waffle gate
parallel transistors is based on a silicon carbon semiconductor. In
other embodiments, the plurality of dissimilar square waffle gate
parallel transistors is based on printing electronics
manufacturing. And in yet other embodiments, other transistor types
may be used to realize the features discussed throughout this
application.
[0106] The various embodiments described above can be combined to
provide further embodiments. These and other changes can be made to
the embodiments in light of the above-detailed description. In
general, in the following claims, the terms used should not be
construed to limit the claims to the specific embodiments disclosed
in the specification and the claims, but should be construed to
include all possible embodiments along with the full scope of
equivalents to which such claims are entitled. Accordingly, the
claims are not limited by the disclosure.
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