U.S. patent application number 16/029677 was filed with the patent office on 2018-11-15 for low power scheme for bit flipping low density parity check decoder.
The applicant listed for this patent is Silicon Motion Inc.. Invention is credited to Chen-Yu Weng.
Application Number | 20180331696 16/029677 |
Document ID | / |
Family ID | 59856151 |
Filed Date | 2018-11-15 |
United States Patent
Application |
20180331696 |
Kind Code |
A1 |
Weng; Chen-Yu |
November 15, 2018 |
LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK
DECODER
Abstract
A method for dynamically adapting a clock frequency used to
perform low-density parity check (LDPC) decoding includes: setting
a first clock frequency for performing a first LDPC decoding
iteration on a received codeword to generate a decoded codeword;
performing a successive plurality of LDPC decoding iterations on
the decoded codeword; at the end of each LDPC decoding iteration,
determining a number of error bits of the decoded codeword and a
throughput of the LDPC decoding iteration; and when a number of the
error bits increases, increasing the clock frequency for performing
a next LDPC decoding iteration so that a throughput of the next
LDPC decoding iteration is the same as the throughput of the
immediately preceding iteration. The first clock frequency is set
according to a number of error bits in an immediately previous
decoding operation.
Inventors: |
Weng; Chen-Yu; (Kaohsiung
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Silicon Motion Inc. |
Hsinchu County |
|
TW |
|
|
Family ID: |
59856151 |
Appl. No.: |
16/029677 |
Filed: |
July 9, 2018 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
15073606 |
Mar 17, 2016 |
10050642 |
|
|
16029677 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03M 13/3715 20130101;
H03M 13/1111 20130101; H03M 13/1108 20130101 |
International
Class: |
H03M 13/11 20060101
H03M013/11 |
Claims
1. A method for dynamically adapting a clock frequency used to
perform low-density parity check (LDPC) decoding, the method
comprising: setting a first clock frequency for performing a first
LDPC decoding iteration on a received codeword to generate a
decoded codeword; performing a successive plurality of LDPC
decoding iterations on the decoded codeword; at the end of each
LDPC decoding iteration, determining a number of error bits of the
decoded codeword and a throughput of the LDPC decoding iteration;
and when a number of the error bits increases, increasing the clock
frequency for performing a next LDPC decoding iteration so that a
throughput of the next LDPC decoding iteration is the same as the
throughput of the immediately preceding iteration.
2. The method of claim 1, wherein the LDPC decoding is hard
decision decoding using a bit flipping algorithm, and the method
further comprises: at the end of each decoding iteration,
determining a syndrome weight; monitoring the syndrome weights over
the plurality of decoding iterations; when the syndrome weights
begin to overlap, performing a final decoding iteration using the
bit flipping algorithm; and increasing the clock frequency and
switching the decoding mode to hard decision soft decoding
mode.
3. The method of claim 1, wherein the first clock frequency is set
according to a number of error bits in an immediately previous
decoding operation.
4. A low-density parity check (LDPC) decoder which dynamically
adapts a clock frequency used to perform decoding, the LDPC decoder
comprising: an oscillator, for providing a clock to the LDPC
decoder for a plurality of decoding iterations, wherein a first
clock frequency of the oscillator is set for performing a first
LDPC decoding iteration of the plurality of decoding iterations on
a received codeword to generate a decoded codeword; a check
syndrome weight circuit, for determining a number of error bits of
the decoded codeword at the end of each decoding iteration; and a
processor, coupled to the oscillator and the check syndrome weight
circuit, for controlling operations of the LDPC decoder, wherein
the processor determines a throughput of each LDPC decoding
iteration, and when a number of the error bits increases, the
processor increases the clock frequency for performing a next LDPC
decoding iteration of the plurality of decoding iterations so that
a throughput of the next LDPC decoding iteration is the same as the
throughput of an immediately preceding iteration.
5. The LDPC decoder of claim 4, wherein the LDPC decoding is hard
decision decoding using a bit flipping algorithm, the check
syndrome weight circuit further determines a syndrome weight at the
end of each decoding iteration, the processor further monitors the
syndrome weights over the plurality of decoding iterations, and
when the syndrome weights begin to overlap, the processor controls
the LDPC decoder to perform a final decoding iteration using the
bit flipping algorithm, controls the oscillator to increase the
clock frequency, and controls the LDPC decoder to switch the
decoding mode to hard decision soft decoding mode.
6. The LDPC decoder of claim 4, wherein the first clock frequency
is set according to a number of error bits in an immediately
previous decoding operation.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation application of U.S.
patent application Ser. No. 15/073,606, which was filed on Mar. 17,
2016, the contents of which are included herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] This invention relates to low-density parity check decoding,
and more particularly, to a low-density parity check decoder and
decoding method which can save power.
2. Description of the Prior Art
[0003] Low-density parity check (LDPC) decoders use a linear error
correcting code with parity bits. Parity bits provide a decoder
with parity equations which can validate a received codeword. For
example, a low-density parity check is a fixed length binary code
wherein all the symbols added together will equal zero.
[0004] During encoding, all data bits are repeated and transmitted
to encoders, wherein each encoder generates a parity symbol.
Codewords are formed of k information digits and r check digits. If
the length of the codeword is n then the information digits, k,
will equal n-r. The codewords can be represented by a parity check
matrix, which consists of r rows (representing equations) and n
columns (representing digits), and is represented in FIG. 1. The
codes are called low-density because the parity matrix will have
very few `1`s in comparison to the number of `0`s. During decoding,
each parity check is viewed as a single parity check code, and is
then cross-checked with others. Decoding occurs at check nodes, and
cross-checking occurs at variable nodes.
[0005] LDPC engines support three modes: hard decision hard
decoding, soft decision hard decoding, and soft decision soft
decoding. FIG. 1 illustrates the parity check matrix H and a Tanner
graph, which is another way of representing the codewords, and is
used to explain the operation of the LDPC decoder for hard decision
soft decoding when using a bit flipping algorithm.
[0006] The check nodes, which are represented by the square boxes,
are the number of parity bits; and the variable nodes, which are
represented by the circular boxes, are the number of bits in a
codeword. If a code symbol is involved in a particular equation, a
line is drawn between the corresponding check node and variable
node. `Messages`, which are estimates, are passed along the
connecting lines, and combined in different ways at the nodes.
Initially, the variable nodes will send an estimate to the check
nodes on all connecting lines containing a bit believed to be
correct. Each check node then takes all the other connected
estimates, makes new estimates for each variable node based on this
information, and passes the new estimate back to the variable
nodes. The new estimate is based on the fact that the parity check
equations force all variable nodes connected to a particular check
node to sum to zero.
[0007] The variable nodes receive the new information and use a
majority rule (a hard decision) to determine if the value of the
original bit they sent was correct. If not, the original bit will
be `flipped`. The bit is then sent back to the check nodes, and
these steps are repeated for a predetermined number of iterations
or until the parity check equations at the check nodes are
satisfied. If these equations are satisfied (i.e. the value
calculated by the check nodes matches the value received from the
variable nodes) then Early Termination can be activated, which
allows the system to exit the decoding process before the maximum
number of iterations is reached.
[0008] The parity check constraints are performed by doing a
syndrome check. A valid codeword will satisfy the equation
HC.sup.T=S=0, wherein H is the parity matrix, C is the hard
decision codeword and S is the syndrome. When the syndrome equals
zero, this means that no further information is required and the
decoding process is complete. Typically, a hard decision and a
syndrome check are performed during each iteration, wherein a
non-zero syndrome means there is odd parity and a new decoding
iteration is required.
[0009] Decoders have a power issue, wherein the more complicated
they are, the more power they use. The above bit flipping algorithm
can support both hard decision hard decoding and hard decision soft
decoding modes. Hard decision hard decoding is the lowest power
mode as it only involves 1 bit. As the number of error bits
increases, however, the power issue starts to become more
important. Above about 25 error bits, the throughput of the bit
flipping algorithm starts to drop. Above about 40 error bits, it is
better to switch to hard decision soft decoding, but the speed of
the algorithm will be very unstable when a different mode is
entered.
SUMMARY OF THE INVENTION
[0010] A method for dynamically adapting a clock frequency used to
perform low-density parity check (LDPC) decoding is disclosed. The
method comprises: setting a first clock frequency for performing a
first LDPC decoding iteration on a received codeword to generate a
decoded codeword; performing a successive plurality of LDPC
decoding iterations on the decoded codeword; at the end of each
LDPC decoding iteration, determining a number of error bits of the
decoded codeword and a throughput of the LDPC decoding iteration;
and when a number of the error bits increases, increasing the clock
frequency for performing a next LDPC decoding iteration so that a
throughput of the next LDPC decoding iteration is the same as the
throughput of the immediately preceding iteration. The first clock
frequency is set according to a number of error bits in an
immediately previous decoding operation.
[0011] In the above method, the LDPC decoding is hard decision
decoding using a bit flipping algorithm. At the end of each
decoding iteration, a syndrome weight is determined. The syndrome
weights are monitored over the plurality of decoding iterations.
When the syndrome weights begin to overlap, a final decoding
iteration is performed using the bit flipping algorithm, the clock
frequency is increased, and the decoding mode is switched to hard
decision soft decoding mode.
[0012] A low-density parity check (LDPC) decoder which dynamically
adapts a clock frequency used to perform decoding is disclosed. The
LDPC decoder comprises: an oscillator, for providing a clock to the
LDPC decoder for a plurality of decoding iterations, wherein a
first clock frequency of the oscillator is set for performing a
first LDPC decoding iteration of the plurality of decoding
iterations on a received codeword to generate a decoded codeword; a
check syndrome weight circuit, for determining a number of error
bits of the decoded codeword at the end of each decoding iteration;
and a processor, coupled to the oscillator and the check syndrome
weight circuit, for controlling operations of the LDPC decoder,
wherein the processor determines a throughput of each LDPC decoding
iteration, and when a number of the error bits increases, the
processor increases the clock frequency for performing a next LDPC
decoding iteration of the plurality of decoding iterations so that
a throughput of the next LDPC decoding iteration is the same as the
throughput of an immediately preceding iteration. The first clock
frequency is set according to a number of error bits in an
immediately previous decoding operation.
[0013] In the above apparatus, the check syndrome weight circuit
further determines a syndrome weight at the end of each decoding
iteration, the processor further monitors the syndrome weights over
the plurality of decoding iterations, and when the syndrome weights
begin to overlap, the processor controls the LDPC decoder to
perform a final decoding iteration using the bit flipping
algorithm, controls the oscillator to increase the clock frequency,
and controls the LDPC decoder to switch the decoding mode to hard
decision soft decoding mode.
[0014] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is an illustration of a parity check matrix Tanner
graph for low-density parity check decoding.
[0016] FIG. 2 is a diagram of an LDPC decoder according to an
exemplary embodiment of the present invention.
DETAILED DESCRIPTION
[0017] The present invention provides a frequency auto-tuning
scheme in order to control power consumption vs. throughput
issues.
[0018] As detailed in the background, bit-flipping can support all
modes, but is best used for hard decision hard decoding which is a
low power mode. Even in hard decision hard decoding, throughput
drops above about 25 error bits. When hard decision soft decoding
is entered, both bit-flipping and an N2 decoding engine can be
used. Above 40 error bits, however, N2 is much more reliable.
Therefore, a method is proposed which can provide a power boost via
increasing clock frequency for bit-flipping during hard decision
hard decoding, and can provide a further power boost when the mode
changes to hard decision soft decoding.
[0019] Syndrome weight is used to determine an appropriate time for
providing these clock frequency boosts. The syndrome weight is the
number of non-zero components or unsatisfied check nodes in a
trapping set (a sub graph of the Tanner graph of an LDPC code which
causes decoder failure). As the syndrome weight will increase on
average with the number of error bits, and the throughput of the BF
engine also decreases as the errors increase, syndrome weight is a
good indicator for when power boost is required.
[0020] In each iteration, the syndrome weight is first obtained,
and a clock frequency is set accordingly. For a first iteration, a
previous number of error bits can be obtained and used to set the
initial clock frequency. During subsequent iterations, the syndrome
weight is obtained each time, and used to maintain or increase the
clock frequency. The aim is to maintain the throughput at
approximately 400 MHz
[0021] As the errors start to increase, the syndrome weight will
begin to overlap during the bit flipping hard decision hard
decoding mode. This is an indication that hard decision soft
decoding mode needs to be entered. As detailed above, changing the
mode requires a power boost, which means the clock frequency should
be increased. In general, the bit flipping can go through one more
iteration when it is detected that the syndrome weights begin to
overlap before increasing the clock frequency and changing decoding
modes.
[0022] The above method comprises two sub-methods. The first
sub-method always returns to the initial clock frequency at the end
of decoding, and then uses previous error bits to set the initial
clock frequency for a next stage of decoding. The second sub-method
maintains the latest clock frequency even when decoding is
finished, and uses this clock frequency as the initial clock
frequency for the next stage of decoding. The first sub-method can
be termed an individual mode, and is better for decoding
performance as the initial clock frequency is a better match for
random data. The second sub-method can be termed a forward mode,
and is better for power usage.
[0023] Please refer to FIG. 2, which is a diagram of an LDPC
decoding engine according to an exemplary embodiment of the present
invention. The LDPC decoding engine 200 comprises an order memory
230 which stores channel values. The channel values and
corresponding metrics are passed to a subtractor, and D values are
sent to the compare circuit 210 for updating the channel values.
The D values are also sent to the Dapp_memory 250, and are sent to
a processer block 290, which outputs modified metrics. The modified
channel values and metrics are combined at the adder to generate a
new APP value, which is sent to the permutator 270 for activating a
syndrome check via the Early Termination (ET) Check circuit 280.
The ET Check circuit 280 also comprises a check syndrome weight
circuit 260, which is coupled to an oscillator 265 that generates a
clock frequency for the LDPC decoding engine 200. The check
syndrome weight circuit 260 is used for determining the syndrome
weight and using the syndrome weight to update the clock frequency.
A signal is output from the check syndrome weight circuit 260 to
the oscillator 265, which generates an updated clock signal CLK
with a frequency according to the syndrome weight.
[0024] The present invention therefore provides a method and
apparatus for auto-tuning a clock frequency during both hard
decision hard decoding and hard decision soft decoding to maintain
throughput when a number of error bits increases. By monitoring the
syndrome weight, the throughput vs. power consumption issue can be
controlled, and a power boost can be provided when hard decision
hard decoding mode switches to hard decision soft decoding in order
to prevent unstable speed. In this way, power consumption can be
controlled.
[0025] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *