U.S. patent application number 15/590143 was filed with the patent office on 2018-11-15 for refresh in memory based on a set margin.
The applicant listed for this patent is Micron Technology, Inc.. Invention is credited to Paolo Amato, Marco Sforzin.
Application Number | 20180330774 15/590143 |
Document ID | / |
Family ID | 64097406 |
Filed Date | 2018-11-15 |
United States Patent
Application |
20180330774 |
Kind Code |
A1 |
Sforzin; Marco ; et
al. |
November 15, 2018 |
REFRESH IN MEMORY BASED ON A SET MARGIN
Abstract
The present disclosure includes apparatuses and methods related
to refresh in memory. An apparatus can refresh an array of memory
cells in response to a portion of memory cells in an array having
threshold voltages that are greater than a reference voltage. The
reference voltage can be determined by the threshold voltage being
within a set margin of a second state.
Inventors: |
Sforzin; Marco; (Cernusco
Sul Naviglio, IT) ; Amato; Paolo; (Treviglio,
IT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Family ID: |
64097406 |
Appl. No.: |
15/590143 |
Filed: |
May 9, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 16/32 20130101;
G11C 13/0061 20130101; G11C 2207/104 20130101; G11C 11/406
20130101; G05F 3/26 20130101; G11C 16/0483 20130101; G11C 16/3418
20130101; G11C 2211/4062 20130101; G11C 16/10 20130101; G11C
11/40607 20130101; G11C 13/0033 20130101; G11C 16/349 20130101 |
International
Class: |
G11C 11/406 20060101
G11C011/406; G05F 3/26 20060101 G05F003/26; G11C 16/04 20060101
G11C016/04; G11C 16/10 20060101 G11C016/10; G11C 16/34 20060101
G11C016/34 |
Claims
1-16. (canceled)
17. A method, comprising: measuring a voltage associated with a
first number of memory cells in an array of memory cells; and
refreshing the array of memory cells in response to the voltage
being within a set margin of a reference voltage, wherein the set
margin is based on an amount of time to complete refreshing the
array of memory cells and the set margin is based on the speed and
size of a memory device to have enough time to do a refresh
operation before reaching the reference voltage, and wherein the
memory device includes the array of memory cells and a monitor
array.
18. (canceled)
19. The method of claim 17, wherein refreshing the array of memory
cells improves read margin of the array of memory cells.
20-22. (canceled)
23. An Apparatus, comprising: an array of memory cells; and a
controller configured to: measure a voltage associated with a first
number of memory cells in the array of memory cells; and refresh
the array of memory cells in response to the voltage being within a
set margin of a reference voltage, wherein the set margin is based
on an amount of time to complete the refresh of the array of memory
cells and the set margin is based on the speed and size of a memory
device to have enough time to do a refresh operation before
reaching the reference voltage, and wherein the memory device
includes the array of memory cells and a monitor array.
Description
TECHNICAL FIELD
[0001] The present disclosure relates generally to memory devices,
and more particularly, to apparatuses and methods for refresh in
memory.
BACKGROUND
[0002] Memory devices are typically provided as internal,
semiconductor, integrated circuits in computers or other electronic
devices. There are many different types of memory including
volatile and non-volatile memory. Volatile memory can require power
to maintain its data and includes random-access memory (RAM),
dynamic random access memory (DRAM), and synchronous dynamic random
access memory (SDRAM), among others. Non-volatile memory can
provide persistent data by retaining stored data when not powered
and can include NAND flash memory, NOR flash memory, read only
memory (ROM), Electrically Erasable Programmable ROM (EEPROM),
Erasable Programmable ROM (EPROM), and resistance variable memory
such as phase change random access memory (PCRAM), resistive random
access memory (RRAM), and magnetoresistive random access memory
(MRAM), among others.
[0003] Memory is also utilized as volatile and non-volatile data
storage for a wide range of electronic applications. Non-volatile
memory may be used in, for example, personal computers, portable
memory sticks, digital cameras, cellular telephones, portable music
players such as MP3 players, movie players, and other electronic
devices. Memory cells can be arranged into arrays, with the arrays
being used in memory devices.
[0004] Memory can be part of a memory system used in computing
devices. Memory systems can include volatile, such as DRAM, for
example, and/or non-volatile memory, such as Flash memory or RRAM,
for example.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1A is a block diagram of an apparatus in the form of a
computing system including a memory system in accordance with a
number of embodiments of the present disclosure.
[0006] FIG. 1B is a block diagram of an apparatus in the form of a
memory device in accordance with a number of embodiments of the
present disclosure.
[0007] FIG. 2 is a block diagram of a portion of an array of memory
cells in accordance with a number of embodiments of the present
disclosure.
[0008] FIG. 3 illustrates a diagram associated with performing
refresh in memory in accordance with a number of embodiments of the
present disclosure.
DETAILED DESCRIPTION
[0009] The present disclosure includes apparatuses and methods
related to refresh in memory. An example apparatus can refresh an
array of memory cells in response to a portion of memory cells in
the array having threshold voltages that are greater than a
reference voltage.
[0010] In one or more embodiments of the present disclosure, a
controller can be configured to refresh an array of memory cells in
response to a portion of memory cells in the array having threshold
voltages that are greater than a reference voltage. The controller
can be configured to refresh memory cells programmed to a first
state and/or to a second state, for example. The controller can
also be configured to apply a current to a portion of the array of
memory cells and measure the voltages of the portion of the array
of memory cells. The current can be applied during set periods of
time (e.g., periodically) or can be applied continuously. The
controller can be configured to refresh the memory cells in the
array in response to the portion of the array of memory cells
having threshold voltages that are greater than the reference
voltage. A refresh operation can include reprogramming the memory
cells to the state which they had been previously programmed.
Refreshing the array of memory cells can improve read margin of the
array of memory cells.
[0011] In one or more embodiments of the present disclosure, the
controller is configured to measure a voltage associated with a
portion of memory cells (e.g., a monitor array of memory cells) in
the array of memory cells and refresh the array of memory cells in
response to the voltage being within a set margin of a reference
voltage. The threshold voltage associated with memory cells can
change over time reducing and/or eliminating a read margin
associated with adjacent data states. Therefore, according to
embodiments of the present disclosure a refresh operation can be
used to reestablish the read margins associated with adjacent data
states. The portion of memory cells can be connected in parallel.
In one or more embodiments, the number of memory cells in the
monitor array can depend on a reference voltage.
[0012] In one or more embodiments, another array of memory cells
can be used to store data during the refresh operation. The
controller can include, for example, a buffer that stores the data
during the refresh operation. In one or more embodiments, the
memory device can include a buffer that stores the data during the
refresh operation. Also, another memory device, such as a NAND
flash memory device, can be used to store data during the refresh
operation.
[0013] In the following detailed description of the present
disclosure, reference is made to the accompanying drawings that
form a part hereof, and in which is shown by way of illustration
how a number of embodiments of the disclosure may be practiced.
These embodiments are described in sufficient detail to enable
those of ordinary skill in the art to practice the embodiments of
this disclosure, and it is to be understood that other embodiments
may be utilized and that process, electrical, and/or structural
changes may be made without departing from the scope of the present
disclosure.
[0014] As used herein, "a number of" something can refer to one or
more of such things. For example, a number of memory devices can
refer to one or more of memory devices. Additionally, designators
such as "M", "N", "S", "T", "X", "Y", as used herein, particularly
with respect to reference numerals in the drawings, indicates that
a number of the particular feature so designated can be included
with a number of embodiments of the present disclosure.
[0015] The figures herein follow a numbering convention in which
the first digit or digits correspond to the drawing figure number
and the remaining digits identify an element or component in the
drawing. Similar elements or components between different figures
may be identified by the use of similar digits. As will be
appreciated, elements shown in the various embodiments herein can
be added, exchanged, and/or eliminated so as to provide a number of
additional embodiments of the present disclosure. In addition, the
proportion and the relative scale of the elements provided in the
figures are intended to illustrate various embodiments of the
present disclosure and are not to be used in a limiting sense.
[0016] FIG. 1A is a functional block diagram of a computing system
100 including an apparatus in the form of a number of memory
systems 104-1 . . . 104-N, in accordance with one or more
embodiments of the present disclosure. As used herein, an
"apparatus" can refer to, but is not limited to, any of a variety
of structures or combinations of structures, such as a circuit or
circuitry, a die or dice, a module or modules, a device or devices,
or a system or systems, for example. In the embodiment illustrated
in FIG. 1A, memory systems 104-1 . . . 104-N can include one or
more memory devices, such as memory devices 110-1, . . . , 110-X,
110-Y. Memory devices 110-1, . . . , 110-X, 110-Y can include
volatile memory and/or non-volatile memory. In a number of
embodiments, memory systems 104-1, . . . , 104-N can include a
multi-chip device. A multi-chip device can include a number of
different memory types. For example, a memory system can include a
number of chips having non-volatile or volatile memory on any type
of a module. In FIG. 1A, memory system 104-1 is coupled to the host
102 via channels 112-1 can include memory devices 110-1, . . . ,
110-X. For example, memory device 110-1 can be a non-volatile
cross-point array memory device and 110-X can be a NAND flash
memory device. In this example, each memory device 110-1, . . . ,
110-X, 110-Y includes a controller 114. Controller 114 can receive
commands from host 102 and control execution of the commands on a
memory device. The host 102 can send commands to the memory devices
110-1, . . . , 110-X, 110-Y. For example, the host can communicate
on the same channel (e.g., channel 112-1) with a non-volatile
cross-point array memory device and a NAND flash memory device that
are both on the same memory system.
[0017] As illustrated in FIG. 1A, a host 102 can be coupled to the
memory systems 104-1 . . . 104-N. In a number of embodiments, each
memory system 104-1 . . . 104-N can be coupled to host 102 via a
channel. In FIG. 1A, memory system 104-1 is coupled to host 102 via
channel 112-1 and memory system 104-N is coupled to host 102 via
channel 112-N. Host 102 can be a laptop computer, personal
computers, digital camera, digital recording and playback device,
mobile telephone, PDA, memory card reader, interface hub, among
other host systems, and can include a memory access device (e.g., a
processor). One of ordinary skill in the art will appreciate that
"a processor" can intend one or more processors, such as a parallel
processing system, a number of coprocessors, etc.
[0018] Host 102 includes a host controller 108 to communicate with
memory systems 104-1 . . . 104-N. The host controller 108 can send
commands to the memory devices 110-1, . . . , 110-X, 110-Y via
channels 112-1 . . . 112-N. The host controller 108 can communicate
with the memory devices 110-1, . . . , 110-X, 110-Y and/or the
controller 114 on each of the memory devices 110-1, . . . , 110-X,
110-Y to read, write, and erase data, among other operations. A
physical host interface can provide an interface for passing
control, address, data, and other signals between the memory
systems 104-1 . . . 104-N and host 102 having compatible receptors
for the physical host interface. The signals can be communicated
between host 102 and memory devices 110-1, . . . , 110-X, 110-Y on
a number of buses, such as a data bus and/or an address bus, for
example, via channels 112-1 . . . 112-N.
[0019] The host controller 108 and/or controller 114 on a memory
device can include control circuitry (e.g., hardware, firmware,
and/or software). In one or more embodiments, the host controller
108 and/or controller 114 can be an application specific integrated
circuit (ASIC) coupled to a printed circuit board including a
physical interface. Also, each memory device 110-1, . . . , 110-X,
110-Y can include buffer 116 of volatile and/or non-volatile
memory. Buffer 116 can be used to buffer data that is used during
execution of read commands and/or write commands. The buffer 116
can be configured to store signals, address signals (e.g., read
and/or write commands), and/or data (e.g., write data). The buffer
can temporarily store signals and/or data while commands are
executed.
[0020] The memory devices 110-1, . . . , 110-X, 110-Y can provide
main memory for the memory system or could be used as additional
memory or storage throughout the memory system. Each memory device
110-1, . . . , 110-X, 110-Y can include one or more arrays of
memory cells (e.g., non-volatile memory cells). The arrays can be
flash arrays with a NAND architecture, for example. Embodiments are
not limited to a particular type of memory device. For instance,
the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM,
and flash memory, among others.
[0021] The embodiment of FIG. 1A can include additional circuitry
that is not illustrated so as not to obscure embodiments of the
present disclosure. For example, the memory systems 104-1 . . .
104-N can include address circuitry to latch address signals
provided over I/O connections through I/O circuitry. Address
signals can be received and decoded by a row decoder and a column
decoder to access the memory devices 110-1, . . . , 110-X, 110-Y.
It will be appreciated by those skilled in the art that the number
of address input connections can depend on the density and
architecture of the memory devices 110-1, . . . , 110-X, 110-Y.
[0022] FIG. 1B is a block diagram of an apparatus in the form of a
memory device in accordance with a number of embodiments of the
present disclosure. In FIG. 1B, memory device 110 can include a
controller 114 and an array of memory cells 117. Controller 114 can
include monitor circuitry 118 and/or memory, such as SRAM memory,
that can be a buffer 116. The array 117 can include one or more
arrays of memory cells. The one or more arrays can be non-volatile
memory arrays and/or volatile memory arrays. The array 117 can
include a monitor array 113. The monitor array 113 can include
memory cells coupled together in parallel via a bit line. In a
number of embodiments, a current can be applied to the monitor
array 113 to measure a voltage associated with the monitor array
113. The array 117 and the monitor array 113 can be refreshed in
response to the voltage being within a set margin of a reference
voltage.
[0023] Array 117 and/or monitor array 113 can include buffers which
can be used to store cell data during a refresh operation. The
buffer can receive commands from controller 114 and the monitor
circuitry 118 can be configured to execute commands to apply the
current to the monitor array 113.
[0024] FIG. 2 is a block diagram of a portion of an array 201 of
memory cells 207 in accordance with a number of embodiments of the
present disclosure. The array 201 can be a two terminal cross-point
array having memory cells 207 located at the intersections of a
first plurality of conductive lines (e.g., access lines) 203-0,
203-1, . . . , 203-T, which may be referred to herein as word
lines, and a second plurality of conductive lines (e.g., data/sense
lines, 205-0, 205-1, . . . , 205-M) which may be referred to herein
as bit lines. The designators N and M can have various values.
Embodiments are not limited to a particular number of word lines
and/or bit lines. As illustrated, the word lines 203-0, 203-1, . .
. , 203-T are parallel to each other and are orthogonal to the bit
lines 205-0, 205-1, . . . , 205-S, which are substantially parallel
to each other; however, embodiments are not so limited. The
conductive lines can include conductive material (e.g., a metal
material). Examples of the conductive material include, but are not
limited to, tungsten, copper, titanium, aluminum, and/or
combinations thereof, among other conductive materials.
[0025] Each memory cell 207 may include a memory element (e.g., a
resistive memory element) coupled in series with a select device
(e.g., an access device) in accordance with a number of embodiments
described herein. The memory element and the select device are
discussed further herein.
[0026] The select devices can be operated (e.g., turned on/off) to
select/deselect the memory element in order to perform operations
such as data programming (e.g., writing, and/or data sensing (e.g.,
reading operations)). The select device can be a diode, a bipolar
junction transistor, a MOS transistor, and/or an Ovonic threshold
switch, among other devices. In operation, appropriate voltage
and/or current signals (e.g., pulses) can be applied to the bit
lines and word lines in order to program data to and/or read data
from the memory cells 207. The memory cells 207 can be programmed
to a set state (e.g., low resistance) or a reset state (e.g., high
resistance). As an example, the data stored by a memory cell 207 of
array 201 can be determined by turning on a select device and
sensing a current through the memory element. The current sensed on
the bit line corresponding to the memory cell 207 being read
corresponds to a resistance level of the memory element (e.g., a
resistance level of a resistance variable material) which in turn
may correspond to a particular data state (e.g., a binary value).
The array 201 can have an architecture other than that illustrated
in FIG. 2, as will be understood by one of ordinary skill in the
art.
[0027] The array 201 can be a two dimensional array. For example,
the memory cells 207 of the array 201 can be arranged between the
access lines, 203-0, 203-1, . . . , 203-T and the data/sense lines,
205-0, 205-1, . . . , 205-S in a single level. The array 201 can be
a three dimensional array. For example, the memory cells of the
array can be arranged in multiple levels, where each of the
multiple levels has memory cells organized in a cross point
architecture. For three dimensional array embodiments of the
present disclosure, a vertical string of memory cells can be
coupled to a data line and a plurality of access lines coupled to
the vertical string of memory cells, for instance.
[0028] The access lines 203-0, 203-1, . . . , 203-T and the
data/sense lines 205-0, 205-1, . . . , 205-S can be coupled to
decoding circuits formed in a substrate material (e.g., formed
adjacent to or for example below) the array 201 and used to
interpret various signals (e.g., voltages and/or currents) on the
access lines and/or the data/sense lines. As an example, the
decoding circuits may include row decoding circuits for decoding
signals on the access lines, and column decoding circuits for
decoding signals on the data/sense lines.
[0029] As used in the present disclosure, the term substrate
material can include silicon-on-insulator (SOI) or
silicon-on-sapphire (SOS) technology, doped and undoped
semiconductors, epitaxial layers of silicon supported by a base
semiconductor foundation, conventional metal oxide semiconductors
(CMOS) (e.g., a CMOS front end with a metal backend) and/or other
semiconductor structures and technologies. Various elements (e.g.,
transistors, and/or circuitry), such as decode circuitry for
instance, associated with operating the array 201 can be formed
in/on the substrate material such as via process steps to form
regions or junctions in the base semiconductor structure or
foundation.
[0030] The memory cells 207 can be formed using various processing
techniques such as atomic material deposition (ALD), physical vapor
deposition (PVD), chemical vapor deposition (CVD), supercritical
fluid deposition (SFD), molecular beam expitaxy (MBE), patterning,
etching, filling, chemical mechanical planarization (CMP),
combinations thereof, and/or other suitable processes. In
accordance with a number of embodiments of the present disclosure,
materials may be grown in situ.
[0031] FIG. 3 illustrates a diagram associated with performing
refresh in memory in accordance with a number of embodiments of the
present disclosure. The monitor circuitry (e.g., monitor circuitry
118 in FIG. 1B) can track the threshold voltage 330 of a portion of
memory cells in the array of memory cells, (e.g., a monitor array
of memory cells). Tracking the threshold voltage 330 of a portion
of memory cells (e.g., the monitor array) can be executed via a
controller configured to apply a current to the portion of the
array of memory cells and measure a voltage associated with the
portion of memory cells. The current can be applied during set
periods of time (e.g., periodically) or can be applied
continuously. The controller can be configured to refresh a portion
of the memory cells in the array in response to the portion of
memory cells (e.g., the monitor array) having a threshold voltage
and/or threshold voltages that are greater than a reference
voltage. Refreshing the array of memory cells can improve read
margin of the array of memory cells.
[0032] The memory cells of the monitor array can be programmed to a
particular data state (e.g., a first state voltage 326 or to a
second state voltage 322, for example). In this example for
illustration, the memory cells of the monitor array are initially
programmed to a first state voltage 326. However, embodiments are
not limited to memory cells initially programmed to a first state
voltage 326. The controller (e.g., controller 114 in FIG. 1B) can
refresh the array of memory cells in response to the memory cells
in the monitor array having threshold voltages 330 that are greater
than a reference voltage 324. The reference voltage 324 can be
determined by the threshold voltage 330 being within a set margin
334 of the second state voltage 322 (e.g., a reference voltage for
the second state). The set margin 334 can depend on the speed and
the size of the memory device to have enough time to do a refresh
operation before memory cells programmed to the first state 326
reach the second state voltage 322. When the threshold voltage 330
of memory cells in the monitor array reaches the reference voltage
324, a refresh operation can be enabled 328. A refresh operation
can reprogram at least a portion of the array of memory cells to a
data state which they were previously programmed. For example,
memory cells programmed to state 326 and have their threshold
voltage change over time, as show in FIG. 3, can be programmed so
their threshold voltage returns to state 326 during a refresh
operation. When the refresh operation is completed 332, the memory
cells of the array can be programmed to the state which they had
been previously programmed. In this example, the memory cells in
the array initially programmed to state 326 can be reprogrammed to
a threshold voltage associated with the state 326. However, if the
memory cells were initially programmed to state 322, the memory
cells could be programmed to a threshold voltage associated with
the state 322 during a refresh operation. In one or more
embodiments, a first number of memory cells in the array can be
programmed to the state 326 and/or a second number of memory cells
in the array can be programmed to the state 322. During a refresh
operation, the first number of memory cells in the array can be
reprogrammed to the first state voltage 326 and/or the second
number of memory cells can be reprogrammed to the second state
voltage 322.
[0033] In one or more embodiments, the portion of memory cells that
are being monitored can be within one or more monitor arrays. The
memory cells in the monitor array can be connected in parallel via
a bit line. In one or more embodiments the number of memory cells
in the monitor array can depend on the reference voltage.
[0034] Although specific embodiments have been illustrated and
described herein, those of ordinary skill in the art will
appreciate that an arrangement calculated to achieve the same
results can be substituted for the specific embodiments shown. This
disclosure is intended to cover adaptations or variations of
various embodiments of the present disclosure. It is to be
understood that the above description has been made in an
illustrative fashion, and not a restrictive one. Combination of the
above embodiments, and other embodiments not specifically described
herein will be apparent to those of skill in the art upon reviewing
the above description. The scope of the various embodiments of the
present disclosure includes other applications in which the above
structures and methods are used. Therefore, the scope of various
embodiments of the present disclosure should be determined with
reference to the appended claims, along with the full range of
equivalents to which such claims are entitled.
[0035] In the foregoing Detailed Description, various features are
grouped together in a single embodiment for the purpose of
streamlining the disclosure. This method of disclosure is not to be
interpreted as reflecting an intention that the disclosed
embodiments of the present disclosure have to use more features
than are expressly recited in each claim. Rather, as the following
claims reflect, inventive subject matter lies in less than all
features of a single disclosed embodiment. Thus, the following
claims are hereby incorporated into the Detailed Description, with
each claim standing on its own as a separate embodiment.
* * * * *