U.S. patent application number 15/554751 was filed with the patent office on 2018-08-23 for memory diagnosis apparatus and memory diagnosis program.
This patent application is currently assigned to Mitsubishi Electric Corporation. The applicant listed for this patent is Mitsubishi Electric Corporation. Invention is credited to Takahiro AKIMOTO, Ryoya ICHIOKA, Ryoichi SASAKI.
Application Number | 20180240532 15/554751 |
Document ID | / |
Family ID | 56878663 |
Filed Date | 2018-08-23 |
United States Patent
Application |
20180240532 |
Kind Code |
A1 |
ICHIOKA; Ryoya ; et
al. |
August 23, 2018 |
MEMORY DIAGNOSIS APPARATUS AND MEMORY DIAGNOSIS PROGRAM
Abstract
A memory diagnosis apparatus to diagnose whether a fault occurs
in a memory includes a diagnosis execution unit to divide the
memory into a plurality of areas, select two or more base areas
that are diagnostic targets from among the areas to carry out a
memory diagnosis including a reading test and a writing test, and
perform only the writing test in carrying out the memory diagnosis
on a same base area for second or more times. The diagnosis
execution unit is implemented by an arithmetic device that is a
processing circuit that executes a memory diagnosis program stored
in a storage device.
Inventors: |
ICHIOKA; Ryoya; (Tokyo,
JP) ; SASAKI; Ryoichi; (Tokyo, JP) ; AKIMOTO;
Takahiro; (Tokyo, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Mitsubishi Electric Corporation |
Tokyo |
|
JP |
|
|
Assignee: |
Mitsubishi Electric
Corporation
Tokyo
JP
|
Family ID: |
56878663 |
Appl. No.: |
15/554751 |
Filed: |
March 10, 2015 |
PCT Filed: |
March 10, 2015 |
PCT NO: |
PCT/JP2015/057050 |
371 Date: |
August 31, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 12/16 20130101;
G11C 29/06 20130101; G11C 29/36 20130101; G11C 29/16 20130101; G11C
2029/4402 20130101; G11C 29/38 20130101 |
International
Class: |
G11C 29/38 20060101
G11C029/38; G11C 29/36 20060101 G11C029/36 |
Claims
1. A memory diagnosis apparatus to diagnose whether a fault occurs
in a memory, the memory diagnosis apparatus comprising a diagnosis
executor to divide the memory into a plurality of areas, select two
or more base areas as diagnostic targets from among the areas to
carry out a memory diagnosis including a reading test and a writing
test, and perform only the writing test in carrying out a memory
diagnosis on a same base area for second or more times.
2. The memory diagnosis apparatus according to claim 1, comprising:
a base-area diagnosis manager to receive from the diagnosis
executor a notification that the memory diagnosis on the base areas
has been completed, manage whether a memory diagnosis has been
carried out on each of the areas into which the memory is divided,
and reply to the diagnosis executor regarding whether a memory
diagnosis has been already carried out on an area about which the
diagnosis executor has inquired; and a base-area selector to select
base areas that are areas on which the memory diagnosis is to be
carried out, and inform the diagnosis executor of the selected base
areas, wherein the diagnosis executor inquires of the base-area
diagnosis manager whether a memory diagnosis has been carried out
on base areas informed from the base-area selector, and carries out
a memory diagnosis on the base areas informed from the base-area
selector, on a basis of a reply to the inquiry.
3. A non-transitory computer-readable medium storing a memory
diagnosis program to cause a programmable logic controller to
perform a process of diagnosing whether a fault occurs in a memory,
wherein the memory diagnosis program causes the programmable logic
controller to perform a process of dividing the memory into a
plurality of areas, and a process of selecting two or more base
areas as diagnostic targets from among the areas to carry out a
memory diagnosis including a reading test and a writing test, and
performing only the writing test in carrying out a memory diagnosis
on a same base area for second or more times.
4. The non-transitory computer-readable medium according to claim
3, wherein the memory diagnosis program causes the programmable
logic controller to function as a diagnosis executor to carry out
the memory diagnosis on the base areas, a base-area diagnosis
manager to receive from the diagnosis executor a notification that
the memory diagnosis on the base areas has been completed, manage
whether a memory diagnosis has been carried out on each of the
areas into which the memory is divided, and reply to the diagnosis
executor regarding whether a memory diagnosis has been already
carried out on an area about which the diagnosis executor has
inquired, and a base-area selector to select base areas that are
areas on which the memory diagnosis is to be carried out, and
inform the diagnosis executor of the selected base areas, wherein
the diagnosis executor inquires of the base-area diagnosis manager
whether a memory diagnosis has been carried out on base areas
informed from the base-area selector, and carries out a memory
diagnosis on the base areas informed from the base-area selector,
on a basis of a reply to the inquiry.
Description
FIELD
[0001] The present invention relates to a memory diagnosis
apparatus and a memory diagnosis program that detect a memory
fault.
BACKGROUND
[0002] As disclosed in Patent Literature 1, there has been a
conventionally-known technique to divide the memory to be diagnosed
into a plurality of areas, and perform a combination of two types
of commonly-known memory diagnoses on a combination of the divided
areas to thereby detect a memory fault.
[0003] It is common that a diagnosis on a memory applied to a
safety device is required to detect two types of faults referred to
as "coupling fault" and "stuck-at fault". The coupling fault is a
fault in which the value of a certain cell within the memory causes
an unwanted change in the value of another cell. The stuck-at fault
is a fault in which the value of a certain cell within the memory
is fixed at 0 or 1, and cannot be changed.
[0004] The necessary procedure to detect a coupling fault and a
stuck-at fault has been disclosed in Non Patent Literature 1.
CITATION LIST
Patent Literature
[0005] Patent Literature 1: Japanese Patent Application Laid-open
No. H10-154105
Non Patent Literature
[0005] [0006] Non Patent Literature 1: RAVINDRA NAIR, SATISH. M.
THATTE, AND JACOB A. ABRAHAM: Efficient Algorithms for Testing
Semiconductor Random-Access Memories. IEEE TRANSACTIONS ON
COMPUTERS, VOL. c-27, No. 6, JUNE 1978 pp. 572-576
SUMMARY
Technical Problem
[0007] However, the invention disclosed in Patent Literature 1
listed above carries out a fault diagnosis by dividing the memory
into a plurality of areas, and performing the same process on each
combination of the areas. This means that an omissible part of the
procedure in detecting a memory fault is repeatedly performed,
which poses a problem of a longer processing time.
[0008] The present invention has been achieved in view of the above
problems, and an object of the present invention is to provide a
memory diagnosis apparatus that reduces the processing time
required for a memory diagnosis without decreasing the diagnostic
rate.
Solution to Problem
[0009] To solve the problem and achieve the object, the present
invention provides a memory diagnosis apparatus to diagnose whether
a fault occurs in a memory, the memory diagnosis apparatus
comprising a diagnosis execution unit to divide the memory into a
plurality of areas, select two or more base areas as diagnostic
targets from among the areas to carry out a memory diagnosis
including a reading test and a writing test, and perform only the
writing test in carrying out a memory diagnosis on a same base area
for second or more times.
Advantageous Effects of Invention
[0010] The memory diagnosis apparatus of the present invention
achieves an effect of reducing the processing time required for the
memory diagnosis without decreasing the diagnostic rate.
BRIEF DESCRIPTION OF DRAWINGS
[0011] FIG. 1 is a diagram illustrating a functional configuration
of a memory diagnosis apparatus according to a first
embodiment.
[0012] FIG. 2 is a diagram illustrating a hardware configuration of
a programmable logic controller that implements the memory
diagnosis apparatus according to the first embodiment.
[0013] FIG. 3 is a diagram illustrating a configuration of the
memory diagnosis apparatus according to the first embodiment.
[0014] FIG. 4 is a flowchart illustrating an operation of the
memory diagnosis apparatus according to the first embodiment.
[0015] FIG. 5 is a schematic diagram illustrating an example of an
operation of the memory diagnosis apparatus according to the first
embodiment.
[0016] FIG. 6 is a schematic diagram illustrating another example
of the operation of the memory diagnosis apparatus according to the
first embodiment.
DESCRIPTION OF EMBODIMENT
[0017] An exemplary embodiment of a memory diagnosis apparatus and
a memory diagnosis program according to the present invention will
be described below in detail with reference to the accompanying
drawings. The present invention is not limited to the
embodiment.
First Embodiment
[0018] FIG. 1 is a diagram illustrating a functional configuration
of a memory diagnosis apparatus according to a first embodiment of
the present invention. A memory diagnosis apparatus 10 includes a
base-area diagnosis management unit 11. The base-area diagnosis
management unit 11 receives from a diagnosis execution unit 13
described later a notification that a memory diagnosis on any of
the divided memory areas has been completed, manages whether a
memory diagnosis has been already carried out on each of the
divided memory areas, and replies to the diagnosis execution unit
13 regarding whether a memory diagnosis has been already carried
out on an area about which the diagnosis execution unit 13 has
inquired. The memory diagnosis apparatus 10 further includes a
base-area selection unit 12. The base-area selection unit 12
selects base areas and informs the diagnosis execution unit 13 of
the selected base areas. The base area is a part of plural areas
into which the memory has been divided, and is a basic unit area on
which the memory diagnosis is carried out. The memory diagnosis
apparatus 10 further includes the diagnosis execution unit 13. The
diagnosis execution unit 13 inquires of the base-area diagnosis
management unit 11 whether base areas informed from the base-area
selection unit 12 has been already diagnosed, and performs a memory
diagnosis by carrying out reading tests and writing tests on the
base areas informed from the base-area selection unit 12. The
diagnosis execution unit 13 performs a reading test and a writing
test on each cell within the base area.
[0019] FIG. 2 is a diagram illustrating a hardware configuration of
a programmable logic controller that implements the memory
diagnosis apparatus according to the first embodiment. The
programmable logic controller is hereinafter represented as "PLC".
A PLC 50 is a device that controls a control-target device 80. The
PLC 50 includes an arithmetic device 51 that is a processing
circuit that performs software processing by executing a memory
diagnosis program, a memory 52 that is used as a working area by
the arithmetic device 51, a storage device 53 that stores therein
information, and a communication device 54 that communicates with
the control-target device 80. As the arithmetic device 51, a
central processing unit (CPU), or a system large scale integration
(system LSI) can be used. As the memory 52, a random access memory
(RAM) can be used. As the storage device 53, a hard disc drive or a
solid state drive can be used.
[0020] FIG. 3 is a diagram illustrating a configuration of the
memory diagnosis apparatus according to the first embodiment. The
memory diagnosis apparatus 10 is implemented by the PLC 50
executing a memory diagnosis program and performing software
processing. That is, when the PLC is executing an installed memory
diagnosis program 60 by the arithmetic device 51, the PLC is the
memory diagnosis apparatus 10. The base-area diagnosis management
unit 11, the base-area selection unit 12, and the diagnosis
execution unit 13 are implemented by the arithmetic device 51 that
is a processing circuit that executes the memory diagnosis program
60 stored in the storage device 53. A plurality of processing
circuits may cooperate with each other to implement the above
functions.
[0021] The memory diagnosis program 60 is executed in the
background of a control program 70 to be executed by the PLC 50 in
order to control the control-target device 80. That is, while
executing the control program 70 to control the control-target
device, the arithmetic device 51 executes the memory diagnosis
program 60 to carry out a memory diagnosis on the memory 52.
[0022] The memory diagnosis apparatus 10 according to the first
embodiment divides the memory 52 to be diagnosed, into a plurality
of areas, selects two or more areas as diagnostic targets from
among the areas, and carries out a commonly-known memory diagnosis
on the selected areas. Of the plural areas into which the memory 52
is divided, an area which is a diagnostic target is referred to as
"base area" in the following descriptions. The memory diagnosis
apparatus 10 changes a combination of the areas that are the base
areas, to repeatedly carry out the memory diagnosis thereon, and
defines all the combinations of the areas as base areas. In the
manner as described above, the memory diagnosis apparatus 10
detects a coupling fault between the cells in all the combinations
within the memory 52.
[0023] In carrying out the memory diagnosis on the base area on
which the memory diagnosis has already been carried out, the
diagnosis execution unit 13 omits the reading test on this base
area. The diagnostic procedure that is capable of detecting a
stuck-at fault and a coupling fault has been already determined as
disclosed in Non Patent Literature 1. Even when the diagnosis
execution unit 13 omits the reading test on the area on which the
memory diagnosis has been already carried out, the procedure
necessary to be capable of detecting a stuck-at fault and a
coupling fault for all the cells is still satisfied. Since the
diagnosis execution unit 13 omits the reading test on the area on
which the memory diagnosis has been already carried out, the memory
diagnosis apparatus 10 can complete the memory diagnosis that is
capable of detecting a coupling fault in a shorter time as compared
to the case where the reading test is not omitted.
[0024] The following description is made as to the operation of the
memory diagnosis apparatus where two of the areas into which the
memory is divided are selected as base areas. However, as described
later, three or more areas may be selected as base areas from among
the areas into which the memory is divided.
[0025] FIG. 4 is a flowchart illustrating an operation of the
memory diagnosis apparatus according to the first embodiment. At
Step S101, the memory diagnosis apparatus 10 selects two areas as
base areas that are diagnostic targets from among the areas into
which the memory is divided. Specifically, the diagnosis execution
unit 13 inquires of the base-area selection unit 12 about base
areas that are targets for the memory diagnosis. The base-area
selection unit 12 selects base areas as diagnostic targets, and
informs the diagnosis execution unit 13 of these selected base
areas. The order of selecting different base areas within the
memory is not limited to a particular order. Any order can be
employed as long as all the combinations of the areas into which
the memory 52 is divided are eventually selected.
[0026] At Step S102, the memory diagnosis apparatus 10 determines
whether the memory diagnosis has been carried out on the selected
base areas. Specifically, the diagnosis execution unit 13 inquires
of the base-area diagnosis management unit 11 whether the memory
diagnosis has been already carried out on the base areas informed
from the base-area selection unit 12, in order to confirm whether
the selected base areas have been already diagnosed.
[0027] When the memory diagnosis has not been previously carried
out on the base areas selected by the base-area selection unit 12,
the reply to the inquiry at Step S102 is "NO". At Step S103, on the
basis of the reply from the base-area diagnosis management unit 11,
the diagnosis execution unit 13 carries out the memory diagnosis on
the base areas selected by the base-area selection unit 12. The
memory diagnosis in this example is a common memory diagnosis that
carries out a reading diagnosis and a writing diagnosis. When Step
S103 is finished, the process proceeds to Step S105.
[0028] When the memory diagnosis has been previously carried out on
the base areas selected by the base-area selection unit 12, the
reply to the inquiry at Step S102 is "YES". At Step S104, on the
basis of the reply from the base-area diagnosis management unit 11,
the diagnosis execution unit 13 performs only writing tests on the
base areas on which the memory diagnosis has been previously
carried out. When Step S104 is finished, the process proceeds to
Step S105.
[0029] At Step S105, the memory diagnosis apparatus 10 sets the
base areas on which the memory diagnosis has been carried out, as
the diagnosed base areas. Specifically, after the memory diagnosis
on the base areas has been completed, the diagnosis execution unit
13 informs the base-area diagnosis management unit 11 of the base
areas on which the memory diagnosis has been finished. The
base-area diagnosis management unit 11 memorizes the completion of
the diagnosis on the base areas informed from the diagnosis
execution unit 13.
[0030] At Step S106, the memory diagnosis apparatus 10 determines
whether there is an area that should be diagnosed next.
Specifically, the diagnosis execution unit 13 inquires of the
base-area diagnosis management unit 11 about an area that should be
diagnosed next among the areas into which the memory 52 is divided.
When the base area that should be diagnosed next is not conveyed
from the base-area diagnosis management unit 11, the diagnosis
execution unit 13 determines that the memory diagnosis has been
already carried out on all the combinations of the areas into which
the memory 52 is divided, and therefore there is no base area that
should be diagnosed next (NO at Step S106), and then finishes the
memory diagnosis. When the base area that should be diagnosed next
is conveyed from the base-area diagnosis management unit 11, the
diagnosis execution unit 13 determines that there is a base area
that should be diagnosed next (YES at Step S106), and then the
process returns to Step S101.
[0031] FIG. 5 is a schematic diagram illustrating an example of an
operation of the memory diagnosis apparatus according to the first
embodiment. In this example, the memory 52 is divided into three
areas m.sub.1, m.sub.2, and m.sub.3. In FIG. 5, the areas
surrounded by the dotted line are base areas.
[0032] The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.1 and m.sub.2
selected as the base areas in a cycle "t". The memory diagnosis
apparatus 10 carries out the commonly-known memory diagnosis on the
areas m.sub.1 and m.sub.3 selected as the base areas in a cycle
"t+1". The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.2 and m.sub.3
selected as the base areas in a cycle "t+2". The commonly-known
memory diagnosis in this example is a memory diagnosis that detects
a memory fault by performing the reading test and the writing test
on a cell of the memory 52, and determining whether the test
results match the expected values. Examples of the commonly-known
memory diagnosis include "Abraham" and "March". These
commonly-known memory diagnoses show the diagnosis method of using
various algorithms that process different combinations of cells in
different orders, in accordance with the diagnostic processing time
and the diagnostic rate, to execute the process of "writing and
reading a value to and from a cell of the memory, and confirming
whether the read value matches the written value".
[0033] The diagnosis execution unit 13 performs the reading tests
and writing tests on the areas m.sub.1 and m.sub.2 that are the
base areas in the cycle "t" because there are no areas on which the
memory diagnosis has been carried out.
[0034] The diagnosis execution unit 13 omits the reading test on
the area m.sub.1 and performs only the writing test on the area
m.sub.1 in the cycle "t+1" because the diagnosis execution unit 13
has already carried out the memory diagnosis on the area m.sub.1 in
the cycle "t". Meanwhile, the diagnosis execution unit 13 performs
the reading test and the writing test on the area m.sub.3 that is
the base area.
[0035] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.2 and m.sub.3 and only performs the writing tests
on the areas m.sub.2 and m.sub.3 in the cycle "t+2" because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the area m.sub.2 in the cycle "t" and on the area
m.sub.3 in the cycle "t+1".
[0036] FIG. 6 is a schematic diagram illustrating another example
of the operation of the memory diagnosis apparatus according to the
first embodiment. In this example, the memory 52 is divided into
five areas from m.sub.1 to m.sub.5. Further, in this example, the
memory diagnosis apparatus 10 selects three of the areas as base
areas. In FIG. 6, the areas surrounded by the dotted line are the
base areas.
[0037] The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.1, m.sub.2, and
m.sub.3 as the base areas in the cycle "t". The memory diagnosis
apparatus 10 carries out the commonly-known memory diagnosis on the
areas m.sub.1, m.sub.2, and m.sub.4 as the base areas in the cycle
"t+1". The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.1, m.sub.2, and
m.sub.5 as the base areas in the cycle "t+2". The memory diagnosis
apparatus 10 carries out the commonly-known memory diagnosis on the
areas m.sub.1, m.sub.3, and m.sub.4 as the base areas in a cycle
"t+3". The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.1, m.sub.3, and
m.sub.5 as the base areas in a cycle "t+4". The memory diagnosis
apparatus 10 carries out the commonly-known memory diagnosis on the
areas m.sub.1, m.sub.4, and m.sub.5 as the base areas in a cycle
"t+5". The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.2, m.sub.3, and
m.sub.4 as the base areas in a cycle "t+6". The memory diagnosis
apparatus 10 carries out the commonly-known memory diagnosis on the
areas m.sub.2, m.sub.3, and m.sub.5 as the base areas in a cycle
"t+7". The memory diagnosis apparatus 10 carries out the
commonly-known memory diagnosis on the areas m.sub.2, m.sub.4, and
m.sub.5 as the base areas in a cycle "t+8". The memory diagnosis
apparatus 10 carries out the commonly-known memory diagnosis on the
areas m.sub.3, m.sub.4, and m.sub.5 as the base areas in a cycle
"t+9".
[0038] The diagnosis execution unit 13 performs the reading tests
and the writing tests on the areas m.sub.1, m.sub.2, and m.sub.3
that are the base areas in the cycle "t" because there are no areas
on which the memory diagnosis has been carried out.
[0039] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.1 and m.sub.2 and performs only the writing tests
on these areas in the cycle "t+1", because the diagnosis execution
unit 13 has already carried out the memory diagnosis on the areas
m.sub.1 and m.sub.2 in the cycle "t".
[0040] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.1 and m.sub.2 and performs only the writing tests
on these areas in the cycle "t+2", because the diagnosis execution
unit 13 has already carried out the memory diagnosis on the areas
m.sub.1 and m.sub.2 in the cycle "t".
[0041] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.1, m.sub.3, and m.sub.4, and performs only the
writing tests on these areas in the cycle "t+3", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the areas m.sub.1 and m.sub.3 in the cycle "t", and on
the area m.sub.4 in the cycle "t+1".
[0042] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.1, m.sub.3, and m.sub.5 and performs only the
writing tests on these areas in the cycle "t+4", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the areas m.sub.1 and m.sub.3 in the cycle "t", and on
the area m.sub.5 in the cycle "t+2".
[0043] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.1, m.sub.4, and m.sub.5, and performs only the
writing tests on these areas in the cycle "t+5", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the area m1 in the cycle "t", on the area m.sub.4 in
the cycle "t+1", and on the area m.sub.5 in the cycle "t+2".
[0044] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.2, m.sub.3, and m.sub.4, and performs only the
writing tests on these areas in the cycle "t+6", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the areas m.sub.2 and m.sub.3 in the cycle "t", and on
the area m.sub.4 in the cycle "t+1".
[0045] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.2, m.sub.3, and m.sub.5, and performs only the
writing tests on these areas in the cycle "t+7", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the areas m.sub.2 and m.sub.3 in the cycle "t", and on
the area m.sub.5 in the cycle "t+2".
[0046] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.2, m.sub.4, and m.sub.5, and performs only the
writing tests on these areas in the cycle "t+8", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the area m.sub.2 in the cycle "t", on the area m.sub.4
in the cycle "t+1", and on the area m.sub.5 in the cycle "t+2".
[0047] The diagnosis execution unit 13 omits the reading tests on
the areas m.sub.3, m.sub.4, and m.sub.5, and performs only the
writing tests on these areas in the cycle "t+9", because the
diagnosis execution unit 13 has already carried out the memory
diagnosis on the area m.sub.3 in the cycle "t", on the area m.sub.4
in the cycle "t+1", and on the area m.sub.5 in the cycle "t+2".
[0048] When carrying out the memory diagnosis on the base area that
is the area on which the reading test has been already performed,
the memory diagnosis apparatus 10 according to the first embodiment
omits the reading test on this base area on which the reading test
has been already performed, thereby eliminating the redundant
process. This enables the memory diagnosis apparatus 10 according
to the first embodiment to reduce the processing time without
decreasing the diagnostic rate.
[0049] The above descriptions have been made as to the the example
in which the arithmetic device 51 in the PLC 50 executes the memory
diagnosis program 60 in the background of the control program 70 to
carry out the memory diagnosis on the memory 52. However, an
external computer can be connected to the PLC 50 to cause the
computer to execute the memory diagnosis program so as to carry out
the memory diagnosis. The processing load on the arithmetic device
51 in the PLC 50 can be reduced by causing the external computer
connected to the PLC 50 to execute the memory diagnosis program so
as to carry out the memory diagnosis. This makes it possible for
the PLC 50 to more accurately perform a control operation on the
control-target device 80.
[0050] The configuration described in the above embodiment is only
an example of the contents of the present invention. The
configuration can be combined with other well-known techniques, and
a part of the configuration can be omitted or changed without
departing from the scope of the invention.
REFERENCE SIGNS LIST
[0051] 10 memory diagnosis apparatus [0052] 11 base-area diagnosis
management unit [0053] 12 base-area selection unit [0054] 13
diagnosis execution unit [0055] 50 PLC [0056] 51 arithmetic device
[0057] 52 memory [0058] 53 storage device [0059] 60 memory
diagnosis program [0060] 70 control program [0061] 80
control-target device
* * * * *