U.S. patent application number 15/786118 was filed with the patent office on 2018-08-16 for display device.
The applicant listed for this patent is Samsung Display Co. Ltd.. Invention is credited to Dong Beom CHO, Song Yi HAN, Dae Sik LEE, Hee Bum PARK.
Application Number | 20180233105 15/786118 |
Document ID | / |
Family ID | 63105391 |
Filed Date | 2018-08-16 |
United States Patent
Application |
20180233105 |
Kind Code |
A1 |
CHO; Dong Beom ; et
al. |
August 16, 2018 |
DISPLAY DEVICE
Abstract
A display device includes a display panel including a plurality
of pixels which are connected to a plurality of gate lines and a
plurality of data lines and display a plurality of consecutive
frames of images, a data driver driving the data lines, a gate
driver driving the gate lines, a clock generator outputting a gate
clock signal, which drives the gate driver and swings between a
gate-on voltage and a gate-off voltage, and a signal controller
outputting a gate pulse signal which drives the clock generator and
a data control signal which controls the data driver. The clock
generator includes a voltage maintainer maintaining the gate clock
signal at a reference voltage that has a fixed value between the
gate-on voltage and the gate-off voltage for a predetermined
time.
Inventors: |
CHO; Dong Beom;
(Hwaseong-si, KR) ; PARK; Hee Bum; (Seongnam-si,
KR) ; LEE; Dae Sik; (Hwaseong-si, KR) ; HAN;
Song Yi; (Asan-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Samsung Display Co. Ltd. |
Yongin-si |
|
KR |
|
|
Family ID: |
63105391 |
Appl. No.: |
15/786118 |
Filed: |
October 17, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G09G 2370/08 20130101;
G09G 3/2003 20130101; G09G 5/18 20130101; G09G 2310/0267 20130101;
G09G 2300/0426 20130101; G09G 3/204 20130101; G09G 2310/0289
20130101; G09G 3/3677 20130101; G09G 5/008 20130101; G09G 3/3266
20130101; G09G 3/3696 20130101; G09G 2310/0272 20130101; G09G
3/2096 20130101 |
International
Class: |
G09G 5/00 20060101
G09G005/00; G09G 3/20 20060101 G09G003/20 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 15, 2017 |
KR |
10-2017-0020594 |
Claims
1. A display device, comprising: a display panel including a
plurality of pixels which are connected to a plurality of gate
lines and a plurality of data lines and display a plurality of
consecutive frames of images; a data driver which drives the data
lines; a gate driver which drives the gate lines; a clock generator
which outputs a gate clock signal which drives the gate driver and
swings between a gate-on voltage and a gate-off voltage; and a
signal controller which outputs a gate pulse signal which drives
the clock generator and a data control signal which controls the
data driver, wherein the clock generator includes a voltage
maintainer which maintains the gate clock signal at a reference
voltage that has a fixed value between the gate-on voltage and the
gate-off voltage for a predetermined time.
2. The display device of claim 1, wherein the voltage maintainer
maintains the gate clock signal at the reference voltage during a
blank period between two consecutive frames among the plurality of
consecutive frames.
3. The display device of claim 1, wherein the voltage maintainer
receives the gate-on voltage and the gate-off voltage and outputs
the reference voltage by dividing the gate-on voltage and the
gate-off voltage.
4. The display device of claim 3, wherein the reference voltage is
a median value of the gate-on voltage and the gate-off voltage.
5. The display device of claim 1, wherein the clock generator
provides a gate clock bar signal to the gate driver, and the gate
clock signal and the gate clock bar signal are opposite in phase
and are symmetrical to each other.
6. The display device of claim 1, wherein the clock generator
further includes a gate clock generator which generates the gate
clock signal using the gate-on voltage and the gate-off
voltage.
7. The display device of claim 6, wherein the gate clock generator
includes a first switching circuit which provides one of the
gate-on voltage and the gate-off voltage to an output terminal of
the clock generator in response to the gate pulse signal.
8. The display device of claim 6, wherein the gate clock generator
includes a charge sharer which makes a voltage provided to an
output terminal of the clock generator swing.
9. The display device of claim 8, wherein an output terminal of the
voltage maintainer is connected to the charge sharer.
10. The display device of claim 8, wherein the gate clock generator
further includes a second switching circuit which connects the
output terminal of the clock generator to one of the charge sharer
and a first switching circuit which provides one of the gate-on
voltage and the gate-off voltage in response to the gate pulse
signal.
11. The display device of claim 8, wherein the gate clock generator
further includes a third switching circuit which provides one of
the gate-on voltage and the gate-off voltage to the charge sharer
in response to the gate pulse signal.
12. A display device, comprising: a display panel including a
plurality of pixels which are connected to a plurality of gate
lines and a plurality of data lines and display a plurality of
consecutive frames of images; a data driver which drives the data
lines; a gate driver which drives the gate lines; a clock generator
which outputs a gate clock signal which drives the gate driver and
swings between a gate-on voltage and a gate-off voltage; and a
signal controller which outputs a gate pulse signal which drives
the clock generator and a data control signal which controls the
data driver, wherein the clock generator includes an impedance
control circuit which controls a slew rate of the gate clock
signal.
13. The display device of claim 12, wherein the clock generator
further includes a gate clock generator which generates the gate
clock signal using the gate-on voltage and the gate-off
voltage.
14. The display device of claim 13, wherein the gate clock
generator includes a first switching circuit which provides one of
the gate-on voltage and the gate-off voltage in response to the
gate pulse signal, a charge sharer which provides a voltage which
swings between the gate-on voltage and the gate-off voltage, and a
second switching circuit which connects an output terminal of the
clock generator to one of the charge sharer and the first switching
circuit in response to the gate pulse signal.
15. The display device of claim 14, wherein the impedance control
circuit includes a first impedance control circuit which controls
the slew rate of the gate clock signal during a period when the
gate clock signal swings from one of the gate-on voltage and the
gate-off voltage to a reference voltage between the gate-on voltage
and the gate-off voltage, and the first impedance control circuit
is connected between the second switching circuit and the charge
sharer.
16. The display device of claim 14, wherein the impedance control
circuit includes a second impedance control circuit which controls
the slew rate of the gate clock signal during a period when the
gate clock signal swings from a reference voltage between the
gate-on voltage or the gate-off voltage to one of the gate-on
voltage and the gate-off voltage, and the second impedance control
circuit is connected between the first and second switching
circuits.
17. A display device, comprising: a display panel including a
plurality of pixels which are connected to a plurality of gate
lines and a plurality of data lines and display a plurality of
consecutive frames of images; a data driver which drives the data
lines; a gate driver which drives the gate lines; a clock generator
which outputs a gate clock signal which drives the gate driver and
swings between a gate-on voltage and a gate-off voltage; and a
signal controller which outputs a gate pulse signal which drives
the clock generator and a data control signal which controls the
data driver, wherein the clock generator includes an impedance
control circuit which delays or advance the gate clock signal.
18. The display device of claim 17, wherein the clock generator
further includes a gate clock generator which generates the gate
clock signal using the gate-on voltage and the gate-off
voltage.
19. The display device of claim 18, wherein the gate clock
generator includes a first switching circuit which provides one of
the gate-on voltage and the gate-off voltage in response to the
gate pulse signal, a charge sharer which provides a voltage which
swings between the gate-on voltage and the gate-off voltage, and a
second switching circuit which connects an output terminal of the
clock generator to one of the charge sharer and the first switching
circuit in response to the gate pulse signal.
20. The display device of claim 19, wherein the impedance control
circuit is connected between the second switching circuit and the
output terminal of the clock generator.
Description
[0001] This application claims priority to Korean Patent
Application No. 10-2017-0020594, filed on Feb. 15, 2017, and all
the benefits accruing therefrom under 35 U.S.C. .sctn. 119, the
content of which in its entirety is herein incorporated by
reference.
BACKGROUND
1. Field
[0002] Exemplary embodiments relate to a display device for
displaying an image.
2. Description of the Related Art
[0003] It has become preferable to mount a display device on an
electronic device as a user interface, and various types of display
devices have been developed accordingly. Typically, a liquid
crystal display ("LCD") is a device for displaying an image by
controlling the amount of light coming from the outside thereof,
and an organic light-emitting diode ("OLED") display is a device
for displaying an image using a fluorescent organic compound that
emits light in response to a current being applied thereto.
[0004] In general, a display device includes a display panel for
displaying an image and a data driver and a gate driver for driving
the display panel. The display panel includes a plurality of gate
lines, a plurality of data lines, and a plurality of pixels. The
data driver and the gate driver provide voltages for driving the
pixels to the data lines and the gate lines, respectively.
SUMMARY
[0005] The gate driver may be controlled by a gate clock signal
provided by a clock generator. Even though the gate clock signal is
required to be maintained at a predetermined voltage during a blank
period between consecutive frames that form images displayed on the
display device, but may not be able to be consistently maintained
at the predetermined voltage because of current leakage. Thus, a
structure is desired to maintain the gate clock signal at the
predetermined, fixed voltage during the blank period.
[0006] Also, a structure is desired to improve the response speed
of the gate clock signal and eliminate delays in the gate clock
signal.
[0007] Exemplary embodiments of the invention provide a display
device capable of maintaining a gate clock signal at a
predetermined voltage during a blank period.
[0008] Exemplary embodiments of the invention provide a display
device capable of improving the response speed of a gate clock
signal or eliminating delays in the gate clock signal.
[0009] However, the invention is not restricted to those set forth
herein. The above and other exemplary embodiments of the invention
will become more apparent to one of ordinary skill in the art to
which the invention pertains by referencing the detailed
description of the invention given below.
[0010] According to an exemplary embodiment of the invention, a
display device includes a display panel including a plurality of
pixels which are connected to a plurality of gate lines and a
plurality of data lines and display a plurality of consecutive
frames of images, a data driver which drives the data lines, a gate
driver which drives the gate lines, a clock generator which outputs
a gate clock signal which drives the gate driver and swings between
a gate-on voltage and a gate-off voltage, and a signal controller
which outputs a gate pulse signal, which drives the clock generator
and a data control signal which controls the data driver, where the
clock generator includes a voltage maintainer which maintains the
gate clock signal at a reference voltage that has a fixed value
between the gate-on voltage and the gate-off voltage for a
predetermined time.
[0011] According to another exemplary embodiment of the invention,
a display device includes a display panel including a plurality of
pixels which are connected to a plurality of gate lines and a
plurality of data lines and display a plurality of consecutive
frames of images, a data driver which drives the data lines, a gate
driver which drives the gate lines, a clock generator which outputs
a gate clock signal which drives the gate driver and swings between
a gate-on voltage and a gate-off voltage, and a signal controller
which outputs a gate pulse signal which drives the clock generator
and a data control signal which controls the data driver, where the
clock generator includes an impedance control circuit which
controls a slew rate of the gate clock signal.
[0012] According to still another exemplary embodiment of the
invention, a display device includes a display panel including a
plurality of pixels which are connected to a plurality of gate
lines and a plurality of data lines and display a plurality of
consecutive frames of images, a data driver which drives the data
lines, a gate driver which drives the gate lines, a clock generator
which outputs a gate clock signal which drives the gate driver and
swings between a gate-on voltage and a gate-off voltage, and a
signal controller which outputs a gate pulse signal which drives
the clock generator and a data control signal which controls the
data driver, where the clock generator includes an impedance
control circuit which delays or advance the gate clock signal.
[0013] According to the aforementioned and other exemplary
embodiments of the invention, a display device capable of
maintaining a gate clock signal at a predetermined voltage during a
blank period can be provided.
[0014] Also, a display device capable of improving the response
speed of a gate clock signal or eliminating a delay in the gate
clock signal can be provided.
[0015] Other features and exemplary embodiments may be apparent
from the following detailed description, the drawings, and the
claims to persons of ordinary skill in the art.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above and other exemplary embodiments and features of
the invention will become more apparent by describing in detail
exemplary embodiments thereof with reference to the attached
drawings, in which:
[0017] FIG. 1 is a block diagram of an exemplary embodiment of a
display device according to the invention;
[0018] FIG. 2 is a circuit diagram of an exemplary embodiment of a
clock generator illustrated in FIG. 1;
[0019] FIG. 3 is a waveform diagram showing an exemplary embodiment
of the waveforms of a gate clock signal and a gate clock bar signal
during a blank period;
[0020] FIG. 4 is a block diagram of another exemplary embodiment of
a clock generator of a display device according to the
invention;
[0021] FIG. 5 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention;
[0022] FIG. 6 is a waveform diagram showing an exemplary embodiment
of the waveform of a gate clock signal generated by the clock
generator of FIG. 5 during a period corresponding to a period A of
FIG. 2;
[0023] FIG. 7 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention;
[0024] FIG. 8 is a waveform diagram showing an exemplary embodiment
of the waveform of a gate clock signal generated by the clock
generator of FIG. 7 during a period corresponding to the period A
of FIG. 2;
[0025] FIG. 9 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention;
[0026] FIGS. 10 and 11 are waveform diagrams showing exemplary
embodiments of the waveforms of a gate clock signal generated by
the clock generator of FIG. 9 during a period corresponding to a
period B of FIG. 2;
[0027] FIG. 12 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention; and
[0028] FIG. 13 is a waveform diagram showing an exemplary
embodiment of the waveforms of a gate clock signal and a gate clock
bar signal generated by the clock generator of FIG. 12.
DETAILED DESCRIPTION
[0029] The invention will now be described more fully hereinafter
with reference to the accompanying drawings, in which exemplary
embodiments of the invention are shown. This invention may,
however, be embodied in different forms and should not be construed
as limited to the exemplary embodiments set forth herein. Rather,
these exemplary embodiments are provided such that this disclosure
will be thorough and complete, and will filly convey the scope of
the invention to those skilled in the art. The same reference
numbers indicate the same components throughout the specification.
In the attached figures, the thickness of layers and regions is
exaggerated for clarity.
[0030] It will be understood that, although the terms first,
second, third, etc., may be used herein to describe various
elements, these elements should not be limited by these terms.
These terms are only used to distinguish one element from another
element. Thus, a first element discussed below could be termed a
second element without departing from the teachings of the
invention.
[0031] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting. As
used herein, the singular forms "a," "an," and "the" are intended
to include the plural forms, including "at least one," unless the
content clearly indicates otherwise. "Or" means "and/or." As used
herein, the term "and/or" includes any and all combinations of one
or more of the associated listed items. It will be further
understood that the terms "comprises" and/or "comprising," or
"includes" and/or "including" when used in this specification,
specify the presence of stated features, regions, integers, steps,
operations, elements, and/or components, but do not preclude the
presence or addition of one or more other features, regions,
integers, steps, operations, elements, components, and/or groups
thereof.
[0032] Spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. It
will be understood that the spatially relative terms are intended
to encompass different orientations of the device in use or
operation in addition to the orientation depicted in the figures.
For example, if the device in the figures is turned over, elements
described as "below" or "beneath" other elements or features would
then be oriented "above" the other elements or features. Thus, the
exemplary term "below" can encompass both an orientation of above
and below. The device may be otherwise oriented (rotated 90 degrees
or at other orientations) and the spatially relative descriptors
used herein interpreted accordingly.
[0033] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this
disclosure belongs. It will be further understood that terms, such
as those defined in commonly used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and the invention, and
will not be interpreted in an idealized or overly formal sense
unless expressly so defined herein.
[0034] Hereinafter, exemplary embodiments of the invention will be
described with reference to the attached drawings.
[0035] FIG. 1 is a block diagram of an exemplary embodiment of a
display device according to the invention.
[0036] Referring to FIG. 1, the display device according to the
exemplary embodiment of FIG. 1 includes a display panel 110, a
signal controller 210, a clock generator 220, a gate driver 230,
and a data driver 240.
[0037] The display panel 110 includes a plurality of data lines DL1
through DLm extending in a first direction dr1 and a plurality of
gate lines GL1 through GLn extending in a second direction dr2 to
intersect the data lines DL1 through DLm and further includes a
plurality of pixels PX arranged in a matrix form at the
intersections between the data lines DL1 through DLm and the gate
lines GL1 through GLn. The data lines DL1 through DLm and the gate
lines GL1 through GLn are insulated from each other.
[0038] Although not specifically illustrated, each of the pixels PX
includes a switching transistor (not illustrated) connected to one
of the data lines DL1 through DLm and one of the gate lines GL1
through GLn, and a liquid crystal capacitor (not illustrated) and a
storage capacitor (not illustrated) which are connected to the
switching transistor. FIG. 1 illustrates an example in which the
pixels of a liquid crystal display ("LCD") are arranged in the
display panel 110, but the invention is not limited thereto. That
is, in an alternative embodiment, the pixels PX of an organic
light-emitting diode ("OLED") display device may be arranged in the
display panel 110.
[0039] The signal controller 210 receives control signals CTRL for
controlling an image signal RGB and controlling the display of the
image signal RGB and the control signals CTRL may include, for
example, a vertical synchronization signal, a horizontal
synchronization signal, a main clock signal, and a data enable
signal, from an external source, in an exemplary embodiment. The
signal controller 210 outputs a data signal DATA, which is obtained
by processing the image signal RGB based on the control signals
CTRL to be compatible with the operating conditions of the display
panel 110, and a first driving control signal CONT1 to the data
driver 240 and provides a second driving control signal CONT2 to
the gate driver 230. In an exemplary embodiment, the first driving
control signal CONT1 may include a horizontal synchronization start
signal, a clock signal, and a line latch signal, and the second
driving control signal CONT2 may include a vertical synchronization
start signal STV, and an output enable signal, for example. Also,
the signal controller 210 provides a gate pulse signal CPV to the
clock generator 220.
[0040] The data driver 240 generates a gray voltage for driving
each of the data lines DL1 through DLm in accordance with the data
signal DATA and the first driving control signal CONT1, provided by
the signal controller 210.
[0041] The clock generator 220 generates a gate clock signal CKV
and a gate clock bar signal CKBV in response to the gate pulse
signal CPV provided by the signal controller 210, and provides the
gate clock signal CKV and the gate clock bar signal CKBV to the
gate driver 230. The clock generator 220 may receive a gate-on
voltage Von and a gate-off voltage Voff from an external source and
may generate the gate clock signal CKV and the gate clock bar
signal CKBV based on the gate-on voltage Von and the gate-off
voltage Voff.
[0042] FIG. 1 illustrates an example in which a pair of clock
signals, i.e., the gate clock signal CKV and the gate clock bar
signal CKBV, are generated, but the invention is not limited
thereto. That is, in an alternative embodiment, two pairs of clock
signals, i.e., a first gate clock signal (not illustrated), a
second gate clock signal (not illustrated), a first gate clock bar
signal (not illustrated), and a second gate clock bar signal (not
illustrated), may be generated and may then be provided to the gate
driver 230.
[0043] The gate driver 230 drives the gate lines GL1 through GLm in
response to the second driving control signal CONT2, provided by
the signal controller 210, and the gate clock signal CKV and the
gate clock bar signal CKBV, provided by the clock generator 220.
The gate driver 230 may be implemented not only as a gate driving
integrated circuit ("IC"), but also as a circuit using an amorphous
silicon thin-film transistor ("a-Si TFT")), an oxide semiconductor,
a crystalline semiconductor, or a polycrystalline semiconductor,
for example.
[0044] FIG. 2 is a circuit diagram an exemplary embodiment of the
clock generator illustrated in FIG. 1.
[0045] Referring to FIG. 2, the clock generator 220 includes a gate
clock generator 2261, a control signal generator 2262, and a
voltage maintainer 2263.
[0046] The gate clock generator 2261 generates the gate clock
signal CKV and the gate clock bar signal CKBV in response to
various control signals provided by the control signal generator
2262.
[0047] The control signal generator 2262 generates first through
sixth gate pulse signals CPV1 through CPV6, which may be used for
controlling various switching circuits of the gate clock generator
2261 and the voltage maintainer 2263, in response to the gate pulse
signal CPV provided by the signal controller 210.
[0048] The voltage maintainer 2263 may generate an arbitrary
voltage having a value between the gate-on voltage Von and the
gate-off voltage Voff using the gate-on voltage Von and the
gate-off voltage Voff and may provide the arbitrary voltage to the
gate clock generator 2261.
[0049] Specifically, the gate clock generator 2261 includes first
through fifth switching circuits SW1 through SW5 and a charge
sharer 22611.
[0050] The first switching circuit SW1 provides one of the gate-on
voltage Von and the gate-off voltage Voff to a first output
terminal Nout1 of the clock generator 220 as the gate clock signal
CKV through a second switching circuit SW2 in response to the first
gate pulse signal CPV1.
[0051] The second switching circuit SW2 may either connect the
first switching circuit SW1 and the first output terminal Nout1 of
the clock generator 220, or connect the charge sharer 22611 and the
first output terminal Nout1 of the clock generator 220, in response
to the second gate pulse signal CPV2, and then may output the gate
clock signal CKV to the first output terminal Nout1.
[0052] The third switching circuit SW3 may provide one of the
gate-on voltage Von and the gate-off voltage Voff to the charge
sharer 22611 in response to the third gate pulse signal CPV3.
[0053] The fourth switching circuit SW4 may provide one of the
gate-on voltage Von and the gate-off voltage Voff to the second
output terminal Nout2 of the clock generator 220 as the gate clock
bar signal CKBV through a fifth switching circuit SW5 in response
to the fourth gate pulse signal CPV4.
[0054] The fifth switching circuit SW5 may either connect the
fourth switching circuit SW4 and the second output terminal Nout2
of the clock generator 220, or connect the charge sharer 22611 and
the second output terminal Nout2 of the clock generator 220, in
response to the fifth gate pulse signal CPV5, and then may output
the gate clock bar signal CKBV to the second output terminal
Nout2.
[0055] The charge sharer 22611 couples the first and second output
terminals Nout1 and Nout2 of the clock generator 220 such that the
gate clock signal CKV and the gate clock bar signal CKBV output via
the first and second output terminals Nout1 and Nout2,
respectively, may be matched. To this end, the charge sharer 22611
may include a charge sharing resistor Rs, a first transistor TR1, a
second transistor TR2, and a shared amplifier Drv for driving the
charge sharing resistor Rs, the first transistor TR1, and the
second transistor TR2, but the structure of the charge sharer 22611
is not limited thereto. That is, any circuit configuration that can
match the gate clock signal CKV and the gate clock bar signal CKV
may be used.
[0056] Specifically, the charge sharer 22611 may make the gate
clock signal CKV and the gate clock bar signal CKBV swing from the
gate-on voltage Von to a reference voltage that ranges between the
gate-on voltage Von and the gate-off voltage Voff, or from the
gate-off voltage Voff to the reference voltage. The waveforms of
the gate clock signal CKV and the gate clock bar signal CKBV will
be described later.
[0057] The voltage maintainer 2263 includes first and second
divider resistors Rv1 and Rv2 dividing a voltage supplied thereto
and a sixth switching circuit SW6 providing the divided voltage to
the charge sharer 22611 in response to the sixth gate pulse signal
CPV6.
[0058] The sixth switching circuit SW6 may determine whether to
connect the charge sharer 22611 and the voltage maintainer 2263 in
response to the sixth gate pulse signal CPV6.
[0059] Specifically, the voltage maintainer 2263 may receive the
gate-on voltage Von and the gate-off voltage Voff and may output
the reference voltage produced by dividing the gate-on voltage Von
and the gate-off voltage Voff. The reference voltage may be a fixed
voltage at which the gate clock signal CKV and the gate clock bar
signal CKBV are required to be maintained during a blank period
("Blank" of FIG. 3) between periods of consecutive frames that form
images. During the blank period ("Blank" of FIG. 3), values of the
gate clock signal CKV and the gate clock bar signal CKBV can be
consistently maintained as the fixed reference voltage by the
voltage maintainer 2263 regardless of the occurrence of current
leakage, and as a result, the display quality of the display device
of FIG. 1 according to the invention can be improved.
[0060] In an exemplary embodiment, the reference voltage may have
the median value of the gate-on voltage Von and the gate-off
voltage Voff, i.e., (Von+Voff)/2, for example. In this example, the
first and second divider resistors Rv1 and Rv2 may have the same
resistance. If the reference voltage is (Von+Voff)/2, the gate
clock signal CKV and the gate clock bar signal CKBV may have the
same voltage variation when the blank period ("Blank" of FIG. 3)
ends and a subsequent frame begins, and as a result, display
quality deterioration such as visible horizontal lines that may
appear unintendedly on the display panel 110 can be reduced. This
will hereinafter be described later with reference to FIG. 3.
[0061] FIG. 3 is a waveform diagram showing an exemplary embodiment
of the waveforms of a gate clock signal and a gate clock bar signal
during a blank period.
[0062] Specifically, FIG. 3 shows an exemplary embodiment of the
waveforms of the gate clock signal CKV and the gate clock bar
signal CKBV during the latter half of a previous frame "N-1 Frame",
the blank period "Blank", and the former half of a current frame "N
Frame".
[0063] During the previous frame "N-1 Frame", the gate clock signal
CKV and the gate clock bar signal CKBV may alternately swing
between the gate-on voltage Von and the gate-off voltage Voff
depending on whether the gate pulse signal CPV is on or off. The
gate clock signal CKV and the gate clock bar signal CKBV may be
opposite in phase and may be symmetrical to each other.
[0064] During the blank period "Blank" that follows the previous
frame "N-1 Frame", the gate pulse signal CPV is maintained to be
the "off" status, and as a result, the gate clock signal CKV and
the gate clock bar signal CKBV may be matched by the charge sharer
22611 to be maintained at the reference voltage. In this exemplary
embodiment, the reference voltage may have the median value of the
gate-on voltage Von and the gate-off voltage Voff, i.e.,
(Von+Voff)/2, for example.
[0065] During the blank period "Blank", it is preferable for the
gate clock signal CKV and the gate clock bar signal CKBV to be
consistently maintained without any change. There is a probability
that the levels of the gate clock signal CKV and the gate clock bar
signal CKBV may change due to current leakage unless a separate
power source is provided. Specifically, in the case that the
current leakage exists, at the beginning of the current frame "N
Frame", an amplitude Vu at which the gate clock signal CKV swings
for the first time and an amplitude Vd at which the gate clock bar
signal CKBV swings for the first time may differ from each other,
resulting in different charging rates. Also, even the gate driver
230 may be affected and may thus cause unintended horizontal lines
to appear on a displayed image.
[0066] On the other hand, in the exemplary embodiment of FIG. 2,
the clock generator 220 includes the voltage maintainer 2263, and
the voltage maintainer 2263 forcibly maintains the gate clock
signal CKV and the gate clock bar signal CKBV at the reference
voltage during the blank period "Blank". As a result, the display
quality deterioration that may be caused by current leakage as
mentioned above can be reduced.
[0067] In response to the vertical synchronization start signal STV
being on, the current frame "N Frame" may begin, and the gate clock
signal CKV and the gate clock bar signal CKBV that have been
maintained at the reference voltage begin to swing in opposite
directions from each other. In the exemplary embodiment of FIG. 2,
the amplitudes Vu and Vd are identical, and as a result, the
display quality deterioration can be reduced.
[0068] FIG. 4 is a block diagram of another exemplary embodiment of
a clock generator of a display device according to the
invention.
[0069] A clock generator 220_a according to the exemplary
embodiment of FIG. 4 has almost the same structure as the clock
generator 220 of FIG. 2, except that a voltage sharer 2263_a
includes variable resistors. Accordingly, the clock generator 220_a
will hereinafter be described, focusing mainly on the difference
from the clock generator 220.
[0070] Referring to FIG. 4, the clock generator 220_a includes a
gate clock generator 2261, a control signal generator 2262, and a
voltage maintainer 2263_a.
[0071] The voltage maintainer 2263_a includes first and second
divider resistors Rv1_a and Rv2_a dividing a voltage supplied
thereto and a sixth switching circuit SW6 determining whether to
provide the divided voltage to the charge sharer 22611.
[0072] The first and second divider resistors Rv1_a and Rv2_a,
unlike the first and second divider resistors Rv1 and Rv2 of FIG.
2, may be variable resistors. A reference voltage is determined by
the ratio of the resistances of the first and second divider
resistors Rv1_a and Rv2_a. Thus, if the first and second divider
resistors Rv1_a and Rv2_a do not have the same resistance, the
reference voltage may have a value other than the median value of a
gate-on voltage Von and a gate-off voltage Voff, i.e.,
(Von+Voff)/2. Accordingly, the degree of freedom of the setting of
the reference voltage at which the gate clock signal CKV and the
gate clock bar signal CKBV need to be maintained during the blank
period "Blank" of FIG. 3 increases, and as a result, the display
device according to the exemplary embodiment of FIG. 4 can be
driven more effectively.
[0073] In the exemplary embodiment of FIG. 4, the first and second
divider resistors Rv1_a and Rv2_a are variable resistors, but the
invention is not limited thereto. That is, any circuit
configuration that can divide a voltage supplied to an input
terminal of the sixth switching circuit SW6 into an arbitrary
voltage between the gate-on voltage Von and the gate-off voltage
Voff may be used.
[0074] FIG. 5 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention.
[0075] A clock generator 220_b according to the exemplary
embodiment of FIG. 5 has almost the same structure as the clock
generator 220 of FIG. 2, except that the voltage maintainer 2263 of
FIG. 2 is not provided and first and second impedance control
circuits RCS1 and RCS2 are additionally provided. Accordingly, the
clock generator 220_b will hereinafter be described, focusing
mainly on the differences from the clock generator 220 of FIG.
2.
[0076] Referring to FIG. 5, the clock generator 220_b includes a
gate clock generator 2261_b and a control signal generator
2262_b.
[0077] The gate clock generator 2261_b includes first through fifth
switching circuits SW1 through SW5, a charge sharer 22611, and the
first and second impedance control circuits RCS1 and RCS2.
[0078] The first impedance control circuit RCS1 is connected
between the charge sharer 22611 and the second switching circuit
SW2. The second impedance control circuit RCS2 is connected between
the charge sharer 22611 and the fifth switching circuit SW5.
[0079] The first impedance control circuit RCS1 may control the
slew rate of a gate clock signal CKV during periods when charge
sharing is performed such that the gate clock signal CKV swings
from a gate-off voltage Voff to a reference voltage and when charge
sharing is performed such that the gate clock signal CKV swings
from a gate-on voltage Von to the reference voltage. The slew rate
of a signal means the speed at which the signal reaches a desired
voltage from any particular voltage. The higher the slew rate of
the gate clock signal CKV is, the faster the response speed of the
gate clock signal CKV is. Specifically, the higher the impedance of
the first impedance control circuit RCS1 is, the lower the slew
rate of the gate clock signal CKV is, and the lower the impedance
of the first impedance control circuit RCS1 is, the higher the slew
rate of the gate clock signal CKV is.
[0080] The second impedance control circuit RCS2 may control the
slew rate of a gate clock bar signal CKBV during periods when
charge sharing is performed such that the gate clock bar signal
CKBV swings from the gate-off voltage Voff to the reference voltage
and when charge sharing is performed such that the gate clock bar
signal CKBV swings from the gate-on voltage Von to the reference
voltage. Specifically, the higher the impedance of the second
impedance control circuit RCS2 is, the lower the slew rate of the
gate clock bar signal CKBV is, and the lower the impedance of the
second impedance control circuit RCS2 is, the higher the slew rate
of the gate clock bar signal CKBV is.
[0081] The gate clock signal CKV of FIG. 5 will hereinafter be
described with reference to FIG. 6.
[0082] FIG. 6 is a waveform diagram showing an exemplary embodiment
of the waveform of the gate clock signal generated by the clock
generator of FIG. 5 during a period corresponding to a period A of
FIG. 2.
[0083] Referring to FIG. 6, a period A may be divided into a total
of five sections, i.e., sections A1 through A5, for example. FIG. 6
shows only the gate clock signal CKV, and a detailed description of
the gate clock bar signal CKBV will be omitted because the
description of the gate clock signal CKV is applicable to the gate
clock bar signal CKBV.
[0084] The section A1 may be a period during which the gate clock
signal CKV maintained at the gate-off voltage Voff swings to the
reference voltage (e.g., (Von+Voff)/2) through charge sharing.
[0085] The section A2 may be a period during which the gate clock
signal CKV swings from the reference voltage to the gate-on voltage
Von through charging.
[0086] The section A3 may be a period during which the gate clock
signal CKV, the gate-on voltage Von, is provided to the gate driver
230 of FIG. 1.
[0087] The section A4 may be a period during which the gate clock
signal CKV maintained at the gate-on voltage Von swings to the
reference voltage through charge sharing.
[0088] The section A5 may be a period during which the gate clock
signal CKV swings from the reference voltage to the gate-off
voltage Voff through charging.
[0089] Among the sections A1 through A5, swings of the gate clock
signal CKV that result from charge sharing performed by the charge
sharer 22611 of FIG. 5 may occur only during the sections A1 and
A4.
[0090] As the impedance of the first impedance control circuit RCS1
of FIG. 5 decreases, the gate clock signal CKV may increase faster
during the section A1, and may decrease faster during the section
A4. That is, the response speed, the slew rate, of the gate clock
signal CKV may increase. On the other hand, as the impedance of the
first impedance control circuit RCS1 of FIG. 5 increases, the gate
clock signal CKV may increase more slowly during the section A1,
and may decrease more slowly during the section A4. That is, the
response speed, the slew rate, of the gate clock signal CKV may
decrease.
[0091] In an exemplary embodiment, resistors, inductors,
capacitors, operational amplifiers, or voltage followers using
emitter followers may be used as the first and second impedance
control circuits RCS1 and RCS2 of FIG. 5, for example, and any
circuit configurations that can provide a desired impedance value
may be used as the first and second impedance control circuits RCS1
and RCS2 of FIG. 5.
[0092] FIG. 7 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention.
[0093] A clock generator 220_c according to the exemplary
embodiment of FIG. 7 has almost the same structure as the clock
generator 220_b of FIG. 5 except for the locations of first and
second impedance control circuits RCG1 and RCG2. Accordingly, the
clock generator 220_c will hereinafter be described, focusing
mainly on the difference from the clock generator 220_b.
[0094] Referring to FIG. 7, the clock generator 220_c includes a
gate clock generator 2261_c and a control signal generator
2262_b.
[0095] The gate clock generator 2261_c includes first through fifth
switching circuits SW1 through SW5, a charge sharer 22611, and the
first and second impedance control circuits RCG1 and RCG2.
[0096] The first impedance control circuit RCG1 is connected
between the first and second switching circuits SW1 and SW2. The
second impedance control circuit RCS2 is connected between the
fourth and fifth switching circuits SW4 and SW5.
[0097] The first impedance control circuit RCG1 may control the
slew rate of a gate clock signal CKV during periods when charging
is performed such that the gate clock signal CKV swings from a
reference voltage to a gate-on voltage Von and when charging is
performed such that the gate clock signal CKV swings from a
reference voltage to a gate-off voltage Voff. Specifically, the
higher the impedance of the first impedance control circuit RCG1
is, the lower the slew rate of the gate clock signal CKV is, and
the lower the impedance of the first impedance control circuit RCG1
is, the higher the slew rate of the gate clock signal CKV is.
[0098] The second impedance control circuit RCG2 may control the
slew rate of a gate clock bar signal CKBV during periods when
charging is performed such that the gate clock bar signal CKBV
swings from the reference voltage to the gate-on voltage Von and
when charging is performed such that the gate clock bar signal CKBV
swings from the reference voltage to the gate-off voltage Voff.
Specifically, the higher the impedance of the second impedance
control circuit RCS2 is, the lower the slew rate of the gate clock
bar signal CKBV is, and the lower the impedance of the second
impedance control circuit RCS2 is, the higher the slew rate of the
gate clock bar signal CKBV is.
[0099] The gate clock signal CKV of FIG. 7 will hereinafter be
described with reference to FIG. 8.
[0100] FIG. 8 is a waveform diagram showing an exemplary embodiment
of the waveform of the gate clock signal generated by the clock
generator of FIG. 7 during a period corresponding to the period A
of FIG. 2.
[0101] Referring to FIG. 8, a period A may be divided into a total
of five sections, i.e., sections A1 through A5, for example. The
sections A1 through A5 of FIG. 8 are the same as their respective
counterparts of FIG. 6, and thus, detailed descriptions thereof
will be omitted.
[0102] Among the sections A1 through A5, swings of the gate clock
signal CKV that result from charging using the gate-on voltage Von
and discharging using the gate-off voltage Voff may occur only
during the sections A2 and A5.
[0103] As the impedance of the first impedance control circuit RCG1
of FIG. 7 decreases, the gate clock signal CKV may increase faster
during the section A2, and may decrease faster during the section
A5. That is, the response speed, the slew rate, of the gate clock
signal CKV increase. On the other hand, as the impedance of the
first impedance control circuit RCG1 of FIG. 7 increases, the gate
clock signal CKV may increase more slowly during the section A2,
and may decrease more slowly during the section A5. That is, the
response speed, the slew rate, of the gate clock signal CKV may
decrease.
[0104] In an exemplary embodiment, resistors, inductors,
capacitors, operational amplifiers, and voltage followers using
emitter followers may be used as the first and second impedance
control circuits RCG1 and RCG2 of FIG. 7, for example, and any
circuit configurations that can provide a desired impedance value
may be used as the first and second impedance control circuits RCG1
and RCG2 of FIG. 7.
[0105] FIG. 9 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention.
[0106] A clock generator 220_d according to the exemplary
embodiment of FIG. 9 has almost the same structure as the clock
generator 220_b of FIG. 5 except for the locations of first and
second impedance control circuits RDE1 and RDE2. Accordingly, the
clock generator 220_d will hereinafter be described, focusing
mainly on the difference from the clock generator 220_b.
[0107] Referring to FIG. 9, the clock generator 220_d includes a
gate clock generator 2261_d and a control signal generator
2262_b.
[0108] The gate clock generator 2261_d includes first through fifth
switching circuits SW1 through SW5, a charge sharer 22611, and the
first and second impedance control circuits RDE1 and RDE2.
[0109] The first impedance control circuit RDE1 is connected
between the second switching circuit SW2 and a first output
terminal Nout1 of the clock generator 220_d. The second impedance
control circuit RDE2 is connected between the fifth switching
circuit SW5 and a second output terminal Nout2 of the clock
generator 220_d.
[0110] The first impedance control circuit RDE1 may advance the
gate clock signal CKV or delay the gate clock signal CKV.
[0111] The second impedance control circuit RDE2 may advance the
gate clock bar signal CKBV or delay the gate clock signal CKV.
[0112] Accordingly, if any one of the gate clock signal CKV and the
gate clock bar signal CKBV is delayed or advanced such that the
gate clock signal CKV and the gate clock bar signal CKBV are no
longer matched, the gate clock signal CKV or the gate clock bar
signal CKBV may be delayed or advanced to be re-matched by
controlling the impedances of the first and second impedance
control circuits RDE1 and RDE2.
[0113] The delaying of the gate clock signal CKV of FIG. 9 will
hereinafter be described with reference to FIGS. 10 and 11.
[0114] FIGS. 10 and 11 are waveform diagrams showing exemplary
embodiments of the waveforms of the gate clock signal generated by
the clock generator 220_d of FIG. 9 during a period corresponding
to a period B of FIG. 2.
[0115] Referring to FIG. 10, during a period B, the gate clock
signal CKV lags behind the gate clock bar signal CKBV. In this
case, if the impedance of the first impedance control circuit is
RDE1 of FIG. 9 may be decreased, and as a result, the gate clock
signal CKV may be advanced. Consequently, the gate clock signal CKV
and the gate clock bar signal CKBV may be restored back to be
matched.
[0116] Referring to FIG. 11, during a period B, the gate clock
signal CKV leads the gate clock bar signal CKBV. In this case, if
the impedance of the first impedance control circuit RDE1 of FIG. 9
may be increased, and as a result, the gate clock signal CKV may be
delayed. Consequently, the gate clock signal CKV and the gate clock
bar signal CKBV may be restored back to be matched.
[0117] FIG. 12 is a block diagram of still another exemplary
embodiment of a clock generator of a display device according to
the invention.
[0118] A clock generator 220_e according to the exemplary
embodiment of FIG. 12 has almost the same structure as the clock
generator 220 of FIG. 2 except for the waveforms of first through
sixth gate pulse signals CPV1_e through CPV6_e. Accordingly, the
clock generator 220_e will hereinafter be described, focusing
mainly on the difference from the clock generator 220 of FIG.
2.
[0119] Referring to FIG. 12, the clock generator 220_e includes a
gate clock generator 2261_e, a control signal generator 2262_e, and
a voltage maintainer 2263.
[0120] The control signal generator 2262_e receives a gate pulse
signal CPV from the signal controller 210 of FIG. 1 and generates
the first through sixth gate pulse signals CPV e through CPV6_e.
The first through sixth gate pulse signals CPV1_e through CPV6_e
may slightly differ from the first through sixth gate pulse signals
CPV1 through CPV6, respectively, of FIG. 2. Accordingly, in the
exemplary embodiment of FIG. 13, unlike in the exemplary embodiment
of FIG. 2, a gate clock signal CKV may be controlled to swing ahead
of a gate clock bar signal CKBV, and then, the gate clock bar
signal CKBV may be controlled to swing. The gate clock signal CKV
and the gate clock bar signal CKBV of FIG. 12 will hereinafter be
described with reference to FIG. 13.
[0121] FIG. 13 is a waveform diagram showing an exemplary
embodiment of the waveforms of the gate clock signal and the gate
clock bar signal generated by the clock generator of FIG. 12.
[0122] Referring to FIG. 13, a blank period "Blank" follows a
previous frame "N-1 Frame", and when the blank period "blank" ends,
a gate clock signal CKV and a gate clock bar signal CKBV begin to
swing again. The gate clock bar signal CKBV may swing with a time
delay of a predetermined amount of time td. Accordingly, it is
possible to reduce an overload applied to the clock generator 220_e
of FIG. 12.
[0123] In this exemplary embodiment, the gate clock signal CKV and
the gate clock bar signal CKBV sequentially swing rather than
simultaneously swing at the beginning of a frame, but the invention
is not limited thereto. In general, when a user turns on a display
device that was completely off, control signals for controlling
various elements of the display device begin to swing. In this
case, like the exemplary embodiment of FIG. 12, if the gate clock
signal CKV and the gate clock bar signal CKBV are driven to
sequentially swing, not simultaneously swing, an overload applied
to the display device can be reduced.
[0124] Also, FIGS. 12 and 13 illustrate an example in which the
clock generator 220_e of FIG. 12 generates a pair of clock signals,
i.e., the gate clock signal CKV and the gate clock bar signal CKBV,
and the gate clock signal CKV and the gate clock bar signal CKBV
sequentially swing, but the invention is not limited thereto. That
is, in an alternative embodiment, the clock generator 220_e may
generate two pairs of clock signals, i.e., a first gate clock
signal (not illustrated), a second gate clock signal (not
illustrated), a first gate clock bar signal (not illustrated), and
a second gate clock bar signal (not illustrated). In this case, the
sequence of swing may follow an order of the first gate clock
signal, the second gate clock signal, the first gate clock bar
signal, and the second gate clock bar signal, for example.
[0125] However, the embodiments of the invention are not restricted
to the exemplary embodiments set forth herein. The above and other
effects of the invention will become more apparent to persons of
ordinary skill in the art to which the inventive concept pertains
by referencing the claims
* * * * *