U.S. patent application number 15/943076 was filed with the patent office on 2018-08-09 for system and method for electrical testing of through silicon vias (tsvs).
This patent application is currently assigned to STMicroelectronics S.r.l.. The applicant listed for this patent is STMicroelectronics S.r.l.. Invention is credited to Alberto PAGANI.
Application Number | 20180226307 15/943076 |
Document ID | / |
Family ID | 62045107 |
Filed Date | 2018-08-09 |
United States Patent
Application |
20180226307 |
Kind Code |
A1 |
PAGANI; Alberto |
August 9, 2018 |
SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS
(TSVs)
Abstract
A substrate includes first and second semiconductor layers doped
with opposite conductivity type in contact with each other at a PN
junction to form a junction diode. At least one through silicon via
structure, formed by a conductive region surrounded laterally by an
insulating layer, extends completely through the first
semiconductor layer and partially through the second semiconductor
layer with a back end embedded in, and in physical and electrical
contact with, the second semiconductor layer. A first electrical
connection is made to the first through silicon via structure and a
second electrical connection is made to the first semiconductor
layer. A testing current is applied to and sensed at the first and
second electrical connections in order to detect a defect in the at
least one through silicon via structure.
Inventors: |
PAGANI; Alberto; (Nova
Milanese, IT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics S.r.l. |
Agrate Brianza (MB) |
|
IT |
|
|
Assignee: |
STMicroelectronics S.r.l.
Agrate Brianza (MB)
IT
|
Family ID: |
62045107 |
Appl. No.: |
15/943076 |
Filed: |
April 2, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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15420319 |
Jan 31, 2017 |
9966318 |
|
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15943076 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G01R 31/2853 20130101;
G01R 31/2884 20130101; H01L 22/34 20130101; H01L 22/14 20130101;
H01L 23/481 20130101; H01L 21/76898 20130101; H01L 29/8613
20130101 |
International
Class: |
H01L 21/66 20060101
H01L021/66; G01R 31/28 20060101 G01R031/28; H01L 21/768 20060101
H01L021/768; H01L 23/48 20060101 H01L023/48; H01L 29/861 20060101
H01L029/861 |
Claims
1. A method for testing a wafer including a semiconductor substrate
comprising a first semiconductor layer of a first conductivity type
and a second semiconductor layer of a second conductivity type
opposite the first conductivity type, said first and second
semiconductor layers in contact with each other at a PN junction to
form a junction diode, said wafer further including a first through
silicon via structure comprising a conductive region surrounded
laterally by an insulating layer, said first through silicon via
structure extending completely through the first semiconductor
layer and partially through the second semiconductor layer with a
back end of the first through silicon via structure embedded in the
second semiconductor layer with the conductive region in physical
and electrical contact with the second semiconductor layer, the
method for testing comprising: generating a testing current applied
to flow through the first through silicon via structure; and
sensing said testing current at the first semiconductor layer in
order to detect a fault in the first through silicon via
structure.
2. The method of claim 1, wherein said fault is a defect in the
insulating layer laterally surrounding the conductive region of the
first through silicon via structure.
3. The method of claim 1, wherein the method for testing further
comprises sensing an absence of said testing current at the first
semiconductor layer in order to confirm correct operation of said
first through silicon via structure.
4. The method of claim 1, wherein the wafer further comprises a
second through silicon via structure comprising a conductive region
surrounded laterally by an insulating layer, said second through
silicon via structure extending completely through the first
semiconductor layer and partially through the second semiconductor
layer with a back end of the second through silicon via structure
embedded in the second semiconductor layer with the conductive
region in physical and electrical contact with the second
semiconductor layer, the method for testing further comprising:
sensing an absence of said testing current at the second through
silicon via structure in order to detect a fault in at least one of
the first and second through silicon via structures.
5. The method of claim 4, wherein said fault is a discontinuity of
the conductive region of at least one of the first and second
through silicon via structures.
6. The method of claim 4, wherein said fault is an extension of the
insulating layer laterally surrounding the conductive region to
insulating said conductive region of at least one of the first and
second through silicon via structures from the second semiconductor
layer.
7. The method of claim 1, wherein the wafer further comprises a
second through silicon via structure comprising a conductive region
surrounded laterally by an insulating layer, said second through
silicon via structure extending completely through the first
semiconductor layer and partially through the second semiconductor
layer with a back end of the second through silicon via structure
embedded in the second semiconductor layer with the conductive
region in physical and electrical contact with the second
semiconductor layer, the method for testing further comprising:
sensing said testing current at the second through silicon via
structure in order to confirm correct operation of said first and
second through silicon via structures.
8. A method for testing a through silicon via, wherein the through
silicon via comprises a conductive region surrounded laterally by
an insulating layer, said through silicon via extending completely
through a first semiconductor layer doped with a first conductivity
type and partially through a second semiconductor layer doped with
a second conductivity type, wherein a back end of the conductive
region is in physical and electrical contact with the second
semiconductor layer, the method comprising: generating a testing
current that is applied to the conductive region to flow into the
second semiconductor layer; and sensing said testing current
flowing in the first semiconductor layer in order to detect a fault
in the through silicon via.
9. A method for testing a through silicon via, wherein the through
silicon via comprises a conductive region surrounded laterally by
an insulating layer, said through silicon via extending completely
through a first semiconductor layer doped with a first conductivity
type and partially through a second semiconductor layer doped with
a second conductivity type, wherein a back end of the conductive
region is in physical and electrical contact with the second
semiconductor layer, the method comprising: generating a testing
current that is applied to the conductive region to flow into the
second semiconductor layer; and sensing an absense of said testing
current flowing in the first semiconductor layer in order to
confirm correct operation of the through silicon via.
10. A method for testing through silicon vias, wherein a first
through silicon via comprises a first conductive region surrounded
laterally by a first insulating layer and a second through silicon
via comprises a second conductive region surrounded laterally by a
second insulating layer, said first and second through silicon vias
extending completely through a first semiconductor layer doped with
a first conductivity type and partially through a second
semiconductor layer doped with a second conductivity type, wherein
a back end of each of the first and second conductive regions is in
physical and electrical contact with the second semiconductor
layer, the method comprising: generating a testing current that is
applied to the first conductive region to flow into the second
semiconductor layer; and sensing said testing current flowing in
the second conductive region in order to detect a fault in at least
one of the first and second through silicon vias.
11. A method for testing through silicon vias, wherein a first
through silicon via comprises a first conductive region surrounded
laterally by a first insulating layer and a second through silicon
via comprises a second conductive region surrounded laterally by a
second insulating layer, said first and second through silicon vias
extending completely through a first semiconductor layer doped with
a first conductivity type and partially through a second
semiconductor layer doped with a second conductivity type, wherein
a back end of each of the first and second conductive regions is in
physical and electrical contact with the second semiconductor
layer, the method comprising:: generating a testing current that is
applied to the first conductive region to flow into the second
semiconductor layer; and sensing said testing current flowing in
the second conductive region in order to confirm correct operation
of the first and second through silicon vias.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. application for
patent Ser. No. 15/420,319 filed Jan. 31, 2017, the disclosure of
which is incorporated by reference.
TECHNICAL FIELD
[0002] The present invention relates to a system and to a method
for electrical testing of through silicon vias (TSVs).
BACKGROUND
[0003] FIG. 1 shows a schematic and simplified cross-sectional view
of an electronic integrated circuit wafer 1 comprising: a substrate
3 made of semiconductor material, a first dielectric layer 4, a
second dielectric layer 5 and a passivation dielectric layer 6.
Integrated on and within the substrate 3 are electronic components
(such as, for example, transistor devices 3a ). Integrated within
the first dielectric layer 4 are conductive contacts 4a (for
example, made source/drain/gate regions) and other structures (such
as transistor gates 4b ) surrounded by an insulating material.
Integrated within the second dielectric layer 5 are metal
interconnect lines 5a and metal vias 5b on a plurality of
metallization levels (M1-Mn) that are surrounded by an insulating
material, wherein the interconnect lines and vias are electrically
connected to the contacts 4a and other structures of the first
dielectric layer 4. The passivation dielectric layer 6 includes
contact pads 7 which are electrically connected to the interconnect
lines and vias of the second dielectric layer 5. The top surface of
the passivation dielectric layer 6 is the front face of the wafer
1. The bottom surface of the substrate 3 is the back face of the
wafer 1.
[0004] It is common to utilize Through-Silicon Via or
Through-Semiconductor Via (collectively "TSV") technology in the
fabrication of integrated circuits. A TSV is an interconnection of
conductive material that extends vertically through the integrated
circuit chip so as to enable electrical connection of elements of
the circuit, integrated at various levels of the structure of the
integrated circuit chip, with an external face (front and/or back)
of the integrated circuit. The TSV is developed vertically through
the integrated circuit chip (for example, through the substrate 3
and other included layers of the wafer 1 in such a way that, at the
end of the manufacturing process, the TSV is accessible from the
external face of the integrated circuit chip.
[0005] FIG. 1 shows a number of examples of the use of a TSV 9.
Each TSV 9 forms a conductive interconnection that extends
vertically through the substrate 3 and possibly traverses (fully or
partially) one or more of the layers 4, 5 and 6. In particular, by
way of example, FIG. 1 shows: a TSV 9 which extends through the
layer 4 and partially through the substrate 3; a TSV 9 that extends
at least partially through the layer 5, through the layer 4 and
partially through the substrate 3; and a TSV 9 that extends through
the layers 4 and 5 and partially through the substrate 3.
[0006] For example, the TSVs 9 may be obtained as described in
United States Patent Application Publication No. 2005/0101054
(incorporated by reference), or as described in "Wafer Level 3-D
ICs Process Technology", by Chuan Seng Tan, Ronald J. Gutmann and
L. Rafael Reif, pp. 85-95, Springer-Verlag New York Inc.
(incorporated by reference).
[0007] In the overall fabrication process, the substrate 3 with
electronic components and the first dielectric layer 4 are provided
through appropriate fabrication processes designated by the acronym
FEOL (Front End of Line). The second dielectric layer 5 and
passivation dielectric layer 6, however, are provided through
appropriate fabrication processes designated by the acronym BEOL
(Back End of Line). The illustration in FIG. 1 is at an
intermediate stage of fabrication before the wafer is diced into
individual integrated circuit chips. Thus, after the BEOL, the
manufacturing process may further include the wafer dicing
operation.
[0008] FIG. 2 shows the wafer 1 at a subsequent stage in the
manufacturing process. Here, a step of thinning the back surface of
the substrate 3 (with known techniques of lapping, or "back
grinding") of the wafer 1 has been performed to expose a portion of
the back end 9b of each TSV 9. After completion of the thinning
process, the substrate 3 has a reduced thickness in comparison to
the intermediate stage of FIG. 1, for example a thickness of less
than 100
[0009] In a next step of the manufacturing processes, the wafer 1
may be diced (for example, at the lines 10) so as to define a
plurality of chips 12, each of which contains a respective
electronic integrated circuit. Following dicing, the chips are
packaged to form integrated circuit devices.
[0010] At the end of the manufacturing process, each TSV 9 will
accordingly traverse through the entire thickness of the substrate
3 as shown in FIG. 2, providing for a direct electrical connection
from the back side of the chip 12 to one or more of the included
electronic components, the first dielectric layer 4, the second
dielectric layer 5, and the contact pads 8. The use of TSV
technology is particularly advantageous for providing
three-dimensional packaging structures for the electronic
integrated circuits (referred to in the art as "3D-packaging
techniques" or 3D/2.5D integration techniques). In such structures,
plural chips are stacked one on top of the other using the TSVs 9
to support electrical connections between the stacked chips as well
as with the outside of the package.
[0011] In the light of the critical aspects of the production
process, and given the nature of electrical interconnection
performed by the TSVs 9, it would be advantageous to be able to
verify proper TSV operation at a point of the manufacturing process
preferably before performing dicing of the wafer 1. Such
verification of proper TSV operation would include verification of
the resistance of the path offered to the electric current
circulating through the through TSVs and moreover the detection of
possible leakages, defects and parasitic phenomena, for example, in
regard to the substrate 3. Such TSV testing is, however, difficult
at the stage of manufacturing shown in FIG. 1 because the back end
9b of each TSV 9 is still contained within the body of the
substrate 3 and thus is not directly available to be probed.
[0012] U.S. Pat. No. 9,111,895 (incorporated by reference) teaches
a TSV testing structure and methodology that can be used at the
stage of manufacturing shown in FIG. 1. With reference to FIG. 3,
the substrate 3 is doped with a first conductivity type dopant (for
example, P type). The TSV 9 has its back end 9b embedded in the
substrate 3. The TSV 9 is formed by a conductive region 16 (for
example, made of a metal material such as copper) surrounded
laterally by an insulating layer 18 (for example, made of an
insulating material such as silicon oxide). A region 20 within the
substrate 3 at the back end 9b of the TSV 9 is doped with a second
conductivity type dopant (for example, N type). The metal material
of the TSV conductive region 16 is in direct physical and
electrical contact with the region 20 but is isolated from the
P-type substrate 3 by the combination of the lateral insulating
layer 18 and underlying N-type region 20. The N-type region 20
forms with P-type substrate 3 a PN semiconductor junction (i.e., a
junction diode 22) having an anode terminal provided by the
substrate 3 and a cathode terminal provided by the region 20.
Electrical connection to the anode terminal is made through an
electrical contact 24 made to the substrate 3 while electrical
connection to the cathode terminal is made through an electrical
contact 26 made to the conductive region 16 of the TSV 9. The
electrical contacts 24 and 26 may be implemented, for example,
using electrically conductive structures (contacts, lines, vias)
present within the layers 4 and 5 as well as the pads 7 in the
layer 6.
[0013] In use, the presence of the junction diode 22 at the back
end 9b of the TSV 9, accessible through the electrical contacts 24
and 26 and their associated pads 7 in the layer 6, enables the
electrical testing of the TSV 9 to be carried out. For example, in
a test procedure a test current is circulated for application to
the junction diode 22 and the test current (or corresponding
voltage) is measured. More specificly, in one testing
implementation the junction diode 22 is forward biased so as to
enable the passage of the test current through the conductive
region 16 of the TSV 9. It is thus possible to evaluate, using a
test apparatus coupled to the associated pads 7, the resistance
offered by TSV 9 under test to the passage of the test current. In
particular, it is possible to measure a resistance of a
differential type causing the test current to assume two distinct
values and thus measure two corresponding differences of potential.
The measured differences of potential can be evaluated to determine
a fault of the TSV 9 under test. Chips with fauty TSVs 9 can be
identified and then discarded following the thinning of the
substrate 3 and subsequent dicing operations.
[0014] FIG. 4 shows a schematic and simplified view of the testing
apparatus for performing a wafer-level testing of electrical
characteristics. The wafer 1 is mounted to a chuck 30. A probe head
32 is arranged with a plurality of probes 34 can be actuated so as
to approach the front face of the wafer 1 and cause the plurality
of probes 34 to be placed into physical and electrical contact with
the pads 7 of the wafer 1. The probe head 32 is mounted to a
support 36 (for example, a printed circuit board). The probe head
32, probes 34 and support 36 form a device known to those skilled
in the wafer test art as a probe card 38. FIG. 3 illustrates the
physical and electrical contacting of the probes 34 with the pads 7
of the wafer 1. It is through the probes that the test current is
applied and the potential measurements are made under the direction
and control of connected Automated Test Equipement (ATE). As known
in the art, ATE is configured to perform automatic procedures for
testing and electrical sorting the various chips within the wafer 1
(before the corresponding dicing operation is performed) so as to
select the chips that are operating properly for their subsequent
packaging. This operation is known as "Electrical Wafer Sort" (EWS)
or "Wafer Sort" (WS) and envisages execution of appropriate
electrical tests on the electronic integrated circuits, and in this
case the TSVs 9, in the various chips.
[0015] Although FIG. 3 illustrates a preferred implementation where
the probes 34 make physical and electrical contact with the pads 7,
it will be understood that in alternative implementations the probe
34 may alternatively make physical and electrical contact directly
with the front end 9a of the TSVs 9. This can be accomplished, for
example, in situations where the TSVs extend up to layer 6 (and are
exposed through the layer 6) or in situations where testing is
performed prior to BEOL processing and the formation of layers 5
and 6.
[0016] Details of possible testing scenarios, as well as other
related TSV testing structures, are provided in U.S. Pat. No.
9,111,895 and will not be repeated here.
SUMMARY
[0017] In an embodiment, an apparatus comprises: a semiconductor
substrate including a first semiconductor layer of a first
conductivity type and a second semiconductor layer of a second
conductivity type opposite the first conductivity type, said first
and second semiconductor layers in contact with each other at a PN
junction to form a junction diode; a first through silicon via
structure comprising a conductive region surrounded laterally by an
insulating layer, said first through silicon via structure
extending completely through the first semiconductor layer and
partially through the second semiconductor layer with a back end of
the first through silicon via structure embedded in the second
semiconductor layer with the conductive region in physical and
electrical contact with second conductivity type doped
semiconductor material of the second semiconductor layer; a first
electrical connection made to a front end of the first through
silicon via structure; and a second electrical connection made to
first conductivity type doped semiconductor material of the first
semiconductor layer.
[0018] In an embodiment, a method is presented for testing a wafer
including a semiconductor substrate comprising a first
semiconductor layer of a first conductivity type and a second
semiconductor layer of a second conductivity type opposite the
first conductivity type, said first and second semiconductor layers
in contact with each other at a PN junction to form a junction
diode, said wafer further including a first through silicon via
structure comprising a conductive region surrounded laterally by an
insulating layer, said first through silicon via structure
extending completely through the first semiconductor layer and
partially through the second semiconductor layer with a back end of
the first through silicon via structure embedded in the second
semiconductor layer with the conductive region in physical and
electrical contact with second conductivity type doped
semiconductor material of the second semiconductor layer.
[0019] The method for testing comprises: generating a testing
current applied to flow through the first through silicon via
structure; and sensing said testing current at the first
semiconductor layer in order to detect a fault in the first through
silicon via structure. The method for testing further comprises:
generating a testing current applied to flow through the first
through silicon via structure; and sensing said testing current at
the first semiconductor layer in order to confirm correct operation
of said first through silicon via structure.
[0020] In an embodiment, a method is presented for testing a wafer
including a semiconductor substrate comprising a first
semiconductor layer of a first conductivity type and a second
semiconductor layer of a second conductivity type opposite the
first conductivity type, said first and second semiconductor layers
in contact with each other at a PN junction to form a junction
diode, said wafer further including a first and second through
silicon via structures each comprising a conductive region
surrounded laterally by an insulating layer, said first and second
through silicon via structures extending completely through the
first semiconductor layer and partially through the second
semiconductor layer with a back end of the first and second through
silicon via structures embedded in the second semiconductor layer
with the conductive region in physical and electrical contact with
second conductivity type doped semiconductor material of the second
semiconductor layer.
[0021] The method for testing comprises: generating a testing
current applied to flow through the first through silicon via
structure; and sensing said testing current at the second through
silicon via structure in order to confirm correct operation of said
first and second through silicon via structures.
[0022] The method for testing comprises: generating a testing
current applied to flow through the first through silicon via
structure; and sensing an absence of said testing current at the
second through silicon via structure in order to detect a fault in
at least one of the first and second through silicon via
structures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] For a better understanding of the present invention,
preferred embodiments thereof are now described, purely by way of
non-limiting example and with reference to the attached drawings,
wherein:
[0024] FIG. 1 is a schematic cross-section of a wafer of
semiconductor material, in which through vias are provided, at an
intermediate stage of a manufacturing process;
[0025] FIG. 2 is a schematic cross-section of the wafer of FIG. 1
at an end stage of the manufacturing process;
[0026] FIG. 3 illustrates a TSV testing structure and methodology
as taught by U.S. Pat. No. 9,111,895;
[0027] FIG. 4 is a schematic illustration of part of a testing
apparatus for electrical testing of a wafer of semiconductor
material;
[0028] FIG. 5 is a schematic cross-section of a wafer of
semiconductor material, in which through vias are provided, at an
intermediate stage of a manufacturing process;
[0029] FIG. 6 illustrates an improved TSV testing structure and
methodology using the wafer of FIG. 5; and
[0030] FIGS. 7A-7E illustrate testing scenarios using the improved
TSV testing structure and methodology of FIG. 6.
DETAILED DESCRIPTION
[0031] FIG. 5 shows a schematic and simplified cross-sectional view
of an electronic integrated circuit wafer 1' comprising: a
substrate 3' of semiconductor material, a first dielectric layer 4,
a second dielectric layer 5 and a passivation dielectric layer 6.
The substrate 3' comprises a first layer 3n of semiconductor
material doped with a first conductivity type dopant (for example,
N type) and a second layer 3p of semiconductor material doped with
a second conductivity type dopant (for example, P type). The
formation of a substrate 3' having opposite conductivity type doped
layers 3n and 3p in contact with each other as shown may be
accomplished using a number of different techniques, known to those
skilled in the art, including dopant implantation with diffusion or
epitaxial growth with insitu doping or subsequent implantation and
diffusion. Although layers 3n and 3p are shown in the example of
FIG. 5 as being doped n-type and p-type, respectively, it will be
understood that the layers could alternatively be doped p-type and
n-type, respectively. Still further, the layer 3p could be
implemented in an embodiment as a doped well structure contained
within the layer 3n.
[0032] Integrated on and within the substrate layer 3p are
electronic components (such as, for example, transistor devices 3a
). Integrated within the first dielectric layer 4 are contacts 4a
(for example, made source/drain/gate regions) and other structures
(such as transistor gates 4b ) surrounded by an insulating
material. Integrated within the second dielectric layer 5 are
interconnect lines 5a and vias 5b on a plurality of metallization
levels (M1-Mn) that are surrounded by an insulating material,
wherein the interconnect lines and vias are electrically connected
to the contacts 4a and other structures of the first dielectric
layer 4. The passivation dielectric layer 6 includes contact pads 7
which are electrically connected to the interconnect lines and vias
of the second dielectric layer 5. The top surface of the
passivation dielectric layer 6 is the front face of the wafer 1'.
The bottom surface of the substrate 3 is the back face of the wafer
1'.
[0033] Through-Silicon Via or Through-Semiconductor Via
(collectively "TSV") technology is further used to form an
interconnection of conductive material that extends vertically
through the integrated circuit chip so as to enable electrical
connection of elements of the circuit, integrated at various levels
of the structure of the integrated circuit chip, with an external
face (front and/or back) of the integrated circuit. The TSV is
developed vertically through the integrated circuit chip (for
example, through the substrate substrate 3' and other included
layers of the wafer 1' in such a way that, at the end of the
manufacturing process the TSV is accessible from the external face
of the integrated circuit chip.
[0034] FIG. 5 shows a number of examples of the use of a TSV 9.
Each TSV 9 forms a conductive interconnection that extends
vertically through the substrate 3' and possibly traverses (fully
or partially) one or more of the layers 4, 5 and 6. In particular,
by way of example, FIG. 1 shows: a TSV 9 which extends through the
first dielectric layer 4 and partially through the substrate 3'
(for example, completely through layer 3p and partially through
layer 3n ); a TSV 9 that extends at least partially through the
second dielectric layer 5, through the first dielectric layer 4 and
partially through the substrate 3' (for example, completely through
layer 3p and partially through layer 3n ); and a TSV 9 that extends
through the first and second dielectric layers 4 and 5 and
partially through the substrate 3' (for example, completely through
layer 3p and partially through layer 3n ).
[0035] In the overall fabrication process, the substrate 3' with
electronic components and the first dielectric layer 4 are provided
through appropriate processes designated by the acronym FEOL (Front
End of Line). The second dielectric layer 5 and passivation
dielectric layer 6, however, are provided through appropriate
processes designated by the acronym BEOL (Back End of Line). The
illustration in FIG. 5 is at an intermediate stage of fabrication
before subsequent substrate 3' thinning (compare to FIG. 2) and
before the wafer 1' is diced into individual integrated circuit
chips. Thus, after the BEOL, the manufacturing process may further
include the substrate thinning and wafer dicing operations.
[0036] Reference is now made to FIG. 6 which illustrates an
improved TSV testing structure and methodology that can be used at
the stage of manufacturing shown in FIG. 5. With reference to FIG.
6, each TSV 9 passes completely through the layer 3p of the
substrate 3' and has its back end 9b embedded in the layer 3n of
the substrate 3'. Each TSV 9 is formed by a conductive region 16
(for example, made of a metal material such as copper) surrounded
laterally by an insulating/dielectric layer 18 (for example, made
of an insulating material such as silicon oxide). In this
configuration, distinct from the prior art implementation of FIG.
3, the conductive region 16 of the TSV 9 is in direct physical and
electrical contact with the n-type doped semiconductor material of
the substrate layer 3n. The layer 3p forms with layer 3n of the
substrate 3' a PN semiconductor junction (i.e., a junction diode
22') having an anode terminal formed by the substrate layer 3p and
a cathode terminal formed by the substrate layer 3n. Electrical
connection to the anode terminal is made through an electrical
contact 24 made to the substrate layer 3p while electrical
connection to the cathode terminal is made through an electrical
contact 26 made to the conductive region 16 of the TSV 9. The
electrical contacts 24 and 26 may be implemented, for example,
using electrically conductive structures (contacts, vias, lines)
present within the layers 5 and 6 as well as the pads 7 in the
layer 6.
[0037] In use, the presence of the junction diode 22' formed by the
PN junction of layer 3p /3n, accessible through the electrical
contacts 24 and 26 and their associated pads 7 in the layer 6,
enables the electrical testing of the included TSVs 9 to be carried
out. In a test procedure using the testing apparatus of FIG. 3, for
example, a current 50 is applied by the ATE and probe card 38 to
node A at a selected one of the included TSVs 9 and first sensed at
node B associated with the anode of the junction diode 22'. If no
current is detected by the ATE at node B as shown in a simplified
example with FIG. 7A (or if only a very small reverse bias leakage
current is detected at node B), then it can be concluded that the
TSV 9 at node B, as well as other TSVs electrically coupled to the
substrate layer 3n, is properly laterally insulated from the
substrate layer 3p by the insulating/dielectric layer 18.
Conversely, if current 50 is detected at node B as shown in a
simplified example with FIG. 7B, this indicates a failure
(reference 60) of the lateral isolation (formed by insulating layer
18) of one or more of the TSVs electrically coupled to the
substrate layer 3n. Then, sensing by the ATE is further performed
at node C at another of the included TSVs 9. If the current 50
applied to node A is detected by the ATE at the node C as shown in
a simplified example with FIG. 7C, then it can be concluded that
the TSVs associated with nodes A and C are properly conducting
current flow. Conversely, if the current 50 applied to node A is
not detected by the ATE at node C, this indicates a fault
(reference 62) due to a defect in the construction of at least one
of the TSVs 9 (for example, due to interruption of the conductive
region 16 of the TSV 9, as shown in a simplified example with FIG.
7D, or presence on an insulating film at the back end 9b of the TSV
9, as shown in a simplified example with FIG. 7E). Chips with fauty
TSVs 9 can be identified and then discarded following the thinning
of the substrate 3 and subsequent dicing operations.
[0038] In order to provide some control over which TSVs 9 are
grouped together for testing, trench isolation structures 40 may be
formed in the substrate 3'. The trench isolation structures 40
extend through the substrate layer 3p and eventually at least
partially into the substrate layer 3n. The trench isolation
structures 40 delimit a region of the substrate layer 3p and thus
define a set of TSVs which are subject to a common testing. This
set of TSVs may be a subset of the TSVs integrated in the chip 12,
or all TSVs of the chip 12, or TSVs belonging to a plurality of
chips 12 of the wafer. Alternatively, the trench isolation
structures 40 may be omitted. In other embodiments, trench
isolation structures may be provided for other reasons unrelated to
the TSV testing disclosed herein.
[0039] The method of forming the TSVs 9 may, for example, comprise
a masking of the substrate 3' followed by an anisotropic etch to
forming an opening extending through the layer 3p and partially
into the layer 3n. Then, the side wall and bottom of the opening is
lined by an insulating layer (for example, using a conformal
dielectric deposition or a thermal oxidation). An anisotropic etch
is then performed to remove the insulating layer at the bottom of
the opening. A barrier layer (for example, TiN) may be deposited in
the opening and the opening is then subsequently filled with a
conductive material, for example using a damascene and polishing
operation or other known techniques.
[0040] This method for electrical testing of TSVs 9 can be applied
to a 3D chip 12 as shown in FIG. 5 that comprises active integrated
electronic components such as transistor devices 3a or it can be
applied to a 2.5D chip 12 as shown in FIG. 6, also called
interposer or silicon interposer, that does not include active
integrated electronic components in layer 3p. Considering a 3D chip
12, this method for electrical testing of TSVs 9 can be applied
using a BIST (Built-In Self Test) circuit embedded in the 3D chip
12 (for example using circuitry like the transistor devices 3a in
layer 3p connected as needed to the TSVs and layer 3p ) as shown in
FIG. 5, or without any BIST circuit, using only the ATE that is
linked or connected to the 3D chip 12 from the outside as shown in
FIG. 6. With respect to considering a 2.5D chip 12, this testing
method is applied by an ATE because active integrated electronic
components are, in general, absent in the interposer.
[0041] Moreover, this method for electrical testing of TSVs 9, can
be applied to any other through via in any semiconductor substrate,
and thus it is not limited to silicon substrates.
[0042] The foregoing description has provided by way of exemplary
and non-limiting examples providing a full and informative
description of the exemplary embodiment of this invention. However,
various modifications and adaptations may become apparent to those
skilled in the relevant arts in view of the foregoing description,
when read in conjunction with the accompanying drawings and the
appended claims. However, all such and similar modifications of the
teachings of this invention will still fall within the scope of
this invention as defined in the appended claims.
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