U.S. patent application number 15/668767 was filed with the patent office on 2018-06-21 for cmos image sensor with shared sensing node.
This patent application is currently assigned to ASML Netherlands B.V.. The applicant listed for this patent is ASML Netherlands B.V., CARL ZEISS AG. Invention is credited to Oh-Bong KWON.
Application Number | 20180175094 15/668767 |
Document ID | / |
Family ID | 36756096 |
Filed Date | 2018-06-21 |
United States Patent
Application |
20180175094 |
Kind Code |
A1 |
KWON; Oh-Bong |
June 21, 2018 |
CMOS Image Sensor with Shared Sensing Node
Abstract
A CMOS image sensor has a pixel array provided with a plurality
of unit pixels arranged in a matrix shape of rows and columns. Each
of the unit pixels includes a photocharge generation means for
generating photocharges by absorbing an external light; and a
sensing node for receiving the photocharges transferred from the
photocharge generation means, wherein the sensing node of the unit
pixel in a previous scan line is shared with a sensing node of a
unit pixel in a current scan line in response to a line select
signal of the current line.
Inventors: |
KWON; Oh-Bong; (Cheongju-Si,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ASML Netherlands B.V.
CARL ZEISS AG |
Veldhoven
Oberkochen |
|
NL
DE |
|
|
Assignee: |
ASML Netherlands B.V.
Veldhoven
NL
CARL ZEISS AG
Oberkochen
DE
|
Family ID: |
36756096 |
Appl. No.: |
15/668767 |
Filed: |
August 4, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14147021 |
Jan 3, 2014 |
9728574 |
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15668767 |
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13410875 |
Mar 2, 2012 |
8625017 |
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14147021 |
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11345207 |
Jan 31, 2006 |
8149312 |
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13410875 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H04N 5/3559 20130101;
H01L 27/14641 20130101; H04N 5/3745 20130101; H01L 27/14643
20130101; H04N 5/335 20130101 |
International
Class: |
H01L 27/146 20060101
H01L027/146; H04N 5/3745 20110101 H04N005/3745; H04N 5/335 20110101
H04N005/335; H04N 5/355 20110101 H04N005/355 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 31, 2005 |
KR |
10-2005-0008654 |
Claims
1. A method, comprising: collecting charge generated by a first
pixel of a plurality of pixels; transferring charge generated by
the first pixel to a first sensing node of the first pixel and to a
second sensing node of a second pixel of the plurality of pixels;
and generating, based on charge transferred to both the first
sending node and the second sensing node, an output signal that is
indicative of charge collected by the first pixel.
Description
INCORPORATION BY REFERENCE
[0001] This application incorporates by reference in their
entireties U.S. patent application Ser. No. 14/147,021, filed Jan.
3, 2014, U.S. patent application Ser. No. 13/410,875, filed Mar. 2,
2012, and U.S. patent application Ser. No. 11/345,207, filed Jan.
31, 2016.
FIELD OF THE INVENTION
[0002] The present invention relates to a complementary metal oxide
semiconductor (hereinafter, referred to as a CMOS) image sensor;
and, more particularly, to a pixel array of a CMOS image sensor for
increasing storage capacitance of a sensing node.
DESCRIPTION OF RELATED ARTS
[0003] In general, an image sensor is an apparatus for capturing an
image using a characteristic of a semiconductor which is sensitive
to a light. Every portion of each object existing in nature has
different brightness and wavelength so that it shows different
electrical values at respective pixels that sense an incident light
corresponding to each portion of the object. In this manner, the
image sensor serves a role of converting these electrical values
into predetermined levels of signals which can be processed through
a circuitry.
[0004] FIG. 1 is a block diagram setting forth a conventional CMOS
image sensor.
[0005] Referring to FIG. 1, the conventional CMOS image sensor
includes an interface unit 10, a pixel array 20, an analog-digital
converter 30 and a buffer 40. Herein, the interface unit 10
controls overall operation of the CMOS image sensor, and acts as an
interface with respect to an external system. The pixel array 20 is
configured with an N number of pixel columns and an M number of
pixel rows to have N.times.M number of pixels so that the pixel
array 20 senses information with regard to an image inputted from
an exterior, wherein each pixel is constructed such that its
photosensitivity may be maximized. The analog-digital converter 30
converts an analog voltage sensed at each pixel of the image sensor
into a digital voltage to be processed at a digital system. The
buffer 40 stores the digitalized image data of the pixel in
response to the output of the analog-digital converter 30.
[0006] In addition, the analog-digital converter 30 is provided
with a digital-analog converter (DAC) 31 and a voltage comparator
32. The DAC 31 generates a reference voltage in ramp type which is
linearly decreased with a clock, wherein the reference voltage is
used for being compared with a voltage sensed at each pixel. The
voltage comparator 32 configured with N number of arrangements
compares the sensed voltage, i.e., an analog voltage, outputted
from the pixel array 20 with the reference voltage of the DAC 31,
and outputs a write enable signal which allows a counter value
outputted from the interface unit 10 to be written to the buffer 40
while the reference voltage is higher than the sensed voltage.
[0007] If the CMOS image sensor employs a correlated double
sampling (CDS) method in order to produce high quality image, each
unit pixel 100 and 120 of the pixel array is configured with one
photodiode and four transistors, as illustrated in FIG. 2. In
detail, the four transistors are configured with a transfer
transistor M21 for transferring photocharges generated at the
photodiode 101 to a sensing node A, a reset transistor M11 for
discharging the photocharges stored at the sensing node A in order
to detect a next signal, a drive transistor M31 for acting as a
source follower, and a select transistor M41 for switching and
addressing.
[0008] Herein, in the CDS method, a voltage corresponding to a
reset level is obtained by turning on the reset transistor M11 but
turning off the transfer transistor M21, and subsequently, the
photocharges generated at the photodiode 101 are read to obtain a
data voltage level by turning off the reset transistor M11 but
turning on the transfer transistor M21. Thereafter, a voltage
difference between the reset voltage level and the data voltage
level is obtained as a pure image data signal.
[0009] FIG. 3 is a control timing diagram illustrating signals
controlling each transistor in the unit pixel of FIG. 2. Referring
to FIG. 3, an operation of the unit pixel will be set forth for
every section in detail here below.
[0010] 1) A Section
[0011] In this section, the transfer transistor M21 and the reset
transistor M11 are turned on, but the select transistor M41 is
turned off. Therefore, the photodiode 101 is in a state of a fully
depletion.
[0012] 2) B Section
[0013] In this section, the transfer transistor M21 is turned off
so that the photodiode 101 absorbs the light to generate the
photocharges. Thus, the generated photocharges are integrated
during this section. Meanwhile, the section B maintains till the
transfer transistor M21 is turned on again regardless of the states
of the reset and select transistors M11 and M41.
[0014] 3) C Section
[0015] In this section, the reset transistor M11 is turned on, and
the transfer transistor M21 maintains to be turned off, bur the
select transistor M41 is turned on so that a reset voltage level is
transferred through the drive transistor M31 and the select
transistor M41.
[0016] 4) D Section
[0017] In this section, the reset transistor M11 is turned off so
as to settle the reset voltage level generated during the section
C.
[0018] 5) E Section
[0019] This is a section for sampling the reset voltage level of
the section D.
[0020] 6) F Section
[0021] In this section, the reset transistor M11 and the select
transistor M41 maintain to be turned off and on, respectively, and
the transfer transistor M21 is turned on so that the photocharges
integrated at the photodiode 101 during the section B are
transferred to the sensing node A. Thus, a data voltage level is
transferred through the drive transistor M31 and the select
transistor M41.
[0022] 7) G Section
[0023] In this section, the transfer transistor M21 is turned off
so as to settle the data voltage level generated during the section
F.
[0024] 8) H Section
[0025] This section is for sampling the data voltage level of the
section G.
[0026] The reset voltage level and the data voltage level which are
sampled at the section E and H respectively, are outputted to the
analog-digital converter 30 and then, are converted into a digital
data. The difference value between the digitally-converted reset
voltage level and the data voltage level becomes an output image
data of the CMOS image sensor for the image inputted through the
photodiode 101.
[0027] Herein, the other unit pixels of the conventional CMOS image
sensor operate like that of the unit pixel 100 which has been
described above. In case of employing a row-by-row scanning type in
the pixel array, the scanning is performed from a first row to a
last row in sequence.
[0028] Therefore, for example, when obtaining a data from a pixel
of an nth row after obtaining a data from a pixel of an n-1th row,
photocharges are integrated anew after cleaning up all the pixels
corresponding to a first to the n-1th rows.
[0029] Meanwhile, as described above, the photodiode constituting
each unit pixel should have high capacitance for generating the
photocharges and integrating them in order to obtain good image
quality. To this end, an attempt for improving fill-factor has been
made using a technology of increasing a photodiode area and so
forth.
[0030] However, the sensing node in the conventional CMOS image
sensor, which is implemented as a high concentration impurity
diffusion region, does not have capacitance enough to receive
increased photocharges in spite of the enhanced fill-factor, which
makes it difficult to obtain a desired photosensitivity after
all.
SUMMARY OF THE INVENTION
[0031] It is, therefore, an object of the present invention to
provide a CMOS image sensor of which a capacitance of a sensing
node is increased by sharing the sensing node of an adjacent
non-selected pixel while a selected pixel operates, in order that
the sensing node may receive photocharges generated much more due
to an enhanced fill-factor.
[0032] In accordance with an aspect of the present invention, there
is provided A CMOS image sensor having a pixel array provided with
a plurality of unit pixels arranged in a matrix shape of rows and
columns, each of the unit pixel including: a photocharge generation
means for generating photocharges by absorbing an external light;
and a sensing node for receiving the photocharges transferred from
the photocharge generation means, wherein the sensing node of the
unit pixel in a previous scan line is shared with a sensing node of
a unit pixel in a current scan line in response to a line select
signal of the current line.
[0033] In accordance with another aspect of the present invention,
there is provided A CMOS image sensor including: a pixel array in
which a plurality of unit pixels are arranged in a matrix shape of
rows and columns; and a switching means for interconnecting a
sensing node of a selected unit pixel to a sensing node of another
neighboring unit pixel in response to a select signal, to increase
a storage capacitance of the sensing node of the selected pixel.
Herein, the unit pixel includes a photocharge generation means for
generating photocharges by absorbing an external light; a sensing
node for receiving the photocharges transferred from the
photocharge generation means; a transfer means for transferring the
photocharges from the photocharge generation means to the sensing
node; a rest means for resetting the sensing node; an output means
for outputting an electric signal in response to the sensing node;
and an addressing means of which one side is connected to the
output means for switching and addressing in response to the select
signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The above and other objects and features of the present
invention will become better understood with respect to the
following description of the preferred embodiments given in
conjunction with the accompanying drawings, in which:
[0035] FIG. 1 is a block diagram of a conventional CMOS image
sensor;
[0036] FIG. 2 is a circuit diagram setting forth a pixel array of
the conventional CMOS image sensor;
[0037] FIG. 3 is a timing diagram setting forth a unit pixel of
FIG. 2; and
[0038] FIG. 4 is a circuit diagram illustrating a pixel array of a
CMOS image sensor in accordance with an embodiment of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0039] A CMOS image sensor with shared sensing node in accordance
with exemplary embodiments of the present invention will be
described in detail with reference to the accompanying
drawings.
[0040] FIG. 4 is a circuit diagram illustrating a pixel array of a
CMOS image sensor in accordance with an embodiment of the present
invention. In particular, FIG. 4 represents three unit pixels which
are successively arranged in the same column among a plurality of
unit pixels in the pixel array.
[0041] The CMOS image sensor of the present invention is configured
with a pixel array in which a plurality of unit pixels are arranged
in a column direction and a row direction, like typical
constitutions. The CMOS image sensor is driven by a line scanning
fashion where a scanning is performed line by line, i.e., row by
row or column by column, in sequence. Unlike the prior art, a
sensing node SN2 of a pixel in a currently scanning line, e.g., an
nth row of FIG. 4, is shared with a sensing node SN1 of a pixel in
a lately scanned line, e.g., an n-1th row of FIG. 4, and receives
photocharges from a photodiode PD2 of the pixel in the currently
scanning line.
[0042] FIG. 4 illustrates one embodiment that the line scanning is
performed row by row, in which the sensing nodes are shared with a
nearest-neighboring pixel arranged in the same column. However, if
the line scanning is a column scanning fashion, i.e., scanned
column by column, the sensing nodes are shared with a
nearest-neighboring pixel arranged in the same row.
[0043] The sharing scheme of the sensing nodes is accomplished
through a switching device which connects the sensing nodes of the
neighboring pixels, wherein the switching device is controlled by a
line select signal. To this end, the switching device in the
embodiment of FIG. 4 is configured with an NMOS transistor M400 of
which a source and a drain are connected between the sensing node
SN2 of the selected pixel and the sensing node SN1 of the lately
selected pixel, wherein a row select signal SX2 of the currently
scanning row is inputted a gate thereof.
[0044] Referring to FIG. 4, the CMOS image sensor in accordance
with the present invention will be set forth more fully in detail
herebelow.
[0045] In FIG. 4, it is shown only three unit pixels for the sake
of illustrative purpose, which are arranged at intersections of a
predetermined one column and an n-1th row, an nth row and an n-1th
row, respectively.
[0046] Considering the constitutions of the unit pixel of the nth
row, the unit pixel includes a photocharge generator PD2 for
receiving a light from an object to generate photocharges, a
sensing node SN2 for receiving the photocharges from the
photocharge generator PD2, a transfer unit M421 for transferring
the photocharges from the photocharge generator PD2 to the sensing
node SN2, a reset unit M422 for resetting the sensing node SN2, an
output unit M423 for outputting an electric signal corresponding to
the sensing node SN2, and an addressing unit M424 of which one side
is connected to the output unit M423 for switching and addressing
in response to a row select signal SX2. Herein, the photocharge
generator PD2 is configured with a photodiode. The addressing unit
M424 is configured with an NMOS transistor of which one side is
connected to the output unit M423 and the other side is connected
to an output line. The output unit M423 is configured with an NMOS
transistor of which one side is connected to a first power terminal
VCC and the other is connected to the addressing unit M424. The
reset unit M422 is configured with an NMOS transistor of which one
side is connected to the first power terminal VCC and the other
side is connected to the sensing node SN2. The transfer unit M421
is configured with an NMOS transistor of which one side is
connected to the photocharge generator PD2 and the other is
connected to the sensing node SN2.
[0047] The unit pixels in the n-1th row and the n+1th row are
identical in the constitution to the unit pixel of the nth row.
Thus, further descriptions for them will be omitted herein.
[0048] In addition, as described above, in order to increase the
storage capacitance of the sensing node, the CMOS image sensor of
the present invention further includes the switching device M400
and M450 for interconnecting the sensing node of the currently
selected pixel to the sensing node of the nearest-neighboring pixel
which is lately scanned, in response to the row select signal. In
detail, the switching device M400 and M500 is configured with an
NMOS transistor of which a source and a drain are connected to the
sensing node of the currently selected pixel and the sensing node
of the nearest-neighboring pixel which is lately scanned, wherein
the row select signal is inputted to a gate thereof.
[0049] For example, if the unit pixel of the nth row is being
scanned now, the sensing node SN1 of the unit pixel in the n-1th
row which has been scanned lately and the sensing node SN2 of the
unit pixel in the nth row are shared with each other so as to
receive the photocharges from the photodiode PD2 of the unit pixel
in the nth row.
[0050] As stated above, since the CMOS image sensor of the present
invention shares the sensing node of the nearest-neighboring unit
pixel of a non-selected line when the specific unit pixel of a
selected line is operating, it is possible to receive much more
photocharges generated due to the enhanced fill-factor. That is,
the storage capacitance of the sensing node is increased in virtue
of the sharing scheme of the sensing node between
nearest-neighboring pixels so that it is possible to implement a
high quality CMOS image sensor.
[0051] The present application contains subject matter related to
the Korean patent application No. KR 2005-08654, filed in the
Korean Patent Office on Jan. 31, 2005, the entire contents of which
being incorporated herein by reference.
[0052] While the present invention has been described with respect
to certain preferred embodiments, it will be apparent to those
skilled in the art that various changes and modifications may be
made without departing from the spirit and scope of the invention
as defined in the following claims.
* * * * *