U.S. patent application number 15/429188 was filed with the patent office on 2018-06-21 for methods for fabricating metal gate structures.
This patent application is currently assigned to Shanghai Huali Microelectronics Corporation. The applicant listed for this patent is Shanghai Huali Microelectronics Corporation. Invention is credited to Yu Bao.
Application Number | 20180174923 15/429188 |
Document ID | / |
Family ID | 58892085 |
Filed Date | 2018-06-21 |
United States Patent
Application |
20180174923 |
Kind Code |
A1 |
Bao; Yu |
June 21, 2018 |
METHODS FOR FABRICATING METAL GATE STRUCTURES
Abstract
One aspect of the present disclosure is a method of fabricating
metal gate by forming a silicon-nitride layer (SiN) over a dummy
gate at a second metal gate type transistor region (e.g. NMOS)
avoid dummy gate loss during a CMP process for a PMOS gate. The
method can comprise after performing a patterning process to remove
hard masks at PMOS and NMOS regions, forming a SiN layer over the
NMOS region; performing a patterning process to open the PMOS
region and filling gate materials in the PMOS region; performing a
CMP to polish a top surface of PMOS such that the polishing stops
at SiN. In this way, dummy gate loss can be reduced during the
first aluminum CMP step and thus can reduce initial height of dummy
gate as compared to the convention method, and improve the filling
process of the dummy gate as compared to the conventional
method.
Inventors: |
Bao; Yu; (Shanghai,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Shanghai Huali Microelectronics Corporation |
Shanghai |
|
CN |
|
|
Assignee: |
Shanghai Huali Microelectronics
Corporation
Shanghai
CN
|
Family ID: |
58892085 |
Appl. No.: |
15/429188 |
Filed: |
February 10, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/6656 20130101;
H01L 21/823842 20130101; H01L 29/66545 20130101; H01L 21/32139
20130101; H01L 21/0217 20130101; H01L 21/31144 20130101; H01L
21/823828 20130101; H01L 29/78 20130101; H01L 21/31116 20130101;
H01L 21/0332 20130101; H01L 21/3212 20130101; H01L 29/4941
20130101; H01L 29/4966 20130101 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238; H01L 29/66 20060101 H01L029/66; H01L 21/3213 20060101
H01L021/3213; H01L 21/02 20060101 H01L021/02; H01L 21/321 20060101
H01L021/321; H01L 21/311 20060101 H01L021/311; H01L 21/033 20060101
H01L021/033 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 16, 2016 |
CN |
201611170270.2 |
Claims
1. A method for fabricating metal gates for a semiconductor device,
the method comprising: providing a substrate; and providing a first
metal gate type transistor region and a second metal gate type
transistor region on the substrate, wherein each of the first metal
gate type transistor region and second metal gate type transistor
region comprise a dummy gate; providing a zero order interlayer
dielectric layer (ILD0 layer) around the first metal gate type
transistor region and the second metal gate type transistor region;
forming a hard mask layer over the ILD0 layer; performing a
patterning processing to remove portion of the hard mask layer to
reveal dummy gates at the first metal gate type transistor region
and the second metal gate type transistor region; forming a
silicon-nitride (SiN) layer over the dummy gate at the second metal
gate type transistor region; performing a patterning process to
remove the dummy gate in the first metal gate type transistor
region and to form a first metal gate in the first metal gate type
transistor region, the first metal gate being of the first metal
gate type; performing a first chemical mechanical polishing (CMP)
process to polish the first metal gate in the first metal gate type
transistor region such that the polishing by the CMP process stops
at the SiN layer; and removing the SiN layer.
2. The method of claim 1, wherein the first metal gate type is
PMOS, and the second metal gate type is NMOS.
3. The method of claim 1, wherein the first metal gate type is
NMOS, and the second metal gate type is PMOS.
4. The method of claim 1, further comprising: forming a hard mask
layer over the ILD0 layer after the first layer is removed
performing a patterning process to remove the dummy gate in the
second metal gate type transistor region and to form a second metal
gate in the second metal gate type transistor region, the second
metal gate being of the second metal gate type; performing a
chemical mechanical polishing (CMP) process to polish the second
metal gate in the second metal gate type transistor region, wherein
the CMP process comprises removing the hard mask layer.
5. The method of claim 1, wherein the hard mask layer comprises
titanium nitride (TiN).
6. The method of claim 1, wherein the thickness of the SiN layer is
at least 100 Angstroms.
7. The method of claim 1, wherein the SiN layer is removed using a
dry etching process.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention is directed to semiconductor processes
and devices.
[0002] Since the early days when Dr. Jack Kilby at Texus Instrument
invented the integrated circuit, scientists and engineers have made
numerous inventions and improvements on semiconductor devices and
processes. The last five decades or so have seen a significant
reduction in semiconductor sizes, which translate to ever
increasing processing speed and decreasing power consumption. And
so far, the development of semiconductor has generally followed
Moore's Law, which roughly states that the number of transistors in
a dense integrated circuit doubles approximately every two years.
Now, semiconductor processes are pushing toward below 20 nm, where
some companies are now working on 14 nm processes. Just to provide
a reference, a silicon atom is about 0.2 nm, which means the
distance between two discrete components manufactured by a 20 nm
process is just about a hundred silicon atoms.
[0003] Manufacturing semiconductor devices has thus become more and
more challenging and pushing toward the boundary of what physically
possible. Huali Microeletronic Corporation.TM. is one of the
leading semiconductor fabrication companies that has focused on the
research and development of semiconductor devices and
processes.
[0004] When fabricating transistors with typical gate dimensions
below 50 nm, the so-called "high-k/metal gate" (HKMG) technology
has become popular. According to the HKMG manufacturing process
flow, an insulating layer included in the gate electrode is
comprised of a high-k material. This is in contrast to the
conventional oxide/polysilicon (poly/SiON) method, whereby the gate
electrode insulating layer is typically comprised of an oxide,
preferably silicon dioxide or silicon oxynitride in the case of
silicon-based devices. Currently, two different approaches exist
for implementing HKMG in the semiconductor fabrication process
flow. In the first approach, called gate-first, the fabrication
process flow is similar to that followed during the traditional
poly/SiON method. Formation of the gate electrode, including the
high-k dielectric film and the work function metal film, is
initially performed, followed by the subsequent stages of
transistor fabrication, e.g., definition of source and drain
regions, silicidation of portions of the substrate surface,
metallization, etc. On the other hand, according to the second
scheme, also known as gate-last or replacement gate, fabrication
stages such as dopant ion implantation, source and drain region
formation and substrate silicidation are performed in the presence
of a sacrificial dummy gate. The dummy gate is replaced by the real
gate after the high-temperature source/drain formation and all
silicide annealing cycles have been carried out.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIGS. 1A-F illustrate a process of a conventional two-step
CMP process for manufacturing a semiconductor device.
[0006] FIG. 2A illustrates, during an improved two-step CMP process
for manufacturing a semiconductor device in accordance with the
disclosure, after the ILD0 CMP, a patterning process may be
performed to reveal PMOS and NMOS dummy gates to remove a hard mask
layer over the PMOS and NMOS.
[0007] FIG. 2B illustrates a silicon nitride (SiN) layer may be
formed over NMOS.
[0008] FIG. 2C illustrates substitute materials may be filled in
PMOS region to form a PMOS gate and a CMP process may be formed to
polish a top surface of the PMOS gate.
[0009] FIG. 2D illustrates the SiN layer over the NMOS shown in 2B
may be removed and a patterning process may be performed to remove
the dummy gate at NMOS.
[0010] FIG. 2E illustrates substitute materials may be filled in
NMOS region to form a NMOS gate.
[0011] FIG. 2F illustrates a CMP process may be formed to polish a
top surface of the NMOS gate.
[0012] A further understanding of the nature and advantages of
various embodiments may be realized by reference to the following
figures. In the appended figures, similar components or features
may have the same reference label. Further, various components of
the same type may be distinguished by following the reference label
by a dash and a second label that distinguishes among the similar
components. If only the first reference label is used in the
specification, the description is applicable to any one of the
similar components having the same first reference label
irrespective of the second reference label.
DETAILED DESCRIPTION OF THE INVENTION
[0013] The present disclosure relates to fabrication of
high-k/metal gate (HKMG) stacks for semiconductors, in particular
to reducing diffusion of O2 into the IL after the HKMG stack is
formed.
[0014] The following description is presented to enable one of
ordinary skill in the art to make and use the invention and to
incorporate it in the context of particular applications. Various
modifications, as well as a variety of uses in different
applications will be readily apparent to those skilled in the art,
and the general principles defined herein may be applied to a wide
range of embodiments. Thus, the present invention is not intended
to be limited to the embodiments presented, but is to be accorded
the widest scope consistent with the principles and novel features
disclosed herein.
[0015] In the following detailed description, numerous specific
details are set forth in order to provide a more thorough
understanding of the present invention. However, it will be
apparent to one skilled in the art that the present invention may
be practiced without necessarily being limited to these specific
details. In other instances, well-known structures and devices are
shown in block diagram form, rather than in detail, in order to
avoid obscuring the present invention.
[0016] The reader's attention is directed to all papers and
documents which are filed concurrently with this specification and
which are open to public inspection with this specification, and
the contents of all such papers and documents are incorporated
herein by reference. All the features disclosed in this
specification (including any accompanying claims, abstract, and
drawings), may be replaced by alternative features serving the
same, equivalent or similar purpose, unless expressly stated
otherwise. Thus, unless expressly stated otherwise, each feature
disclosed is one example only of a generic series of equivalent or
similar features.
[0017] Furthermore, any element in a claim that does not explicitly
state "means for" performing a specified function, or "step for"
performing a specific function, is not to be interpreted as a
"means" or "step" clause as specified in 35 U.S.C. Section 112,
Paragraph 6. In particular, the use of "step of" or "act of" in the
Claims herein is not intended to invoke the provisions of 35 U.S.C.
Section 112, Paragraph 6.
[0018] Please note, if used, the labels left, right, front, back,
top, bottom, forward, reverse, clockwise and counter clockwise have
been used for convenience purposes only and are not intended to
imply any particular fixed direction. Instead, they are used to
reflect relative locations and/or directions between various
portions of an object.
[0019] The use of aluminum or aluminum alloy for metal gate
electrodes in a high-k gate structure has cost and performance
advantages. The aluminum gate chemical mechanical polishing (CMP)
process is a very important process for manufacturing high-k metal
gate transistors with aluminum gates. In order to increase the gap
filling space, a CMP process of aluminum gate structures typically
includes two CMP steps: a CMP process for P-type aluminum gate
transistors (PFET) and a CMP process for N-type aluminum gate
transistors (NFET). In the CMP process for the PFET, the dummy poly
is first removed in the PMOS region. During that step, the work
function deposition of the PMOS region is then completed and the
metal gate of the PMOS region is formed. After the metal gate of
the PMOS region is formed, the dummy poly is removed in the NMOS
region, and the work function deposition of the NMOS region is then
completed and the metal gate of the NMOS region is formed. Although
this two-step CMP process is relatively lengthy, it avoids
selective etching of the work function metal deposition, which can
be more difficult to control.
[0020] FIGS. 1A-F illustrate a process of a conventional two-step
CMP process for manufacturing a semiconductor device. FIG. 1A
illustrates, through this process, a semiconductor device 100 can
be provided over a substrate. As shown, spacers 106a-b can be
provided over the substrate using a double sidewall spacer process.
For illustrative purposes, the term sidewall spacers may be
referred to as both the first sidewall spacer 106a and the second
sidewall spacer 106b. In one embodiment, the sequential structure
of the sidewall spacers 106 from inside to outside is the silicon
oxide layer the first sidewall spacer 106 a--the silicon nitride
layer of the first sidewalls spacer 106 a--the silicon oxide layer
of the second sidewall spacers 106 b--the silicon nitride layer of
the second sidewall spacer 106b. In other embodiments, the sidewall
spacers 106 may be formed by a single sidewall spacer process,
e.g., the sidewall spacer may be made of only one of silicon oxide
and silicon nitride.
[0021] As also shown in FIG. 1A, an interlayer dielectric layer 104
may be formed on the substrate for example by a CVD process or a
PVD process. The interlayer dielectric layer 104 may be referred to
as a zero order interlayer dielectric layer, or ILD0. The
interlayer dielectric layer 104 may be made of any appropriate
isolation material, such as silicon oxide or silicon nitride, etc.
As still shown, the semiconductor device 100 may comprise a first
dummy gate 108a in a P-type metal gate transistor region (PFET), a
second dummy gate 108b in an N-type metal gate transistor region
(NFET). As also shown, a hard mark layer 102 may be formed over
ILD0 104. The hard mask layer 102 may be formed after a CMP process
on the ILD0 104 and comprises titanium nitride (TiN), and/or
HMOX.
[0022] FIG. 1B illustrates a patterning process can be performed
such that the dummy gate 108a at PFET can be removed to form a
cavity 110. FIG. 1C illustrates PFET work function metal gate
materials (e.g., aluminum) can be deposited into the cavity 110 to
form a PFET substitute metal gate 112a. FIG. 1D illustrates an
aluminum CMP process can then be used to polish the top surface of
the substitute metal gate 112a to ensure the height of the metal
gate 112a. The ILD0 104 is typically used to reduce the excessive
damage during this CMP process to ensure the accuracy of the height
of the substituted metal gate 112a deposited. Further, the ILD0 104
may be also used as a stress relief layer for subsequently formed
vias and metal interconnections to protect the semiconductor device
100. Specifically, during this CMP process, a relatively high
polishing speed may be used to polish the substituted metal gate
112a and as well as ILD0 104. FIG. 1E illustrates the dummy gate
108b at NFET is removed to form a cavity 110. FIG. 1F illustrates
work function metal gate materials can be deposited into the cavity
110 to form a NFET substitute metal gate 112b and another CMP
process may be performed to level the substitute metal gate 112b
with ILD0 104.
[0023] Since the conventional two-step CMP process as described
above typically employs a polish slurry that has a polysilicon
removal rate greater than the aluminum removal rate, there tends to
be over-polishing on the surface of dummy gate 108b during the CMP
for the PMOS gate 112a. Conventionally, to address such
over-polishing, extra ILD0 104 may be deposited. For example, if
the desired thickness of ILD0 104 is 600 angstroms after the PMOS
and NMOS gates are formed, and each ILD0 CMP process causes 100
angstrom loss due to the over-polishing, the initial ILD0 104 may
be deposited at 800 angstrom thick to account for the ILD0 loss
during the aforementioned the two-step CMP process.
[0024] However, since the initial thickness of the ILD0 is also the
height of cavities 110 formed during the dummy gate removal.
Accordingly, thicker ILD0 means deeper cavity 110 and an increased
height of dummy gate in the cavity. This increased ratio (due to
having to account for the dummy gate losses) can increase the
difficulty for filling the gate materials in cavity 110.
[0025] The present disclosure addresses and solves the current
problem of increased difficulty for filling the gate materials in
cavity 110 due to having to account for dummy gate losses during
the two-step CMP process. One aspect of the present disclosure is a
method of fabricating metal gate by forming a SiN layer over a
second metal gate transistor type region (e.g., NMOS) before
performing gate material filling and CMP at a first metal gate
transistor type region (e.g., PMOS)
[0026] Additional aspects and other features of the present
disclosure will be set forth in the description which follows and
in part will be apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the present disclosure. The advantages of the present
disclosure may be realized and obtained as particularly pointed out
in the appended claims.
[0027] According to the present disclosure, some technical effects
may be achieved in part by a method of fabricating a metal gate the
method comprising: after performing a patterning process to remove
hard masks at PMOS and NMOS regions, forming a SiN layer over the
NMOS region; performing a patterning process to open the PMOS
region and filling gate materials in the PMOS region; performing a
CMP to polish a top surface of PMOS such that the polishing stops
at SiN. In this way, dummy gate loss can be reduced during the
first aluminum CMP step and thus can reduce initial height of dummy
gate as compared to the convention method, and improve the filling
process of the dummy gate as compared to the conventional
method.
[0028] FIGS. 2A-E illustrate an improved process of fabricating
metal gates for a semiconductor device in accordance with a
disclosure. The process illustrated in these figures introduces
improvements over the two-step CMP process described and
illustrated above through FIGS. 1A-F, and thus will be described
with reference to FIGS. 1A-F. It should be understood although the
improved process illustrated in these figures start with a PMOS
gate fabrication, this is not intended to be limiting. In some
other embodiments, the improved process in accordance with the
disclosure can start with a NMOS gate fabrication. FIG. 2A
illustrates, during this improved process, after the ILD0 CMP, a
hard mask layer 102 can be formed over ILD0 104 and a patterning
process can be performed to reveal dummy gates 108a and 108b, at
PMOS and NMOS regions respectively.
[0029] FIG. 2B illustrates the dummy gate 108a can be removed to
form a cavity 110a. In some embodiments, this removal can be done
by using a Tetramethylammonium hydroxide (TMAH) process that can
dissolve polycrystalline silico. In some embodiments, the opening
of cavity 110a can be made wider than the width of dummy gate 108.
Also shown in FIG. 2B is that a SiN layer 202 can be formed over
dummy gate 108b at NMOS region when removing the dummy gate 108a.
Although the thickness of the SiN layer 202 may be however desired,
a thickness of 100 Angstroms or more is preferred for the SiN layer
202. In some embodiments, the SiN layer 202 may be formed after the
dummy gate 108a before filling in substitute gate materials in the
cavity 110a. FIG. 2C illustrates a patterning process can be
performed such that substituted gate materials can be filled into
cavity 110a to form gate 114a. Also illustrated in FIG. 2C is that
an aluminum CMP can be performed to polish the top surface of the
gate 114a such that the polishing is controlled to stop at the top
surface of the SiN layer 202. In some embodiments, as shown here,
the CMP process for PMOS gate may leave some gate material over the
hard mask layer 102 after the polishing stops at the SiN layer 202.
FIG. 2D illustrates after the CMP for the PMOS gate 114a, the SiN
layer 202 can be removed for example by a dry etching process, and
dummy gate 108b can be removed to form cavity 110b. FIG. 2E
illustrates substitute gate material can be filled in cavity 110b
to form a NMOS gate 114b. In some embodiments, not shown here, a
TiN layer may be formed over the PMOS gate 114a before removing the
SiN layer 202 and the dummy gate 114b. FIG. 2F illustrates another
aluminum CMP can be performed to polish the top surface of the NMOS
gate 114b. By this improved process, through depositing the SiN
layer 202 as illustrated, the dummy gate loss can be avoided during
the first aluminum CMP step in the process.
[0030] Embodiments of the present invention provide many advantages
over existing techniques and methods, as explained throughout the
parts of the application. It is to be appreciated that embodiments
of the present invention are compatible with existing systems and
processes. For example, the shaped cavities described according to
the embodiments of the present invention can be manufactured using
existing equipment. The shaped cavities according to embodiments of
the present invention can be easily used in manufacturing various
types of devices, such as CMOS, PMOS, NMOS, etc.
[0031] While the above is a full description of the specific
embodiments, various modifications, alternative constructions and
equivalents may be used. In addition to what is described above,
there are other embodiments as well. Therefore, the above
description and illustrations should not be taken as limiting the
scope of the present invention which is defined by the appended
claims.
* * * * *