U.S. patent application number 15/612982 was filed with the patent office on 2018-05-17 for fractional-n jitter attenuator.
This patent application is currently assigned to Perceptia Devices, Inc.. The applicant listed for this patent is Perceptia Devices, Inc.. Invention is credited to Andre Grouwstra, Julian Jenkins.
Application Number | 20180138915 15/612982 |
Document ID | / |
Family ID | 62108126 |
Filed Date | 2018-05-17 |
United States Patent
Application |
20180138915 |
Kind Code |
A1 |
Jenkins; Julian ; et
al. |
May 17, 2018 |
FRACTIONAL-N JITTER ATTENUATOR
Abstract
A phase-locked loop (PLL) has a primary loop (with a reference
clock) and a secondary loop (with a stable reference clock). The
secondary loop may include a fractional-N PLL, and may include a
secondary loop filter, oscillator, output clock counter, and phase
predictor using a rational secondary frequency control word (FCW).
The primary loop has a register sampling the oscillator phase from
the counter, and a phase predictor which uses a primary
fractional-N FCW to calculate a predicted phase as an integer
number. The primary loop forwards the integer difference between
the sampled phase and the predicted phase to a primary loop filter,
which outputs the secondary FCW. The primary loop filter has a much
lower bandwidth than the secondary loop filter. The PLL may have
multiple primary loops, with a hitless switching function. A
primary loop may have sleep mode. The PLL may also provide an
oscillator sleep function.
Inventors: |
Jenkins; Julian; (Kurraba
Point, AU) ; Grouwstra; Andre; (Morgan Hill,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Perceptia Devices, Inc. |
Scotts Valley |
CA |
US |
|
|
Assignee: |
Perceptia Devices, Inc.
Scotts Valley
CA
|
Family ID: |
62108126 |
Appl. No.: |
15/612982 |
Filed: |
June 2, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62422736 |
Nov 16, 2016 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03L 7/14 20130101; H03L
7/0992 20130101; H03L 7/085 20130101; H03L 2207/50 20130101; H03L
7/181 20130101; H03L 7/091 20130101; H03L 7/0802 20130101; H03L
7/087 20130101; H03L 7/1976 20130101; H03L 7/093 20130101; H03L
7/235 20130101 |
International
Class: |
H03L 7/14 20060101
H03L007/14; H03L 7/091 20060101 H03L007/091; H03L 7/197 20060101
H03L007/197 |
Claims
1. A fractional-N jitter attenuator, comprising: (a) a primary
loop, including: (i) a primary counter with an input and an output,
wherein the primary counter may include a modulo-K counter; (ii) a
primary register with a first input coupled with the primary
counter output and a second input configured for receiving a
primary reference clock signal, wherein the primary register is
configured to store a primary sampled phase from the primary
counter output upon receiving a primary reference clock signal
pulse; (iii) a primary fractional phase predictor with a first
input configured for receiving the primary reference clock signal,
wherein the primary fractional phase predictor is configured to
calculate a primary predicted phase upon receiving a primary
reference clock signal pulse, and wherein the primary predicted
phase includes an integer number and is based on a rational number
primary frequency control word (FCW); (iv) one of a primary
subtractor and a primary adder, configured for calculating an
integer number primary difference between the primary predicted
phase and the primary sampled phase; (v) a primary loop filter,
configured to receive the primary integer number difference, and to
provide a primary loop filtering action to generate a secondary
FCW; and (b) a secondary loop including a fractional-N PLL with a
first input configured for receiving a stable reference clock
signal, a second input configured for receiving the secondary FCW,
and an output configured to provide an output clock signal based on
the stable reference clock signal and the secondary FCW, the
secondary loop output being coupled with the primary counter input
and with a fractional-N jitter attenuator output.
2. The fractional-N jitter attenuator of claim 1, wherein the
secondary loop comprises: a controlled oscillator with an output
coupled with the secondary loop output, wherein the controlled
oscillator is configured to produce an output clock signal at its
output; a secondary counter with an input and an output, wherein
the input is coupled with the controlled oscillator output, and
wherein the secondary counter may include a modulo-K counter; a
secondary register with a first input coupled with the secondary
counter output and a second input configured for receiving the
stable reference clock signal, wherein the secondary register is
configured to store a secondary sampled phase from the secondary
counter output upon receiving a stable reference clock signal
pulse; a secondary phase predictor with a first input configured
for receiving the stable reference clock signal, wherein the
secondary phase predictor is configured to calculate a secondary
predicted phase based on the secondary FCW upon receiving a stable
reference clock signal pulse; one of a secondary subtractor and a
secondary adder, configured for calculating a secondary difference
between the secondary predicted phase and the secondary sampled
phase; and a secondary loop filter configured to receive the
secondary difference and provide a secondary loop filtering action
to generate an oscillator control code, the oscillator control code
being forwarded to the controlled oscillator and controlling a
controlled oscillator frequency.
3. The fractional-N jitter attenuator of claim 2, wherein the
primary and the secondary counters are combined into a single
counter.
4. The fractional-N jitter attenuator of claim 1, wherein a primary
loop filter bandwidth is at least one hundred times smaller than a
secondary loop filter bandwidth.
5. The fractional-N jitter attenuator of claim 1, further
comprising a time-to-digital converter coupled with the controlled
oscillator output, and configured to measure a fraction of a cycle
of the output clock signal upon receiving a primary reference clock
signal pulse, and wherein the primary sampled phase includes a
measured fraction of the cycle.
6. The fractional-N jitter attenuator of claim 2, further
comprising a time-to-digital converter coupled with the controlled
oscillator output, and configured to measure a fraction of a cycle
of the output clock signal upon receiving a stable reference clock
pulse, and wherein the secondary sampled phase includes a measured
fraction of the cycle.
7. The fractional-N jitter attenuator of claim 1, further
comprising a primary sleep signal input coupled with a first input
of a gate, and wherein a second input of the gate is configured to
receive the primary reference clock signal, the gate providing a
gated primary reference clock signal at an output, wherein the gate
output is coupled with the primary fractional phase predictor and
the primary register.
8. The fractional-N jitter attenuator of claim 1, wherein a range K
of the primary counter is at least two times larger than a maximum
number of output clock signal cycles during a primary reference
clock signal cycle.
9. The fractional-N jitter attenuator of claim 1, wherein the
primary fractional phase predictor has a range that is at least two
times larger than a maximum number of output clock signal cycles
during a primary reference clock signal cycle.
10. The fractional-N jitter attenuator of claim 1, wherein the
primary fractional phase predictor includes an interpolator for
determining an integer number part of the primary predicted phase
based on a fractional part of the FCW.
11. The fractional-N jitter attenuator of claim 10, wherein the
interpolator performs a noise-shaping function to move at least a
part of quantization noise energy from low frequencies to higher
frequencies.
12. The fractional-N jitter attenuator of claim 11, wherein the
interpolator includes one of a sigma delta modulator, a bandpass
sigma delta modulator, parallel sigma delta modulators, a
multistage noise shaping (MASH) modulator, and a sturdy MASH
(SMASH) modulator.
13. The fractional-N jitter attenuator of claim 2, further
comprising an oscillator sleep signal input, wherein the controlled
oscillator is configured to stop operation when it receives an
asserted oscillator sleep control signal.
14. The fractional-N jitter attenuator of claim 1, comprising
multiple primary loops.
15. The fractional-N jitter attenuator of claim 14, wherein at
least one of the multiple primary loops has a monitor-and-adjust
function to provide for hitless switching, and wherein the
monitor-and-adjust function monitors a primary difference in the
one of the multiple primary loops and adjusts a fractional phase
predictor value to minimize the primary difference.
16. A method for jitter attenuation, comprising the following
steps: (a) in a primary PLL loop, based on a primary reference
clock signal and a rational first frequency control word (FCW),
calculating an integer primary predicted phase; based on the
primary reference clock signal and a secondary PLL loop output
clock signal, sampling a phase at a counter output to obtain an
integer primary sampled phase, wherein the counter may include a
modulo-K counter; calculating a primary difference by subtracting
the primary sampled phase from the primary predicted phase; (b)
loop filtering the primary difference in a primary loop filter to
obtain a rational second FCW; (c) forwarding the second FCW to a
secondary loop; (d) based on the second FCW and a secondary
reference clock signal, calculating a secondary predicted phase;
based on the secondary reference clock signal and the secondary PLL
loop output clock signal, sampling a phase to obtain a secondary
sampled phase; calculating a secondary difference by subtracting
the secondary sampled phase from the secondary predicted phase; and
(e) loop filtering the secondary difference in a secondary loop
filter to obtain an oscillator control code to control a controlled
oscillator and to determine a frequency of the secondary PLL loop
output clock signal.
17. A programmable jitter attenuator, comprising: a fractional-N
PLL with a stable reference signal input and a frequency control
word (FCW) input, configured to produce an output clock signal at a
PLL output; a counter with an input coupled with the PLL output,
wherein the counter may include a modulo-K counter; a programmable
processor with a first input coupled with a counter output, a
second input configured for receiving a primary reference clock
signal, and an output coupled with the fractional-N PLL FCW input
to provide a secondary FCW; a memory coupled with the programmable
processor and configured to store at least one of program
instructions or data; wherein the programmable processor is
programmed to execute instructions for the following operations:
(a) in the programmable processor, based on the primary reference
clock signal and a rational primary FCW, calculating an integer
primary predicted phase; based on the primary reference clock
signal and the fractional-N PLL output clock signal, sampling a
phase at the counter output to obtain an integer primary sampled
phase; calculating a primary difference by subtracting the primary
sampled phase from the primary predicted phase; (b) loop filtering
the primary difference in a primary loop filter to obtain the
secondary FCW; and (c) forwarding the secondary FCW to the
fractional-N PLL to control the fractional-N PLL and to determine a
frequency of the fractional-N PLL output clock signal.
18. A tangible non-transitory memory, carrying software
instructions for the following operations: (a) in a programmable
processor, based on a primary reference clock signal and a rational
primary FCW, calculating an integer primary predicted phase; based
on the primary reference clock signal and a fractional-N PLL output
clock signal, sampling a phase at a counter output to obtain an
integer primary sampled phase, wherein the counter may include a
modulo-K counter; calculating a primary difference by subtracting
the primary sampled phase from the primary predicted phase; (b)
loop filtering the primary difference in a primary loop filter to
obtain a rational secondary FCW; and (c) forwarding the secondary
FCW to the fractional-N PLL to control the fractional-N PLL and to
determine a frequency of the fractional-N PLL output clock
signal.
19. A programmable jitter attenuator, comprising: a controlled
oscillator with an oscillator control code (OCC) input, and an
output configured to produce an output clock signal; a counter with
an input coupled with the controlled oscillator output, wherein the
counter may include a modulo-K counter; a programmable processor
with a first input coupled with a counter output, a second input
configured for receiving a primary reference clock signal, a third
input configured for receiving a secondary reference signal, and an
output coupled with the controlled oscillator input to provide an
OCC; a tangible non-transitory memory coupled with the programmable
processor and configured to store at least one of program
instructions or data; wherein the programmable processor is
programmed to execute instructions for the following operations:
(a) based on a primary reference clock signal and a rational
primary frequency control word (FCW), calculating an integer
primary predicted phase; based on the primary reference clock
signal and the output clock signal, sampling a phase at the counter
output to obtain an integer primary sampled phase; calculating a
primary difference by subtracting the primary sampled phase from
the primary predicted phase; (b) loop filtering the primary
difference in a primary loop filter to obtain a secondary FCW; (c)
based on the secondary FCW and the secondary reference clock
signal, calculating a secondary predicted phase; based on the
secondary reference clock signal and the output clock signal,
sampling a phase to obtain a secondary sampled phase; calculating a
secondary difference by subtracting the secondary sampled phase
from the secondary predicted phase; (d) loop filtering the
secondary difference in a secondary loop filter to obtain the OCC
to control a frequency of the output clock signal; and (e)
forwarding the OCC to the OCC input.
20. The programmable jitter attenuator of claim 19, wherein the OCC
is digital.
21. The programmable jitter attenuator of claim 19, wherein the OCC
is analog, the programmable jitter attenuator further comprising a
digital-to-analog converter to convert a digital OCC provided by
the programmable processor to analog.
22. A tangible non-transitory memory, carrying software
instructions for the following operations: (a) in a programmable
processor, based on a primary reference clock signal and a rational
primary frequency control word (FCW), calculating an integer
primary predicted phase; based on a primary reference clock signal
and a controlled oscillator output clock signal, sampling a phase
at a counter output to obtain an integer primary sampled phase,
wherein the counter may include a modulo-K counter; calculating a
primary difference by subtracting the primary sampled phase from
the primary predicted phase; (b) filtering the primary difference
in a primary loop filter to obtain a secondary FCW; (c) based on
the secondary FCW and a secondary reference clock signal,
calculating a secondary predicted phase; based on the secondary
reference clock signal and the output clock signal, sampling a
phase to obtain a secondary sampled phase; calculating a secondary
difference by subtracting the secondary sampled phase from the
secondary predicted phase; (d) filtering the secondary difference
in a secondary loop filter to obtain an oscillator control code
(OCC) to control a frequency of the output clock signal; and (e)
forwarding the OCC to a controlled oscillator input.
Description
CROSS REFERENCES TO RELATED APPLICATIONS
[0001] This application claims priority from U.S. provisional
patent application Ser. No. 62/422,736, entitled "Low-Power
Single-Loop and Multiple-Loop Fractional-N PLLs" filed on Nov. 16,
2016, which is hereby incorporated by reference as if set forth in
full in this application for all purposes.
[0002] This application is related to U.S. patent application Ser.
No. ______, entitled "Low-Power Fractional-N PLLs", filed on
<date>, which is hereby incorporated by reference as if set
forth in full in this application for all purposes.
BACKGROUND
[0003] The present invention relates generally to electronic
circuits used to generate clock signals and in particular to
digital phase-locked loops (PLLs).
[0004] Phase-Locked Loops (PLLs) are circuits that produce an
output clock signal whose phase is locked to the phase of an input
reference clock signal. Phase, in the context of a PLL, means a
signal's frequency value integrated over time, i.e., the signal's
accumulated number of clock pulses. The ratio of the frequency of
the output clock signal and the frequency of the reference clock
signal can be a positive integer number, in which case the PLL is
called an integer-N PLL; or it can be a positive rational number,
in which case the PLL is called a fractional-N PLL. Rational
numbers are numbers that can be expressed as a ratio of two
integers. In the context of this document, a fractional-N number is
a positive rational number consisting of an integer part (obtained
by rounding down to the nearest integer number) and a fractional
part.
[0005] A PLL includes a controlled oscillator that produces the
output clock signal. An analog PLL usually has a voltage-controlled
oscillator (VCO), and a digital PLL may have a digitally-controlled
oscillator (DCO). A PLL locks the phase (and as a result,
frequency) of the output clock signal to the reference clock signal
by measuring the accumulated number of output clock cycles, and
adjusting the controlled oscillator frequency when the measured
number deviates from a required number, referred to as or obtained
from a frequency control word (FCW). The ratio of output clock
cycles to reference clock cycles, measured over some duration, is
called the PLL's multiplication factor. When a PLL is in lock, its
multiplication factor matches its FCW.
[0006] Frequency-Locked Loops (FLLs) are circuits that produce an
output clock signal whose frequency is locked to the frequency of
an input reference clock signal. Compared to a PLL, an FLL lacks
the integration or accumulation over time. A PLL's integration may
occur anywhere in its loop, for example in feedback circuits, or in
feedforward circuits such as a loop filter. Whereas a PLL in lock
will lock both frequency and phase ratios in output and reference
signals, an FLL may lock only the frequency ratio but not
necessarily the phase ratio.
[0007] In an integer-N PLL, the frequency resolution of the output
clock signal equals the frequency of the reference clock signal,
since the output clock frequency equals a positive integer number
times the reference clock frequency. Increasing or decreasing the
positive integer number by one will result in the output clock
frequency increasing or decreasing by one times the reference
frequency. A finer output frequency resolution can be achieved by
using a lower reference clock frequency. However, in practical PLLs
this may increase the jitter.
[0008] A fractional-N PLL can have a much better output clock
frequency resolution without the need for a low reference clock
frequency, as the ratio between the output clock and reference
clock frequencies can be a positive rational number. An example of
a fractional-N PLL is described in U.S. Pat. No. 8,994,523,
entitled Phase-Locked Loop Apparatus and Method by Jenkins. The
circuits described there provide potentially very high accuracy and
low jitter, but at the expense of some energy. However, there is
also a need for fractional-N PLLs that consume very little power,
even if they operate with more jitter.
[0009] While most PLLs and FLLs have a single feedback loop, and
are capable of locking to a single reference clock signal, some
PLLs have multiple parallel feedback loops, allowing to lock to one
of multiple reference clock signals, not necessarily of the same
frequency. The capability to switch between the different reference
clock signals without facing a discontinuity in phase and therefore
a possibly extended lock-in time is called hitless switching. An
example hitless switching PLL is described in U.S. Pat. No.
9,007,105 by Jenkins.
[0010] A jitter attenuator is a PLL with the capability to provide
an output clock signal whose jitter is substantially lower than
jitter in the reference clock signal. A jitter attenuator usually
has nested feedback loops. For example, it may have one or more
primary feedback loops and one secondary feedback loop. The
secondary loop may be locked to a highly stable reference source,
such as a crystal oscillator, whereas the primary loop(s) may be
locked to one or more unstable or jittery reference sources. The
jitter attenuator's average output clock frequency may be locked to
the frequency of one of the jittery reference sources, whereas its
jitter may be determined by the stable reference source.
[0011] In many PLLs, whether used for logic clocking, video
clocking, instrumentation, wireless, wired or optical
communication, there is a need to lower power usage.
[0012] Reference to any prior art in the specification is not, and
should not be taken as, an acknowledgment or any form of suggestion
that this prior art forms part of the common general knowledge in
the USA, China, Australia, or any other jurisdiction or that this
prior art could reasonably be expected to be ascertained,
understood and regarded as relevant by a person skilled in the
art.
SUMMARY
[0013] In a first aspect (for example, FIGS. 11 and 12), an
embodiment of the invention includes a primary loop with a primary
reference clock input, and a secondary loop with a stable reference
clock signal input. The secondary loop includes a fractional-N PLL,
which may include a controlled oscillator, a modulo-K counter
coupled with the controlled oscillator, a secondary register, a
secondary phase predictor, a secondary subtractor or adder, and a
secondary loop filter. The secondary loop operates as a basic
fractional-N PLL, generating an output clock signal whose phase is
locked to the stable reference clock signal phase based on a
secondary frequency control word (FCW).
[0014] The primary loop includes a primary register, clocked by the
primary reference clock signal, sampling a modulo-K counter (its
own, or one shared with the secondary loop) output to obtain a
primary sampled phase as an integer number. A primary fractional
phase predictor calculates a primary predicted phase as an integer
number of clock cycles, based on the phase of the primary reference
clock signal (i.e., the number of reference clock signal pulses
received) and on a rational number primary FCW. A primary
subtractor or adder calculates the primary difference between the
primary sampled phase and the primary predicted phase. A primary
loop filter takes the primary difference (an integer number) and
filters it to generate the secondary FCW.
[0015] The modulo-K counter, the primary fractional phase
predictor, and the secondary phase predictor may each have a range
that is much larger than a maximum number of output clock cycles
during a reference clock signal cycle. The primary fractional phase
predictor may include an interpolator for determining an integer
number part of the primary predicted phase based on a fractional
part of the primary FCW. The interpolator may provide a
noise-shaping function, for example a sigma delta modulator or a
multistage noise shaping (MASH) modulator.
[0016] In embodiments, the primary loop filter bandwidth may be
much smaller than the secondary loop filter bandwidth. In some
embodiments, the secondary loop may include a time-to-digital
converter and may use rational numbers for the primary and/or
secondary FCW, a secondary predicted phase, a secondary sampled
phase, and a secondary phase difference. In other embodiments, some
or all of these secondary loop numbers may be integer.
[0017] In further embodiments (for example, as in FIG. 13), the
primary loop has a primary sleep signal input coupled with a gate
that blocks the primary reference clock signal when a primary sleep
mode control signal is asserted. Yet further embodiments may
include an oscillator sleep control signal input, to stop operation
of the controlled oscillator.
[0018] Even further embodiments may have multiple primary loops,
which may have monitor-and-adjust functions to provide for hitless
switching.
[0019] In a second aspect (FIG. 14), an embodiment provides a
method for jitter attenuation, with the following steps: (a) in a
primary PLL loop, based on a primary reference clock signal and a
rational first FCW, calculating an integer primary predicted phase;
based on the primary reference clock signal and a secondary PLL
loop output clock signal, sampling a phase at a modulo-K counter
output to obtain an integer primary sampled phase; calculating a
primary difference by subtracting the primary sampled phase from
the primary predicted phase; (b) forwarding the primary difference
to a secondary loop; (c) loop filtering the primary difference in a
primary loop filter to obtain a second FCW; (d) based on the second
FCW and a secondary reference clock signal, calculating a secondary
predicted phase; based on the secondary reference clock signal and
the secondary PLL loop output clock signal, sampling a phase to
obtain a secondary sampled phase; calculating a secondary
difference by subtracting the secondary sampled phase from the
secondary predicted phase; and (e) loop filtering the secondary
difference in a secondary loop filter to obtain an oscillator
control code to control a controlled oscillator and to determine a
frequency of the secondary PLL loop output clock signal.
[0020] In a third aspect (for example, FIG. 15 or FIG. 16), an
embodiment provides a programmable system for jitter attenuation,
and in a fourth aspect, an embodiment provides a tangible
non-transitory memory with instructions to provide a jitter
attenuation function.
[0021] As used herein, except where the context requires otherwise,
the term "comprise" and variations of the term, such as
"comprising", "comprises" and "comprised", are not intended to
exclude further additives, components, integers or steps.
[0022] Further aspects of the present invention and further
embodiments of the aspects described in the preceding paragraphs
will become apparent from the following description, given by way
of example and with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The invention will be described with reference to the
drawings, in which:
[0024] FIG. 1 illustrates a fractional-N PLL according to an
embodiment of the invention;
[0025] FIGS. 2A-D illustrate example fractional phase predictors
according to embodiments of the invention;
[0026] FIG. 3 illustrates a method for generating an output clock
signal whose phase is locked to a reference clock signal phase by a
rational number according to an embodiment of the invention;
[0027] FIG. 4 illustrates a programmable system capable of
implementing PLL methods according to embodiments of the invention;
and
[0028] FIG. 5 illustrates a fractional-N PLL with sleep modes
according to embodiments of the invention;
[0029] FIGS. 6 illustrates a mode diagram according to an
embodiment of the invention;
[0030] FIG. 7 illustrates a method to maintain phase lock and/or
approximate frequency lock in a PLL over a sleep period according
to an embodiment of the invention;
[0031] FIG. 8 illustrates a hitless switching multiple-loop PLL
according to an embodiment of the invention;
[0032] FIG. 9 illustrates a hitless switching multiple-loop PLL
with sleep modes according to an embodiment of the invention;
[0033] FIG. 10 illustrates a method for hitless switching in a
multiple-loop PLL according to an embodiment of the invention;
[0034] FIG. 11 illustrates a jitter attenuator according to an
embodiment of the invention;
[0035] FIG. 12 illustrates additional details of a jitter
attenuator according to some embodiments of the invention;
[0036] FIG. 13 illustrates details of a jitter attenuator with
multiple primary loops according to an embodiment of the
invention;
[0037] FIG. 14 illustrates a method for jitter attenuation
according to an embodiment of the invention;
[0038] FIG. 15 illustrates a programmable system capable of
implementing jitter attenuation methods according to embodiments of
the invention; and
[0039] FIG. 16 illustrates another programmable system capable of
implementing jitter attenuation methods according to embodiments of
the invention.
DETAILED DESCRIPTION
[0040] Phase-Locked Loops (PLLs) are circuits that produce an
output clock signal whose phase is locked to the phase of a
reference clock input signal. Phase, in the context of a PLL, means
a signal's frequency value integrated over time, i.e., the signal's
accumulated number of clock pulses. The ratio of the frequency of
the output clock signal and the frequency of the reference clock
signal can be a positive integer number, in which case the PLL is
called an integer-N PLL; or it can be a positive rational number,
in which case the PLL is called a fractional-N PLL. Rational
numbers are numbers that can be expressed as a ratio of two
integers. In the context of this document, a fractional-N number is
a positive rational number consisting of an integer part (obtained
by rounding down to the nearest integer number) and a fractional
part.
[0041] A digital PLL may measure the output clock phase, and
compare the measured phase with a required or predicted phase. The
required ratio is sometimes referred to as or obtained from a
frequency control word (FCW). The ratio of oscillator output clock
cycles to input reference clock cycles is called the PLL's
multiplication factor. When a PLL is in lock, its multiplication
factor matches its FCW. Embodiments of the invention perform
measurement of the output phase by counting the output clock cycles
in a modulo-K counter, which accumulates fully completed (i.e.,
integer) cycles only. A fractional phase predictor generates an
integer comparison phase, based on the reference clock and a
fractional-N FCW. The embodiments performs phase comparison using a
digital subtractor (or adder). They filter the comparison result in
a loop filter, and use the loop filter output to control the
oscillator. Embodiments of the invention are related to (but
different than) an earlier fractional-N PLL with a time-to-digital
converter described in U.S. Pat. No. 8,994,523, entitled
Phase-Locked Loop Apparatus and Method by Jenkins, which relied on
rational rather than integer phase comparison.
[0042] A modulo-K counter, for the purposes of this patent
document, is a counter that counts up to K pulses at an input,
providing a counted value at an output, restarting at a start value
upon counting every K.sup.th pulse. A modulo-K counter may count up
or count down. The start value may be zero, or any other value. The
counted value may be expressed as a binary number, or in any other
representation of a number. Examples in this patent document are
based on up-counting from a value 0 to a value K-1, after which the
counter restarts at 0. However, mutatis mutandis, all examples are
equally valid for counters counting down or starting at different
values. The value of K may be fixed, or it may be programmable, or
it may be made to vary over time.
[0043] FIG. 1 illustrates a fractional-N PLL 100 according to an
embodiment of the invention. PLL 100 receives reference clock
signal 101 and produces output clock signal 102. The frequency
ratio of output clock signal 102 and reference clock signal 101 is
determined by a fractional-N FCW that includes integer number N 103
and fraction of N 104. Controlled oscillator 110 produces output
clock signal 102. Modulo-K counter 120 accumulates the controlled
oscillator 110 frequency by counting cycles of output clock signal
102. Therefore, the modulo-K counter 120 output signal (at 105) is
representative for the phase of output clock signal 102. Upon
receiving a reference clock signal 101 pulse, register 130 samples
phase 105, stores it, and makes it available as sampled phase 106.
Register 130 may include a set of parallel latches, for example
D-latches with enable and data inputs, each latch for one bit of
the phase 105 code word, each latch triggered by reference clock
signal 101, and each latch providing one bit of the sampled phase
106 code word.
[0044] Fractional phase predictor 140 takes integer number N 103
and fraction of N 104, and upon receiving a reference clock signal
101 pulse, fractional phase predictor 140 calculates predicted
phase 107 as explained later with reference to FIGS. 2A-D. Although
fractional phase predictor 140 receives a fractional-N FCW,
embodiments may output predicted phase signal 107 as only an
integer number. Subtractor 150 calculates a difference 108 between
a required phase and a measured phase by subtracting sampled phase
106 from predicted phase 107. Loop filter 160 integrates and
filters difference 108 to produce oscillator control code 109,
which controls the frequency of output clock signal 102.
[0045] The fractional-N FCW includes integer number N 103, which
may have any integer value below a maximum R.sub.N, where R.sub.N
stands for the range of integer number N 103. It further includes
fraction of N 104, which may be expressed as an integer value M
below a maximum RM, where R.sub.M stands for the range of fraction
of N 104. The PLL 100 multiplication factor is f.sub.out/
f.sub.ref=(N+M/R.sub.M).
[0046] Modulo-K counter 120 and fractional phase predictor 140 need
to be able to track the phase of the output clock signal over a
sufficiently large range. For modulo-K counter 120 this range
equals K: upon reaching a counted value of K-1, the counter
continues counting at 0. Naturally, the range K needs to be large
enough to count R.sub.N cycles of output clock signal 102 during
one cycle of reference clock signal 101. To correct large phase
errors, or to relock at the correct phase after lock has been
temporarily lost, embodiments of the invention may use a large
range K, for instance K>>R.sub.N. For example, the range K of
the modulo-K counter may be at least two times larger than a
maximum number of output clock signal cycles R.sub.N during a
reference clock signal cycle. Thus, the maximum value of a phase
error is not limited by the period of reference clock signal 101,
but by the larger of K and a range of fractional phase predictor
140. The range of fractional phase predictor 140 is clarified with
reference to FIG. 2A.
[0047] FIG. 1 shows fractional-N PLL 100 as an example embodiment
with up-counting modulo-K counter 120 and an up-counting fractional
phase predictor 140. Other embodiments may use a down-counter
and/or a down-counting fractional phase predictor. Counting limits
may be chosen different than 0 and K, for example K and 0, or 0 and
-K, or any other set of integer values that differ by K. Some
embodiments may use an adder instead of a subtractor, and calculate
the sampled phase as a negative value.
[0048] In an embodiment alternative to FIG. 1, subtractor 150 is
omitted. The fractional phase predictor outputs a series of integer
numbers whose average equals the FCW determined by N (103) and
fraction of N (104). The embodiment programs the value of K in
modulo-K counter 120 to be equal to the output number of the
fractional phase predictor. Modulo-K counter 120 counts down from
the pre-programmed K to zero. Upon achieving zero, modulo-K counter
120 presets to the next K value that is output by the fractional
phase predictor. The embodiment interprets a counter output value
that is in a range below K as a negative number, meaning that the
controlled oscillator frequency is higher than the K times the
reference clock signal 101 frequency. In yet another alternative
embodiment, the K value is programmed similarly, however, the
counter counts down between K/2 and -K/2.
[0049] FIGS. 2A-D illustrate example fractional phase predictors
200A-D according to embodiments of the invention. If fractional-N
PLL 100 is in lock, then f.sub.out/f.sub.ref=FCW=(N+M/R.sub.M).
[0050] It follows that after c cycles of reference clock signal
101, there should be c.times.FCW cycles of output clock signal 102.
A fractional phase predictor takes a fractional-N FCW, but it
outputs an integer predicted phase, therefore, the predicted phase
may have the value round(c.times.FCW). Thus, the predicted phase
includes quantization noise. The range of a fractional phase
predictor is determined by the maximum value that the predicted
phase can have, i.e. the maximum value of round(c.times.FCW).
[0051] A most basic embodiment of a fractional phase predictor, as
will also be shown in FIG. 2B, is a fractional-N accumulator, whose
output bits are truncated to carry only the integer result of the
accumulation. However, simple truncation may introduce a
quantization noise spectrum that causes unacceptable output clock
jitter in some applications. Therefore, we prefer to view the
fractional phase predictor from the perspective described below.
All embodiments receive the fractional-N FCW that includes integer
number N 103 and fraction of N 104, as well as reference clock
signal 101. They all output the predicted phase 107 as an integer
number.
[0052] FIG. 2A illustrates a general embodiment 200A of fractional
phase predictor 140.
[0053] General embodiment 200A includes an integer-N accumulator
comprising adder 201 and register 202. Adder 202 adds integer
number N 103, predicted phase 107, and interpolated value 222 to
produce sum 221. Upon receiving a reference clock signal 101 pulse,
register 202 samples sum 221, stores it, and outputs it as an
updated value of predicted phase 107. Interpolator 203 receives
fraction of N 104 and outputs interpolated value 222. Interpolator
203 may provide dithering or noise shaping to change the
quantization noise spectrum and move part of the quantization noise
energy from low frequencies to higher frequencies. This is
advantageous for fractional-N PLL 100 in FIG. 1, because loop
filter 160 will generally be more effective in removing
high-frequency noise than low-frequency noise, as a result of which
controlled oscillator 110 will deliver a more stable output clock
signal 102. Interpolator 203 may provide dithering or noise shaping
through any method known in the art, for example using a sigma
delta modulator, a bandpass sigma delta modulator, parallel sigma
delta modulators, a multistage noise shaping (MASH) modulator, a
sturdy MASH (SMASH) modulator, etc.
[0054] FIG. 2B illustrates an example fractional phase predictor
200B according to an embodiment of the invention, wherein the
interpolator comprises a first order MASH modulator. Items 201 and
202, as well as signals 221 and 222 are the same as in FIG. 2A.
Interpolator 203 is implemented as an accumulator of fraction of N
104, comprising adder 204 and register 205. Adder 204 sums fraction
of N 104 and accumulated fraction 224 to produce sum 223. Upon
receiving a reference clock signal 101 pulse, register 205 samples
sum 223, stores it, and outputs it as an updated value of
accumulated fraction 224. When adder 204 overflows, it outputs a
carry signal as interpolated value 222 for adder 201.
[0055] MASH modulators have been well covered in the art. They were
first described by T. Hayashi, Y. Inabe, K. Uchimura, and A. Iwata
in "A multi stage delta-sigma modulator without double integration
loop" (ISSCC Digest of Technical Papers, pp. 182-183, 1986). FIGS.
2C and 2D illustrate embodiments 200C and 200D of the invention
using second and third order MASH modulators. Further embodiments
may implement even higher order MASH implementation. Basically,
each higher order implementation of a MASH modulator adds a stage
that takes quantization noise remaining from the previous stage and
moves it up to higher frequencies. Some embodiments of the
invention will work as required by an application just by
implementing a first order MASH interpolator, whereas other
embodiments may require a second or higher order MASH or other
modulator.
[0056] Although the example fractional phase predictors in FIGS.
2A-D have been described with adders to calculate a positive
integer predicted phase 107, other embodiments may use subtractors
and other elements to calculate the same result or to calculate a
negative integer value for predicted phase 107. All such variations
are within the ambit and scope of the present invention.
[0057] FIG. 3 illustrates a method 300 for generating an output
clock signal whose phase is locked to a reference clock signal
phase by a rational number according to an embodiment of the
invention. Method 300 comprises the following steps.
[0058] Step 310--in a controlled oscillator, generating an output
clock signal, wherein an output clock frequency is controlled by an
oscillator control code.
[0059] Step 320--in a modulo-K counter, counting a number of output
clock cycles. The modulo-K counter may count up or down, between a
minimum value, for example 0, and a maximum value, for example K-1.
Once it has reached the maximum (or minimum) value, it continues
counting at the minimum (or maximum) value, respectively. In some
embodiments, the value of K may be much higher than a maximum value
of the rational number, for example, at least two times higher.
[0060] Step 330--upon receiving a reference clock signal pulse,
sampling the counted number of output clock cycles and storing the
sampled number of output clock cycles in a register.
[0061] Step 340--upon receiving the reference clock signal pulse,
calculating an integer number of predicted output clock cycles
based on an integer number representing the reference clock signal
phase and a rational frequency control word number. Embodiments may
perform the calculation by accumulating at least part of the
frequency control word for each newly received reference clock
signal pulse. The reference clock signal phase is determined by the
number of received reference clock signal pulses. An embodiment may
increment the number of predicted output clock cycles with the
value of the frequency control word each time it receives a
reference clock signal pulse; therefore, the number of predicted
output clock cycles will equal the reference clock signal phase
times the frequency control word. Embodiments may further perform
noise shaping by shifting quantization noise to higher frequencies,
for example by using delta sigma modulators or MASH modulators.
Steps 330 and 340 may occur in either order or in parallel.
[0062] Step 350--calculating a difference between the integer
number of predicted output clock cycles and the sampled number of
output clock cycles, and forwarding the difference to a digital
loop filter.
[0063] Step 360--in the digital loop filter, filtering the
calculated difference to generate an updated oscillator control
code, and in the controlled oscillator, updating the output clock
frequency. The digital loop filter may have any frequency and phase
transfer function as usual or as known in the art of PLL design
provided that the transfer function enables PLL stability. In
embodiments, filter parameters in the digital loop filter may be
fixed or programmable.
[0064] Step 370--upon receiving successive reference clock signal
pulses, updating the sampled number of output clock cycles and the
predicted output clock cycles to provide the controlled oscillator
updated oscillator control codes to lock the output clock signal
phase to the reference clock signal phase.
[0065] FIG. 4 illustrates a programmable system 400 capable of
implementing PLL methods according to embodiments of the invention.
System 400 is a PLL that comprises a controlled oscillator 410, a
modulo-K counter 420, a programmable processor 430, and a memory
440. Programmable system 400 is configured to store software
instructions and/or data in memory 440. Programmable processor 430
receives reference clock signal 401, and a FCW comprising integer
part N 403 and fractional part M 404. Programmable processor 430
outputs oscillator control code 405 to controlled oscillator 410.
Controlled oscillator 410, whose frequency is controlled by
oscillator control code 405, outputs the output clock 402. Modulo-K
counter 420 counts cycles of output clock 402, and its output
signal 406 is a measure for the output clock phase, which it feeds
back to programmable processor 430. Some embodiments may store
integer part N 403 and fractional part M 404 as parameters in
memory 440, either as part of the software instructions or as part
of the data. Further embodiments may receive multiple reference
clock signals, and may work with multiple FCWs. Yet further
embodiments may use separate memories for software instructions and
data.
[0066] Programmable processor 430 may, for example, be programmed
to execute instructions for the following operations:
[0067] (a) upon receiving a reference clock signal 401 pulse,
sampling a modulo-K counter 420 output value 406 and storing the
output value 406 as a sampled phase in a register;
[0068] (b) upon receiving the reference clock signal 401 pulse,
calculating an integer number of predicted output clock cycles
based on an integer number representing a reference clock signal
phase and a rational number representing a FCW;
[0069] (c) calculating a difference between the integer number of
predicted output clock cycles and the sampled phase;
[0070] (d) integrating and filtering the calculated difference to
generate an updated oscillator control code; and
[0071] (e) upon receiving a successive reference clock signal
pulse, updating the sampled phase and the number of predicted
output clock cycles to provide the controlled oscillator updated
oscillator control codes to lock the output clock signal phase to
the reference clock signal phase.
[0072] FIG. 5 illustrates a fractional-N PLL 500 with sleep modes
according to embodiments of the invention. Some embodiments,
capable of maintaining phase lock over a sleep period (ignoring the
reference clock during the sleep period), feature gated output
clock signal 502A. Other embodiments, capable of maintaining
approximate frequency lock while free-running during a partial
sleep period, feature ungated output clock signal 502B. Yet other
embodiments feature both gated output clock signal 502A and ungated
output clock signal 502B.
[0073] PLL 500 is similar to PLL 100 of FIG. 1, with the addition
of sleep mode control signals Sleep1 (505) and SleepOsc (506) and
associated gates 522 and 528. A line above a signal name indicates
that the signal is asserted when it is low. PLL 500 has the
following modes: active, first sleep, and in some embodiments also
second sleep. In active mode, the signals Sleep1 (505) and SleepOsc
(506) are de-asserted. In first sleep mode, the signal Sleep1 (505)
is asserted and SleepOsc (506) is de-asserted. In second sleep
mode, both signals Sleep1 (505) and SleepOsc (506) are asserted. In
active mode, PLL 500 operates the same as PLL 100. In the example
embodiment drawn, Sleep1 (505) may be changed synchronously to
reference clock signal 501.
[0074] In active mode, controlled oscillator 520 oscillates, and
its output signal, which may be available as ungated output clock
signal 502B, passes through gate 522, which may comprise an AND
gate as shown in this example, to gated output clock signal 502A
and to modulo-K counter 524. Modulo-K counter 524 calculates the
controlled oscillator 520 phase 508 by counting cycles of gated
output clock signal 502A. Upon receiving a reference clock signal
501, passing through gate 528, which may comprise an AND gate as
shown in this example, register 526 samples phase 508, stores it,
and makes it available as sampled phase 509. Register 526 may
include a set of parallel latches, for example D-latches with
enable and data inputs, each latch for one bit of the phase 508
code word, each latch triggered by gated reference clock 510, and
each latch providing one bit of the sampled phase 509 code
word.
[0075] Fractional phase predictor 530 takes integer number N 503
and fraction of N 504 (together a fractional-N FCW), and upon
receiving gated reference clock signal 510, fractional phase
predictor 530 calculates predicted phase signal 511 such as was
explained in detail with reference to FIGS. 2A-D. Although
fractional phase predictor 530 receives a fractional-N FCW,
embodiments may output predicted phase signal 511 as only an
integer number. Subtractor 532 calculates a difference 512 between
a required phase and a measured phase by subtracting sampled phase
509 from predicted phase 511. Loop filter 534 integrates and
filters difference 512 to produce oscillator control code 513,
which controls the controlled oscillator 520's frequency.
[0076] The fractional-N FCW includes integer number N 503, which
may have any integer value below a maximum R.sub.N, where R.sub.N
stands for the range of integer number N 503. It further includes
fraction of N 504, which may have any integer value M below a
maximum R.sub.M, where R.sub.M stands for the range of fraction of
N 504. The PLL 500 multiplication factor is
f.sub.out/f.sub.ref=(N+M/R.sub.M).
[0077] Modulo-K counter 524 and fractional phase predictor 530 need
to be able to track the phase of the output clock over a
sufficiently large range. For modulo-K counter 524 this range
equals K: upon reaching a counted value of K-1, the counter
continues counting at 0. Naturally, the range K needs to be large
enough to count R.sub.N cycles of gated output clock signal 502A
during one cycle of gated reference clock 510. To correct large
phase errors, or to relock at the correct phase after lock has been
temporarily lost, embodiments of the invention may use a large
range K, for instance K>>R.sub.N. For example, the range K of
the modulo-K counter may be at least two times larger than a
maximum number of output clock signal cycles R.sub.N during a
reference clock signal cycle. Thus, the maximum value of the phase
error is not limited by the period of the reference clock signal
501, but by the larger of K and the range of fractional phase
predictor 530.
[0078] First sleep mode commences when signal Sleep1 (505) is
asserted, for example, as drawn when it is pulled low. At that
time, gate 528 blocks reference clock signal 501, and gate 522
blocks gated output clock signal 502A. Therefore, modulo-K counter
524 receives no clock cycles to count, and fractional phase
predictor 530 and register 526 do not update. As a result, the
embodiment uses less power in modulo-K counter 524, register 526,
fractional phase predictor 530, subtractor 532, and loop filter
534. Signal SleepOsc (506) may subsequently be asserted to enter
second sleep mode and stop controlled oscillator 520 to save
further power.
[0079] Signal SleepOsc (506) is de-asserted no later than signal
Sleep1 (505) is de-asserted, i.e., oscillator 520 is started no
later than reference clock signal 501 and output clock signal 502
are (re-)enabled. By starting controlled oscillator 520 early and
by stopping it late with reference to signal Sleep1 (505), a user
can isolate gated output clock signal 502A from controlled
oscillator 520 start-up or power-down behavior.
[0080] To maintain phase accuracy, signal Sleep1 (505) must be
asserted and de-asserted synchronously to reference clock signal
502. Some embodiments may enforce synchronicity by passing signal
Sleep1 (505) to a D-latch 536 enabled by reference clock signal
501, and using a D-latch output signal 505A as an input signal for
gates 528 and 522.
[0081] An embodiment of example fractional-N PLL 500 that does not
require synchronicity of signal Sleep1 (505) to reference clock
signal 501 may copy either sampled phase 509 or sampled phase 509
corrected for a current difference 512 (by subtracting the current
difference 512 from sampled phase 509) to a register in fractional
phase predictor 530 upon receiving the first reference clock signal
501 pulse after sleep mode, such that a discontinuity in phase
difference is avoided and the updated difference 512 equals zero or
the current difference 512. For example, an embodiment using the
fractional phase predictor 200A in FIG. 2A may copy the sampled
phase 509 in FIG. 5 to register 202 in FIG. 2A. Or the embodiment
may correct sampled phase 509 by subtracting a current difference
512 and copy the corrected value to register 202. However, in such
an embodiment, example fractional-N PLL 500 only maintains
approximate frequency lock but not phase lock over the sleep mode
period.
[0082] FIG. 5 shows example fractional-N PLL 500 as an embodiment
with up-counting modulo-K counter 524 and an up-counting fractional
phase predictor 530. Other embodiments may use a down-counter
and/or a down-counting fractional phase predictor. Counting limits
may be chosen different than 0 and K, for example K and 0, or 0 and
-K, or any other set of values that differ by K. Some embodiments
may use an adder instead of a subtractor, and calculate the sampled
phase as a negative value. FIG. 5 shows example fractional-N PLL
500 as an embodiment with AND gates for gates 522 and 528, and with
the signals Sleep1 and SleepOsc asserted negative. A person having
ordinary skill in the art will know that gating of reference clock
signal 501 and output clock signal 502A can just as easily be
achieved with another type of gate, such as a NAND gate, an OR
gate, a NOR gate, an XOR gate, a pass gate, and a combination of
any number of those gates, and with either one or both of the sleep
signals asserted positive. Such embodiments are fully within the
scope and ambit of the invention.
[0083] Whereas the use of gated output clock signal 502A allows
keeping phase lock over a period of at least the first sleep mode,
ignoring any reference clock cycles during the period, the use of
ungated output clock signal 502B allows maintaining approximate
frequency lock while free-running during the first sleep mode.
Embodiments keep the loop filter 534 output at a fixed oscillator
control code, approximately fixing the output clock signal 502B
frequency. During first sleep mode, only controlled oscillator 520
is active, and example fractional-N PLL 500 can save power of
operating the other included circuits.
[0084] FIG. 6 illustrates a mode diagram 600 according to an
embodiment of the invention.
[0085] Mode diagram 600 in FIG. 6 illustrates the modes in FIG. 5.
There are three modes: active mode, first sleep mode, and (in some
embodiments) second sleep mode. An embodiment transitions from the
active mode to the first sleep mode when the signal Sleep1 is
asserted, and from the first sleep mode to active mode when the
signal Sleep1 is de-asserted. An embodiment that also has the
second sleep mode transitions from the first sleep mode to the
second sleep mode when the signal SleepOsc is asserted, and it
transitions from the second sleep mode to the first sleep mode when
the signal SleepOsc is de-asserted.
[0086] In the first sleep mode, the embodiment disables the
reference clock signal, the gated output clock signal, the modulo-K
counter, the register, the fractional phase predictor, the
subtractor, and the loop filter. In the second sleep mode, it
disables the same circuits as in the first sleep mode, as well as
the controlled oscillator.
[0087] FIG. 7 illustrates method 700 to maintain phase lock and/or
approximate frequency lock in a PLL over a sleep period, wherein
the PLL has an active mode and at least a first sleep mode, and the
PLL is configured to receive a reference clock signal and at least
a first sleep mode control signal. Method 700 comprises the
following steps.
[0088] Step 710--during active mode, upon receiving a reference
clock signal pulse, determining a controlled oscillator's phase,
determining a predicted phase, and adjusting a controlled
oscillator frequency based on a difference between the controlled
oscillator's phase and the predicted phase. An embodiment may
sample the controlled oscillator's phase in a register and store it
as an integer number. The embodiment may determine the predicted
phase based on a fractional-N FCW and calculate the predicted phase
as an integer number. The embodiment may perform noise shaping on
the predicted phase.
[0089] Step 720--receiving a change in the first sleep mode control
signal. In some embodiments, the change in the first sleep mode
control signal may arrive synchronously with the reference clock
signal.
[0090] Step 730--upon determining that the first sleep mode control
signal is asserted: [0091] a. canceling the active mode [0092] b.
entering the first sleep mode [0093] c. freezing sampled and
predicted phase values, phase difference, loop filter internal
values, and a resulting oscillator control code (OCC) [0094] d.
blocking the reference clock signal and a gated output clock signal
[0095] e. (optional) continuing to use an ungated output clock
signal as a signal in approximate frequency lock with the reference
clock signal [0096] f. continuing with step 720.
[0097] Step 740--upon determining that the first sleep mode control
signal is not asserted: [0098] a. canceling the first sleep mode
[0099] b. entering active mode [0100] c. unfreezing the sampled and
predicted phase values, phase difference, loop filter internal
values, and the resulting OCC [0101] d. unblocking the reference
clock signal and the gated output clock signal, wherein the gated
output clock signal may be used as a signal in phase lock with the
reference clock signal [0102] e. continuing with step 710.
[0103] In embodiments in which the de-asserted first sleep mode
control signal may arrive a-synchronously with the reference clock
signal, step 740 may further comprise: determining an updated
predicted phase by copying either an updated sampled phase or a
corrected updated sampled phase to a register in a fractional phase
predictor, wherein the corrected updated sampled phase includes the
updated sampled phase minus a current difference.
[0104] Method 700 may additionally include the following steps:
[0105] Step 750--receiving a change in a second sleep mode control
signal. Note that after step 730, an embodiment may receive either
a change in the first sleep mode control signal (step 720) or in
the second sleep mode control signal (step 750), and in both cases
it responds correctly. This means that an embodiment, after step
730, may continue with either step 720 or step 750 as required by
the sleep mode control signal that is changing. The embodiment
monitors both signals in parallel.
[0106] Step 760--upon determining that the second sleep mode
control signal is asserted: [0107] a. entering a second sleep mode
[0108] b. stopping the controlled oscillator [0109] c. continuing
with step 750.
[0110] Step 770--upon determining that the second sleep mode
control signal is not asserted: [0111] a. canceling the second
sleep mode [0112] b. starting the controlled oscillator [0113] c.
continuing with step 720.
[0114] FIG. 8 illustrates a hitless switching multiple-loop PLL 800
according to an embodiment of the invention. Some applications use
multiple reference clock signals. This may for instance be the case
when the best reference signal is not always available, but there
are some backup reference signals that can be used instead. Or the
system may have multiple active modes, where each mode provides its
own reference clock signal. The reference clock signals may have
different frequencies, and/or different reference clock signals may
need multiplication with different FCWs.
[0115] The capability to switch between the different reference
clock signals without facing a discontinuity in phase and therefore
a possibly extended lock-in time is called hitless switching. An
example hitless switching PLL is described in U.S. Pat. No.
9,007,105 by Jenkins. Some embodiments of the present invention, as
described in the following, are related to the PLL in U.S. Pat. No.
9,007,105.
[0116] Multiple-loop PLL 800 features 2 or more parallel loops,
each dedicated to one of the reference clock signals 801.1-801.n,
and each taking a FCW comprising integer number N.x (803.x) and
fraction M.x (804.x). Multiple-loop PLL 800 has the following
common blocks, shared by all loops: controlled oscillator 810,
modulo-K counter 820, multiplexer 870, and loop filter 880. The
frequency of controlled oscillator 810 is controlled by oscillator
control code 889. Controlled oscillator generates output clock
signal 802, which is also an input signal for modulo-K counter 820
that measures an integer value for phase 884.
[0117] Each loop has an individual register 830.1-830.n, subtractor
840.1-840.n, fractional phase predictor 850.1-850.n, and
monitor-and-adjust block 860.1-860.n. Each register 830.x, upon
receiving a reference clock signal 801.x pulse, samples phase 884
and stores it as sampled phase 885.x. Each fractional phase
predictor 850.x, upon receiving a reference clock signal 801.x
pulse, calculates a predicted phase 886.x. Each subtractor 840.x
subtracts sampled phase 885.x from predicted phase 886.x to
calculate difference 887.x. Each difference 887.x is an input
signal for multiplexer 870, which selects one of them and passes it
to loop filter 880 as the selected difference 888. Loop filter 880
integrates and filters the selected difference 888 to produce
oscillator control code 889.
[0118] Fractional phase predictors 850.x take integer numbers N
803.x and their fractions M 804.x (together forming fractional-N
FCWs), and upon receiving a reference clock signal 801.x pulse, a
fractional phase predictor 850.x calculates predicted phase 886.x
as explained earlier with reference to FIGS. 2A-D. Although
fractional phase predictor 850.x receives a fractional-N FCW,
embodiments may output predicted phase signal 886.x as only an
integer number.
[0119] Modulo-K counter 820 and fractional phase predictors
850.1-850.n need to be able to track the phase of the output clock
over a sufficiently large range. For modulo-K counter 820 this
range equals K: upon reaching a counted value of K-1, the counter
continues counting at 0. Naturally, the range K needs to be large
enough to count R.sub.N cycles of output clock signal 802 during
one cycle of reference clock signal 801.x. To correct large phase
errors, or to relock at the correct phase after lock has been
temporarily lost, embodiments of the invention may use a large
range K, for instance K>>R.sub.N. For example, the range K of
the modulo-K counter 820 may be at least two times larger than a
maximum number of output clock signal cycles R.sub.N during a
reference clock signal cycle. Thus, the maximum value of a phase
error is not limited by the period of reference clock signal 801.x,
but by the larger of K and a range of fractional phase predictor
850.x. The range of fractional phase predictors 850.x has been
clarified with reference to FIG. 2A.
[0120] The monitor-and-adjust blocks 860.1-860.n are active only
for loops that are not selected by multiplexer 870.
Monitor-and-adjust blocks 860.1-860.n monitor the differences
887.1-887.n from the respective subtractors 840.1-840.n and adjust
registers (not shown) inside fractional phase predictors
850.1-850.n to minimize these differences 887.1-887.n.
[0121] A simple embodiment of a monitor-and-adjust block 860.x may
just copy the sampled phase 885.x into the register (not shown, but
for instance register 202 in FIG. 2A) inside fractional phase
predictor 850.x so that the last prediction is effectively
correct.
[0122] The monitor-and-adjust blocks 860.1-860.n are enabled only
for fractional phase predictors 850.1-850.n that are not currently
used for the active loop through multiplexer 870. Any adjustment in
the currently active loop can break the desired relationship
between input and output frequency. The function of a
monitor-and-adjust block 860.x is to maintain the minimum phase
error of currently unused reference clock signal 801.x, and
indicate if its frequency is at the desired ratio to the output
clock signal.
[0123] In embodiments of the invention, multiplexer 870 can be
replaced by an averaging block that creates an error signal
replacing selected difference 888 by averaging all the differences
887.1-887.n that are currently valid and whose monitor-and-adjust
blocks 860.1-860.n have the difference 887.1-887.n associated with
any valid reference clock signal 801.1-801.n close to zero. In this
case, output clock signal 802 is effectively locked to all valid
inputs and altering the members of the valid set has an even
smaller impact on phase.
[0124] An embodiment can be optimized to have less circuitry. For
example, instead of individual monitor-and-adjust blocks
860.1-860.n, an embodiment may have a single monitor-and-adjust
block that cycles through fractional phase predictors 850.1-850.n,
adjusting only one at a time.
[0125] FIG. 8 shows multiple-loop PLL 800 as an example embodiment
with up-counting modulo-K counter 820 and an up-counting fractional
phase predictors 850.1-850.n. Other embodiments may use a
down-counter and/or down-counting fractional phase predictors.
Counting limits may be chosen different than 0 and K, for example K
and 0, or 0 and -K, or any other set of integer values that differ
by K. Some embodiments may use adders instead of subtractors, and
calculate the sampled phases as negative values.
[0126] FIG. 9 illustrates a hitless switching multiple-loop PLL 900
with sleep modes according to an embodiment of the invention.
Multiple-loop PLL 900 is similar to multiple-loop PLL 800, with the
addition of sleep mode(s). Each loop may have an extra input
Sleep.x, driving a gate 914.x, which may comprise an AND gate as
shown in this example. Gate 914.x blocks reference clock signal
901.x in sleep mode, and passes it on in active mode. The Sleep.x
signal further stops monitor-and-adjust block 960.x in sleep mode.
Embodiments may allow each loop individually to enter a sleep mode
or active mode. Whereas multiplexer 970 will select only one loop
at a time, this does not necessarily mean that all other loops can
be in sleep mode. For hitless switching to occur, a loop needs to
be active even while it is not selected. However, if a loop has
been active for at least once cycle of reference clock signal
901.x, then, as drawn in FIG. 9, hitless switching can occur.
[0127] The embodiment may further include sleep mode signal
SleepOsc, which can stop operation of controlled oscillator 910.
This type of sleep mode impacts all loops, and fully halts
operation of multiple-loop PLL 900.
[0128] FIG. 9 shows example multiple-loop PLL 900 as an embodiment
with up-counting modulo-K counter 920 and an up-counting fractional
phase predictors 950.x. Other embodiments may use down-counters
and/or down-counting fractional phase predictors. Counting limits
may be chosen different than 0 and K, for example K and 0, or 0 and
-K, or any other set of integer values that differ by K. Some
embodiments may use an adder instead of subtractor 940.x, and
calculate the sampled phase as a negative value. FIG. 9 shows
example multiple-loop PLL 900 as an embodiment with AND gates for
gates 914.1-914.n, and with the signals Sleep1 and SleepOsc
asserted negative. A person having ordinary skill in the art will
know that gating of reference clock signals 901.1-901.n can just as
easily be achieved with another type of gate, such as a NAND gate,
an OR gate, a NOR gate, an XOR gate, a pass gate, and a combination
of any number of those gates, and with either one or both of the
sleep signals asserted positive. Such embodiments are fully within
the scope and ambit of the invention.
[0129] FIG. 10 illustrates a method 1000 for hitless switching in a
multiple-loop PLL according to an embodiment of the invention.
Method 1000 comprises the following steps.
[0130] Step 1010--in a modulo-K counter, continuously counting a
number of controlled oscillator output clock signal cycles.
[0131] Step 1020--receiving a reference clock pulse.
[0132] Step 1030--determining in which loop the reference clock was
received.
[0133] Step 1040--upon determining that a first pulse of a first
reference clock signal was received in a selected first loop,
sampling the number of output clock cycles to obtain a first
sampled phase. Based on a first rational FCW and the first pulse,
calculating a first predicted phase as an integer number in a first
fractional phase predictor. Forwarding a first difference between
the first predicted phase and the first sampled phase to a loop
filter to generate a first oscillator control code to control a
frequency of the controlled oscillator. Continue with step
1020.
[0134] Step 1050--upon determining that a second pulse of a second
reference clock signal was received in a second loop that is not
selected, sampling the number of output clock cycles to obtain a
second sampled phase. Based on a second rational FCW and the second
pulse, calculating a second predicted phase as an integer number in
a second fractional phase predictor. Calculating a second
difference between the second predicted phase and the second
sampled phase.
[0135] Step 1060--updating a register in the second fractional
phase predictor such that the second difference remains within a
small margin of zero. The small margin may be a margin that is
calculated from the loop gain. The feedback loop in a PLL will
operate to keep the first difference small, or generally the phase
difference of the selected loop, where the maximum size of the
difference depends on the loop gain. A larger gain will result in a
smaller difference, therefore the margin is inversely proportional
to the loop gain. Continue with step 1020.
[0136] Some embodiments may set the small margin at zero and simply
copy the value of the second sampled phase into the register in the
second fractional phase predictor.
[0137] Method 1000 may further comprise the following steps (not
shown in FIG. 10):
[0138] Step 1070--upon receiving a loop sleep signal for the second
loop: disabling updating of the second sampled phase, disabling the
second fractional phase predictor.
[0139] Step 1080--upon receiving the loop sleep signal for the
second loop: disabling a second monitor-and-adjust function.
[0140] Step 1090--upon receiving a PLL sleep signal, disabling the
controlled oscillator.
[0141] FIG. 11 illustrates a jitter attenuator 1100 according to an
embodiment of the invention. The concept of a jitter attenuator is
that a primary loop can lock to a primary reference clock signal
with poor jitter behavior, whose frequency must be followed by an
output clock signal, and that a secondary loop creates the actual
output clock signal, based on the phase and stability of a
secondary reference clock signal. By using different
characteristics for loop filters for the primary loop and the
secondary loop, embodiments can set different output clock phase
noise spectra for the two different reference clock signal sources.
For example, the active primary loop may determine the average
frequency and lowest frequency phase noise, whereas the secondary
loop may determine phase noise at higher frequencies. This can be
accomplished by using a primary loop filter bandwidth that is much
smaller than a secondary loop filter bandwidth, for example at
least one hundred times smaller.
[0142] Jitter attenuator 1100 comprises a primary loop 1112 and a
secondary loop 1110 which includes a fractional-N PLL. Primary loop
1112 includes a primary modulo-K counter 1122B whose input is
coupled with a clock output of the fractional-N PLL in secondary
loop 1110. A primary register 1142 has an input coupled with the
primary modulo-K counter output, and a sample input that is clocked
by a primary reference clock signal 1101 received at a primary
reference clock signal 1101 input. Primary modulo-K counter 1122B
measures the phase of the fractional-N PLL output clock signal
1102, and primary register 1142 samples the phase upon receiving a
primary reference clock signal 1101 pulse to obtain sampled phase
1155. Primary loop 1112 further includes primary fractional phase
predictor 1146, which has an input for primary reference clock
signal 1101. Primary fractional phase predictor 1146 calculates a
primary predicted phase 1156 upon receiving a primary reference
clock signal 1101 pulse. Primary predicted phase 1156 includes an
integer number and is based on a rational number primary frequency
control word (FCW) that may include integer part 1103 (N) and
fractional part 1104 (M). Primary subtractor or adder 1144
calculates an integer number primary difference 1157 between the
primary predicted phase 1156 and the primary sampled phase 1155.
Primary loop filter 1128 filters the primary difference 1157 to
obtain secondary FCW 1158. Secondary FCW 1158 may include a
rational number.
[0143] Secondary loop 1110 includes a first input which is
configured for receiving a stable reference clock signal 1105, for
example from a crystal oscillator, and a second input configured
for receiving the secondary FCW 1158. Its output is configured to
provide an output clock signal based on the stable reference clock
signal and the secondary FCW.
[0144] FIG. 12 illustrates additional details of jitter attenuator
1200 according to some embodiments of the invention. Jitter
attenuator 1200 has an architecture similar to jitter attenuator
1100 in FIG. 11. Similar numbered blocks and signals in FIG. 12
have the same meanings and functions as in FIG. 11.
[0145] Its fractional-N PLL in secondary loop 1210 includes
controlled oscillator 1220, modulo-K counter 1222A, secondary
register 1224, phase predictor 1220, secondary subtractor or adder
1226, and secondary loop filter 1232. Controlled oscillator 1220
generates output clock signal 1202, which is also forwarded to
modulo-K counter 1222A which outputs measured phase signal 1250. In
some embodiments, modulo-K counter 1222A and 1225B may be combined
into a single modulo-K counter, providing measured phase signal
1250 both to primary register 1242 and secondary register 1224.
Secondary register 1224, upon receiving a secondary reference clock
signal 1205 pulse, samples measured phase signal 1250 and delivers
secondary sampled phase 1251 to secondary subtractor 1226. Phase
predictor 1230, clocked by secondary reference clock signal 1205,
calculates secondary predicted phase 1252. Secondary subtractor
1226 calculates a secondary difference 1253 between secondary
predicted phase 1252 and secondary sampled phase 1251, and forwards
secondary difference 1253 to secondary loop filter 1232, which
integrates and filters secondary difference 1253 to provide
oscillator control code 1254 to control the frequency of controlled
oscillator 1220. The secondary sampled phase 1251, secondary
predicted phase 1252, and secondary difference 1253 may be limited
to integer numbers, as discussed in reference to earlier PLLs in
this patent document, or they may include rational numbers as
illustrated in FIG. 13.
[0146] FIG. 13 illustrates details of a jitter attenuator 1300 with
multiple primary loops according to an embodiment of the invention.
It combines elements of the low-power hitless switching PLL in FIG.
9 with the jitter attenuator in FIG. 11 or 12. Jitter attenuator
1300 includes two or more parallel primary loops (shown in blocks
1312 and 1313) that share secondary loop 1310 functioning as a
controlled oscillator. The primary loops have primary reference
clock signal inputs 1301.1-1301.n, FCWs comprising integer part N
1303.1-1303.n and fractional part M 1304.1-1304.n. In some
embodiments, one or more of the loops may also have an input for
loop sleep signal Sleep.1-Sleep.n. The secondary loop has a
secondary reference clock signal 1305 input, which may, for
example, be coupled to a crystal oscillator, and an output for
output clock signal 1302.
[0147] Each primary loop includes a primary register (e.g., 1342)
to sample measured phase 1350 at the output of modulo-K counter
1324 upon receiving a gated reference clock signal (e.g., 1371)
pulse. The gated reference clock signal is derived from a primary
reference clock signal (e.g., 1301.n) and a sleep control signal
(e.g., Sleep.n) through one or more logic gates, e.g., gate 1340.
The primary register delivers a primary sampled phase (e.g., 1372)
at its output.
[0148] A fractional phase predictor (e.g., 1346) calculates an
integer primary predicted phase (e.g., 1373) based on a rational
FCW, e.g., including integer part N 1303.n and fractional part M
1304.n, and based on the number of gated reference clock signal
pulses received via the one or more logic gates, e.g., gate 1340. A
primary subtractor, e.g., 1344, subtracts the primary sampled phase
from the primary predicted phase to obtain an integer primary phase
difference (e.g., 1374). The embodiment provides the primary phase
difference to a monitor and adjust block or function (e.g., 1348)
and to multiplexer 1334. Multiplexer 1334 selects an active primary
loop by passing its primary phase difference (e.g., 1374) as the
selected primary phase difference 1355 to primary loop filter 1328,
which calculates secondary FCW 1356 for the secondary loop
1310.
[0149] Secondary loop 1310 includes controlled oscillator 1320,
modulo-K counter 1324 including a secondary register (not drawn) to
output secondary sampled phase 1351, phase predictor 1330,
secondary subtractor or adder 1326, and secondary loop filter 1332.
Controlled oscillator 1320 generates output clock signal 1302,
which is also forwarded to modulo-K counter 1324, which further
outputs measured phase 1350. The secondary register, upon receiving
a secondary reference clock signal 1305 pulse, samples measured
phase signal 1350 and delivers secondary sampled phase 1351 to
secondary subtractor 1326. Phase predictor 1330, clocked by
secondary reference clock signal 1305, calculates secondary
predicted phase 1352. Secondary subtractor 1326 calculates a
secondary difference 1353 between secondary predicted phase 1352
and secondary sampled phase 1351, and forwards secondary difference
1353 to secondary loop filter 1332, which integrates and filters
secondary difference 1353 to provide oscillator control code 1354
to control the frequency of controlled oscillator 1320. The
secondary sampled phase 1351, secondary predicted phase 1352, and
secondary difference 1353 may be limited to integer numbers, as
discussed in reference to earlier PLLs in this patent document, or
they may include rational numbers as illustrated here. Phase
sampler 1311 may include time-to-digital converter 1322 to measure
fractions of cycles of output clock signal 1302 in relation to
active edges of secondary reference clock signal 1305. An
embodiment may scale an output value of time-to-digital converter
1322 and add it to the output value of modulo-K counter 1324 to
produce a rational value for secondary sampled phase 1351. The use
of rational values for 1351-1353 may lead to exceptionally low
jitter in output clock signal 1302, although at the expense of
extra complexity (inclusion of time-to-digital converter 1322) and
higher power consumption.
[0150] Modulo-K counter 1324, fractional phase predictor 1346, and
phase predictor 1330 need to be able to track the phase of the
output clock signal over a sufficiently large range. For modulo-K
counter 1324 this range equals K: upon reaching a counted value of
K-1, the counter continues counting at 0. Naturally, the range K
needs to be large enough to count R.sub.N cycles of output clock
signal 1302 during one cycle of primary reference clock signal
1301.n. To correct large phase errors, or to relock at the correct
phase after lock has been temporarily lost, embodiments of the
invention may use a large range K, for instance K>>R.sub.N.
For example, the range K of the modulo-K counter 1324 may be at
least two times larger than a maximum number of output clock signal
cycles R.sub.N during a reference clock signal cycle. Thus, the
maximum value of a phase error is not limited by the period of
primary reference clock signal 1301.n, but by the larger of K and a
range of fractional phase predictor 1346. The range of fractional
phase predictor 1346 has been clarified with reference to FIG. 2A.
For phase predictor 1330, the same or similar concepts apply.
[0151] The monitor-and-adjust blocks (e.g. 1348 in block 1313) are
active only for loops that are not selected by multiplexer 1334.
Monitor-and-adjust blocks monitor the primary difference signals
from the respective subtractors and adjust registers (not shown)
inside fractional phase predictors to minimize the primary
differences.
[0152] Any adjustment in the currently active loop can break the
desired relationship between input and output frequency. The
function of a monitor-and-adjust block is to maintain the minimum
primary difference of a currently unused primary reference clock
signal, and indicate if its frequency is at the desired ratio to
the output clock signal.
[0153] The monitor-and-adjust blocks may also generate a signal
(not shown) to indicate which primary reference clock signals have
matching frequencies to the primary reference clock signal that
jitter attenuator 1300 is currently locked to. A simpler embodiment
of a monitor-and-adjust block just copies the primary sampled phase
into a register (not shown) inside the fractional phase predictor
so that the last prediction is effectively correct.
[0154] In embodiments of the invention, multiplexer 1334 can be
replaced by an averaging block that creates an error signal
replacing selected primary difference 1374 by averaging all the
primary differences that are currently valid and whose
monitor-and-adjust blocks have the primary difference associated
with any valid primary reference clock signal 1301.1-1301.n close
to zero. In this case, output clock signal 1302 is effectively
locked to all valid inputs and altering the members of the valid
set has an even smaller impact on phase.
[0155] An embodiment can be optimized to have less circuitry. For
example, instead of individual monitor-and-adjust blocks, an
embodiment may have a single monitor-and-adjust block that cycles
through the fractional phase predictors of all active loops,
adjusting only one at a time.
[0156] In some embodiments, a primary loop can have an individual
sleep mode. This is illustrated in block 1313, where gate 1340 is
configured to interrupt primary reference clock signal 1301.n. When
primary loop sleep signal Sleep.n is asserted, gated reference
clock signal 1371 is inactive, and fractional phase predictor 1346
cannot calculate updates for primary predicted phase 1373 and
register 1342 cannot update primary sampled phase 1372. In further
embodiments, primary loop sleep signal Sleep.n can also place
monitor-and-adjust block 1348 in sleep mode, such that effectively
all circuits in primary loop block 1313 are inactive. An embodiment
whose primary loops are all in sleep mode may place loop filter
1328 in sleep mode, maintaining a constant output. When this
occurs, the secondary loop enters a holdover mode, maintaining
frequency lock to the secondary reference clock signal 1305, where
the output clock signal 1302 frequency is determined by the last
active primary loop.
[0157] An embodiment may further include sleep mode signal
SleepOsc, which can stop operation of controlled oscillator 1320.
This type of sleep mode impacts all loops, and fully halts
operation of jitter attenuator 1300.
[0158] FIG. 13 shows example jitter attenuator 1300 as an
embodiment with up-counting modulo-K counter 1324 and an
up-counting fractional phase predictors. Other embodiments may use
down-counters and/or down-counting fractional phase predictors.
Counting limits may be chosen different than 0 and K, for example K
and 0, or 0 and -K, or any other set of integer values that differ
by K. Some embodiments may use an adder instead of a subtractor,
and calculate a sampled phase as a negative value. FIG. 13 shows
example jitter attenuator 1300 as an embodiment with AND gates for
gates 1340, and with the signals Sleep1 and SleepOsc asserted
negative. A person having ordinary skill in the art will know that
gating of primary reference clock signals 1301.1-1301.n can just as
easily be achieved with another type of gate, such as a NAND gate,
an OR gate, a NOR gate, an XOR gate, a pass gate, and a combination
of any number of those gates, and with either one or both of the
sleep signals asserted positive. Such embodiments are fully within
the scope and ambit of the invention.
[0159] FIG. 14 illustrates a method 1400 for jitter attenuation
according to an embodiment of the invention. Method 1400 comprises
the following steps.
[0160] Step 1410--in a primary PLL loop, based on a primary
reference clock signal and a rational first FCW, calculating an
integer primary predicted phase. Based on the primary reference
clock signal and a secondary PLL loop output clock signal, sampling
a phase at a counter output to obtain an integer primary sampled
phase. The counter may be a modulo-K counter. Calculating a primary
difference by subtracting the primary sampled phase from the
primary predicted phase.
[0161] Step 1420--loop filtering the primary difference in a
primary loop filter to obtain a second FCW.
[0162] Step 1430--forwarding the second FCW to a secondary
loop.
[0163] Step 1440--based on the second FCW and a secondary reference
clock signal, calculating a secondary predicted phase. Based on the
secondary reference clock signal and the secondary PLL loop output
clock signal, sampling a phase to obtain a secondary sampled phase.
Calculating a secondary difference by subtracting the secondary
sampled phase from the secondary predicted phase.
[0164] Step 1450--loop filtering the secondary difference in a
secondary loop filter to obtain an oscillator control code to
control a controlled oscillator and to determine a frequency of the
secondary PLL loop output clock signal.
[0165] FIG. 15 illustrates a programmable system 1500 capable of
implementing jitter attenuation methods according to embodiments of
the invention. System 1500 is a jitter attenuator that comprises a
fractional-N PLL 1510, a modulo-K counter 1520, a programmable
processor 1530, and a memory 1540. Memory 1540 may be tangible, and
it may be non-transitory. Programmable processor 1530 is configured
to store software instructions and/or data in memory 1540.
Fractional-N PLL 1510 receives stable reference clock signal 1505
(for example, from a crystal oscillator). Programmable processor
1530 receives reference clock signal 1501, and a primary FCW
comprising integer part N 1503 and fractional part M 1504.
Programmable processor 1530 outputs secondary FCW 1506 to
fractional-N PLL 1510. Fractional-N PLL 1510, whose frequency is
controlled by secondary FCW 1506, outputs the output clock 1502.
Modulo-K counter 1520 counts cycles of output clock 1502, and its
output signal 1507 is a measure for the output clock phase, which
it feeds back to programmable processor 1530. Some embodiments may
store integer part N 1503 and fractional part M 1504 as parameters
in memory 1540, either as part of the software instructions or as
part of the data. Further embodiments may receive multiple
reference clock signals, and may work with multiple FCWs. Yet
further embodiments may use separate tangible non-transitory
memories for software instructions and data.
[0166] Programmable processor 1530 is programmed to execute
instructions for, for example, the following operations:
[0167] (a) in programmable processor 1530, based on the primary
reference clock signal and a rational primary FCW, calculating an
integer primary predicted phase; based on the primary reference
clock signal and the fractional-N PLL 1510 output clock signal
1502, sampling a phase at the modulo-K counter 1520 output to
obtain an integer primary sampled phase; calculating a primary
difference by subtracting the primary sampled phase from the
primary predicted phase;
[0168] (b) loop filtering the primary difference in a primary loop
filter to obtain the secondary FCW; and
[0169] (c) forwarding the secondary FCW to fractional-N PLL 1510 to
control fractional-N PLL 1510 and to determine a frequency of the
fractional-N PLL 1510 output clock signal 1502.
[0170] FIG. 16 illustrates another programmable system, 1600,
capable of implementing jitter attenuation methods according to
embodiments of the invention. System 1600 is a jitter attenuator
that comprises a controlled oscillator 1610, a modulo-K counter
1620, a programmable processor 1630, a memory 1640, and optionally
a time-to-digital converter 1650. Memory 1640 may be tangible, and
it may be non-transitory. Programmable processor 1630 is configured
to store software instructions and/or data in memory 1640.
Controlled oscillator 1610 receives oscillator control code 1606
from programmable processor 1630. Programmable processor 1630
receives reference clock signal 1601, a primary FCW comprising
integer part N 1603 and fractional part M 1604, and stable
reference clock signal 1605, which may, for example, come from a
crystal oscillator. Controlled oscillator 1610, whose frequency is
controlled by oscillator control code 1606, outputs the output
clock 1602. Modulo-K counter 1620 counts cycles of output clock
1602, and its output signal 1607 is a measure for the output clock
phase, which it feeds back to programmable processor 1630.
Embodiments that include time-to-digital converter 1650 measure
fractions of cycles of output clock signal 1602 in relation to
active edges of stable reference clock signal 1605. An embodiment
may scale an output value of time-to-digital converter 1650 and add
it to the output value of modulo-K counter 1620 to produce a
rational value for a secondary sampled phase, comprising integer
part 1607 and fractional part 1608.
[0171] Some embodiments may store integer part N 1603 and
fractional part M 1604 as parameters in memory 1640, either as part
of the software instructions or as part of the data. Further
embodiments may receive multiple reference clock signals, and may
work with multiple FCWs. Yet further embodiments may use separate
tangible non-transitory memories for software instructions and
data.
[0172] Programmable processor 1630 is programmed to execute
instructions for, for example, the following operations:
[0173] (a) based on a primary reference clock signal 1601 and a
rational first FCW (1603, 1604), calculating an integer primary
predicted phase. Based on the primary reference clock signal 1601
and controlled oscillator 1610 output clock signal 1602, sampling a
phase at the modulo-K counter 1620 output to obtain an integer
primary sampled phase. Calculating a primary difference by
subtracting the primary sampled phase from the primary predicted
phase.
[0174] (b) filtering the primary difference in a primary loop
filter to obtain a second FCW.
[0175] (c) based on the second FCW and stable reference clock
signal 1605, calculating a secondary predicted phase. Based on the
secondary reference clock signal and the secondary PLL loop output
clock signal, sampling a phase to obtain a secondary sampled phase.
Calculating a secondary difference by subtracting the secondary
sampled phase from the secondary predicted phase.
[0176] (d) filtering the secondary difference in a secondary loop
filter to obtain an oscillator control code 1606 to control
controlled oscillator 1610 and to determine a frequency of the
output clock signal 1602.
[0177] It will be understood that the invention disclosed and
defined in this specification extends to all alternative
combinations of two or more of the individual features mentioned or
evident from the text or drawings. All of these different
combinations constitute various alternative aspects of the
invention.
[0178] Although the description has been described with respect to
particular embodiments thereof, these particular embodiments are
merely illustrative, and not restrictive. For instance, many of the
operations can be implemented on a printed card board PCB using
off-the-shelf devices, in a System-on-Chip (SoC),
application-specific integrated circuit (ASIC), programmable
processor, or in a programmable logic device such as a
field-programmable gate array (FPGA), obviating a need for at least
part of the dedicated hardware. All such variations and
modifications are to be considered within the ambit of the present
invention the nature of which is to be determined from the
foregoing description.
[0179] Any suitable technology for manufacturing electronic devices
can be used to implement the circuits of particular embodiments,
including bipolar, JFET, MOS, NMOS, PMOS, CMOS, BiCMOS, HBT,
MESFET, FinFET, etc. Different semiconductor materials can be
employed, such as silicon, germanium, SiGe, GaAs, InP, graphene,
etc. Circuits may have single-ended or differential inputs, and
single-ended or differential outputs. Terminals to circuits may
function as inputs, outputs, both, or be in a high-impedance state,
or they may function to receive supply power, a ground reference, a
reference voltage, a reference current, or other. Although the
physical processing of signals may be presented in a specific
order, this order may be changed in different particular
embodiments. In some particular embodiments, multiple elements,
devices, or circuits shown as sequential in this specification can
be operating in parallel.
[0180] Particular embodiments or parts of an embodiment may be
implemented in a tangible, non-transitory computer-readable storage
medium for use by or in connection with an instruction execution
system, apparatus, system, or device. Particular embodiments can be
implemented in the form of control logic in software, firmware,
hardware or a combination of those. The control logic, when
executed by one or more processors, may be operable to perform that
which is described in particular embodiments. For example, a
tangible medium such as a hardware storage device can be used to
store the control logic, which can include executable
instructions.
[0181] It will also be appreciated that one or more of the elements
depicted in the drawings/figures can also be implemented in a more
separated or integrated manner, or even removed or rendered as
inoperable in certain cases, as is useful in accordance with a
particular application. It is also within the spirit and scope to
implement a program or code that can be stored in a
machine-readable medium to permit a computer to perform any of the
methods described above.
[0182] As used in the description herein and throughout the claims
that follow, "a", "an", and "the" includes plural references unless
the context clearly dictates otherwise. Also, as used in the
description herein and throughout the claims that follow, the
meaning of "in" includes "in" and "on" unless the context clearly
dictates otherwise.
[0183] Thus, while particular embodiments have been described
herein, latitudes of modification, various changes, and
substitutions are intended in the foregoing disclosures, and it
will be appreciated that in some instances some features of
particular embodiments will be employed without a corresponding use
of other features without departing from the scope and spirit as
set forth. Therefore, many modifications may be made to adapt a
particular situation or material to the essential scope and
spirit.
* * * * *