U.S. patent application number 15/862924 was filed with the patent office on 2018-05-10 for electronic device, in particular for protection against overvoltages.
This patent application is currently assigned to STMicroelectronics SA. The applicant listed for this patent is STMicroelectronics SA. Invention is credited to Johan Bourgeat, Jean Jimenez.
Application Number | 20180130788 15/862924 |
Document ID | / |
Family ID | 55361668 |
Filed Date | 2018-05-10 |
United States Patent
Application |
20180130788 |
Kind Code |
A1 |
Bourgeat; Johan ; et
al. |
May 10, 2018 |
ELECTRONIC DEVICE, IN PARTICULAR FOR PROTECTION AGAINST
OVERVOLTAGES
Abstract
An electronic device is formed by a sequence of at least two
thyristors coupled in series in a same conduction direction. Each
thyristor has a gate of a first conductivity type. The gates of the
first conductivity type for the thyristors in the sequence are
coupled together in order to form a single control gate.
Inventors: |
Bourgeat; Johan; (Saint
Pierre d'Allevard, FR) ; Jimenez; Jean; (Saint
Theoffrey, FR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics SA |
Montrouge |
|
FR |
|
|
Assignee: |
STMicroelectronics SA
Montrouge
FR
|
Family ID: |
55361668 |
Appl. No.: |
15/862924 |
Filed: |
January 5, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15096975 |
Apr 12, 2016 |
9899366 |
|
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15862924 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/0262 20130101;
H01L 29/7436 20130101; H01L 29/1095 20130101; H01L 29/744 20130101;
H01L 27/0251 20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02; H01L 29/10 20060101 H01L029/10; H01L 29/74 20060101
H01L029/74; H01L 29/744 20060101 H01L029/744 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 19, 2015 |
FR |
1561135 |
Claims
1. An integrated circuit, comprising: a semiconductor body having a
first conductivity type; and a first thyristor formed in said
semiconductor body, comprising: a first semiconductor region in the
semiconductor body having a second conductivity type opposite to
the first conductivity type, the first semiconductor region forming
an anode of the first thyristor; a second semiconductor region in
the semiconductor body having the second conductivity type, the
first and second semiconductor regions separated from each other by
a portion of the semiconductor body, the second semiconductor
region forming a cathode of the first thyristor; and wherein the
semiconductor body forms a cathode control gate of the first
thyristor.
2. The integrated circuit of claim 1, further comprising a first
heavily doped region of the first conductivity type formed in said
portion of the semiconductor body and configured to provide a
contact for said cathode control gate.
3. The integrated circuit of claim 2, wherein said first heavily
doped region of the first conductivity type surrounds the first and
second semiconductor regions and passes between the first and
second semiconductor regions.
4. The integrated circuit of claim 2, further comprising: a second
heavily doped region of the second conductivity type formed within
the first semiconductor region; and a third heavily doped region of
the first conductivity type formed within the second semiconductor
region.
5. The integrated circuit of claim 4, further comprising a fourth
heavily doped region of the second conductivity type formed within
the second semiconductor region and in contact with the third
heavily doped region.
6. The integrated circuit of claim 5, wherein the fourth heavily
doped region is shorted to the third heavily doped region.
7. The integrated circuit of claim 1, further comprising a second
thyristor formed in said semiconductor body, comprising: a third
semiconductor region in the semiconductor body having the second
conductivity type, the third semiconductor region forming an anode
of the second thyristor; a fourth semiconductor region in the
semiconductor body having the second conductivity type, the third
and fourth semiconductor regions separated from each other by the
portion of the semiconductor body, the fourth semiconductor region
forming a cathode of the second thyristor; and wherein the
semiconductor body forms a cathode control gate of both the first
and second thyristors.
8. The integrated circuit of claim 7, further comprising an
electrical connection configured to connect the cathode of the
first thyristor to the anode of the second thyristor.
9. The integrated circuit of claim 7, further comprising: a first
heavily doped region of the first conductivity type formed in said
portion of the semiconductor body separating the first and second
semiconductor regions and configured to provide a contact for said
cathode control gate of the first thyristor; and a second heavily
doped region of the first conductivity type formed in said portion
of the semiconductor body separating the third and fourth
semiconductor regions and configured to provide a contact for said
cathode control gate of the second thyristor.
10. The integrated circuit of claim 9, further comprising: a third
heavily doped region of the first conductivity type formed in a
portion of the semiconductor body separating the first and second
thiyristors and configured to provide a contact for said cathode
control gate of the first and second thyristors.
11. An integrated circuit, comprising: a semiconductor body having
a first conductivity type; a first semiconductor region in the
semiconductor body having a second conductivity type opposite to
the first conductivity type; a second semiconductor region in the
semiconductor body having the second conductivity type; wherein the
first semiconductor region is separated from the second
semiconductor regions by a first portion of the semiconductor body;
and a first heavily doped region of the first conductivity type
formed as a ring surrounding the first and second semiconductor
regions and further extending through said first portion of the
semiconductor body between the first and second semiconductor
regions.
12. The integrated circuit of claim 11, further comprising: a
second heavily doped region of the second conductivity type formed
within the first semiconductor region; and a third heavily doped
region of the first conductivity type formed within the second
semiconductor region.
13. The integrated circuit of claim 12, further comprising a fourth
heavily doped region of the second conductivity type formed within
the second semiconductor region and in contact with the third
heavily doped region.
14. The integrated circuit of claim 13, wherein the fourth heavily
doped region is shorted to the third heavily doped region.
15. The integrated circuit of claim 12, wherein the second heavily
doped region is an anode terminal of a thyristor, the third heavily
doped region is a cathode terminal of the thyristor and the first
heavily doped region is a control gate of the thyristor.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application for
patent Ser. No. 15/096,975 filed Apr. 12, 2016, which claims
priority from French Application for Patent No. 1561135 filed Nov.
19, 2015, the disclosures of which are incorporated by
reference.
TECHNICAL FIELD
[0002] Embodiments of the invention relate to electronic devices,
such as electronic devices based on thyristors, also referred to by
a person skilled in the art by the acronym "SCR" ("Silicon
Controlled Rectifier"), and especially those designed to protect
components against overvoltages, in particular overvoltages such as
parasitic overvoltages produced during operation of the component,
but also overvoltages occurring during electrostatic discharges
("ElectroStatic Discharge": ESD).
BACKGROUND
[0003] Conventionally, a thyristor is made to conduct when the
voltage across its terminals becomes greater than a trigger
voltage.
[0004] Further to the trigger voltage, another important parameter
of a thyristor is the holding voltage, that is to say the minimum
voltage such that the thyristor remains conductive after having
been triggered.
[0005] In certain applications, thyristors have a high trigger
voltage, for example around 3.6 V, but a low holding voltage, for
example around 1.2 V, which may then be less than the rated supply
voltage of the integrated circuit incorporating such thyristors.
This is the case, for example, with an integrated circuit having a
supply voltage of 3.3 V.
[0006] Consequently, during operation of the integrated circuit,
the thyristors may be triggered and become conductive during an
electrical overstress ("Electrical OverStress": EOS) and then
continue to conduct until they are destroyed, because the supply
voltage of the circuit is then always greater than the holding
voltage of these thyristors.
[0007] One solution, based on a protective device having a
structure of three cascoded thyristors, is generally proposed in
order to increase the holding voltage of such a protective
device.
[0008] However, such a structure with three thyristors also
increases the trigger voltage and the surface occupancy of the
device on silicon.
SUMMARY
[0009] Thus, according to one embodiment, it is proposed to improve
the performance of protective electronic devices based on
thyristors by increasing the holding voltage without significantly
increasing the trigger voltage.
[0010] According to another embodiment, it is proposed to produce
such a device without having a significant effect on the surface
occupancy on silicon.
[0011] One aspect proposes an electronic device comprising a
sequence of at least two thyristors coupled in series in the same
conduction direction (the anode and the cathode of two adjacent
thyristors of the sequence are connected), each thyristor having a
gate of a first conductivity type, all the gates of the first
conductivity type of the thyristors being coupled in order to form
a single gate.
[0012] Thus, the thyristors of the sequence are so to speak
"merged" by connecting their gates of the same conductivity type in
order to form a device having a single gate, for example of the
first conductivity type, which will be connectable to a single
trigger circuit. The holding voltage of the device is thus
increased without significantly increasing, or even without
modifying, the trigger voltage in comparison with that of a single
thyristor, this trigger voltage being moreover much less than that
of the cascoded structure of the prior art.
[0013] By way of indication but without limitation, the gates are
advantageously of N-type conductivity, although they could be of
P-type conductivity.
[0014] According to one embodiment, all the thyristors of the
electronic device are arranged in the same semiconductor body
having the first conductivity type.
[0015] Each thyristor has, within the semiconductor body, a first
semiconductor region having a second conductivity type opposite to
the first conductivity type and a second semiconductor region
having the second conductivity type and including a semiconductor
zone having the first conductivity type.
[0016] The first semiconductor region of a thyristor of the
sequence is coupled by a metallization lying above the
semiconductor body to the semiconductor zone of the preceding
thyristor in the sequence. The semiconductor body forms the single
gate.
[0017] Such an embodiment makes it possible to limit the surface
occupancy on silicon.
[0018] Furthermore, the semiconductor body has, for example, a zone
doped more heavily than the rest of the body. This may surround all
the semiconductor regions and form a contact for the single
gate.
[0019] The electronic device furthermore advantageously has a
trigger circuit coupled to the single gate.
[0020] According to a preferred embodiment, the sequence of
thyristors comprises a first thyristor and a second thyristor. The
anode of the second thyristor is coupled to the cathode of the
first thyristor.
[0021] According to this preferred embodiment, the trigger circuit
is coupled to the single gate and to the cathode of the second
thyristor.
[0022] Such a structure with two thyristors coupled in series may
advantageously reduce by up to 40% the surface occupancy compared
with the solution with three cascoded thyristors, while offering a
higher holding voltage and a threshold voltage substantially equal
to that of an electronic device having a single thyristor.
[0023] The electronic device may be used to protect a component
arranged between the two ends of the sequence of thyristors. The
trigger circuit may, for example, be coupled to the single gate and
to one of the ends of the sequence.
[0024] In an embodiment, an integrated circuit comprises: a
semiconductor body having a first conductivity type; a first
semiconductor region in the semiconductor body having a second
conductivity type opposite to the first conductivity type; a second
semiconductor region in the semiconductor body having the second
conductivity type; wherein the first semiconductor region is
separated from the second semiconductor regions by a first portion
of the semiconductor body; and a first heavily doped region of the
first conductivity type formed as a ring surrounding the first and
second semiconductor regions and further extending through said
first portion of the semiconductor body between the first and
second semiconductor regions.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Other advantages and characteristics of the invention will
become apparent on studying the detailed description of embodiments
which are taken by way of non-limiting examples and illustrated by
the appended drawings, in which:
[0026] FIG. 1 is a schematic diagram of an electronic device;
[0027] FIG. 2 is a top view of an integrated circuit fabrication of
the device of FIG. 1;
[0028] FIG. 3 is a cross sectional view of the integrated circuit
fabrication; and
[0029] FIG. 4 is a further schematic diagram of an electronic
device.
DETAILED DESCRIPTION
[0030] FIG. 1 schematically illustrates an example of an electronic
device DE.
[0031] The device DE illustrated in FIG. 1 comprises a first
thyristor TH1 and a second thyristor TH2, which are connected in
series in the same conduction direction between a first terminal B1
and a second terminal B2. In this context, the phrase "in the same
conduction direction" is intended to mean a connection between the
anode and the cathode of two adjacent thyristors of the
sequence.
[0032] The thyristor TH1 has an anode A1 coupled to the first
terminal B1, a cathode K1 and a gate G1, for example the N-type
gate. The thyristor TH2 has an anode A2 coupled to the cathode K1,
a cathode K2 coupled to the second terminal B2, and its N-type gate
G2 coupled to the gate G1 so as to form a single N-type gate
GU.
[0033] Reference will now be made to FIG. 2, which shows a diagram
of the implementation of the electronic device DE described above
and illustrated in FIG. 1 on silicon, and to FIG. 3, which is a
view in section along the line of FIG. 2.
[0034] The thyristors TH1 and TH2 are formed in the same
semiconductor body CS, for example of the N type.
[0035] Each thyristor TH1 or TH2 has, in the body CS, a first
semiconductor region RS1 of P-type conductivity having a first
semiconductor zone ZSFD1 doped more heavily (of the P+ type). This
first region RS1 forms the anode A1 or A2 of the thyristor TH1 or
TH2, and the first semiconductor zone ZSFD1 forms a contacting
region of the anode A1 or A2. The anode A1 of the first thyristor
TH1 is connected to the first terminal B1 of the electronic device
DE.
[0036] Each thyristor TH1 or TH2 furthermore has, in the body, a
second semiconductor region RS2 of the P type containing a second
semiconductor zone ZSFD2 of the opposite conductivity type and
doped more heavily (N+ type). The second semiconductor zones ZSFD2
respectively form the cathodes K1 and K2 of the thyristors TH1 and
TH2.
[0037] The second semiconductor region RS2 of each thyristor forms
the P-type gate of this thyristor and furthermore has a third
semiconductor zone ZSFD3 of the same conductivity type and doped
more heavily (P+ type). The P-type gate is in this case
short-circuited with the cathode zone ZSFD2 by a metallization (not
represented in the figures) between the zones ZSFD2 and ZSFD3,
because it is not used as a trigger gate.
[0038] The anode A2 of the second thyristor TH2 is connected to the
cathode K1 of the first thyristor TH1 by a metallization lying
above the body CS, and the cathode of the second thyristor is
connected to the second terminal B2.
[0039] The entire semiconductor body CS forms de facto the single
N-type gate GU of the electronic device DE.
[0040] In this regard, the semiconductor body CS advantageously has
a contact zone ZCFD doped more heavily than the rest of the body
CS. This contact zone ZCFD surrounds all the semiconductor regions
RS1 and RS2 and forms a contacting zone of the single N-type gate
GU.
[0041] Such an integrated electronic device DE having two
thyristors TH1 and TH2 advantageously makes it possible to reduce
by up to 40% the surface occupancy compared with the solution of a
protective device having a structure with three cascoded
thyristors.
[0042] As regards the trigger voltage and the holding voltage of
such a device, they are respectively of the order of 3.6 volts and
4 volts for implementation in a 28 nm CMOS technology.
[0043] Such a device is therefore highly suitable for protecting a
component of an integrated circuit supplied with a supply voltage
of 3.3 volts against overvoltages occurring during operation of the
component.
[0044] Reference will now be made in this regard more particularly
to FIG. 4 in order to illustrate an example of the application of
the electronic device DE for the protection of a component 1
coupled between the first terminal B1 and the second terminal B2.
For example, the component 1 may be a microcontroller or a
processor core.
[0045] The first terminal B1 may, for example, be an input/output
terminal ("I/O pad") of the integrated circuit containing the
component, and the terminal B2 may be intended to be grounded.
[0046] As illustrated in FIG. 4, the device DE has a trigger
circuit connected in this case between the single gate GU and the
terminal B2.
[0047] The trigger circuit CD may be based on MOS transistors with
hybrid operation, as described in the international patent
application WO 2011/089179 or U.S. Pat. No. 9,019,666 (incorporated
by reference). Specifically, it has been shown in this
international patent application WO 2011/089179 that such
transistors may also be used to form a trigger circuit.
[0048] More precisely, the trigger circuit CD in this case has a
first NMOS transistor TN1 with hybrid operation, the gate GN1 and
the substrate SBN1 of which are connected together to the source
SN1 of the transistor TN1 by a first resistor R1, and a second NMOS
transistor TN2 with hybrid operation, the drain DN2 of which is
connected to the source SN1 of the first transistor TN1, and the
gate GN2 and substrate SBN2 of which are connected together to the
source SN2 of the second transistor TN2 by a second resistor R2,
the source SN2 of this second transistor TN2 being connected to the
cathode K2 of the second thyristor TH2 and therefore to the second
terminal B2.
[0049] Other conventional structures of trigger circuits (not
illustrated), for example MOS transistors whose gate and substrate
are connected to earth (here to the terminal B2), which are
commonly referred to by a person skilled in the art by the acronym
"GGNMOS" ("Grounded-Gate NMOS"), are also possible.
[0050] It should be noted that the trigger circuit CD may
advantageously be a trigger circuit identical to that implemented
in a conventional protective device having a single thyristor.
[0051] Thus, with a trigger voltage of the order of 3.6 volts, a
holding voltage of the order of 4 volts and a supply voltage of 3.3
volts, triggering in the event of an overstress on the component
during operation does not maintain a conductive state of the
electronic device DE at the end of the overstress.
[0052] Thus, an electronic device for protection against
overvoltages is obtained which has a high holding voltage while
avoiding a significant increase in the trigger voltage compared
with a protective device having a single thyristor. Such an
electronic device advantageously requires a reduced surface
occupancy on silicon compared with a protective device having three
thyristors.
[0053] Of course, such a device may also be used to protect the
component against electrostatic discharges (ESD) when the component
is not in operation, i.e. not supplied.
[0054] It would be possible to increase further the number of
thyristors of the sequence, their gates being connected together in
order to form the single gate. This would make it possible to
increase the holding voltage of the overall device further. In this
case, the number of elements of the trigger circuit, for example
the number of transistors with hybrid operation connected in
series, would be increased accordingly in comparison with the
embodiment of FIG. 4.
[0055] From an integration point of view, all the thyristors would
then be produced in the same semiconductor body CS (FIGS. 2 and 3),
with the anode of one thyristor of the sequence connected by a
metallization to the cathode of the thyristor preceding it in the
sequence.
* * * * *