U.S. patent application number 15/339621 was filed with the patent office on 2018-05-03 for input/output pins for chip-embedded substrate.
The applicant listed for this patent is Infineon Technologies Americas Corp.. Invention is credited to Eung San Cho, Danny Clavette.
Application Number | 20180122745 15/339621 |
Document ID | / |
Family ID | 61912393 |
Filed Date | 2018-05-03 |
United States Patent
Application |
20180122745 |
Kind Code |
A1 |
Cho; Eung San ; et
al. |
May 3, 2018 |
INPUT/OUTPUT PINS FOR CHIP-EMBEDDED SUBSTRATE
Abstract
Input/output pins for a chip-embedded substrate may be
fabricated by applying a contact-distinct volume of solder to at
least two contacts that are recessed within the chip-embedded
substrate, temperature-cycling the chip-embedded substrate to
induce solder reflow and define an input/output pin for each one of
the at least two contacts, and machining the input/output pin for
each one of the at least two contacts to extend exposed from the
chip-embedded substrate to a common height within specification
tolerance. Such a technique represents a paradigm shift in that the
manufacturer of the chip-embedded substrate, as opposed to the
immediate customer of the manufacturer, may assume the burden of
quality control with respect to minimizing unintended solder void
trapping under the input/output pins, thereby reinforcing existing
customer loyalty and potentially attracting new customers.
Inventors: |
Cho; Eung San; (Torrance,
CA) ; Clavette; Danny; (Greene, RI) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Infineon Technologies Americas Corp. |
El Segundo |
CA |
US |
|
|
Family ID: |
61912393 |
Appl. No.: |
15/339621 |
Filed: |
October 31, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/73267
20130101; H01L 2924/10272 20130101; H01L 2224/2518 20130101; H01L
21/486 20130101; H01L 2224/04105 20130101; H01L 2924/13091
20130101; H01L 2021/6009 20130101; H01L 2924/1033 20130101; H01L
2924/13064 20130101; H01L 2224/24137 20130101; H01L 2224/12105
20130101; H01L 2924/13055 20130101; H01L 24/25 20130101; H01L
23/481 20130101; H01L 2224/32225 20130101; H01L 21/52 20130101;
H01L 23/5389 20130101; H01L 2224/06181 20130101; H01L 24/24
20130101; H01L 24/19 20130101; H01L 25/16 20130101; H01L 2021/60135
20130101; H01L 2924/10253 20130101 |
International
Class: |
H01L 23/538 20060101
H01L023/538; H01L 23/48 20060101 H01L023/48; H01L 21/48 20060101
H01L021/48; H01L 21/52 20060101 H01L021/52 |
Claims
1. A method comprising: applying a contact-distinct volume of
solder to at least two contacts recessed at different depths from a
same surface within a chip-embedded substrate; temperature-cycling
the chip-embedded substrate to induce solder reflow and define an
input/output pin for each one of the at least two contacts; and
machining the input/output pin for each one of the at least two
contacts to extend exposed from the chip-embedded substrate to a
common height within specification tolerance.
2. The method of claim 1, wherein applying the contact-distinct
volume of solder comprises: applying a first volume of solder to a
first one of the at least two contacts and a second volume of
solder that is different than the first volume of solder to a
second one of the at least two contacts.
3. The method of claim 1, wherein applying the contact-distinct
volume of solder comprises: positioning a mask to the chip-embedded
substrate so that a first aperture of the mask is aligned with a
first one of the at least two contacts and a second aperture of the
mask that is sized different than the first aperture is aligned
with a second one of the at least two contacts.
4. The method of claim 1, wherein applying the contact-distinct
volume of solder comprises: aligning a substrate that has a
particular solder ball pattern with the chip-embedded substrate;
and engaging the substrate that has the particular solder ball
pattern to the chip-embedded substrate so that a first volume of
solder is applied to a first one of the at least two contacts and a
second volume of solder that is different than the first volume of
solder is applied to a second one of the at least two contacts.
5. The method of claim 1, wherein applying the contact-distinct
volume of solder comprises: selecting a substrate from among a
plurality of substrates each one that exhibits a solder ball
pattern specific to a type of chip-embedded substrate aligning the
substrate with the chip-embedded substrate; and engaging the
substrate that has the particular solder ball pattern to the
chip-embedded substrate so that a first volume of solder is applied
to a first one of the at least two contacts and a second volume of
solder that is different than the first volume of solder is applied
to a second one of the at least two contacts.
6. The method of claim 1, further comprising: selecting the
chip-embedded substrate from among a plurality of chip-embedded
substrates each one that exhibits a distinct embedded circuit
architecture.
7. The method of claim 1, further comprising: selecting the
chip-embedded substrate from among a plurality of chip-embedded
substrates each one that exhibits a distinct embedded circuit
architecture, wherein the chip-embedded substrate comprises an
integrated circuit and a plurality of through-via conductors each
one that is electrically coupled to the integrated circuit and to a
particular one of the at least two contacts recessed within the
chip-embedded substrate.
8. The method of claim 1, further comprising: selecting the
chip-embedded substrate from among a plurality of chip-embedded
substrates each one that exhibits a distinct embedded circuit
architecture, wherein the chip-embedded substrate comprises an
integrated circuit, at least two discrete transistors and a
plurality of through-via conductors each one that is electrically
coupled to the integrated circuit, to a particular one of the at
least two contacts recessed within the chip-embedded substrate and
to a particular one of the at least two discrete transistors.
9. The method of claim 1, machining the input/output pin for each
one of the at least two contacts comprises: shaping the
input/output pin for each one of the at least two contacts so that
an exposed contact surface of a first input/output pin is
approximately coplanar with an exposed contact surface of a second
input/output pin.
10. The method of claim 1, further comprising: mounting the
chip-embedded substrate to a printed circuit board wherein the
input/output pin for each one of the at least two contacts is
coupled to a particular contact pad of the printed circuit
board.
11-19. (canceled)
20. A method comprising: depositing solder to each one of a
plurality of differently-sized contacts recessed at different
depths within a chip-embedded substrate that comprises power
converter circuitry; temperature-cycling the chip-embedded
substrate to induce solder reflow and define an input/output pin
for each one of the plurality of contacts that is electrically
coupled to the power converter circuitry via a corresponding one of
the plurality of contacts; and machining the input/output pin for
each one of the at least two contacts to extend exposed from the
chip-embedded substrate to a common height within specification
tolerance.
Description
BACKGROUND
[0001] Surface-mount technology is a production method for
electronics that involves attaching passive or active components,
such as those realized by chip-embedded packaging technologies for
example, to a printed circuit board. Such components may be
soldered to the printed circuit board to establish connections with
other components mounted to the printed circuit board.
SUMMARY
[0002] The present disclosure relates to input/output (1/O) pins
for a chip-embedded substrate (CES). In an aspect, a method
comprises applying a contact-distinct volume of solder to at least
two contacts that are recessed within a CES, temperature-cycling
the CES to induce solder reflow and define an I/O pin for each one
of the at least two contacts, and machining the I/O pin for each
one of the at least two contacts to extend exposed from the CES to
a common height within specification tolerance. It is contemplated
that the I/O pins may be defined or fabricated by a manufacturer of
the CES, as opposed to an immediate customer of the manufacturer.
Such an implementation represents a paradigm shift in that the
manufacturer of the CES may assume the burden of quality control
with respect to minimizing unintended solder void trapping under
the I/O pins, thereby reinforcing existing customer loyalty and
potentially attracting new customers. This is because both existing
and potential new customers may realize a substantial cost savings
as their own surface-mount assembly processes may be simplified or
streamlined by reducing the number of steps required to
surface-mount the CES to a printed circuit board (PCB) in order to
produce an electronics product or circuit that incorporates or
leverages the functionality of the CES. Additionally, the cost
savings may propagate through the supply chain all the way to the
ultimate consumer electronics customer.
BRIEF DESCRIPTION OF DRAWINGS
[0003] FIG. 1 shows a schematic diagram of a power converter built
around a CES that itself includes a plurality of I/O pins defined
in accordance with the disclosure.
[0004] FIG. 2 shows a cross-sectional diagram of the CES of FIG. 1,
wherein the CES is realized as a single-chip-embedded
substrate.
[0005] FIGS. 3-6 show the CES of FIG. 2 at various steps during a
process of defining a plurality of I/O pins in accordance with the
disclosure.
[0006] FIGS. 7-8 show the CES of FIG. 2 at various steps during a
process of surface-mounting the CES to a PCB in accordance with the
disclosure.
[0007] FIG. 9 shows a cross-sectional diagram of the CES of FIG. 1,
wherein the CES is realized as a multi-chip-embedded substrate.
[0008] FIG. 10 shows the CES of FIG. 9 at a step during a process
of defining a plurality of I/O pins in accordance with the
disclosure.
[0009] FIGS. 11-12 show the CES of FIG. 9 at various steps during a
process of surface-mounting the CES to a PCB in accordance with the
disclosure.
[0010] FIG. 13 shows an example method for defining a plurality of
I/O pins in accordance with the disclosure.
DETAILED DESCRIPTION
[0011] FIG. 1 shows a schematic diagram of a power converter 100
built around a CES 102 that includes a plurality of I/O pins 104A-E
(collectively, "I/O pins 104") defined in accordance with the
present disclosure. It is contemplated that I/O pins 104 may be
defined or fabricated by a manufacturer of CES 102, as opposed to
an immediate customer of the manufacturer. Such an implementation
represents a paradigm shift in that the manufacturer of CES 102 may
assume the burden of quality control with respect to minimizing
unintended solder void trapping under I/O pins 104. Short term, a
degradation in performance of power converter 100 attributable to
solder voids under I/O pins 104, due to a defect-related series
resistance, may occur if the solder voids are relatively large
and/or significant in terms of density. By assuming the burden of
quality control with respect to minimizing unintended solder void
trapping under I/O pins 104, the manufacturer of CES 102 can better
insure that rated device level characteristics of CES 102 are
realized, as opposed to being inadvertently compromised by the
immediate customer during their own processes for surface-mounting
CES 102 to a substrate such as a PCB to produce power converter
100. By extension, the reputation of the manufacturer for producing
high-performance devices (i.e., CES 102) may be protected and not
threatened due to a perceived degradation in performance that is
not attributable to CES 102.
[0012] With respect to power converter 100, power converter 100 may
comprise a multi-phase power converter, such as a half-bridge DC-DC
buck converter for converting an input DC signal to an output DC
signal with a stepped-down voltage. For each phase, a multi-phase
power converter may comprise a half-bridge circuit and an inductor.
As a DC-to-DC buck converter, power converter 100 may operate as a
voltage regulator in a variety of applications. In some examples,
power converter 100 may be designed for high-power applications
that leverage high currents and/or voltages. However, the
techniques of the present disclosure may apply to other circuits
and configurations, such as other types of power converters and
including multi-phase power converters.
[0013] In the example shown, power converter 100 includes
transistors 106, 108 and control circuitry 110 coupled together in
a particular topology. Although, power converter 100 may include
more or fewer components than depicted in FIG. 1. Power converter
100 further includes an input node that corresponds to an instance
of I/O pin 104E, a switch node that corresponds to an instance of
I/O pin 104C, and a reference node that corresponds to an instance
of (discussed further below) at least one of I/O pins 104A, 104B,
104D, as well as other nodes not explicitly shown in FIG. 1. In
general, each one of the mentioned nodes is configured to connect
to one or more external components.
[0014] For example, the input node may connect to a power supply,
the switch node may connect to an inductor 112 that in turn is
connected to a capacitor 114 as shown in FIG. 1, and the reference
node may connect to a reference voltage, such as reference ground.
Additionally, control circuitry 110 may connect to reference ground
and a circuit that is external CES 102 through a node that is not
shown. And, while inductor 112 and capacitor 114 are each depicted
in FIG. 1 as being external to CES 102, CES 102 may in some
examples be fabricated such that the inductance and capacitance
presented by inductor 112 and capacitor 114, respectively, may be
realized within or by CES 102 (e.g., via parasitic L/C introduced
by the package of CES 102, etc.).
[0015] Although each one of transistors 106, 108 is depicted in
FIG. 1 as a metal-oxide-semiconductor field-effect transistor
(MOSFET), it is contemplated that any electrical device whose
electrical properties are voltage-controllable may be leveraged.
For example, transistors 104, 106 may comprise bipolar junction
transistors (BJTs), insulated-gate bipolar transistors (IGBTs),
high-electron-mobility transistors (HEMTs), gallium-nitride-based
transistors (GaNTs), and/or other elements that are
voltage-controllable. Further, transistors 106, 108 may comprise
n-type transistors or p-type transistors. For example, an n-type
MOSFET may include an n-channel for electrons to flow through a
p-substrate between load terminals. In some examples, transistors
106, 108 may comprise other voltage-controlled devices, such as
diodes. Transistors 106, 108 may also include freewheeling diodes
connected in parallel with transistors to prevent reverse breakdown
of transistors 106, 108. In some examples, transistors 106, 108 may
operate as switches or as voltage-controlled resistor devices.
[0016] In an example, transistors 106, 108 may comprise vertical
power transistors. For a vertical power transistor, the source
terminal and the drain terminal may be on opposite sides or
opposite surfaces of the transistor. Drain-source current in a
vertical power transistor may flow through the transistor from
top-bottom or from bottom-top. In still other examples, transistors
106, 108 may include more than two transistors, such as in
multi-phase power converters or other more complex power circuits.
For example, in a multi-phase power converter, power converter 100
may have one high-side transistor and one low-side transistor for
each phase. Therefore, a multi-phase power converter may include
one or more replications of power converter 100 as depicted in FIG.
1.
[0017] FIG. 1 depicts transistors 106, 108 with three terminals:
drain (D), source (S), and gate (G). The drain and source may be
load terminals, and the gate may be a control terminal. Current may
flow between the drain and source of transistors 106, 108, based on
the voltage at the gate. More specifically, current may flow from
the input node to the switch node as shown in FIG. 1 via the drain
and source of transistor 106, based on the voltage at the gate of
transistor 106. Current may flow from the switch node through the
drain and source of transistor 108 to the reference node, as shown
in FIG. 1, based on the voltage at the gate of transistor 108.
Transistor 106 may comprise a high-side transistor, and the
transistor 108 may comprise a low-side transistor.
[0018] Transistors 106, 108 may comprise various material
compounds, such as silicon (Si), silicon carbide (SiC), gallium
nitride (GaN), or any other combination of one or more
semiconductor materials. To take advantage of higher power density
requirements in some circuits, power converters may operate at
higher frequencies. Improvements in magnetics and faster switching,
such as GaN switches, may support higher frequency converters.
These higher frequency circuits may require control signals to be
sent with more precise timing than for lower frequency
circuits.
[0019] Control circuitry 110 may deliver modulation signals, such
as pulse-width modulated (PWM) signals, pulse density modulation
(PDM) signals, or other modulation signals to the control terminals
of transistors 106, 108. FIG. 1 depicts control circuitry 110 as
one component, but control circuitry 110 may comprise a modulation
control circuit and a driver circuit as separate components. In
such an implementation, one or both of the PWM control circuit and
the driver circuit may be located external to power converter 100.
Together, transistors 106, 108 and control circuitry 110 as shown
in FIG. 1 may comprise a semiconductor device package, such as a
chip-embedded substrate, an integrated circuit, or any other
suitable package.
[0020] Inductor 112 may comprise a coil inductor or any suitable
inductor. Inductor 112 may connect to the switch node and an output
node as shown in FIG. 1. Inductor 112 may impede the flow of
alternating-current (AC) electricity, while allowing DC electricity
to flow between the switch node and the output node. Capacitor 114
may comprise a film capacitor, an electrolytic capacitor, a ceramic
capacitor, or any suitable type of capacitor or capacitors.
Capacitor 114 may connect to the output node and the reference
node. Capacitor 114 may impede the flow of DC current, while
allowing AC current to flow between the output node and the
reference node. Capacitor 114 may act as a smoothing capacitor for
the voltage at the output node to moderate fluctuations in the
voltage at the output node.
[0021] As mentioned above, it is contemplated that I/O pins 104 may
be defined or fabricated by a manufacturer of CES 102, as opposed
to an immediate customer of the manufacturer. Additionally, it is
contemplated that the architecture of CES 102 may be
implementation-specific, and thus may be realized in many different
ways. An example of a distinct embedded circuit architecture for
CES 102 is shown and discussed in connection with FIG. 2. Another
example of a distinct embedded circuit architecture for CES 102 is
shown and discussed in connection with FIG. 9. An example method
for defining I/O pins 104, irrespective of architecture of CES 102,
is shown and discussed in connection with FIG. 13.
[0022] FIG. 2 shows a cross-sectional diagram of CES 102 of FIG. 1,
wherein CES 102 is realized as a single-chip-embedded substrate.
Thus, transistors 106, 108 and control circuitry 110 (see FIG. 1)
are, collectively, implemented by or as an integrated circuit (IC)
202 that is embedded within CES 102. As depicted, IC 202 is
electrically-accessible via each one of a first conductor network
and a second conductor network that is at least partially embedded
within CES 102.
[0023] Specifically, with reference to the upper left-hand side of
IC 202 in FIG. 2, the first conductor network comprises
(counterclockwise) a first IC contact 204, a first via structure
206, a passivation contact 208 (e.g., Ni/Au, etc.) that is
positioned within a first recess 210 of a top side 212 of CES 102,
a passivation contact 214 that is positioned within a first recess
216 of a bottom side 218 of CES 102, a passivation contact 219 that
is positioned within a second recess 220 of bottom side 218 of CES
102, and an IC contact area 222 that is along an entire side of IC
202. A node defined by the respective elements of the first
conductor network corresponds to the reference node of CES 102 as
shown in FIG. 1. Thus, the architecture of CES 102 is such that the
reference node is accessible from both top side 212 and bottom side
218 of CES 102 where, as discussed below, CES 102 may in one
example be surface-mounted to a PCB along bottom side 218 of CES
102.
[0024] With reference to the upper right-hand side of IC 202 in
FIG. 2, the second conductor network comprises (clockwise) a third
IC contact 224, a second via structure 226, a passivation contact
228 that is positioned within a second recess 230 of top side 212
of CES 102, and a passivation contact 232 that is positioned within
a third recess 234 of bottom side 218 of CES 102. A node defined by
the respective elements of the second conductor network corresponds
to the switch node as shown in FIG. 1. Thus, the architecture of
CES 102 is such that the switch node is accessible from both top
side 212 and bottom side 218 of CES 102.
[0025] With reference to top side 212 of CES 102 in FIG. 2, each
one of first recess 210 and second recess 230 is formed within a
thin-film dielectric 236, and each one of passivation contact 208
of first recess 210 and passivation contact 228 of second recess
230 is positioned at the bottom of first recess 210 and second
recess 230, respectively, such that a gap 237 is defined between
each one of passivation contact 208 and passivation contact 228 and
a beveled surface 238 of dielectric 236. As discussed below, a
contact-specific volume of solder may be positioned within each one
of first recess 210 and second recess 230 during a process of
defining respective I/O pins 104 such that the reference node of
CES 102 (see FIG. 1), and the switch node of CES 102, is
electrically-accessible from top side 212 of CES 102, and gap 237
may insure that during solder-reflow each one of passivation
contact 208 and passivation contact 228 is fully-alloyed. Although,
it is contemplated that gap 237 is an optional feature.
[0026] With reference to bottom side 218 of CES 102 in FIG. 2, each
one of first recess 216, second recess 220 and third recess 234 is
formed within a thin-film dielectric 240, and each one of
passivation contact 214 of first recess 216, passivation contact
219 of second recess 220 and passivation contact 232 of third
recess 234 is positioned immediately adjacent to or abuts a beveled
surface 242 of dielectric 240 at the bottom of first recess 216,
second recess 220 and third recess 234, respectively. As discussed
below, a contact-specific volume of solder may be positioned within
each one of first recess 216, second recess 220 and third recess
220 during a process of defining respective I/O pins 104 such that
the reference node of CES 102, and the switch node of CES 102, is
electrically-accessible from bottom side 218 of CES 102. In some
examples, a gap may be defined between any particular one of
passivation contact 214, passivation contact 219 and passivation
contact 232 and beveled surface 242 of dielectric 240. Although an
optional feature, such a gap may be defined as illustrated by gap
237 in FIG. 2.
[0027] As mentioned above, a contact-specific volume of solder may
be positioned within each one of first recess 210 and second recess
230 of top side 212 of CES 102 during a process of defining I/O
pins 104 such that the reference node and the switch node of CES
102 is electrically-accessible from top side 212 of CES 102.
Additionally, a contact-specific volume of solder may be positioned
within each one of first recess 216, second recess 220 and third
recess 220 during a process of defining I/O pins 104 such that the
reference node and the switch node of CES 102, is
electrically-accessible from bottom side 218 of CES 102.
[0028] As an example, a contact-specific volume of solder may be
positioned within first recess 210 of top side 212 of CES 102
during a process of defining an instance of L/O pin 104D (see FIG.
1), and a contact-specific volume of solder may be positioned
within second recess 230 of top side 212 of CES 102 during a
process of defining an instance of I/O pin 104C. Additionally, a
contact-specific volume of solder may be positioned within first
recess 216 of bottom side 218 of CES 102 during a process of
defining an instance of I/O pin 104A, a contact-specific volume of
solder may be positioned within second recess 220 of bottom side
218 of CES 102 during a process of defining an instance of I/O pin
104B, and a contact-specific volume of solder may be positioned
within third recess 234 of bottom side 218 of CES 102 during a
process of defining an instance of I/O pin 104C. Further, it is
contemplated that a contact-specific volume of solder may be
positioned within one or more recesses along top side 212 and/or
bottom side 218 of CES 102 not explicitly shown in FIG. 2.
[0029] As an example, a contact-specific volume of solder may be
positioned within a recess (not shown, but may be similar to any
one of recess 210, recess 216, recess 220 of FIG. 2) along top side
212 of CES 102 during a process of defining an instance of I/O pin
104E (see FIG. 1). Additionally, or alternatively, a
contact-specific volume of solder may be positioned within a recess
(not shown, but may be similar to any one of recess 210, recess
216, recess 220 of FIG. 2) along bottom side 218 of CES 102 during
a process of defining an instance of I/O pin 104E. In these and
other examples, the phrase "an instance of" is intended to indicate
that the architecture of CES 102 is such that any particular one of
I/O pins 104 may be defined so that any particular node of CES 102
is electrically-accessible from top side 212 and/or bottom side 218
of CES 102 (e.g., similar to the switch node as shown in FIG. 2,
etc.). FIGS. 3-6 show CES 102 at various steps during a process of
defining I/O pins 104 in accordance with the present
disclosure.
[0030] Specifically, FIGS. 3-6 show CES 102 of FIG. 2 at various
steps during a process of defining I/O pins 104A-C such that the
reference node and the switch node of CES 102 is
electrically-accessible from bottom side 218 of CES 102. It is
contemplated that the same and other steps may be implemented
during a process of defining I/O pins 104 such that the reference
node and the switch node of CES 102 is electrically-accessible from
top side 212 of CES 102. By extension, it is contemplated that the
same and other steps may be implemented during a process of
defining I/O pins 104 such that any particular node of CES 102 is
electrically-accessible from one or both of top side 212 and bottom
side 218 of CES 102.
[0031] FIG. 3 shows a mask 244 positioned to dielectric 240 of
bottom side 218 of CES 102, and a substrate 246 that is aligned
with CES 102 such that each one of a plurality of solder balls
248A-C (collectively, "solder balls 248"), as arranged in a
particular pattern on substrate 246, is aligned with a
corresponding aperture formed within mask 244. Each one of solder
balls 248 has a contact-specific volume of solder. In these and
other examples, the phrase "a contact-specific volume of solder" is
intended to indicate that a particular amount of solder material is
deposited within each one of first recess 216, second recess 220,
and third recess 234 of bottom side 218 of CES 102 during a process
of defining respective instances of I/O pins 104. In the example of
FIG. 3, solder balls 248A and 248C exhibit an approximately same
volume of solder that is different than solder ball 248B. This is
because respective dimensions (e.g., depth, height, differential
cross-sectional area, etc.) of each one of first recess 216 and
third recess 234 is approximately the same, but different than
respective dimensions of second recess 220, such that the shape and
form of first recess 216 is approximately the same as the shape and
form of third recess 234. Shape and form of first recess 216 and
third recess 234 may be "approximately" but not precisely the same
because of variations introduced during the manufacture of CES
102.
[0032] FIG. 4 shows each one of solder balls 248 positioned to a
corresponding one of first recess 216, second recess 220 and third
recess 234 of bottom side 218 of CES 102, through a corresponding
aperture formed within mask 244. In practice, solder may be
positioned to first recess 216, second recess 220 and third recess
234 through a corresponding aperture formed within mask 244 by many
different techniques. For example, instead of the substrate-based
implementation as shown in FIGS. 3-4, a screen-printing technique
may be used during a process of defining I/O pins 104. Other
examples are possible as well.
[0033] Once each one of solder balls 248 is positioned to a
corresponding one of first recess 216, second recess 220 and third
recess 234, as shown in FIG. 4, solder-reflow and pin-machining
processes may be performed to define L/O pins 104A-C. FIG. 5 shows
I/O pins 104A-C immediately following solder-reflow processes
(e.g., temperature-cycling, re-flux, drying bake, etc.), and thus
each one of I/O pins 104A-C as extending from dielectric 240 of CES
102 exhibits an irregular or unshaped form. FIG. 6 shows I/O pins
104A-C immediately following pin-machining processes (e.g.,
grinding or etching, polishing, etc.), and thus each one of I/O
pins 104A-C as extending from dielectric 240 exhibits a regular or
shaped form. In particular, FIG. 6 shows each one of I/O pins
104A-C machined so as to extend from CES 102 to a common height 250
within specification tolerance (lower left-hand side).
[0034] The phrase "to a common height within specification
tolerance" is intended to indicate that each one of I/O pins 104
may not extend precisely to height 250 as measured from surface 252
of dielectric 240 to a flat end surface 254 of I/O pins 104, as
shown in FIG. 6, but that there may be some variance or variation
(e.g., +/-2 .mu.m, etc.) such that on the macroscale end surface
254 of each one I/O pins 104A-C may exhibit roughness and/or not
lie precisely in plane 256. However, on the microscale, and to the
naked eye, end surface 254 of each one I/O pins 104A-C may appear
to lie precisely within plane 256m, co-planar. It is contemplated
that such co-planarity may facilitate precision surface-mounting of
CES 102 to a PCB along bottom surface 218 of CES 102, and at
low-cost and without risk of unintended solder void trapping under
I/O pins 104 as, in each one of the examples of the disclosure, I/O
pins 104 are (pre-)defined by a manufacturer of the CES 102. FIGS.
7-8 show CES 102 at various steps during a process of
surface-mounting CES 102 to a PCB in accordance with the present
disclosure.
[0035] Specifically, FIG. 7 shows a PCB 258 that is aligned with
CES 102 such that each one of a plurality of contact pads 260A-C
(collectively, "contact pads 260"), as arranged in a particular
pattern on PCB 258, is aligned with a corresponding one of I/O pins
104A-C. FIG. 8 shows CES 102 surface-mounted to PCB 258 along
bottom surface 218 of CES 102 by contacts 262A-C (collectively,
"contacts 262") which are formed by joining I/O pins 104A-C with
corresponding ones of contact pads 260A-C.
[0036] FIG. 9 shows a cross-sectional diagram of CES 102 of FIG. 1,
wherein CES 102 is realized as a multi-chip-embedded substrate.
Thus, each one of transistors 106, 108 and control circuitry 110
(see FIG. 1) is implemented by or as a discrete component that is
embedded within CES 102. Specifically, control circuitry 110 is
implemented by or as an integrated circuit (IC) 902 in the example
of FIG. 9, transistor 106 is implemented by or as a vertical power
transistor 904 in the example of FIG. 9, and transistor 108 is
implemented by or as a vertical power transistor 906 in the example
of FIG. 9.
[0037] In this example, with reference to the bottom right-hand
side of FIG. 9, a passivation contact 908 that is positioned within
a first recess 910 of a bottom side 912 of CES 102 is, together
with a passivation contact 914 that is positioned within a second
recess 916 of bottom side 912 of CES 102, connected to a first via
structure 918 that is embedded within CES 102. Electrically, first
via structure 918 corresponds to the input node of CES 102 (see
FIG. 1). With additional reference to the upper left-hand side of
FIG. 9, IC 902 is connected to first via structure 918 by a first
IC contact 920, and first via structure 918 is connected to the
gate node of transistor 904 (see transistor 106 in FIG. 1).
Further, IC 902 is connected to a first conductor structure 922
that is embedded within CES 102 by a second IC contact 924, and
first conductor structure 922 is connected to the drain node of
transistor 904. Further, IC 902 is connected to a second conductor
structure 926 that is embedded within CES 102 by a third IC contact
928, and second conductor structure 926 is connected to both the
source node of transistor 904 and to the drain node of transistor
906 (see transistor 108 in FIG. 1). Electrically, second conductor
structure 926 corresponds to the switch node of CES 102.
[0038] With reference to the bottom left-hand side of FIG. 9, a
passivation contact 930 that is positioned within a third recess
932 of bottom side 912 of CES 102 is, together with a passivation
contact 934 that is positioned within a fourth recess 936 and a
passivation contact 938 that is positioned within a fifth recess
940 of bottom side 912 of CES 102, connected to a second via
structure 942 that is embedded within CES 102. IC 902 is connected
to second via structure 942 by a fourth IC contact 944 and by a
backside contact 946 to IC 902 that in turn is connected the source
node of transistor 906 (see FIG. 1). Electrically, second via
structure 942 corresponds to the reference node of CES 102.
Further, IC 902 is connected to a third conductor structure 948,
that is embedded within CES 102, by a fifth IC contact 950, and
third conductor structure 948 is connected to the gate node of
transistor 906.
[0039] Similar to the example of FIG. 2, a contact-specific volume
of solder may be positioned within each one of first recess 910,
second recess 916, third recess 932, fourth recess 936 and fifth
recess 940 of bottom side 912 of CES 102 during a process of
defining respective I/O pins 104. As an example, a contact-specific
volume of solder may be positioned within first recess 910, and
within second recess 916, of bottom side 912 of CES 102 during a
process of defining an instance of I/O pin 104E (see FIG. 1), and a
contact-specific volume of solder may be positioned within third
recess 932, and within fourth recess 936 and within fifth recess
940, of bottom side 912 of CES 102 during a process of defining an
instance of I/O pins 104D, 104B and 104A, respectively.
Additionally, it is contemplated that a contact-specific volume of
solder may be positioned within one or more recesses along a top
side 952 and/or bottom side 912 of CES 102 not explicitly shown in
FIG. 9.
[0040] As an example, a contact-specific volume of solder may be
positioned within a recess (not shown, but may be similar to any
one of recess 910, recess 916, recess 932, recess 936, recess 940
of FIG. 2) along top side 952 and/or bottom side 912 of CES 102
during a process of defining an instance of I/O pin 104C (see FIG.
1). In these and other examples, the phrase "an instance of" is
intended to indicate that the architecture of CES 102 may be such
that any particular one of I/O pins 104 may be defined or
fabricated such that any particular node of CES 102 is
electrically-accessible from top side 952 and/or bottom side 912 of
CES 102. FIGS. 10-11 show CES 102 at various steps during a process
of defining I/O pins 104 in accordance with the present
disclosure.
[0041] Specifically, FIGS. 10-11 show CES 102 of FIG. 9 at various
steps during a process of defining I/O pins 104A, 104B, 104D, 104E
such that the reference node of CES 102, and the input node of CES
102, is electrically-accessible from bottom side 912 of CES 102. It
is contemplated that the same and other steps may be implemented
during a process of defining I/O pins 104 such that the reference
node of CES 102, and the input node of CES 102, is
electrically-accessible from top side 952 of CES 102. By extension,
it is contemplated that the same and other steps may be implemented
during a process of defining I/O pins 104 such that any particular
node of CES 102 is electrically-accessible from one or both of top
side 952 and bottom side 912 of CES 102.
[0042] FIG. 10 shows a mask 954 positioned to a dielectric 956 of
bottom side 912 of CES 102, and a substrate 958 that is aligned
with CES 102 such that each one of a plurality of solder balls
960A-C (collectively, "solder balls 960"), as arranged in a
particular pattern on substrate 958, is aligned with a
corresponding aperture formed within mask 954. In this example,
solder balls 960A and 960E and, separately, solder balls 960C and
960D, exhibit an approximately same volume of solder that is
different than solder ball 960B. This is because respective
dimensions of each one of third recess 932 and first recess 910
and, separately, each one of fifth recess 940 and second recess
916, are approximately the same, but different than respective
dimensions of fourth recess 940. Shape and form of particular
recesses of FIG. 9 may be "approximately" but not precisely the
same because of variations introduced during the manufacture of CES
102.
[0043] Once each one of solder balls 960 is positioned to a
corresponding one of first recess 910, second recess 916, third
recess 932, fourth recess 936 and fifth recess 940 of bottom side
912 of CES 102, solder-reflow and pin-machining processes may be
performed to define respective instances of I/O pins 104. FIG. 11
shows I/O pins 104A, 104B, 104D and 104E (see FIG. 1) following
solder-reflow and pin-machining processes, and thus each one of I/O
pins 104A, 104B, 104D and 104E exhibits a regular or shaped form.
In particular, FIG. 11 shows each one of I/O pins 104A, 104B, 104D
and 104E machined so as to extend from CES 102 to a common height
962 within specification tolerance (lower left-hand side).
[0044] The phrase "to a common height within specification
tolerance" is intended to indicate that each one of I/O pins 104
may not extend precisely to height 962 as measured from a surface
964 of dielectric 956 to a flat end surface 966 of I/O pins 104, as
shown in FIG. 11, but that there may be some variance or variation,
such that on the macroscale end surface 966 of each one I/O pins
104 may exhibit roughness and/or not lie precisely in a plane 938.
However, on the microscale, and to the naked eye, end surface 966
of each one I/O pins 104 may appear to lie precisely within plane
968, i.e., "co-planar." It is contemplated that such co-planarity
may facilitate precision surface-mounting of CES 102 to a PCB along
bottom surface 912 of CES 102, and at low-cost and without risk of
unintended solder void trapping under I/O pins 104 as, in each one
of the examples of the disclosure, I/O pins 104 are (pre-)defined
by a manufacturer of the CES 102.
[0045] FIG. 11 further shows a PCB 970 that is aligned with CES 102
such that each one of a plurality of contact pads 972A-E
(collectively, "contact pads 972"), as arranged in a particular
pattern on PCB 970, is aligned with a corresponding one of I/O pins
104A, 104B, 104D and 104E. FIG. 12 shows CES 102 surface-mounted to
PCB 970 along bottom surface 912 of CES 102 by contacts 974A-E
(collectively, "contacts 974") which are formed by joining I/O pins
104A. 104B, 104D and 104E with corresponding ones of contact pads
972A-E.
[0046] FIG. 13 shows an example method 1300 for defining a
plurality of L/O pins in accordance with the disclosure. The
example method 1300 comprises the step of selecting (1302) a
substrate that has a solder ball pattern that is specific to a type
of CES. An example of such a substrate is shown in FIG. 3 as
substrate 246. Another example of such a substrate is shown in FIG.
10 as substrate 958. The example method 1300 further comprises the
step of engaging (1304) the substrate that has the solder ball
array to the CES to deposit solder to each one of a plurality of
contacts of the CES that are recessed within the CES. Another
example of such a step is shown in FIG. 4. The example method 1300
further comprises the step of temperature-cycling (1306) the CES to
induce solder reflow and define an L/O pin for each one of the
contacts of the CES that are recessed within the CES. Another
example of such a step is shown in FIG. 5. The example method 1300
further comprises the step of machining (108) the I/O pin for each
one of the contacts of the CES that are recessed within the CES to
extend exposed from the CES to a common height within specification
tolerance. An example of such as step is shown in FIG. 6. Another
example of such a step is shown in FIG. 11. The example method 1300
further comprises the step of surface-mounting (1310) the CES to a
printed circuit board (PCB) to establish I/O connections through
traces to other components and devices surface-mounted to the PCB.
An example of such as step is shown in FIG. 8. Another example of
such a step is shown in FIG. 12.
[0047] The example method 1300 represents a paradigm shift in that
the manufacturer of the CES may assume the burden of quality
control with respect to minimizing unintended solder void trapping
under the I/O pins, thereby reinforcing existing customer loyalty
and potentially attracting new customers. This is because both
existing and potential new customers may realize a substantial cost
savings as their own surface-mount assembly processes may be
simplified or streamlined by reducing the number of steps required
to surface-mount the CES to a PCB in order to produce an
electronics product or circuit that incorporates or leverages the
functionality of the CES. Further, the cost savings may propagate
through the supply chain all the way to the ultimate consumer
electronics customer. Further, the manufacturer of CES can better
insure that rated device level characteristics of CES are realized,
as opposed to being inadvertently compromised by the immediate
customer during their own processes for surface-mounting CES to a
substrate such as a PCB to produce an electronics product or
circuit that incorporates or leverages the functionality of the
CES. By extension, the reputation of the manufacturer for producing
high-performance devices may be protected and not threatened due to
a perceived degradation in performance that is not attributable to
CES.
[0048] Additionally, the following numbered examples demonstrate
one or more aspects of the disclosure.
Example 1
[0049] A method comprising: applying a contact-distinct volume of
solder to at least two contacts recessed within a chip-embedded
substrate; temperature-cycling the chip-embedded substrate to
induce solder reflow and define an input/output pin for each one of
the at least two contacts; and machining the input/output pin for
each one of the at least two contacts to extend exposed from the
chip-embedded substrate to a common height within specification
tolerance.
Example 2
[0050] The method of example 1, wherein applying the
contact-distinct volume of solder comprises: applying a first
volume of solder to a first one of the at least two contacts and a
second volume of solder that is different than the first volume of
solder to a second one of the at least two contacts.
Example 3
[0051] The method of any one of examples 1-2, wherein applying the
contact-distinct volume of solder comprises: positioning a mask to
the chip-embedded substrate so that a first aperture of the mask is
aligned with a first one of the at least two contacts and a second
aperture of the mask that is sized different than the first
aperture is aligned with a second one of the at least two
contacts.
Example 4
[0052] The method of any one of examples 1-3, wherein applying the
contact-distinct volume of solder comprises: aligning a substrate
that has a particular solder ball pattern with the chip-embedded
substrate; and engaging the substrate that has the particular
solder ball pattern to the chip-embedded substrate so that a first
volume of solder is applied to a first one of the at least two
contacts and a second volume of solder that is different than the
first volume of solder is applied to a second one of the at least
two contacts.
Example 5
[0053] The method of any one of examples 1-4, wherein applying the
contact-distinct volume of solder comprises: selecting a substrate
from among a plurality of substrates each one that exhibits a
solder ball pattern specific to a type of chip-embedded substrate;
aligning the substrate with the chip-embedded substrate; and
engaging the substrate that has the particular solder ball pattern
to the chip-embedded substrate so that a first volume of solder is
applied to a first one of the at least two contacts and a second
volume of solder that is different than the first volume of solder
is applied to a second one of the at least two contacts.
Example 6
[0054] The method of any one of examples 1-5, further comprising:
selecting the chip-embedded substrate from among a plurality of
chip-embedded substrates each one that exhibits a distinct embedded
circuit architecture.
Example 7
[0055] The method of any one of examples 1-6, further comprising:
selecting the chip-embedded substrate from among a plurality of
chip-embedded substrates each one that exhibits a distinct embedded
circuit architecture, wherein the chip-embedded substrate comprises
an integrated circuit and a plurality of through-via conductors
each one that is electrically coupled to the integrated circuit and
to a particular one of the at least two contacts recessed within
the chip-embedded substrate.
Example 8
[0056] The method of any one of examples 1-7, further comprising:
selecting the chip-embedded substrate from among a plurality of
chip-embedded substrates each one that exhibits a distinct embedded
circuit architecture, wherein the chip-embedded substrate comprises
an integrated circuit, at least two discrete transistors and a
plurality of through-via conductors each one that is electrically
coupled to the integrated circuit, to a particular one of the at
least two contacts recessed within the chip-embedded substrate and
to a particular one of the at least two discrete transistors.
Example 9
[0057] The method of any one of examples 1-8, machining the
input/output pin for each one of the at least two contacts
comprises: shaping the input/output pin for each one of the at
least two contacts so that an exposed contact surface of a first
input/output pin is approximately coplanar with an exposed contact
surface of a second input/output pin.
Example 10
[0058] The method of any one of examples 1-9, further comprising:
mounting the chip-embedded substrate to a printed circuit board
wherein the input/output pin for each one of the at least two
contacts is coupled to a particular contact pad of the printed
circuit board.
Example 11
[0059] A semiconductor device package, comprising: a chip-embedded
substrate that includes at least two exposed input/output pins each
one that exhibits a cross-sectional area distinct from at least one
other of the at least two exposed input/output pins and that
extends from the chip-embedded substrate to a height that is common
for each of the at least two exposed input/output pins within
specification tolerance.
Example 12
[0060] The semiconductor device package of example 11, wherein a
first one of the at least two exposed input/output pins extends
from a first contact that is recessed within the chip-embedded
substrate and a second one of the at least two exposed input/output
pins extends from a second contact that is recessed within the
chip-embedded substrate at a depth different than the first
contact.
Example 13
[0061] The semiconductor device package of any one of examples
11-12, wherein an exposed surface of a first one of the at least
two exposed input/output pins is approximately coplanar with an
exposed surface of a second one of the at least two exposed
input/output pins.
Example 14
[0062] The semiconductor device package of any one of examples
11-13, wherein an unexposed surface of each at least one of the at
least two exposed input/output pins is in contact with a beveled
surface of a dielectric material of the chip-embedded
substrate.
Example 15
[0063] The semiconductor device package of any one of examples
11-14, wherein the chip-embedded substrate comprises power
converter circuitry and each one of the at least two exposed
input/output pins is electrically coupled to a node of the power
converter circuitry via a corresponding contact that is recessed
within the chip-embedded substrate.
Example 16
[0064] The semiconductor device package of any one of examples
11-15, wherein the chip-embedded substrate comprises an integrated
circuit and a plurality of through-via conductors each one that is
electrically coupled to the integrated circuit and to a particular
one of the at least two exposed input/output pins via a
corresponding contact that is recessed within the chip-embedded
substrate.
Example 17
[0065] The semiconductor device package of any one of examples
11-16, wherein the chip-embedded substrate comprises an integrated
circuit, at least two discrete transistors and a plurality of
through-via conductors each one that is electrically coupled to the
integrated circuit and to a particular one of the at least two
exposed input/output pins and a particular one of at least two
discrete transistors via a corresponding contact that is recessed
within the chip-embedded substrate.
Example 18
[0066] The semiconductor device package of any one of examples
11-17, wherein the at least two exposed input/output pins are each
electrically coupled to an integrated circuit embedded within the
chip-embedded substrate via a corresponding contact that is
recessed within the chip-embedded substrate.
Example 19
[0067] The semiconductor device package of any one of examples
11-18, wherein the at least exposed input/output pins are each
electrically coupled to an integrated circuit and to a transistor
embedded within the chip-embedded substrate via a corresponding
contact that is recessed within the chip-embedded substrate.
Example 20
[0068] A method comprising: depositing solder to each one of a
plurality of differently-sized contacts recessed at different
depths within a chip-embedded substrate that comprises power
converter circuitry; temperature-cycling the chip-embedded
substrate to induce solder reflow and define an input/output pin
for each one of the plurality of contacts that is electrically
coupled to the power converter circuitry via a corresponding one of
the plurality of contacts; and machining the input/output pin for
each one of the at least two contacts to extend exposed from the
chip-embedded substrate to a common height within specification
tolerance.
[0069] Various examples of the disclosure have been described. Any
combination of the described systems, operations, or functions is
contemplated. These and other examples are within the scope of the
following claims.
* * * * *