U.S. patent application number 15/244819 was filed with the patent office on 2018-03-15 for asymmetrical blocking bidirectional gallium nitride switch.
The applicant listed for this patent is David Sheridan. Invention is credited to David Sheridan.
Application Number | 20180076310 15/244819 |
Document ID | / |
Family ID | 61265173 |
Filed Date | 2018-03-15 |
United States Patent
Application |
20180076310 |
Kind Code |
A1 |
Sheridan; David |
March 15, 2018 |
ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH
Abstract
A high electron mobility transistor (HEMT)gallium nitride (GaN)
bidirectional blocking device includes a hetero-j unction structure
comprises a first semiconductor layer interfacing a second
semiconductor layer of two different band gaps thus generating an
interface layer as a two-dimensional electron gas (2 DEG) layer.
The HEMT GaN bidirectional blocking device further includes a first
source/drain electrode and a second source/drain electrode disposed
on two opposite sides of a gate electrode disposed on top of said
hetero-junction structure for controlling a current flow between
the first and second source/drain electrodes in the 2 DEG layer
wherein the gate electrode is disposed at a first distance from the
first source/drain electrode and a second distance from the second
source/drain electrode and the first distance is different from the
second distance.
Inventors: |
Sheridan; David;
(Greensboro, NC) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Sheridan; David |
Greensboro |
NC |
US |
|
|
Family ID: |
61265173 |
Appl. No.: |
15/244819 |
Filed: |
August 23, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/402 20130101;
H01L 29/404 20130101; H01L 29/66462 20130101; H01L 29/42356
20130101; H01L 29/4236 20130101; H01L 29/7786 20130101; H01L
29/7787 20130101; H01L 29/4966 20130101; H01L 29/205 20130101; H01L
29/1066 20130101; H01L 29/2003 20130101 |
International
Class: |
H01L 29/778 20060101
H01L029/778; H01L 29/40 20060101 H01L029/40; H01L 29/20 20060101
H01L029/20; H01L 29/205 20060101 H01L029/205; H01L 29/423 20060101
H01L029/423; H01L 29/49 20060101 H01L029/49 |
Claims
1. A high electron mobility transistor (HEMT) gallium nitride (GaN)
bidirectional blocking device comprising: a hetero junction
structure comprises a first semiconductor layer interfacing a
second semiconductor layer of two different band gaps thus
generating an interface layer as a two-dimensional electron gas (2
DEG) layer; and a first source/drain electrode and a second
source/drain electrode disposed on two opposite sides of a gate
electrode disposed on top of said hetero junction structure for
controlling a current flow between the first and second
source/drain electrodes in the 2 DEG layer wherein the gate
electrode is disposed at a first distance from the first
source/drain electrode and a second distance from the second
source/drain electrode and the first distance is different from the
second distance.
2. The HEMT GaN bidirectional blocking device of claim 1 wherein:
the gate electrode further comprises a first field plate extending
toward the first source/drain electrode and a second field plate
extending toward the second source/drain electrode wherein the
first field plate and second field plate are configure
asymmetrically.
3. The HEMT GaN bidirectional blocking device of claim 1 further
comprising: a sapphire substrate for supporting the hetero junction
structure thereon.
4. The HEMT GaN bidirectional blocking device of claim 1 wherein:
the hetero junction structure comprises a gallium nitride (GaN) as
the first semiconductor layer interfacing an AlGaN layer as the
second semiconductor layer.
5. The HEMT semiconductor power device of claim 1 wherein: the
first semiconductor layer is an N-type gallium nitride layer and
the second semiconductor layer is an N-type AlGaN layer disposed on
top of the gallium nitride layer.
6. The HEMT GaN bidirectional blocking device of claim 1 further
comprising: a GaN buffer layer disposed on top of a bottom
substrate for supporting the hetero junction structure thereon.
7. The HEMT GaN bidirectional blocking device of claim 1 wherein:
the gate electrode comprises a P-type AlGaN gate.
8. The HEMT GaN bidirectional blocking device of claim 1 wherein:
the first source/drain electrode and the second source/drain
electrode are composed of a metal selected from a group of metals
consists of Ti, Al, Ni and Au.
9. A high electron mobility transistor (HEMT) gallium nitride (GaN)
bidirectional blocking device comprising: a hetero junction
structure comprises a first semiconductor layer interfacing a
second semiconductor layer of two different band gaps thus
generating an interface layer as a two-dimensional electron gas (2
DEG) layer; and a first source/drain electrode and a second
source/drain electrode disposed on two opposite sides of a top
surface of the hetero junction structure; the first source/drain
electrode further includes a first field plate extending laterally
toward the second source/drain electrode with a first gate disposed
underneath the first field plate; and the second source/drain
electrode further includes a second field plate extending laterally
toward the first source/drain electrode with a second gate disposed
underneath the first field plate wherein the first field plate is
configured to be asymmetrically relative to the second field
plate.
10. The HEMT GaN bidirectional blocking device of claim 9 wherein:
the first field plate has a length represented by L.sub.SD-FP1 and
the second field plate has a length represented by L.sub.SD-FP2 and
wherein L.sub.SD-FP1 is different from L.sub.SD-FP2.
11. The HEMT GaN bidirectional blocking device of claim 9 further
comprising: a sapphire substrate for supporting the hetero junction
structure thereon.
12. The HEMT GaN bidirectional blocking device of claim 9 wherein:
the hetero junction structure comprises a gallium nitride (GaN) as
the first semiconductor layer interfacing an AlGaN layer as the
second semiconductor layer.
13. The HEMT semiconductor power device of claim 9 wherein: the
first semiconductor layer is an N-type gallium nitride layer and
the second semiconductor layer is an N-type AlGaN layer disposed on
top of the gallium nitride layer.
14. The HEMT GaN bidirectional blocking device of claim 9 further
comprising: a GaN buffer layer disposed on top of a bottom
substrate for supporting the hetero junction structure thereon.
15. The HEMT GaN bidirectional blocking device of claim 1 wherein:
the first gate and the second gate comprise a first P-type AlGaN
gate and a second P-type AlGaN gate.
16. The HEMT GaN bidirectional blocking device of claim 1 wherein:
the first source/drain electrode and the second source/drain
electrode are composed of a metal selected from a group of metals
consists of Ti, Al, Ni and Au.
17. A method of forming a high electron mobility transistor (HEMT)
gallium nitride (GaN) bidirectional blocking device comprising:
forming a hetero-junction structure from a first semiconductor
layer interfacing a second semiconductor layer having different
band gaps to make a two dimensional gas (2 DEG) at the hetero
junction structure; forming a first source/drain electrode and
second source/drain electrode on a top surface and at two opposite
ends of the hetero junction structure; and forming a gate on the
top surface of the hetero junction structure with a distance from
the first source/drain electrode represented by L.sub.GS1/D2 and a
distance from the second source/drain electrode represented by
L.sub.GS2/D1 wherein L.sub.GS1/D2 is different from
L.sub.GS2/D1.
18. The method of claim 17 wherein: the process of forming the gate
further comprising a step of forming the gate as P-type AlGaN
gate.
19. A method of forming a high electron mobility transistor (HEMT)
gallium nitride (GaN) bidirectional blocking device comprising:
forming a hetero junction structure from a first semiconductor
layer interfacing a second semiconductor layer having different
band gaps to make a two dimensional gas (2 DEG) at the hetero
junction structure; forming a first source/drain electrode and
second source/drain electrode on a top surface and at two opposite
ends of the hetero junction structure; forming a first field plate
extending from the first source/drain electrode toward the second
source/drain electrode and forming a second field plate extending
from the second source/drain electrode toward the first
source/drain electrode with the second field plate configured
asymmetrically from the first field plate; forming a first gate
underneath the first field plate and forming a second gate
underneath the second field plate.
20. The method of claim 17 wherein: the process of forming the
first and the second gates further comprise a step of forming the
gates as P-type AlGaN gates.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The invention relates generally to the configurations and
methods of manufacturing the semiconductor devices. More
particularly, this invention relates to an asymmetrical blocking
gallium nitride (GaN) switch.
2. Description of the Prior Art
[0002] Conventional methods of configuring and manufacturing a
gallium nitride (GaN) based field effect transistors (FETs) are
still challenged with the technical issues for providing a
bidirectional asymmetrical blocking capabilities to function as a
bidirectional switch. It is often demanded to provide lateral GaN
based asymmetrical blocking function for optimal applications in
devices such as direct high voltage buck converter and dual boost
bridgeless PFC.
[0003] However, the benefits of asymmetrical blocking are not
achieved due to the limitations in the conventional applications of
the blocking switches. Specifically, for bidirectional switch
applications, the RB-IGBT devices and symmetrical bidirectional
blocking GaN switches are commonly implemented. The silicon based
bidirectional blocking devices are vertical devices and are
intrinsically symmetrical. The GaN devices as shown in FIGS. 1A,
1B, 1C, 1D and 1E are commonly optimized for symmetric blocking
capabilities where the symmetric blocking capability is set by the
Rds,on and that is in turn dictated by the symmetric field plating
capacitance.
[0004] Therefore, there is a need to provide new and improved
device configuration and manufacturing methods to make
bidirectional GaN blocking switches with asymmetrical blocking
capabilities to resolve the above mentioned limitations and
difficulties.
SUMMARY OF THE PRESENT INVENTION
[0005] It is therefore an aspect of the present invention to
provide a new and improved device configuration and manufacturing
method to provide a high electron mobility transistor (HEMT) power
device that provides the functions of asymmetrical bidirectional
blocking switch such that the above discussed difficulties and
limitations may be resolved.
[0006] Specifically, it is an aspect of the present invention to
provide improved device configuration and method for manufacturing
a semiconductor GaN-based HEMT power device with the functions of
asymmetrical bidirectional blocking for applications to switch with
asymmetrical voltage stress such that the Rds-on and the capacitive
loss can be minimized thus reduce the unnecessary loss caused by
symmetrical blocking switches commonly implemented in the
conventional designs.
[0007] It is another aspect of the present invention to provide
improved device configuration and method for manufacturing the
GaN-based high electron mobility transistor (HEMT) power device
with optimized lateral configuration for designing and
manufacturing asymmetrical blocking switches such that commonly
layout constraint that impose different parasitic inductances to
cause asymmetrical blocking and asymmetrical voltage overshoots may
be better considered and controlled as part of the design and
manufacturing processes.
[0008] It is another aspect of the present invention to provide
improved device configuration and method for manufacturing a
semiconductor GaN-based HEMT power device with asymmetrical
blocking capabilities with configurations by implementing either a
single or dual gate configurations such that the switch functions
and performances of the switching devices may be more flexible and
conveniently controlled.
[0009] Briefly in a preferred embodiment this invention discloses a
high electron mobility transistor (HEMT)gallium nitride (GaN)
bidirectional blocking device that includes a hetero-junction
structure comprising a first semiconductor layer interfacing a
second semiconductor layer of two different band gaps thus
generating an interface layer as a two-dimensional electron gas (2
DEG) layer. The HEMT GaN bidirectional blocking device further
includes a first source/drain electrode and a second source/drain
electrode disposed on two opposite sides of a gate electrode
disposed on top of the hetero-junction structure for controlling a
current flow between the first and second source/drain electrodes
in the 2 DEG layer wherein the gate electrode is disposed at a
first distance from the first source/drain electrode and a second
distance from the second source/drain electrode and the first
distance is different from the second distance.
[0010] These and other objects and advantages of the present
invention will no doubt become obvious to those of ordinary skill
in the art after having read the following detailed description of
the preferred embodiment, which is illustrated in the various
drawing figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1A to 1E are cross sectional views and circuit
diagrams to show a conventional GaN-based HEMT symmetrical blocking
switching devices,
[0012] FIGS. 2 to 5 are cross sectional views of the asymmetrical
blocking switching devices as different preferred embodiment of
this invention.
[0013] FIGS. 6A to 6G are a series of cross sectional views to
illustrate the processing steps of manufacturing the devices of
this invention.
[0014] FIGS. 7A to 7H are a series of cross sectional views to
illustrate the processing steps of manufacturing the devices of
this invention.
[0015] FIGS. 8A to 8I are a series of cross sectional views to
illustrate the processing steps of manufacturing the devices of
this invention.
[0016] FIGS. 9A to 9G are a series of Cross sectional views to
illustrate the processing steps of manufacturing the devices of
this invention.
[0017] FIGS. 10A to 10H are a series of cross sectional views to
illustrate the processing steps of manufacturing the devices of
this invention.
[0018] FIGS. 11A to 11I are a series of cross sectional views to
illustrate the processing steps of manufacturing the devices of
this invention.
DETAILED DESCRIPTION OF THE METHOD
[0019] Referring to FIG. 2 for a cross sectional view of a
bidirectional GaN switch formed as a high electron mobility
transistor (HEMT) semiconductor power device 100 of this invention.
The bidirectional GaN switching device 100 comprises an AlGaN layer
120 epitaxial grows on top of gallium nitride (GaN) layer 115 thus
forming an AlGaN/GaN hetero-junction located at the interface. The
AlGaN/GaN heterojunction structure is supported on buffer layer 110
supported on a substrate 105. A first electrode 140-1 and a second
electrode 140-2 are disposed on two opposite sides of a gate
electrode 135 to control the bidirectional current flow through the
hetero-junction between the interface of the AlGaN and GaN layers.
The gate electrode 135 is insulated front the AlGaN layer 120. In
order to configure the bidirectional GaN switch as an asymmetrical
block switch, the distance between the first electrode 140-1 and
the gate 135, i.e., L.sub.GS1/D2 is formed to be different from the
distance between the second electrode 140-2 and the gate 135, i.e.,
L.sub.GS2/D1. Therefore, in this bi-directional GaN HEMT single
gate device m shown in FIG. 2, it is designed to have asymmetric
blocking because the distance from the gate to respective
source/drain regions are different. i.e., LGD1.noteq.LGD2,
Furthermore, the field plates 135-FP1 and 135-FP2 on the gate 135
are also formed to be asymmetric to achieve asymmetric
blocking.
[0020] FIG. 2A is another embodiment of an asymmetrical
bidirectional GaN switch of this invention similar to the device as
that shown in FIG. 2. The only difference is the gate 135P of this
embodiment is formed as a p-type AlGaN gate.
[0021] Referring to FIG. 3 for a cross sectional view of a
bidirectional asymmetrical blocking switch formed as a GaN high
electron mobility transistor (HEMT) semiconductor power device 200
of this invention. The bidirectional GaN switch device 200
comprises an AlGaN layer 120 epitaxial grown on top of gallium
nitride (GaN) layer 115 thus forming an AlGaN/GaN hetero-junction
located at the interface. The AlGaN/GaN hetero-junction structure
is supported on buffer layer 110 supported on a substrate 105. A
first electrode 140-1 and a second electrode 140-2 are disposed on
two opposite sides of a top surface of tile AlGaN layer 120. The
asymmetrical blocking switch farther comprises drill gates 135-1
and 135-2 disposed under the field plates 140-1-FP and 140-2-FP
respectively.
[0022] In order to configure the bidirectional blocking switch as
an asymmetrical block switch, the field plates of the first and the
second drain/source electrodes, i.e., first field plate
L.sub.SD-FP1 is formed to have different length from second field
plate L.sub.SD-FP2. The distances between the gate and the
electrodes, i.e., L.sub.GS1 and L.sub.GS2 may also be formed to
have an asymmetric configuration as well.
[0023] Referring to FIG. 4 for a cross sectional view of a
bidirectional asymmetrical blocking switch formed as a single gate
metal insulator semiconductor field effect transistor (MISFET)
semiconductor power device 300 of this invention. The bidirectional
GaN switch device 300 comprises an AlGaN layer 120 epitaxial grown
on top of gallium nitride is (GAN) layer 115 thus forming an
AlGaN/GaN hetero-junction located at the interface. The AlGaN/GaN
hetero-junction structure is supported buffer layer 110 supported
on a substrate 105. The bidirectional asymmetrical blocking switch
300 further includes a cap/passivation layer 125 that is formed as
a layer of high resistance such as a layer of GaN/SiN/SiO2 and is a
thin layer ranging between 2 to 200 nanometers. The cap/passivation
layer 125 may be formed as a passivation or a gate dielectric layer
composed of SiN or SiO2.
[0024] A first electrode 140-1 and a second electrode 140-2 are
disposed on two opposite sides of a gate electrode 135 to control
the bidirectional current flow through the hetero junction between
the interface of the AlGaN and GaN layers. In order to configure
the bidirectional GaN switch as an asymmetrical block switch, the
distance between the first electrode 140-1 and the gate 135, i.e.,
L.sub.GS1/D2 is formed to be different from the distance between
the second electrode 140-2 and the gate 135, i.e., L.sub.GS2/D1.
Therefore, in this bi-directional GaN HEMT single gate device as
shown in FIG. 4, it is designed to have asymmetric blocking because
the distance from the gate to respective source/drain regions are
different, i.e., L.sub.GD1.noteq.L.sub.GD2. Furthermore, the field
plates 135-FP1 and 135-FP2 on the gate 135 are also formed to be
asymmetric to achieve asymmetric blocking.
[0025] Referring to FIG. 5 for a cross sectional view of an
alternate embodiment of this invention. The bidirectional switch is
formed as a bidirectional GaN high electron mobility transistor
(HEMT) semiconductor power device 400. The bidirectional GaN switch
device 400 comprises an AlGaN layer 120 epitaxial grown on top of
gallium nitride (GaN) layer 115 thus forming an AlGaN/GaN hetero
junction located at the interface. The AlGaN/GaN hetero-junction
structure is supported on buffer layer 110 supported on a substrate
105. A first electrode 140-1 and a second electrode 140-2 are
disposed on two opposite sides of a gate electrode 135 to control
the bidirectional current flow through the hetero junction between
the interface of the AlGaN and GaN layers. The gate electrode 135T
is formed as a trenched gate that is insulated from the AlGaN layer
120 by an insulation layer 125T. In order to configure the
bidirectional GaN switch as an asymmetrical block switch, the
distance between the first electrode 140-1 and the gate 135T, i.e.,
L.sub.GS1/D2 is formed to be different from the distance between
the second electrode 140-2 and the gate 135T, i.e., L.sub.GS2/D1.
Therefore, in this bi-directional enhance mode GaN HEMT single gate
device as shown in FIG. 5, it is designed to have asymmetric
blocking because the distance from the gate to respective
source/drain regions are different, i.e.,
L.sub.GD1.noteq.L.sub.GD2. Furthermore, the field plates 135-FP1
and 135-FP2 on the gate 135 are also formed to be asymmetric to
achieve asymmetric blocking.
[0026] FIGS. 6A to 6G are a series of cross sectional views to
illustrate the processing steps for manufacturing a bi-directional
asymmetrical central MIS gate blocking GaN switch of this
invention. In FIG. 6A, the process flow starts with a substrate
105. The substrate 105 may be silicon (Si), silicon carbide (SiC),
Gallium nitride (GaN), or a sapphire substrate. In FIG. 6B, an
epitaxial layer 110 as a buffer layer is grown. The buffer layer
may be grown by different methods and may be the combinations of
layers including GaN, AlN, AlGaN, etc. The buffer layer 110 grown
as epitaxial layer may have a thickness ranging between 0.25 .mu.m
to 7 .mu.m depending on the voltage for specific applications. The
buffer layer 110 may be doped with Fe, C or it may also be
unintentionally doped. In FIG. 6C, a channel layer composed of GaN
epitaxial layer 115 is grown. The channel layer has a layer
thickness ranging from 100 to 400 nanometers (nm). In FIG. 6D, a
barrier epitaxial 120 is grown. The barrier epitaxial layer 120 may
be formed with Al.sub.xGa.sub.1-xN (for example, 0.18<x<28)
that has a thickness ranging between 10 to 30 nm, or may be formed
with AlN with a thickness ranging between 2 to 10 nm. The barrier
epitaxial layer 120 is composed of a material that has a bandgap
larger than GaN. In FIG. 6E, a cap/passivation layer 125 is
deposited. The cap or passivation layer may be a layer of high
resistance such as a layer of GaN/SiN/SiO2 and is formed as a thin
layer ranging between 2 to 200 nanometers. The cap/passivation
layer 125 may be formed as a layer of insulator to function as a
passivation or a gate dielectric layer composed of SiN or SiO2. In
FIG. 6F, the source/drain ohmic contacts are formed by applying a
standard process to form the metal contacts 130-1 and 130-2
composed of metals of Ti, Al, Ni, or Au. In FIG. 6G, processes are
carried out to form the gate/field plate 135 and the source/drain
field plates 140-1 and 140-2. The configuration of the gate 135 and
the source/drain field plates 140-1 and 140-2 depends on the device
voltage and the epitaxial design of the asymmetrical blocking
switches as discussed above.
[0027] FIGS. 7A to 7H are a series of cross sectional views to
illustrate the processing steps for manufacturing a bi-directional
asymmetrical central P-type gate blocking GaN switch with an
asymmetric central gate of this invention. In FIG. 7A, the process
flow starts with a substrate 105. The substrate 105 may be silicon
(Si), silicon carbide (SiC), Gallium nitride (GaN), or a sapphire
substrate. In FIG. 7B, an epitaxial layer 110 as a buffer layer is
grown. The buffer layer may be grown by different methods and may
be the combinations of layers including GaN, AlN, AlGaN, etc. The
buffer layer 110 grown as epitaxial layer may have a thickness
ranging between 0.25 .mu.m to 7 .mu.m depending on the voltage for
specific applications. The buffer layer 110 may be doped with Fe, C
or it may also be unintentionally doped. In FIG. 7C, a channel
layer composed of GaN epitaxial layer 115 is grown. The channel
layer has a layer thickness ranging from 100 to 400 nanometers
(nm). In FIG. 7D, a barrier epitaxial 120 is grown. The barrier
epitaxial layer 120 may be formed with Al.sub.xGa.sub.1-xN (for
example, 0.18<x<28) that has a thickness ranging between 10
to 30 nm, or may be formed with AlN with a thickness ranging
between 2 to 10 nm. The barrier epitaxial layer 120 is composed of
a material that has a bandgap larger than GaN. In FIG. 7E, a P-type
epitaxial layer 150 is deposited. The P-type epitaxial layer may be
a similar material such as a GaN or AlGaN and doped with P-type
dopant such as Mg and is formed as a thin layer ranging between 2
to 200 nanometers. In FIG. 7F, an etch process is carried out to
pattern the P-epitaxial layer 150 for defining a gate area. In FIG.
7G, the source/drain ohmic contacts are formed by applying a
standard process to form the metal contacts 130-1 and 130-2
composed of metals of Ti, Al, Ni, or Au. In FIG. 7H, a
cap/passivation layer 125 is deposited. The cap or passivation
layer may be a layer of high resistance such as a layer of
GaN/SiN/SiO2 and is formed as a thin layer ranging between 2 to 200
nanometers. The cap/passivation layer 125 may be formed as a layer
of insulator to function as a passivation or a gate dielectric
layer composed of SiN or SiO2. Then processes are carried out to
form the gate/field plate 135 and the source/drain field plates
140-1 and 140-2. The configuration of the gate 135 and the
source/drain field plates 140-1 and 140-2 depends on the device
voltage and the epitaxial design of the asymmetrical blocking
switches as discussed above.
[0028] FIGS. 8A to 8I are a series of cross sectional views to
illustrate the processing steps for manufacturing a bi-directional
asymmetrical central trench MIS-gate blocking GaN switch of this
invention. In FIG. 8A, the process flow starts with a substrate
105. The substrate 105 may be silicon (Si), silicon carbide (SiC),
Gallium nitride (GaN), or a sapphire substrate. In FIG. 8B, an
epitaxial layer 110 as a buffer layer is grown. The buffer layer
may be grown by different methods and may be the combinations of
layers including GaN, AlN, AlGaN, etc. The buffer layer 110 grown
as epitaxial layer may have a thickness ranging between 0.25 .mu.m
to 7 .mu.m depending on the voltage for specific applications. The
buffer layer 110 may be doped with Fe, C or it may also be
unintentionally doped. In FIG. 8C, a channel layer composed of GaN
epitaxial layer 115 is grown. The channel layer has a layer
thickness ranging from 100 to 400 nanometers (nm). In FIG. 8D, a
barrier epitaxial 120 is grown. The barrier epitaxial layer 120 may
be formed with Al.sub.xGa.sub.1-xN (for example, 0.18<x<28)
that has a thickness ranging between 10 to 30 nm, or may be formed
with AlN with a thickness ranging between 2 to 10 nm. The barrier
epitaxial layer 120 is composed of a material that has a bandgap
larger than GaN. In FIG. 8E, a cap/passivation layer 125 is
deposited. The cap/passivation layer may be a layer of high
resistance such as a layer of GaN/SiN/SiO2 and is formed as a thin
layer ranging between 2 to 200 nanometers. The cap/passivation
layer 125 may be formed as a layer of insulator to function as a
passivation or a gate dielectric layer composed of SiN or SiO2. In
FIG. 8F, the source/drain ohmic contacts are formed by applying a
standard process to form the metal contacts 130-1 and 130-2
composed of metals of Ti, Al, Ni, or Au. In FIG. 8G, an etch
process is performed to etch through the passivation layer 125 and
the bather layer 120 to open a gate trench 132 into the barrier
layer 120 to reduce the electrons in the two-dimension electron gas
(2 DEG). In FIG. 8H, a gate dielectric layer 128 is deposited. The
gate dielectric layer may compose of Si3N4, SiO2, or other material
with high resistivity. In FIG. 8I, processes are carried out to
form the trench gate/field plate 135' and the source/drain field
plates 140-1 and 140-2. The configuration of the gate 135' and the
source/drain field plates 140-1 and 140-2 depends on the device
voltage and the epitaxial design of the asymmetrical blocking
switches as discussed above.
[0029] FIGS. 9A to 9G are a series of cross sectional view to
illustrate the processing steps for manufacturing a bi-directional
asymmetrical dual MIS-gate blocking GaN switch of this invention.
In FIG. 9A, the process flow starts with a substrate 105. The
substrate 105 may be silicon (Si), silicon carbide (SiC), Gallium
nitride (GaN), or a sapphire substrate. In FIG. 9B, an epitaxial
layer 110 as a buffer layer is grown. The buffer layer may be grown
by different methods and may be the combinations of layers
including GaN, AlN, AlGaN, etc. The buffer layer 110 grown as
epitaxial layer may have a thickness ranging between 0.25 .mu.m to
7 .mu.m depending on the voltage for specific applications. The
buffer layer 110 may be doped with Fe, C or it may also be
unintentionally doped. In FIG. 9C, a channel layer composed of GaN
epitaxial layer 115 is grown. The channel layer has a layer
thickness ranging from 100 to 400 nanometers (nm). In FIG. 9D, a
barrier epitaxial 120 is grown. The barrier epitaxial layer 120 may
be formed with Al.sub.xGa.sub.1-xN (for example, 0.18<x<28)
that has a thickness ranging between 10 to 30 nm, or may be formed
with AlN with a thickness ranging between 2 to 10 nm. The barrier
epitaxial layer 120 is composed of a material that has a bandgap
larger than GaN. In FIG. 9E, a cap/passivation layer 125 is
deposited. The cap or passivation layer may be a layer of high
resistance such as a layer of GaN/SiN/SiO2 and is formed as a thin
layer ranging between 2 to 200 nanometers. The cap/passivation
layer 125 may be formed as a layer of insulator to function as a
passivation or a gate dielectric layer composed of SiN or SiO2. In
FIG. 9F, the source/drain ohmic contacts are formed by applying a
standard process to form the metal contacts 130-1 and 130-2
composed of metals of Ti, Al, Ni, or Au. In FIG. 9G, processes are
carried out to form the dual gates/field plates 135-1, 135-2 and
the source/drain field plates 140-1 and 140-2. The configuration of
the dual gates 135-1 and 135-2 and also the lengths of the
source/drain field plates 140-1 and 140-2 depend on the device
voltage and the epitaxial design of the asymmetrical blocking
switches as discussed above.
[0030] FIGS. 10A to 10H are a series of cross sectional views to
illustrate the processing steps for manufacturing a bi-directional
asymmetrical dual P-type gate blocking GaN switch with an
asymmetric central gate of this invention. In FIG. 10A, the process
flow starts with a substrate 105. The substrate 105 may be silicon
(Si), silicon carbide (SiC), Gallium nitride (GaN), or a sapphire
substrate. In FIG. 10B, an epitaxial layer 110 as a buffer layer is
grown. The buffer layer may be grown by different methods and may
be the combinations of layers including GaN, AlN, AlGaN, etc. The
buffer layer 110 grown as epitaxial layer may have a thickness
ranging between 0.25 .mu.m to 7 .mu.m depending on the voltage for
specific applications. The buffer layer 110 may be doped with Fe, C
or it may also be unintentionally doped. In FIG. 10C, a channel
layer composed of GaN epitaxial layer 115 is grown. The channel
layer has a layer thickness ranging from 100 to 400 nanometers
(nm). In FIG. 10D, a barrier epitaxial 120 is grown. The barrier
epitaxial layer 120 may be formed with Al.sub.xGa.sub.1-xN (for
example, 0.18<x<28) that has a thickness ranging between 10
to 30 nm, or may be formed with AlN with a thickness ranging
between 2 to 10 nm. The barrier epitaxial layer 120 is composed of
a material that has a bandgap larger than GaN. In FIG. 10E, a
P-type epitaxial layer 150 is deposited. The P-type epitaxial layer
may be a layer doped with AlGaN and is formed as a thin layer
ranging between 2 to 200 nanometers. In FIG. 10F, etch process is
carried out to pattern the P-epitaxial layer 150 for defining the
areas 150-1 and 150-2 for dual gates. In FIG. 10G, the source/drain
ohmic contacts are formed by applying a standard process to form
the metal contacts 130-1 and 130-2 composed of metals of Ti, Al,
Ni, or Au. In FIG. 10H, to cap/passivation layer 125 is deposited.
The cap or passivation layer may be a layer of high resistance such
as a layer of GaN/SiN/SiO2 and is formed as a thin layer ranging
between 2 to 200 nanometers. The cap/passivation layer 125 may he
formed as a layer of insulator to function as a passivation or a
gate dielectric layer composed of SiN or SiO2. Then processes are
carried out to from the dual gates/field plates 135-1 and 135-2 and
the source/drain field plates 140-1 and 140-2. The configuration of
the dual gates 135-1, 135-2 and the source/drain field plates 140-1
and 140-2 depends on the device voltage and the epitaxial design of
the asymmetrical blocking switches as discussed above.
[0031] FIGS. 11A to 11I are a series of cross sectional views to
illustrate the processing steps for manufacturing a bi-directional
asymmetrical dual trench MIS-gate blocking GaN switch of this
invention. In FIG. 11A, the process flow starts with a substrate
105. The substrate 105 may tie silicon (Si), silicon carbide (SiC).
Gallium nitride i/GaN), or a sapphire substrate. In FIG. 11B, an
epitaxial layer 110 as a buffer layer is grown. The buffer layer
may be grown by different methods and may be the combinations of
layers including GaN, AlN, AlGaN, etc, The buffer layer 110 grown
as epitaxial layer may have a thickness ranging between 0.25 .mu.m
to 7 .mu.m depending on the voltage for specific applications. The
buffer liver 110 may be doped with Fe, C or it may also be
unintentionally doped. In FIG. 11C, a channel layer composed of GaN
epitaxial layer 115 is grown. The channel layer has a layer
thickness ranging from 100 to 400 nanometers (nm). In FIG. 8D, a
barrier epitaxial 120 is grown. The barrier epitaxial layer 120 may
be formed with Al.sub.xGa.sub.1-xN (for example, 0.18<x<28)
that has a thickness ranging between 10 to 30 nm, or may be formed
with AlN with a thickness ranging between 2 to 10 nm. The barrier
epitaxial layer 120 is composed of a material that has a bandgap
larger than GaN. In FIG. 11E, a cap/passivation layer 125 is
deposited. The cap or passivation layer may be a layer of high
resistance such as a layer of GaN/SiN/SiO2 and is formed as a thin
layer ranging between 2 to 200 nanometers. The cap/passivation
layer 125 may be formed as a layer of insulator to function as a
passivation or a gate dielectric layer composed of SiN or SiO2. In
FIG. 11F, the source/drain ohmic contacts are formed by applying, a
standard process to for the metal contacts 130-1 and 130-2 composed
of metals of Ti, Al, Ni, or Au. In FIG. 11G, an etch process is
performed to etch through the passivation layer 125 and the barrier
layer 120 to open dual gate trenches 132-1 and 132-2 into the
barrier layer 120 to reduce the electrons in 2 DEG. In FIG. 11H, a
gate dielectric layer 128 is deposited into the dual gate trenches
132-1 and 132-2. The gate dielectric layer may compose of Si3N4,
SiO2, or other material with high resistivity. In FIG. 11I,
processes are carried out to form the dual trench gates/field
plates 135-1' and 135-2' and the source/drain field plates 140-1
and 140-2. The configuration of the dual trench gates 135-1' and
135-2', and the source/drain field plates 140-1 and 140-2 depends
on the device voltage and the epitaxial design of the asymmetrical
blocking switches as discussed above.
[0032] Although the present invention has been described in terms
of the presently preferred embodiment, it is to be understood that
such disclosure is not to be interpreted as limiting. Various
alterations and modifications will no doubt become apparent to
those skilled in the art after reading the above disclosure.
Accordingly, it is intended that the appended claims be interpreted
as covering all alterations and modifications as fall within the
true spirit and scope of the invention.
* * * * *