U.S. patent application number 15/442274 was filed with the patent office on 2018-03-15 for semiconductor device.
This patent application is currently assigned to Toshiba Memory Corporation. The applicant listed for this patent is Toshiba Memory Corporation. Invention is credited to Masumi SAITOH, Kiwamu SAKUMA.
Application Number | 20180076208 15/442274 |
Document ID | / |
Family ID | 61560268 |
Filed Date | 2018-03-15 |
United States Patent
Application |
20180076208 |
Kind Code |
A1 |
SAKUMA; Kiwamu ; et
al. |
March 15, 2018 |
SEMICONDUCTOR DEVICE
Abstract
The semiconductor device according to the embodiments comprises:
a plurality of first conductive layers arranged in a first
direction above a substrate, the first direction intersecting an
upper surface of the substrate; a semiconductor layer that faces a
side surface of the plurality of first conductive layers and
extends in the first direction as a longitudinal direction thereof;
a wiring portion configured by causing end portions of the first
conductive layers to be at different positions, respectively; and a
transistor located above the wiring portion. The transistor
comprises: a channel portion arranged at a same height as a second
conductive layer, the second conductive layer being one of the
plurality of the first conductive layers; a gate insulating film
arranged on an upper surface of the channel portion; and a gate
electrode layer arranged on an upper surface of the gate insulating
film.
Inventors: |
SAKUMA; Kiwamu; (Yokkaichi,
JP) ; SAITOH; Masumi; (Yokkaichi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Toshiba Memory Corporation |
Minato-ku |
|
JP |
|
|
Assignee: |
Toshiba Memory Corporation
Minato-ku
JP
|
Family ID: |
61560268 |
Appl. No.: |
15/442274 |
Filed: |
February 24, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/4975 20130101;
H01L 27/11578 20130101; H01L 29/1033 20130101; H01L 27/11524
20130101; H01L 29/792 20130101; H01L 27/11575 20130101; H01L
27/11565 20130101; H01L 29/788 20130101; H01L 27/11573 20130101;
H01L 27/11551 20130101; H01L 27/11582 20130101; H01L 27/1157
20130101 |
International
Class: |
H01L 27/11524 20060101
H01L027/11524; H01L 29/788 20060101 H01L029/788; H01L 29/792
20060101 H01L029/792; H01L 29/10 20060101 H01L029/10; H01L 29/49
20060101 H01L029/49; H01L 27/1157 20060101 H01L027/1157; H01L
27/11551 20060101 H01L027/11551; H01L 27/11578 20060101
H01L027/11578 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 12, 2016 |
JP |
2016-177846 |
Claims
1: A semiconductor device, comprising: a plurality of first
conductive layers arranged in a first direction above a substrate,
the first direction intersecting an upper surface of the substrate;
a semiconductor layer that faces a side surface of the plurality of
first conductive layers and extends in the first direction as a
longitudinal direction thereof; a wiring portion configured by
causing end portions of the first conductive layers to be at
different positions, respectively; and a transistor located above
the wiring portion, the transistor comprising: a channel portion
arranged at a same height as a second conductive layer, the second
conductive layer being one of the plurality of the first conductive
layers; a gate insulating film arranged on an upper surface of the
channel portion; and a gate electrode layer arranged on an upper
surface of the gate insulating film.
2: The semiconductor device according to claim 1, wherein the
channel portion has a thickness along the first direction that is
approximately the same as that of the second conductive layer.
3: The semiconductor device according to claim 1, wherein the
second conductive layer is arranged at the highest position, when
seen from the substrate, among the plurality of the first
conductive layers.
4: The semiconductor device according to claim 1, wherein the gate
electrode layer and the second conductive layer include silicide of
same metal.
5: The semiconductor device according to claim 1, wherein the
channel portion is arranged so as to have a longitudinal direction
thereof along a longitudinal direction of a stepwise portion of the
wiring portion.
6: The semiconductor device according to claim 1, wherein the
channel portion has a thickness along the first direction that is
approximately the same as that of the second conductive layer, and
the second conductive layer is a arranged at the highest position,
when seen from the substrate, among the plurality of the first
conductive layers.
7: The semiconductor device according to claim 6, wherein the gate
electrode layer and the second conductive layer include silicide of
same metal.
8: The semiconductor device according to claim 6, wherein the
channel portion is arranged so as to have a longitudinal direction
thereof along a longitudinal direction of a stepwise portion of the
wiring portion.
9: A semiconductor device, comprising: a plurality of first
conductive layers arranged in a first direction above a substrate,
the first direction intersecting an upper surface of the substrate;
a semiconductor layer that faces a side surface of the plurality of
first conductive layers and extends in the first direction as a
longitudinal direction thereof; a wiring portion configured by
causing end portions of the first conductive layers to be at
different positions, respectively; and a transistor located above
the wiring portion, the transistor comprises: third and fourth
conductive layers arranged at a same height as a second conductive
layer, the second conductive layer being one of the plurality of
the first conductive layers; a channel portion provided between the
third and fourth conductive layers and connected therebetween, the
channel portion including a portion provided at a position lower
than the third and fourth conductive layers seen from the
substrate; a gate insulating film arranged at least on an upper
surface of the channel portion; and a gate electrode layer arranged
at least on an upper surface of the gate insulating film.
10: The semiconductor device according to claim 9, wherein the
channel portion has a thickness along the first direction that is
approximately the same as that of the second conductive layer.
11: The semiconductor device according to claim 9, wherein the
second conductive layer is arranged at the highest position, when
seen from the substrate, among the plurality of the first
conductive layers.
12: The semiconductor device according to claim 9, wherein the gate
electrode layer and the second conductive layer include silicide of
same metal.
13: The semiconductor device according to claim 9, wherein the
channel portion is arranged so as to have a longitudinal direction
thereof along a longitudinal direction of a stepwise portion of the
wiring portion.
14: The semiconductor device according to claim 3, wherein the
first conductive layers except the second conductive layer are
composed of a metallic material.
15: The semiconductor device according to claim 14, wherein the
second conductive layer is composed of a semiconductor
material.
16: The semiconductor device according to claim 14, wherein an
insulating layer is formed to surround the periphery of the first
conductive layers composed of the metallic material.
17: The semiconductor device according to claim 11, wherein the
first conductive layers except the second conductive layer are
composed of a metallic material.
18: The semiconductor device according to claim 17, wherein The
second conductive layer is composed of a semiconductor
material.
19: The semiconductor device according to claim 17, wherein an
insulating layer is formed to surround the periphery of the first
conductive layers composed of the metallic material.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is based on and claims the benefit of
priority from prior Japanese Patent Application No. 2016-177846,
filed on Sep. 12, 2016, the entire contents of which are
incorporated herein by reference.
FIELD
[0002] Embodiments described hereinbelow relate to a semiconductor
device.
BACKGROUND
[0003] Flash memory is known as one of semiconductor memory
devices. Specifically, NAND type flash memory is widely used
because of its low cost large capacity.
[0004] In addition, many techniques have been proposed for further
increasing the capacity of NAND type flash memory. One of the
techniques includes a structure where memory cells are arranged
three-dimensionally. In a semiconductor memory device of such a
three-dimensional type, memory cells are arranged along a certain
direction. Conductive layers extend in a direction that is parallel
to a substrate, from the memory cells arranged along the certain
direction, respectively, and are laminated in a direction
perpendicular to the substrate.
[0005] In such a semiconductor memory device of a three-dimensional
type, increasing the number of the lamination of the memory cells
and the conductive layers leads to increase in number of
transistors for connecting the memory cells and the external
circuit. This may cause increase in the occupation area of the
transistors. Accordingly, it is requested that the occupation area
of the transistors be reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a perspective diagram that schematically
illustrates an example of the structure of the nonvolatile
semiconductor memory device 100 according to the first
embodiment.
[0007] FIG. 2 is a perspective diagram showing a structure of the
memory cell array MR of the first embodiment.
[0008] FIG. 3 is an equivalent circuit diagram of one NAND cell
unit NU.
[0009] FIG. 4 is a perspective sectional view of one memory cell
MC.
[0010] FIG. 5 a plan view showing a part of the memory cell array
MR.
[0011] FIG. 6 is a sectional view illustrating a structure of the
memory cell array MR of the first embodiment and the stepwise
portion CR.
[0012] FIG. 7 is a plan view that illustrates arrangement of the
transistors Tr.
[0013] FIG. 8A is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0014] FIG. 8B is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0015] FIG. 8C is process chart that explains a method of
manufacturing the semiconductor memory device 100 of the first
embodiment.
[0016] FIG. 8D is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0017] FIG. 8E is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0018] FIG. 8F is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0019] FIG. 8G is process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0020] FIG. 8H is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0021] FIG. 8I is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
first embodiment.
[0022] FIG. 9 is a sectional view of the memory cell array MR and a
stepwise wiring portion CR of the semiconductor device according to
the second embodiment.
[0023] FIG. 10 is an enlarged perspective diagram of the memory
cell MC of the semiconductor device according to the second
embodiment.
[0024] FIG. 11A is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
second embodiment.
[0025] FIG. 11B is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
second embodiment.
[0026] FIG. 11C is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
second embodiment.
[0027] FIG. 11D is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
second embodiment.
[0028] FIG. 12 is a sectional view of the stepwise wiring portion
CR of the semiconductor device of the third embodiment.
[0029] FIG. 13 is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
third embodiment.
[0030] FIG. 14 is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
third embodiment.
[0031] FIG. 15 is a process chart that explains a method of
manufacturing the semiconductor memory device 100 according to the
third embodiment.
DETAILED DESCRIPTION
[0032] The semiconductor device according to the embodiments
described hereinbelow comprises: a plurality of first conductive
layers arranged in a first direction above a substrate, the first
direction intersecting an upper surface of the substrate; a
semiconductor layer that faces a side surface of the plurality of
first conductive layers and extends in the first direction as a
longitudinal direction thereof; a wiring portion configured by
causing end portions of the first conductive layers to be at
different positions, respectively; and a transistor located above
the wiring portion. The transistor comprises: a channel portion
arranged at a same height as a second conductive layer, the second
conductive layer being one of the plurality of the first conductive
layers; agate insulating film arranged on an upper surface of the
channel portion; and a gate electrode layer arranged on an upper
surface of the gate insulating film.
[0033] The semiconductor memory device according to the embodiments
will be described hereinafter with reference to the accompanying
drawings. Here, these embodiments are only examples, and do not
intend to limit the scope of the present invention. The respective
drawings of the semiconductor memory devices used in the following
embodiments are schematically illustrated, and the thickness, the
width, the ratio, and a similar parameter of the layer are
different from actual parameters.
[0034] The following embodiments relate to a nonvolatile
semiconductor memory device in a structure where a plurality of
metal-oxide-nitride-oxide-semiconductor (MONOS) type memory cells
(transistors) are disposed in a height direction. The MONOS type
memory cell includes: a semiconductor film disposed in a columnar
shape perpendicular to the substrate as a channel, and a gate
electrode film disposed on the side surface of the semiconductor
film via an electric charge accumulating layer. However, these
embodiments are applicable to a semiconductor memory device having
another type, for example, a
semiconductor-oxide-nitride-oxide-semiconductor type (SONGS) memory
cell. In addition, these embodiments are applicable to a
floating-gate type memory cell.
First Embodiment
[0035] FIG. 1 is a perspective diagram that schematically
illustrates an example of the structure of a nonvolatile
semiconductor memory device 100 according to the first embodiment.
The nonvolatile semiconductor memory device 100 includes a memory
cell array MR, word lines WL, source side select gate lines SGS,
drain side select gate lines SGD, bit lines BL, a source line SL, a
stepwise wiring portion CR, and a peripheral transistor Tr. Note
that FIG. 1 schematically illustrates one memory finger MF included
in the memory cell array MR.
[0036] The memory cell array MR includes a memory string MS, a
drain a side select transistor S1, and a source side select
transistor S2. The memory string MS includes a plurality of memory
cells MC (memory transistors) that are series-connected on a
substrate SB. The drain side select transistor S1 and the source
side select transistor S2 are connected to the both ends of the
memory string MS, respectively. The memory string MS, and the drain
side select transistor S1 and the source side select transistor S2
connected to the both ends thereof are referred to as "a NAND cell
unit NU" hereinbelow.
[0037] As will be described below, the memory cell MC has a
structure in which a control gate electrode (a word line WL) is
provided on the side surface of a columnar semiconductor film that
serves as a channel, via a memory layer including a charge
accumulation layer. The drain side select transistor S1 and the
source side select transistor S2 each has a structure in which a
select gate electrode (the drain side select gate line SGD, the
source side select gate line SGS) is provided on the side of the
columnar semiconductor film, via a memory layer including a charge
accumulation layer. FIG. 1 exemplifies a case in which four memory
cells MC are provided in one memory string MS, for simplification
of the drawings. However, it goes without saying that the number of
the memory cells MC in one memory string MS is not limited to
four.
[0038] As shown in FIG. 1, the word lines WL are connected in
common to a plurality of the memory strings MS that are adjacent in
the X direction (wordline direction) and in the Y direction
(bitline direction) in one memory finger MF. In addition, the
source side select gate line SGS is connected in common to a
plurality of the source side select gate transistors S2 that are
adjacent in the X direction and in the Y direction in one memory
finger MF. Similarly, the drain side select gate line SGD is
connected in common to a plurality of the drain side select gate
transistors S1 that are adjacent in the X direction and in the Y
direction in one memory finger MF. It is noted that the source side
select gate gate line SGS and the drain side select gate line SGD
may be collectively and simply referred to as "a select gate line".
In addition, the drain side select transistor S1 and the source
side select transistor S2 may be collectively and simply referred
to as "a select transistor".
[0039] Among the memory cells MC in the memory string MS, one or
more memory cells MC that are adjacent to the source side select
gate line SGS and the drain side select gate line SGD may be dealt
as dummy cells which are not used for storing data. The dummy cells
may be two or more. Instead, the dummy cells may be omitted.
[0040] The bit lines BL are arranged to extend in the Y direction
(bitline direction) that intersects the X direction (wordline
direction). The Y direction is a longitudinal direction of the bit
lines BL. The bit lines BL are arranged in the X direction at a
certain pitch.
[0041] The bit line BL is connected to the plurality of memory
string MS via the drain side select transistors S1. The source line
SL is arranged having its longitudinal direction along the Y
direction. The source line SL is connected to the substrate SB via
a source line contact LI. This allows the source line SL to be
connected to the memory string MS via the source line contact LI,
the substrate SB and the source side select transistor S2.
[0042] Although illustration thereof is omitted, as circuits to
control the voltages of the word line WL, the source line SL, the
drain side select gate line SGD, the source side select gate line
SGS, various types of control circuits are provided. In addition, a
sense amplifier circuit is provided as a circuit to amplify a
signal (a voltage) read to the bit line BL from a selected memory
cell.
[0043] At least some of the above-mentioned various control
circuits may be connected to the word line WL, the bit line BL, and
the select gate lines SGD and SGS via the peripheral transistor Tr
shown in FIG. 1. The peripheral transistor Tr is arranged at an
upper side (Z direction) of the stepwise wiring portion CR. The
peripheral transistor Tr is a thin-film transistor (TFT) having a
structure in which a channel portion CA, a gate insulating film GI,
and a gate electrode layer GE are sequentially stacked from the
lower side in the Z direction (a side that is closed to the
substrate SB).
[0044] The channel portion CA is composed of a semiconductor
material such as polysilicon, for example, and the gate insulating
film GI is formed of an insulating film such as a silicon oxide
film, for example. In addition, the gate electrode layer GE is
composed of a conductive film such as titanium silicide, for
example. Note that, in FIG. 1, the gate electrode layer GE is
provided independently for each of the plurality of peripheral
transistors Tr. This is merely an example. Regarding to a plurality
of the peripheral transistors Tr which can be turned on at the same
time, these transistors may be connected to the same gate electrode
layer GE.
[0045] The above-mentioned channel portion CA is composed of a
material which are the same as that of the the drain side select
gate line SGD. Its thickness in the Z direction is made almost the
same as the thickness of the drain side select gate line SGD in the
Z direction. In addition, the position in the Z direction of the
channel portion CA is generally the same as that of the drain side
select gate line SGD.
[0046] The stepwise wiring portion CR is a wiring portion to
connect the word lines WL, and the select gate lines SGD, SGS to
contacts. The word lines WL, and the select gate lines SGS, SGD
have a structure in which they are processed in a stepwise manner,
such that the word lines WL, and the select gate lines SGS, SGD may
be connected to the contacts independently at the upper surfaces
thereof.
[0047] The upper surfaces of the ends of these wirings processed in
a step-like manner serve as a contact connecting area. Although
illustration is omitted in FIG. 1, contact plugs extend from the
upper surface of the contact connecting area. These contact plugs
are connected to the above-mentioned peripheral transistors Tr, via
upper layer wirings and other contact plugs which are not shown in
the drawings.
[0048] Although the stepwise wiring portion CR is illustrated only
at the X direction side of the memory cell array MR in FIG. 1, the
stepped wiring region CR may be formed to surround the the entire
perimeter of the memory cell array MR including the Y direction
side of the memory cell array MR.
[0049] Next, the derailed structure of the memory cell array MR
will be described with reference to FIG. 2 to FIG. 4. FIG. 2 is a
perspective diagram illustrating a part of the structure of the
memory cell array MR. FIG. 3 is an equivalent circuit diagram of
one NAND cell unit NU. FIG. 4 is a perspective sectional view of
one memory cell MC.
[0050] As shown in FIG. 2, the memory cell array MR has a structure
in which interlayer insulating layers 21 and conductive layers 22
are alternately stacked on the semiconductor substrate SB, along
the Z direction which is perpendicular to the upper surface of the
substrate SB. These conductive layers 22 function as control gates
of the memory cells MC (the word lines WL), the source side select
gate line SGS, and the drain side select gate lines SGD. The
interlayer insulating layers 21 are arranged between these
conductive layers 22 to electrically insulate the conductive layers
22. The conductive layers 22 may be composed of the polysilicon
that is doped with p-type impurities or n-type impurities
(phosphorus or the like). Instead of polysilicon, a metallic
material such as tungsten (W), tungsten nitride (WN), tungsten
silicide (WSix), tantalum (Ta), tantalum nitride (TaN), tantalum
silicide (TaSix), palladium silicide (PdSix), erbium silicide
(ErSix), yttrium silicide (YSix), platinum silicide (PtSix),
hafnium silicide (HfSix), nickel silicide (NiSix), cobalt silicide
(CoSix), titanium silicide (TiSix), vanadium silicide (VSix),
chromic silicide (CrSix), manganese silicide (MnSix), iron silicide
(FeSix), ruthenium (Ru), molybdenum (Mo), titanium (Ti), titanium
nitride (TiN), vanadium (V), chromium (Cr) manganese (Mn), iron
(Fe), cobalt (Co), nickel (Ni), gold (Au) silver (Ag) or copper
(Cu), or the compound of these materials may be used.
[0051] In addition, semiconductor layers 23 are arranged to
penetrate the stacked body of the interlayer insulating layers 21
and the conductive layers 22. The semiconductor layers 23 has its
longitudinal direction along the stacking direction (the Z
direction in FIG. 2), and are arranged at certain pitches in the XY
plane. Formed between the semiconductor layer 23 and the stacked
body of the conductive layers 22 and the interlayer insulating
layers 21 are a tunnel insulating layer 103, a memory layer 104
including a charge accumulation layer, and a block insulating layer
105. The memory layer 104 may be formed of a laminated structure of
a charge accumulation layer such as a silicon nitride film and an
oxide film such as silicon oxide film. Instead of using a silicon
nitride film or the like in the memory layer 104, a floating gate
structure using a conductive film may be employed.
[0052] A threshold voltage of the memory cell MC changes according
to the amount of accumulation of charges to the charge accumulation
layer. The memory cell MC holds data corresponding to this
threshold voltage.
[0053] The semiconductor layer 23 functions as a channel region (a
body) of the memory cells MC included in the NAND cell unit NU and
a channel region of the select transistor S1 and S2. These
semiconductor layers 23 are connected to the bit lines BL via
contacts Cb. The bit lines BL has its longitudinal direction along
the Y direction, and are arranged at a certain pitch in the X
direction.
[0054] The lower end of the semiconductor layer 23 is electrically
connected to the semiconductor substrate SB. The lower end of the
semiconductor layer 23 is electrically connected to the source line
SL via this substrate SB and a source contact LI described
below.
[0055] Note that the stacked body of the interlayer insulating
layers 21 and the conductive layers 22 in the memory cell array MR
is divided into the above-mentioned memory fingers MF. A trench Tb
is formed at the border of the division, and an interlayer
insulating layer not illustrated is embedded in this trench Tb. In
addition, the above-described source contact LI is formed to
penetrate the interlayer insulating layer not illustrated. The
source contact LI is connected to the semiconductor substrate SB at
its lower end, and is connected to the source line SL at its upper
end.
[0056] FIG. 3 is an equivalent circuit diagram of one NAND cell
unit NU. In this memory cell array MR, one NAND cell unit NU
includes a memory string MS, a drain side select transistor S1, and
a a source side select transistor S2. The memory string MS includes
a plurality of memory cells MC. The drain side select transistor S1
is connected between the upper end of the memory string MS and the
the bit line BL. The source side select transistor S2 is connected
between the lower end of the memory string MS and the source line
SL. As described above, some of the memory cells among memory cells
MC that are close to the select transistors S1 and S2 may be used
as dummy cells.
[0057] An example of a specific structure of one memory cell MC
will be shown in FIG. 4. The columnar semiconductor layer 23
includes an oxide film core 101, and a columnar semiconductor 102
that surrounds the periphery of the oxide film core 101. The oxide
film core 101 may be formed of silicon oxide (SiO.sub.2), for
example. The columnar semiconductor 102 may be formed of silicon
(Si), silicon germanium (SiGe), silicon carbide (SiC), germanium
(Ge), or carbon (C). The columnar semiconductor 102 may be formed
of a single layer, or two layers.
[0058] Formed around the columnar semiconductor 102 to surround the
columnar semiconductor 102 are a tunnel insulating layer 103, a
memory layer 104 including a charge accumulation layer, and a block
insulating layer 105. The tunnel insulating layer 103 is formed of
a silicon oxide film (SiO.sub.x), for example, and serves as a
tunnel insulating layer of the memory cell MC. The memory layer 104
includes a charge accumulation layer including a silicon nitride
film (Si.sub.3N.sub.4), and has a function of trapping electrons
injected from the columnar semiconductor 102 via the tunnel
insulating layer 103 by a write operation. The block insulating
layer 105 may be formed of a silicon oxide film, for example,
[0059] The tunnel insulating layer 103, the memory layer 104 and
the block insulating layer 105 gate totally referred to as "a gate
insulation layer GL". Although the gate insulation layer GL in FIG.
4 includes three layers, various kinds of structures that are
different in the number of layers, the order of the layers, the
material of the layers, and the like, may be considered. The gate
insulating film GL necessarily includes a charge accumulation layer
described above.
[0060] Note that, as the material of the tunnel insulating layer
103 and the block insulating layer 105, it is possible to use, in
addition to a silicon oxide film (SiO.sub.x) Y.sub.2O.sub.3,
La.sub.2O.sub.3, Gd.sub.2O.sub.3, Ce.sub.2O.sub.3, CeO.sub.2,
Ta.sub.2O.sub.5, HfO.sub.2, ZrO.sub.2, TiO.sub.2, HfSiO, HfAlO,
ZrSiO, ZrAlO, AlSiO, and the like.
[0061] Although in this example, the tunnel insulating layer 103,
the memory layer 104 and the block insulating layer 105 are
illustrated such that they are formed at the entire surface of the
columnar semiconductor 102, the present invention is not limited to
this example. It is possible that they are formed only on the side
surface of the word lines WL.
[0062] In addition, at the periphery of the columnar semiconductor
102, the interlayer insulating layers 21 and the conductive layers
22 described above are alternately laminated to surround the
columnar semiconductor layer 23, via the tunnel insulating layer
103, the memory layer 104 and the block insulating layer 105
[0063] As shown in FIG. 5, which is a plan view of a part of the
memory cell array MR, the semiconductor layers 23 (the columnar
semiconductors 102) are arranged to be aligned in the oblique
direction to the X direction (wordline direction) and the Y
direction (bitline direction) thereby increasing the concentration
of the semiconductor layers 23 arranged therein, and increasing the
concentration of the memory cells MC arranged therein. One bit line
BL that extends in the Y direction is connected to any one of the
semiconductor layers 23 arranged in the oblique direction. This
allows a bit line BL to be connected to only one memory string MS
in a region sandwiched between two source contacts LI (a memory
finger MF). This is merely an example, and it is possible to align
the semiconductor layers 23 along the X direction and the Y
direction. In addition, the source contact LI is formed to have a
stripe shape having its longitudinal direction in the X direction.
The source contact LI is embedded in the trench Tb via the
interlayer insulating layer 21'.
[0064] FIG. 6 is a sectional view that describes the structure of
the memory cell array MR and the stepwise wiring portion CR. FIG. 7
is A-A' sectional view of FIG. 6.
[0065] On the semiconductor substrate SB, the semiconductor layer
23 extends in a direction perpendicular to the substrate SB. The
semiconductor layer 23 is formed to have its bottom in the
substrate SB. The tunnel insulating layer 103, the memory layer 104
including a charge accumulation layer, and the block insulating
layer 105 are formed on the side surface of the semiconductor layer
23 in this order. The tunnel insulating layer 103, the memory layer
104 including a charge accumulation layer, and the block insulating
layer 105 are formed at a position higher than the surface of the
substrate SB. In addition, a stacked body, in which the conductive
layers 22 and the interlayer insulating layers 21 are stacked
alternately, is formed around the semiconductor layer 23, via the
tunnel insulating layer 103, the memory layer 104 and the block
insulating layer 105.
[0066] Then, the semiconductor layer 23 is electrically connected
to the substrate SB at its lower end. A conductive layer 22 that is
at the highest layer among the plurality of the conductive layers
22 is hereinafter referred to as an uppermost layer conductive
layer 22T. The uppermost conductive layer 22T is different from the
other conductive layers 22 in its material, as will be described
below. For example, the uppermost conductive layer 22T may include
a silicide layer at its upper side, while the other conductive
layers 22 may be conductive layers which do not include any
silicide layers therein. Alternatively, They may be different in
the types of metallic material that constitutes silicide.
[0067] Note that an interlayer insulating film 21T is deposited on
the upper side of the uppermost conductive layer 22T. The contact
plug Cb is formed to penetrate the interlayer insulating layer 21T
and reach the columnar semiconductor 102.
[0068] As shown in FIG. 6, the stepwise wiring portion CR is formed
such that the conductive layers 22 (the second conductive layer)
and the interlayer insulating layers 21 extend from the memory cell
array MR, and their ends are different from one another in position
to have a step-like shape. As shown in FIG. 7, on the upper surface
of the step-like part, contact plugs Ct4 are formed to extend in
the z direction as its longitudinal direction.
[0069] As shown in FIG. 6 and FIG. 7, the peripheral transistor Tr
includes the channel portion CA, the gate insulating film GI and
the gate electrode layer GE.
[0070] The channel portion CA is arranged having its longitudinal
direction along the Y direction. In other words, the channel
portion CA is arranged having its longitudinal direction along the
longitudinal direction of each of the step portions of the stepwise
wiring portion CR. The plurality of the channel portions are
arranged at the same height in the Z direction as the drain side
select gate line SGD, and are arranged such that they are
substantially parallel to one another.
[0071] The channel portion CA constitutes a body of the transistor
Tr. The channel portion CA is a semiconductor layer for forming a
channel by application of a voltage to the gate electrode layer GE.
The upper surface of the channel portion CA is formed so that
contact plugs Ct1 and Ct2 penetrate through the gate insulating
film GI. The peripheral transistor Tr is connected to the stepwise
wiring portion CR (the conductive layers 22) through the contact
plug Ct1, an upper-layer wiring Ut, and the contact plug Ct4. The
material of the channel portion CA is preferably single-crystalline
silicon or polysilicon which is doped with certain impurities, for
example.
[0072] Note that the example shown in FIGS. 6 and 7 shows a
structure in which one gate electrode layer GE is formed across a
plurality of the channel portions CA aligned in the X direction,
thereby a plurality of the peripheral transistors Tr sharing one
gate electrode layer GE. It is possible that, as shown in FIG. 1,
the gate electrode layers GE are separately formed for each of the
peripheral transistors Tr.
[0073] In addition, in the example of FIG. 7, the contact plugs Ct1
and Ct2 are arranged to reach the surface of the channel portion CA
from the upper side of the channel portion CA. This structure is
merely an example. The contact plugs Ct1 and Ct2 may penetrate
through the channel portion CA to reach the conductive layer
22.
[0074] The gate insulating film GI is formed to cover the upper
surface of the channel portion CA, and functions as a gate
insulating film of the peripheral transistor Tr. The material of
the gate insulating film GI may be a silicon oxide film (SiC.sub.2)
or a silicon nitride film (SiN). Metal oxide (e.g., HfO.sub.x) may
also be used.
[0075] The gate electrode layer GE is deposited on the upper
surface of the gate insulating film GI, and functions as a gate
electrode of the peripheral transistor Tr.
[0076] With reference now to FIGS. 8A-8I, a method of manufacturing
the semiconductor memory device according to the first embodiment
will be described.
[0077] FIG. 8A to FIG. 8C are Z-X sectional views showing a process
of manufacturing the semiconductor memory device, and FIG. 8D to
FIG. 8I are Z-X and Z-Y sectional views showing a process of
manufacturing of the same device.
[0078] First, as shown in FIG. 8A, the interlayer insulating layer
21 are laminated on the semiconductor substrate SB, with the
conductive layers 22 sandwiched therebetween. At this stage, the
laminated conductive layers 22 include conductive layers that will
become the word lines WL and the source side select gate line SGS,
except for the drain side select gate line SGD.
[0079] Note that, a conductive layer 22T' that will become the
drain side select gate line SGD is not deposited at this stage, but
will be deposited in a later process.
[0080] Subsequently, as shown in FIG. 8B, after a resist Ml is
deposited on the upper side of the the stacked body of the
conductive layers 22 and the interlayer insulating layers 21, a wet
etching is performed while this resist M1 is subject to a slimming
process by etching gradually. The ends of the conductive layers 22
and the interlayer insulating layers 21 are provided with a
step-like shape, thereby the above-mentioned stepwise wiring region
CR being formed.
[0081] Next, as shown in FIG. 8C, an interlayer insulating layer
21B is deposited to embed the stacked body of the conductive layers
22 and the interlayer insulating layers 21. The upper surface of
interlayer insulating layer 21B is planarized by a CMP method
(Chemical Mechanical Polishing).
[0082] Then, as shown in FIG. 8D, the conductive layer 22T' is
deposited on the entire upper surface of the interlayer insulating
layer 21 and 21B using polysilicon doped with p-type or n-type
impurities, for example. This conductive layer 22T' is a film that
will become the the drain side select gate lines SGD and the
channel portion CA described above.
[0083] The conductive layer 22T' is processed into a plate-like
shape that corresponds to the shape of the memory finger MF at the
position of the memory cell array MR, while it is processed into
stripe shapes having a longitudinal direction along the Y direction
and arranged along the X direction at the position of the stepwise
wiring region CR.
[0084] Then, as shown in FIG. 8E, an insulating film GI' is
deposited on the upper part of an included stacked body, including
the upper surface of the conductive layer 22T' The insulating film
GI' will become the above-mentioned gate insulating film GI in the
stepwise wiring portion CR, while it will be removed in the memory
cell array MR in a later process.
[0085] Note that it is possible that the the gate insulating film
GI is not removed in the memory cell array MR, and is used as an
interlayer insulating layer. The insulating film GI' can be
deposited by a chemical vapor deposition method (CVD method), using
silicon oxide (SiC.sub.2) or the like as its material.
[0086] Next, as shown in FIG. 8F, memory holes MH are formed using
photolithography and etching techniques at a part where the memory
cell array MR shall be formed. Then, the above-mentioned block
insulating layer 105, the memory layer 104 and the tunnel
insulating layer 103 are deposited on the sidewalls of the memory
holes MH in this order, using plasma CVD or the like, to form the
gate insulation layer GL.
[0087] Furthermore, the above-mentioned semiconductor layer 23 is
formed to fill the inside of the memory holes MH to form the memory
unit MU. The semiconductor layer 23 is formed by depositing
amorphous silicon, and thereafter, crystallizing the amorphous
silicon by a certain heat process to form polysilicon. The
crystallized polysilicon becomes the above-mentioned columnar
semiconductor 102. Silicon oxide (SiO.sub.2) is embedded in the
cavity which remained inside the columnar semiconductor 102. This
silicon oxide becomes the above-mentioned oxide film core 101,
thereby completing the semiconductor layer 23.
[0088] Then, as shown in FIG. 8G, a conductive layer 24 is formed
on the entire surface of the insulating film GI' in the stepwise
wiring portion CR, using a material such as polysilicon doped with
impurities. Then, as shown in FIG. 8H, this conductive layer 24 is
processed by photolithography and etching to form the gate
electrode layer GE.
[0089] Subsequently, as shown in FIG. 8H, after removing the
insulating film GI' stacked in the memory cell array MR by etching,
metal (silicide metal) such as titanium (Ti), cobalt (Co), tungsten
(W), and nickel (Ni) is injected into the surface of the conductive
layer 22T' and the conductive layer 24 by sputtering. Thereafter, a
heat process is performed to forma silicide layer at least on the
surface of the conductive layer 22T' including polysilicon and at
least on the surface of the conductive layer 24. Note that it is
possible to change the whole of the conductive layer 22T' and the
conductive layer 24 to the a silicide layer (full silicide).
[0090] Then, as shown in FIG. 8I, an interlayer insulating layer
21C including silicon oxide (SiO.sub.2) is deposited on the upper
part of the stacked body including the upper surfaces of the
conductive layer 22T' and the conductive layer 24, using chemical
vapor deposition or the like.
[0091] Thereafter, the structure of FIG. 6 is completed by forming
previously-described contact plugs.
[0092] In this way, according to the semiconductor memory device of
the first embodiment, the peripheral transistor Tr which connects
various wirings to drive circuits are formed on the upper part of
the stepwise wiring portion CR. Since the stepwise wiring portion
CR and the peripheral transistors Tr positionally overlap in the XY
plane, the peripheral transistors Tr do not have an additional
occupied area in the XY plane. Accordingly, the substantial
occupied area of the peripheral transistors Tr may be reduced.
Accordingly, high integration of the device and downsizing can be
achieved compared to the conventional device in which peripheral
transistors are formed on a substrate SB.
[0093] In addition, the semiconductor memory device of the first
embodiment has a structure in which the channel portion CA that
constitutes a peripheral transistor Tr is located at the same
position in the Z direction (height) as the drain side select gate
line SGD.
[0094] According to such a structure, as compared to the
conventional device in which peripheral transistors are formed on a
substrate SB, the length of the contact plugs can be shortened, the
processing depth for processing can be smaller, and the process
cost can be reduced.
Second Embodiment
[0095] Next, a semiconductor memory device according to the second
embodiment will be described with reference to FIG. 9. FIG. 9 shows
a sectional view of the memory cell array MR and the stepwise
wiring portion CR of the semiconductor device of the second
embodiment.
[0096] In addition, FIG. 10 is an enlarged perspective diagram of
the memory cell MC of the semiconductor device according to the
second embodiment. Since the schematic structure of the device is
substantially the same as that of the first embodiment, the
overlapped explanation will be omitted.
[0097] This second embodiment is different from the first
embodiment in that a conductive layer 22n is composed of a metallic
material such as tungsten (W). In addition, unlike the first
embodiment, the block insulating layer 105 is formed to surround
the periphery of the conductive layers 22a.
[0098] Next, a method of manufacturing the semiconductor memory
device according to the second embodiment will be described with
reference to FIG. 11A to FIG. 11D. When the conductive layers 22n
are composed of a metallic material as in the second embodiment, it
is difficult to form the memory holes MH with high concentration.
Accordingly, this second embodiment may be formed as described
below. First, interlayer insulating layers and sacrifice layers are
formed alternately. After the sacrifice layers are removed, the
cavities formed after the removal of the sacrifice layers (air
gaps) are embedded by conductive layers 22n including a metallic
material.
[0099] Specifically, as shown in FIG. 11A, the interlayer
insulating layers 21 are laminated on the semiconductor substrate
SB, with the sacrifice layers 22S sandwiched therebetween. When the
interlayer insulating layer 21 is a silicon nitride film, the
sacrifice layer 22S may be formed of a silicon nitride film
(Si.sub.3N.sub.4).
[0100] Next, as shown in FIG. 11B, a step-like shape is provided at
the end of the stacked body of the sacrifice layers 22S and the
interlayer insulating layers 21 to forma stepwise wiring portion
CR, similarly to the first embodiment. Subsequently, the interlayer
insulating layer 21B is deposited to embed the stacked body
subsequently. Then, on the part where the memory cell array MR
shall be formed, the memory holes MH are formed similarly to the
first embodiment.
[0101] Furthermore, as shown in FIG. 11C, the memory layer 104 and
the tunnel insulating layer 103 are deposited on the sidewalls of
the memory holes MH in this order, using plasma CVD or the like, to
form the gate insulation layer GL. Then, the above-mentioned
semiconductor layer 23 is formed to fill the inside of the memory
holes MH, thereby the memory unit MU being formed.
[0102] After the memory unit MU is formed, RIE is performed to form
trenches Tb (FIG. 5) that penetrate through the interlayer
insulating layers 21 and the sacrifice layers 22S. Then, wet
etching using the hot phosphoric acid solution is performed through
the trenches Tb. This causes the sacrifice films 22S to be removed,
as shown in FIG. 11D.
[0103] After the sacrifice films 22S are removed, air gap AG is
formed therein. Then, to a wall surface of this air gap AG, the
block insulating film 105 is formed to a certain film thickness
using chemical vapor deposition, and then metal such as tungsten is
embedded in the remained air gap AG, thereby the conductive layer
22n being completed. Thereafter, a structure of FIG. 9 is completed
by performing the same process (FIGS. 8D-8I) as the first
embodiment.
Third Embodiment
[0104] Then, a semiconductor memory device according to the third
embodiment will be described with reference to FIG. 12 to FIG. 15.
The entire structure including the memory cell array MR of the
third embodiment is the same as the structure of the first
embodiment (FIG. 1 to FIG. 5). However, in this third embodiment,
the structure of the peripheral transistors Tr is different from
that of the first embodiment.
[0105] FIG. 12 is a Z-Y sectional view that illustrates a structure
of the peripheral transistor Tr according to the third embodiment,
which corresponds to FIG. 7 of the first embodiment. Since
components that are the same as those in FIG. 7 are assigned with
identical reference numerals in FIG. 12, duplicated explanations
are omitted here.
[0106] The peripheral transistor Tr of the third embodiment
includes, in the Z-Y plane, a channel portion Ca which includes two
conductive layers connected to contact plugs, and a portion that is
connected between these conductive layers and is at a position
lower than these conductive layers when seen from the substrate SB.
For example, the channel portion CA has a concave portion or
U-shape portion that projects into a lower direction (a direction
toward the substrate SB of the Z direction).
[0107] The gate insulating film GI is formed along this channel
portion. The gate electrode layer GE is located on this concave
portion via the gate insulating film GI.
[0108] Although the gate electrode layer GE is formed on the upper
surface of the gate insulating film GI in FIG. 12, it is possible
that the gate electrode layer GE may be formed on the inner wall of
the gate insulating film GI that is provided at the sidewall of the
concave portion.
[0109] In addition, the contact plug Ct5 connected to the channel
portion CA in FIG. 12 are arranged to extend from a lower part of
the channel portion CA, along the Z direction, to reach the
conductive layer 22. This is merely an example, and like an
illustrated example in the first embodiment (FIG. 7), it is
possible that the contact plug Ct5 may extend to the upper side
along the Z direction from the upper surface of the channel portion
CA to be connected to an upper wiring line.
[0110] Then, a method of producing the peripheral transistor Tr of
the third embodiment will be described with reference to FIG. 13 to
FIG. 15. At first, similarly to the first embodiment, a process
shown in FIG. 8A to FIG. 8C is performed to obtain the structure
shown in FIG. 13. Then, as shown in FIG. 14, a rectangular trench
Tc that has its longitudinal direction along the X direction is
formed by photolithography and etching. The rectangular trench Tc
is formed on the uppermost interlayer insulating layer 21B in the
stepwise wiring portion CR, at a position where the peripheral
transistors Tr shall be shall be formed.
[0111] Thereafter, as shown in FIG. 15, similarly to the first
embodiment, the conductive layer 22T' is formed on the interlayer
insulating layers 21 and 21B including the trench Tc. Similarly to
the first embodiment, the conductive layer 22T' on the stepwise
wiring portion CR is processed to a rectangular shape having its
longitudinal direction along the Y direction. This allows the
conductive layer 22T' to become the channel portion CA having a
convex shape as shown in FIG. 12.
[0112] According to this third embodiment, a peripheral transistor
Tr having a large channel length can be formed in a small occupied
area. Accordingly, a large offset area may be provided. This
improves the withstand voltage when a high voltage is applied to
the gate electrode layer GE or the drain.
Others
[0113] While certain embodiments of the inventions have been
described, these embodiments have been presented by way of example
only, and are not intended to limit the scope of the inventions.
Indeed, the novel methods and systems described herein may be
embodied in a variety of other forms; furthermore, various
omissions, substitutions and changes in the form of the methods and
systems described herein may be made without departing from the
spirit of the inventions. The accompanying claims and their
equivalents are intended to cover such forms or modifications as
would fail within the scope and spirit of the inventions.
[0114] For example, the above-mentioned embodiments relate to a
semiconductor memory device. However, the present invention is
generally applicable to semiconductor devices other than
semiconductor memory devices. That is, the present invention is
effectively applicable to semiconductor devices in which a
plurality of conductive layers are laminated, and the conductive
layers are formed to have a step-like shape.
* * * * *