U.S. patent application number 15/256170 was filed with the patent office on 2018-03-08 for nucleation layer for growth of iii-nitride structures.
The applicant listed for this patent is IQE, PLC. Invention is credited to Wayne Johnson, Chen-Kai Kao, Oleg Laboutin, Chien-Fong Lo, Hugues Marchand.
Application Number | 20180069085 15/256170 |
Document ID | / |
Family ID | 59955625 |
Filed Date | 2018-03-08 |
United States Patent
Application |
20180069085 |
Kind Code |
A1 |
Laboutin; Oleg ; et
al. |
March 8, 2018 |
NUCLEATION LAYER FOR GROWTH OF III-NITRIDE STRUCTURES
Abstract
Nucleation layers for growth of III-nitride structures, and
methods for growing the nucleation layers, are described herein. A
semiconductor can include a silicon substrate and a nucleation
layer over the silicon substrate. The nucleation layer can include
silicon and deep-level dopants. The semiconductor can include a
III-nitride layer formed over the nucleation layer. At least one of
the silicon substrate and the nucleation layer can include ionized
contaminants. In addition, a concentration of the deep-level
dopants is at least as high as a concentration of the ionized
contaminants.
Inventors: |
Laboutin; Oleg; (South
Easton, MA) ; Kao; Chen-Kai; (Lexington, MA) ;
Lo; Chien-Fong; (Braintree, MA) ; Johnson; Wayne;
(Hampstead, NC) ; Marchand; Hugues; (Somerville,
MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
IQE, PLC |
St Mellons |
|
GB |
|
|
Family ID: |
59955625 |
Appl. No.: |
15/256170 |
Filed: |
September 2, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/02458 20130101;
H01L 21/02505 20130101; H01L 21/0262 20130101; H01L 29/7787
20130101; H01L 29/2003 20130101; H01L 21/02579 20130101; H01L
29/66462 20130101; H01L 21/0245 20130101; H01L 21/0254 20130101;
H01L 21/02381 20130101; H01L 29/205 20130101; H01L 29/36 20130101;
H01L 21/02631 20130101; H01L 21/02581 20130101; H01L 29/207
20130101 |
International
Class: |
H01L 29/20 20060101
H01L029/20; H01L 29/207 20060101 H01L029/207; H01L 29/36 20060101
H01L029/36; H01L 21/02 20060101 H01L021/02; H01L 29/778 20060101
H01L029/778; H01L 29/66 20060101 H01L029/66; H01L 29/205 20060101
H01L029/205 |
Claims
1. A semiconductor, comprising: a substrate; a nucleation layer
over the substrate and having deep-level dopants; and a III-V layer
formed over the nucleation layer; wherein: at least one of the
substrate and the nucleation layer include ionized contaminants, a
concentration of the deep-level dopants is at least as high as a
concentration of the ionized contaminants, and a concentration of
free holes in the substrate and in the nucleation layer is less
than 10.sup.16 cm.sup.-3.
2. The semiconductor of claim 1, wherein: the substrate comprises a
substrate material; and the deep-level dopants comprise a
deep-level dopant species having deep-level states being separated
from conduction and valence bands of the substrate material by
between 0.3 eV and 0.6 eV.
3. The semiconductor of claim 1, further comprising a
heterostructure between the substrate and the nucleation layer.
4. The semiconductor of claim 1, wherein the deep-level dopant
comprises vanadium.
5. The semiconductor of claim 1, wherein the deep-level dopant
comprises iron.
6. The semiconductor of claim 1, wherein the deep-level dopant
comprises sulfur.
7. The semiconductor of claim 1, wherein the ionized contaminants
comprise a Group III species.
8. The semiconductor of claim 1, wherein the ionized contaminants
comprise ionized acceptor contaminants.
9. The semiconductor of claim 1, wherein the concentration of the
deep-level dopants is between 10.sup.15 cm.sup.-3 and 10.sup.19
cm.sup.-3.
10. The semiconductor of claim 1, wherein the concentration of the
deep-level dopants is between 10.sup.16 cm.sup.-3 and 10.sup.18
cm.sup.-3.
11. (canceled)
12. The semiconductor of claim 1, wherein a concentration of free
holes in the substrate and in the nucleation layer is less than
10.sup.15 cm.sup.-3.
13. The semiconductor of claim 1, wherein a thickness of the
nucleation layer is between 1 nm and 100 nm.
14. The semiconductor of claim 1, wherein a thickness of the
nucleation layer is between 10 nm and 1 .mu.m.
15. The semiconductor of claim 1, wherein a thickness of the
nucleation layer is between 100 nm and 10 .mu.m.
16. The semiconductor of claim 1, wherein a first concentration of
the deep-level dopants at the surface of the nucleation layer
nearest the substrate is higher than a second concentration of the
deep-level dopants at the surface nearest the III-V layer.
17. The semiconductor of claim 1, wherein the substrate material is
silicon.
18. The semiconductor of claim 1, wherein the III-V layer is a
III-nitride layer.
19. A method of growing a semiconductor, comprising: growing a
nucleation layer over a substrate, the nucleation layer having
deep-level dopants; and growing a III-V layer over the nucleation
layer; wherein: at least one of the substrate and the nucleation
layer include ionized contaminants, a concentration of the
deep-level dopants is at least as high as a concentration of the
ionized contaminants, and a concentration of free holes in the
substrate and in the nucleation layer is less than 10.sup.16
cm.sup.-3.
20. The method of claim 19, wherein: the substrate comprises a
substrate material; and the deep-level dopants comprise a
deep-level dopant species having deep-level states being separated
from the conduction and valence bands of the substrate material by
between 0.3 eV and 0.6 eV.
21. The method of claim 19, further comprising growing a
heterostructure between the substrate and the nucleation layer.
22. The method of claim 19, wherein the deep-level dopants comprise
vanadium.
23. The method of claim 19, wherein the deep-level dopants comprise
iron.
24. The method of claim 19, wherein the deep-level dopants comprise
sulfur.
25. The method of claim 19, wherein the ionized contaminants
comprise a Group III species.
26. The method of claim 19, wherein the ionized contaminants
comprise ionized acceptor contaminants.
27. The method of claim 19, wherein the concentration of deep-level
dopants is between 10.sup.15 cm.sup.-3 and 10.sup.19 cm.sup.-3.
28. The method of claim 19, wherein the concentration of deep-level
dopants is between 10.sup.16 cm.sup.-3 and 10.sup.18 cm.sup.-3.
29. (canceled)
30. The method of claim 19, wherein a concentration of free holes
in the substrate and in the nucleation layer is less than 10.sup.15
cm.sup.-3.
31. The method of claim 19, wherein a thickness of the nucleation
layer is between 1 nm and 100 nm.
32. The method of claim 19, wherein a thickness of the nucleation
layer is between 10 nm and 1 .mu.m.
33. The method of claim 19, wherein a thickness of the nucleation
layer is between 100 nm and 10 .mu.m.
34. The method of claim 19, wherein a first concentration of the
deep-level dopants at the surface of the nucleation layer nearest
the substrate is higher than a second concentration of the
deep-level dopants at the surface nearest the III-V layer.
35. The method of claim 19, wherein the substrate material is
silicon.
36. The method of claim 19, wherein the III-V layer is a
III-nitride layer.
37. The method of claim 19, comprising growing the nucleation layer
and III-V layer by metalorganic chemical vapor deposition.
38. The method of claim 19, comprising growing the nucleation layer
and the III-V layer by molecular beam epitaxy.
39. The method of claim 19, comprising growing the nucleation layer
and the III-V layer by halide vapor phase epitaxy.
40. The method of claim 19, comprising growing the nucleation layer
and the III-V layer by physical vapor deposition.
41. The semiconductor of claim 1, wherein: a topmost layer of the
substrate is silicon, and the nucleation layer is silicon.
42. The method of claim 19, wherein: a topmost layer of the
substrate is silicon, and the nucleation layer is silicon.
Description
BACKGROUND
[0001] High electron mobility transistors (HEMT's) grown on high
resistivity silicon (Si) can have degraded performance due to
contamination during fabrication. When a III-nitride layer is grown
on a high resistivity Si substrate for use in a HEMT structure,
acceptor contaminant species can deposit on and/or diffuse to the
top surface of the Si substrate, causing a p-type region to form
there upon ionization of the acceptors. The p-type region can have
a high free hole concentration, resulting in a parasitic conductive
channel. The parasitic channel results in parasitic capacitance
that reduces the transistor performance at high frequencies.
[0002] In addition, the surface of the Si substrate can be
contaminated with oxygen, carbon, and other elements. The
contaminants and impurities may include species deposited on the
surface of the substrate after desorbing from the chamber walls,
adventitious carbon-containing species arising from species present
in the environment, and/or a native oxide resulting from oxidation
of the substrate by oxygen present in the ambient environment.
These contaminants and impurities can lead to the formation of a
highly defective interface between the Si and the III-nitride
layer. This surface contamination and related defects can reduce
the quality of the subsequent III-nitride epitaxial layers and
structures. This reduced quality causes reduced electron mobility,
deteriorating transistor performance, especially at high-voltage
and high-current conditions.
SUMMARY
[0003] Accordingly, nucleation layers for growth of III-V and
III-nitride structures, and methods for growing the nucleation
layers, are described herein. A semiconductor can include a
substrate and a nucleation layer over the substrate. The nucleation
layer can include deep-level dopants. The semiconductor can include
a III-V layer formed over the nucleation layer. At least one of the
substrate and the nucleation layer can include ionized
contaminants. In addition, a concentration of the deep-level
dopants is at least as high as a concentration of the ionized
contaminants.
[0004] The substrate can include a substrate material, and the
deep-level dopants can include a deep-level dopant species having
deep-level states that are separated from the conduction and
valence bands of the substrate material by between 0.3 eV and 0.6
eV. The semiconductor can include a heterostructure between the
substrate and the nucleation layer.
[0005] The deep-level dopant can include one or more of vanadium,
iron, sulfur, and other chemical elements. The ionized contaminants
can include a Group III species. The ionized contaminants can
include ionized acceptor contaminants.
[0006] The concentration of the deep-level dopants can be between
10.sup.15 cm.sup.-3 and 10.sup.19 cm.sup.-3, and/or between
10.sup.16 cm.sup.-3 and 10.sup.18 cm.sup.-3. A concentration of
free holes in the substrate and in the nucleation layer can be less
than 10.sup.16 cm.sup.-3 and/or less than 10.sup.15 cm.sup.-3.
[0007] A thickness of the nucleation layer can be between 1 nm and
100 nm, between 10 nm and 1 .mu.m, and/or between 100 nm and 10
.mu.m.
[0008] A first concentration of the deep-level dopants at the
surface of the nucleation layer nearest the substrate can be higher
than a second concentration of the deep-level dopants at the
surface nearest the III-V layer. The substrate material can be
silicon. The III-V layer can be a III-nitride layer.
[0009] The nucleation layer and III-V layer can be grown by one or
more of metalorganic chemical vapor deposition, molecular beam
epitaxy, halide vapor phase epitaxy, and physical vapor
deposition.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The above and other features of the present disclosure,
including its nature and its various advantages, will be more
apparent upon consideration of the following detailed description,
taken in conjunction with the accompanying drawings in which:
[0011] FIG. 1 depicts initial growth of a compensated nucleation
layer using metalorganic chemical vapor deposition (MOCVD),
according to an illustrative implementation;
[0012] FIG. 2 depicts the formation of an epitaxial nucleation
layer at a time after the initial nucleation depicted in FIG. 1,
according to an illustrative implementation;
[0013] FIG. 3 depicts the formation of a III-nitride layer on a
substrate at a time after the time depicted in FIG. 2, according to
an illustrative implementation;
[0014] FIG. 4 depicts a semiconductor manufactured using the
methods described herein, according to an illustrative
implementation;
[0015] FIG. 5 depicts a semiconductor with III-nitride layers that
can be used to manufacture a high electron mobility transistor
(HEMT), according to an illustrative implementation;
[0016] FIG. 6 depicts a HEMT manufactured using the methods
described herein, according to an illustrative implementation;
and
[0017] FIG. 7 depicts a flowchart of a method for growing
semiconductors with nucleation layers that contain compensating
deep-level dopants, according to an illustrative
implementation.
DETAILED DESCRIPTION
[0018] The systems, devices, and methods described herein include,
among other things, semiconductors having a nucleation layer that
may achieve improved performance. Though not to be bound by theory
or a proposed mechanism of action, it is noted for purposes of
clarity and instruction that the nucleation layer may mitigate
problems caused by parasitic channels and contamination in at least
two ways. First, doping the nucleation layer with deep-level dopant
species may compensate for free holes generated by the ionized
acceptor dopants. Second, growth of the nucleation layer may clean
the substrate surface, and the nucleation layer can physically bury
contaminants and impurities and related defects, such as
dislocations. The semiconductor can include semiconducting,
conducting, and insulating materials. The semiconductor may include
wafers covered with one or more blanket layers, wafers with one or
more patterned layers, wafers with metal interconnects, wafers with
functioning transistors, wafers with integrated circuits, one or
more separated portions of wafers such as a die or multiple dice,
and die or dice that have been packaged.
[0019] Although the systems, devices and methods described herein
are not limited to any particular mechanism of action, it is noted
for purposes of clarity that the deep-level dopants may act as
deep-level traps and may compensate for the ionized acceptor
dopants that deposit on or diffuse to the substrate surface. As
deep-level traps, the deep-level dopants provide recombination
centers, and trap and localize free holes caused by the ionized
acceptor contaminants. The holes may be bound to the deep-level
dopants and are not delocalized (free) throughout the substrate or
nucleation layer. This trapping is understood to lower the free
hole concentration near the surface of the substrate, making the
region more resistive.
[0020] It is also understood and noted for purposes of clarity,
that the nucleation layer may physically bury contaminants and
impurities that deposit on, or have reacted with the top surface of
the substrate. A reducing atmosphere (typically comprising H.sub.2
gas) occurring before and during growth of the nucleation layer is
understood to remove some or all of the carbon- and
oxygen-containing contaminants and impurities, but the nucleation
layer buries any contaminants and impurities that remain. In
addition, the nucleation layer can be thick enough so that
dislocations terminate within it and the upper surface of the
nucleation layer has a reduced dislocation density. By burying
contaminants, impurities, and the dislocations they cause, it is
understood that the nucleation layer provides a clean surface for
growth of a subsequent III-nitride layer. The III-nitride layer is
a layer comprising a Group III species and nitrogen. The Group III
species can include one or more element in Group III of the
Periodic Table, including B, Al, Ga, In, and Tl. The III-nitride
layer can be a compound that includes multiple Group III elements.
The III-nitride layer can include binary compounds such as GaN,
ternary compounds such as Al.sub.xGa.sub.1-xN (0.ltoreq.x.ltoreq.1)
and In.sub.xGa.sub.1-xN (0.ltoreq.x.ltoreq.1), quaternary compounds
such as In.sub.xAl.sub.yGa.sub.1-x-yN (0.ltoreq.x,y.ltoreq.1), and
quinary compounds such as
Ga.sub.xIn.sub.(1-x)As.sub.ySb.sub.zN.sub.(1-y-z)
(0.ltoreq.x,y,z.ltoreq.1). The III-nitride layer can be undoped,
unintentionally doped, or doped with donor or acceptor dopants.
Throughout this disclosure, a III-nitride layer is described in
detail as an example of a III-V layer. However, III-nitride
materials are but a subset of III-V materials, and layers and
materials described herein as III-nitride layers and materials can
be replaced with other III-V layers and materials. III-V layers and
materials include one or more species from Group III of the
Periodic Table (such as the examples listed above) and one or more
species from Group V of the Periodic Table (such as N, P, As, Sb,
and Bi). As later described with reference to FIG. 4, examples of
other III-V materials include one or more of GaAs, InP, InAs, InSb,
InGaAs, GaAsP, InGaAsP, and the like.
[0021] FIG. 1 depicts initial growth of a compensated nucleation
layer using metalorganic chemical vapor deposition (MOCVD). FIG. 1
depicts a substrate 102, a chamber wall 104, a residue layer 114 on
the chamber wall 104, and a precursor inlet 106. The substrate 102
can be any substrate used for growth of III-nitride materials. The
substrate 102 can be a silicon substrate, a high-resistivity
silicon substrate, a silicon-on-insulator (SOI) substrate, and/or
any type of composite substrate in which the top surface comprises
silicon. The above substrates and other substrates can include
single-crystal wafers that are undoped, unintentionally doped, or
doped with donor or acceptor dopants. In the example of a
high-resistivity silicon substrate, the substrate can have a
resistivity of greater than 1,000 ohm-cm, greater than 2,000
ohm-cm, greater than 3,000 ohm-cm, greater than 6,000 ohm-cm, or
greater than 10,000 ohm-cm. The substrate 102 can be a silicon
(111) substrate to facilitate epitaxial growth of III-nitride
materials, or the substrate 102 can include silicon with another
crystal orientation such as silicon (100).
[0022] The precursor inlet 106 schematically represents a precursor
delivery system, which injects the various precursors required to
deposit silicon and III-nitride layers on the substrate 102. As
depicted in FIG. 1, the precursor injector 106 is injecting a
gas-phase silicon precursor 120 and a gas-phase dopant precursor
121.
[0023] Elevating the temperature of the chamber wall 104 is
understood to cause components of the residue layer 114 to desorb
as gas-phase contaminant species 116. The residue layer 114 can be
a III-nitride material that was deposited on the chamber wall 104
during previous operation of the deposition system. Thus, the
contaminant species 116 can be a Group III species which would act
as a p-type dopant in silicon. A portion of the gas-phase species
120, 121, and 116 deposit on the substrate 102 as surface species
124, 125, and 118, respectively. The surface species 124, 125, and
118 can be physisorbed or chemisorbed, and can be cracked or
uncracked. The silicon surface species 124 is the dominant species
on the surface of the substrate 102, but the dopant surface species
125 and the contaminant surface species 118 are present in
concentrations high enough to affect the doping level of the film
that is subsequently grown on the substrate 102. In some examples,
the flow of the gas-phase precursor species 121 from the precursor
injector 106 is adjusted such that the concentration of the dopant
species 125 on the substrate 102 is substantially the same as the
concentration of the contaminant species 118 on the substrate 102.
If diffusion from subsequently deposited layers is expected, the
flow of the gas-phase precursor species 121 can be adjusted to
result in a concentration of the dopant species 121 that is higher
than the concentration of the contaminant species 118. In addition,
some of the silicon precursor species 120 and the dopant species
121 deposit as surface species 122 and 123, respectively, on the
residue layer 114.
[0024] The silicon precursor species 120 can include one or more
silicon CVD precursors. Examples of silicon CVD precursors include
silane, disilane, trisilane, dichlorosilane, trichlorosilane,
methylsilane, diterttiarybutylsilane, silicon tetrachloride,
silicon tetrafluoride, silicon tetrabromide, tetraethoxysilane,
elemental silicon, and higher-order silanes and chlorosilanes.
[0025] The dopant species 121 can include one or more CVD
precursors that deliver deep-level dopants. Examples of deep-level
dopants include sulfur, selenium, vanadium, iron, tantalum,
tellurium, chromium, manganese, or other chemical elements.
Examples of CVD precursors that deliver sulfur include hydrogen
sulfide (H.sub.2S), ditert-butyl sulphide,
bis(trimethylsilyl)sulfide, (R)-(+)-t-butylsulfinamide, diethyl
sulfide, polypropylene sulfide, diisopropylsulfide, elemental
sulfur, and organics, cyclopentadienyls, amines, aminidates,
halides, and aromatics containing sulfur.
[0026] Examples of CVD precursors that deliver selenium include
hydrogen selenide (H.sub.2Se), dimethylselenide,
ditert-butylselenide, elemental selenium, and other chemical
compounds containing selenium.
[0027] Examples of CVD precursors that deliver vanadium include
bis(cyclopentadienyl)vanadium(II), vanadium(V) oxytriisopropoxide,
tetrakis(dimethylamino)vanadium(IV),
tetrakis(diethylamino)vanadium(IV), elemental vanadium, and
organometallics, and cyclopentadienyls, amines, aminidates,
halides, and aromatics containing vanadium.
[0028] Examples of CVD precursors that deliver iron include
bis(cyclopentadienyl)iron (also known as ferrocene),
butylferrocene, dichlorophosphinoferrocene, ethylferrocene,
elemental iron, and cyclopentadienyls, amines, aminidates, halides,
elemental vanadium, and aromatics containing iron.
[0029] Examples of the contaminant species 118 include boron,
aluminum, gallium, indium, thallium, and nitrogen.
[0030] FIG. 2 depicts the formation of an epitaxial nucleation
layer 236 at a time after the initial nucleation depicted in FIG.
1. The surface species 124, 125, and 118 depicted in FIG. 1 have
coalesced into a nucleation layer 236. The nucleation layer 236 is
an epitaxial layer that is lattice-matched to, or is at least
pseudomorphic with, the substrate 102. The nucleation layer 236 can
be a silicon layer. If the substrate 102 is a silicon substrate
and/or includes silicon as a substrate material, the nucleation
layer 236 can be a homoepitaxial silicon layer. Homoepitaxy refers
to the epitaxial growth of a material on a substrate having at
least a top surface of the same material. However, a homoepitaxial
layer can include different doping characteristics (such as dopant
species and concentration) than the material below. The nucleation
layer 236 contains silicon 225, deep-level dopant species 227, and
ionized acceptor contaminant species 226, resulting from
incorporation of the surface species 124, 125, and 118,
respectively. The ionized acceptor contaminant species 226 can
include Group III species such as B, Al, Ga, In, and Tl. The
deep-level dopant species 227 can include one or more of S, Se, V,
Fe, Ta, Te, Cr, Mn, and other chemical elements. The deep-level
dopant species 227 and the ionized acceptor contaminant species 226
can be interstitial or substitutional impurities. In some examples,
one or both of the species 226 and 227 are interstitial impurities
as deposited and become substitutional impurities after annealing.
The annealing can occur in the deposition chamber or in a separate
chamber.
[0031] When using a high-resistivity silicon wafer as the substrate
102, the presence of p-type dopants as the contaminant species 118
could lead to p-type doping of the substrate 102. The free holes
resulting from this p-type doping could lead to the formation of a
low-resistivity (high mobility) parasitic channel in the substrate
102. However, supplying a deep-level dopant that contains
deep-level donor states as the dopant species 121 results in the
deep-level dopant species 227 trapping the free holes, thus
compensating for the p-type doping. When the concentration of the
deep-level dopant species 227 is at least as high as the
concentration of the ionized acceptor contaminant species 226, the
deep-level dopant species 227 compensates for the free holes
generated by the ionized acceptor contaminant species 226,
preventing the formation of a parasitic channel and maintaining the
high resistivity of the substrate 102.
[0032] As described herein, the electrical activity of both
deep-level dopants and acceptor contaminants is approximately 1.
The electrical activity of a species refers to the fraction of
atoms of that species that are ionized. Thus, nearly all of the
acceptors and deep-level dopants are ionized and the concentration
of ionized acceptors or deep-level dopants is approximately
equivalent to the concentration of acceptor contaminant species or
deep-level dopants. However, in some examples, the electrical
activity of the deep-level dopants and/or the acceptors is less
than 1. In these examples, the concentration of ionized deep-level
dopants is at least as high as the concentration of ionized
acceptors. Concentrations of dopants and charge carriers are
sometimes expressed in units of electrons-cm.sup.-3,
holes-cm.sup.-3, or atoms-cm.sup.-3, but more often, the name of
the particle is omitted while referencing the same quantity and
such concentrations are simply expressed in units of cm.sup.-3. A
concentration of deep-level dopant species that is at least as
large as a concentration of ionized acceptor contaminant species
can include a concentration of deep-level dopant species that is
more than 10% lower than, approximately 10% lower than,
approximately 5% lower than, approximately equal to, approximately
5% greater than, approximately 10% greater than, or more than 10%
greater than the concentration of ionized acceptor contaminant
species.
[0033] If the concentration of ionized acceptor contaminant species
is larger than the concentration of deep-level dopant species, the
free hole concentration in the nucleation layer and the nearby
portion of the substrate will be the difference between the
concentration of ionized acceptor contaminant species and the
concentration of deep-level dopant species. Thus, a concentration
of deep-level dopant species that is 10% lower than the
concentration of ionized acceptor contaminant species will result
in a reduction in free hole concentration of an order of magnitude,
compared to a semiconductor without deep-level dopants.
[0034] If the concentration of deep-level dopant species is exactly
equal to the concentration of ionized acceptor contaminant species,
a fully compensated condition exists and the free hole and electron
concentrations in the nucleation layer and the nearby portion of
the substrate will be negligible, due only to thermally generated
carriers.
[0035] If the concentration of deep-level dopant species is larger
than the concentration of ionized acceptor contaminant species, a
fully compensated condition also exists and the free hole and
electron concentration in the nucleation layer and the nearby
portion of the substrate will also be negligible, due only to
thermally generated carriers. The concentrations of thermally
generated carriers in fully compensated conditions are negligible
because the deep-level dopant species do not have any electron
energy states within several multiples of kT (up to 0.3-0.6 eV)
from either the conduction or valence bands of silicon. Here, k
refers to Boltzmann's constant and T refers to the temperature of
the semiconductor in Kelvins.
[0036] At the time depicted in FIG. 2, the surface species 122 and
123 have coalesced into a residue layer 228 that covers the residue
layer 114. The residue layer 228 includes silicon material 229 and
dopant species 233.
[0037] The gas-phase precursor species 120 and 121 continue to
travel to the substrate 102 and deposit as surface species 224 and
225, respectively. In addition, the gas-phase species 120 and 121
travel to the wall 104 and deposit on the residue layer 228 as
surface species 222 and 223, respectively.
[0038] The residue layer 228 is at an elevated temperature due to
the growth conditions and thus some of its component species desorb
as silicon species 230 and dopant species 231. The desorbed species
230 and 231 can also travel to the substrate 102 and deposit as
surface species. However, because the residue layer 228 covers the
residue layer 114, contaminant species such as the contaminant
species 116 do not desorb. Thus, once the residue layer 228 has
formed, it prevents further p-type dopants, such as Group III
elements, from depositing on the substrate 102. Furthermore,
because the concentration of deep-level dopant species 227 is at
least as high as the concentration of ionized acceptor contaminant
species 226, the substrate 102 does not contain a parasitic
channel.
[0039] FIG. 3 depicts the formation of a III-nitride layer on the
substrate 102 at a time after the time depicted in FIG. 2. In FIG.
3, the precursor injection system 106 delivers III-nitride
precursors 340. The III-nitride precursors 340 can include multiple
species of precursor and can be injected by different precursor
delivery lines. The III-nitride precursors can include precursors
that deliver Group III elements such as boron, aluminum, gallium,
indium, and thallium, and/or nitrogen.
[0040] Examples of precursors that deliver aluminum include
trimethylaluminum, triethylaluminum, dimethylaluminumhydride,
dimethylethylamine alane, triisobutylaluminum,
tris(dimethylamido)aluminum(III), aluminum trichloride, elemental
aluminum, and alkyls, alkylamides, alkoxides, amidinates,
.beta.-diketonates, carbonyls, cyclopentadienyls, and
organometallics containing aluminum.
[0041] Examples of precursors that deliver gallium include
trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III),
gallium trichloride, diethylgallium chloride, triisobutylgallium,
elemental gallium, and alkyls, alkylamides, alkoxides, amidinates,
.beta.-diketonates, carbonyls, cyclopentadienyls, and
organometallics containing gallium.
[0042] Examples of precursors that deliver indium include
trimethylindium, triethylindium, dimethylethylindium, indium
trichloride, elemental indium, and alkyls, alkylamides, alkoxides,
amidinates, .beta.-diketonates, carbonyls, cyclopentadienyls, and
organometallics containing indium.
[0043] Examples of precursors that deliver nitrogen include
ammonia, 1.1-dimethylhydrazine, tert-butylamine, phenylhydrazine,
elemental nitrogen, and other gases and organometallics containing
nitrogen.
[0044] The III-nitride precursors travel to the substrate 102 and
deposit as surface species 342. The precursor species 340 also
travels to the wall 104 and deposits as surface species 343. As the
deposition progresses, the surface species 343 form a III-nitride
layer 341 over the residue layer 228. Likewise, the surface species
342 form a III-nitride layer 348 over the silicon layer 236 on the
substrate 102. The III-nitride layer 346 can include one or more
Group III elements.
[0045] Because of the elevated temperature of the wall 104,
III-nitride species 345 will desorb from the III-nitride layer 341.
The III-nitride species 345 can then deposit on to the substrate
102 as surface species 342. However, once the III-nitride layer 341
is continuous and dense, it prevents the sublimation of silicon
species from the residue layer 228. Thus, desorption from a
continuous and dense III-nitride layer 341 does not significantly
affect the composition of the III-nitride layer 348. However,
before the III-nitride layer 341 becomes continuous and dense, some
species from the residue layer 228 can sublimate and can be
deposited in the lower portion of the III-nitride layer 348 as
silicon species 346 and dopant species 347. When a subsequent wafer
is loaded into the chamber, the III-nitride layer 341 can act as a
source of contaminant species in a similar manner for the
subsequent wafer as the residue layer 114 acts for the substrate
102.
[0046] In addition to ionized acceptor species that are deposited
in the silicon layer 236 due to desorption from the residue layer
114, the silicon layer 236 can also include ionized acceptor
contaminant species 350 that diffuse down from the III-nitride
layer 348. This diffusion can occur at significant rates because
the substrate 102 is at an elevated temperature during the
deposition process. In particular, gallium and aluminum can diffuse
into the silicon layer 236 and act as ionized acceptor dopants,
making the silicon layer 236 more p-type and more conductive.
However, the flux of the dopant species 121 during growth of the
silicon layer 236 can be selected to produce a concentration of
deep-level dopants in the silicon layer 236 that is sufficient to
compensate for both ionized acceptor contaminant species 226
originating in the residue layer 114 and ionized acceptor
contaminant species 350 that have diffused from adjacent
layers.
[0047] The deep-level dopant species 227 compensate for the p-type
dopants present in the silicon layer 236 by acting as deep-level
traps. As deep-level traps, the deep-level dopant species 227
provide recombination centers, which trap and localize free holes
caused by the ionized acceptor contaminant species 226 and 350.
This trapping lowers the free hole concentration in the silicon
layer 236, making it more resistive. In some examples, the ionized
acceptor contaminant species 226 are present in the silicon layer
236 at a concentration of approximately 10.sup.17 cm.sup.-3. The
ionized acceptor contaminant species 226 can be present at a
concentration between 10.sup.15 and 10.sup.17 cm.sup.-3, between
10.sup.14 and 10.sup.18 cm.sup.-3, and/or between 10.sup.11 and
10.sup.20 cm.sup.-3. To compensate for the free holes generated by
these p-type dopants, the silicon layer 236 can contain at least an
equivalent concentration of deep-level dopant species 227. Thus, in
this example, the silicon layer 236 should contain a concentration
of deep-level dopant species 227 of at least 10.sup.17 cm.sup.-3,
between 10.sup.15 and 10.sup.19 cm.sup.-3, between 10.sup.16 and
10.sup.18 cm.sup.-3, or higher than 10.sup.18 cm.sup.-3. With the
deep-level dopant species 227 compensating for the presence of free
holes, the free hole concentration can be less than 10.sup.18
cm.sup.-3, less than 10.sup.17 cm.sup.-3, less than 10.sup.16
cm.sup.-3, and/or less than 10.sup.15 cm.sup.-3. In some examples,
the deep-level dopant species 227 can act as a recombination
center, even though the original deep-level trap states have been
compensated by free holes. For example, the deep-level dopant
species in the silicon layer 236 can re-capture electrons from the
conduction band, which then recombine with other free holes. It is
also possible that the deep-level dopant species 227 can directly
capture free holes.
[0048] To act as a deep-level trap, the deep-level dopant species
227 should have an ionization energy that results in electron
states well inside the band gap of the silicon layer 236, far from
the band edges. These deep-level states should be separated from
the conduction and valence band edges by significantly more than
the thermal energy of electrons (kT) at room temperature. For
example, the deep-level states can be separated from one or both of
the band edges by between 0.3 and 0.5 eV. In some examples, the
deep-level states can be separated from one or both of the band
edges by between 0.2 and 0.6 eV, and/or by more than 0.6 eV. One or
more of sulfur (S), vanadium (V), iron (Fe), selenium (Se),
tantalum (Ta), tellurium (Te), chromium (Cr), manganese (Mn), and
other chemical elements act as deep-level traps in silicon and can
be used as the deep-level dopant species 227.
[0049] FIG. 4 depicts a semiconductor 400 manufactured using the
methods described herein. The semiconductor 400 includes a
substrate 402 (e.g., 102), a nucleation layer 436 (e.g., 236) over
the substrate 402, and a III-nitride layer 448 (e.g., 348) over the
nucleation layer 436. In some examples, the III-nitride layer 448
may be replaced with a III-V layer. Examples of III-V materials
include one or more of GaAs, InP, InAs, InSb, InGaAs, GaAsP,
InGaAsP, and the like. The substrate 402 can be a silicon substrate
or a high-resistivity silicon substrate. In the example of a
high-resistivity silicon substrate, the substrate can have a
resistivity of greater than 1,000 ohm-cm, greater than 2,000
ohm-cm, greater than 3,000 ohm-cm, greater than 6,000 ohm-cm, or
greater than 10,000 ohm-cm. The substrate 102 can be a silicon
(111) substrate to facilitate epitaxial growth of the III-nitride
layer 448. The thickness of the nucleation layer 436 can be
approximately 1 .mu.m, between 1 nm and 10 .mu.m (microns or
micrometers), between 1 nm and 100 nm, between 10 nm and 1 .mu.m,
between 100 nm and 1 .mu.m, and/or between 100 nm and 10 .mu.m.
[0050] The nucleation layer 436 buries contaminants and impurities
present on the surface of the substrate 402. The contaminants and
impurities may include species deposited on the surface of the
substrate after desorbing from the chamber walls, as illustrated by
species 118 in FIG. 1. The contaminants and impurities may also
include adventitious carbon-containing species arising from species
present in the environment and/or a native oxide resulting from
oxidation of the substrate 402 by oxygen present in the ambient
environment. A reducing atmosphere (typically comprising H.sub.2
gas) before and during growth of the nucleation layer 436 can
remove some or all of the carbon- and oxygen-containing
contaminants and impurities, but the nucleation layer buries any
contaminants and impurities that remain. In some examples, the
nucleation layer 436 is thick enough that dislocations and other
defects terminate within it and the upper surface of the nucleation
layer 436 has a reduced defect density.
[0051] Furthermore, the nucleation layer 436 physically buries the
contaminants and impurities, providing a clean surface for growth
of the III-nitride layer 448. In some examples, the nucleation
layer 436 does not contain deep-level dopants. In these examples,
the nucleation layer 436 serves to provide a clean surface for
growth of the III-nitride layer 448 but does not affect the carrier
concentration by compensating for impurities that may be present.
By physically burying contaminants and impurities, the nucleation
layer 436 improves the film quality of the III-nitride layer 448,
improving the performance of HEMT devices made using the
semiconductor 400. By compensating ionized acceptor contaminant
species, the nucleation layer 436 reduces or eliminates the
formation of a parasitic conductive channel, improving the
performance of HEMT devices made using the semiconductor 400.
[0052] The III-nitride layer 448 can include one or more
constituent layers. The semiconductor 400 can be an epi-wafer, that
is, a semiconductor wafer covered with blanket epitaxial layers and
no lateral patterning. The epi-wafer may include one or more
non-epitaxial capping layers as well. The epi-wafer can be further
processed by lateral patterning to create transistors. In some
examples, the semiconductor 400 is a wafer that has undergone such
patterning. The semiconductor 400 can also include other layers
(such as metal layers serving as contacts and/or interconnects)
over the III-nitride layer 448 as well. In some examples, the
semiconductor 400 is a portion of an epi-wafer, such as a chip that
has been diced from an epi-wafer.
[0053] FIG. 5 depicts a semiconductor 500 with III-nitride layers
that can be used to manufacture a high electron mobility transistor
(HEMT). The semiconductor 500 includes a substrate 502 (e.g., 402,
102) and a nucleation layer 536 (e.g., 436, 236) over the substrate
502. The semiconductor 500 also includes a III-nitride layer 548
(e.g., 348, 448). The III-nitride layer 548 comprises multiple
layers, including a transition layer 550, a buffer layer 552, a
gallium nitride (GaN) layer 554, and an indium aluminum gallium
nitride (In.sub.xAl.sub.yGa.sub.1-x-yN; 0 x, y 1) layer 558. The
In.sub.xAl.sub.yGa.sub.1-x-yN layer 558 can have a constant
composition (i.e., constant values of x and y) through its
thickness, or can have a varying composition (i.e., varying values
of x and y) through its thickness. In some examples, the
III-nitride layer can comprise one or more layers that include
materials other than III-nitrides. The transition layer 550 may
contain AlN and/or other alloys such as
In.sub.xAl.sub.yGa.sub.1-x-yN, and can serve to transition between
the nucleation layer 536, which can be made of silicon and the
buffer layer 552, which can comprise GaN. The buffer layer 552 can
comprise a relatively thick GaN layer that is thick enough to be
fully relaxed at its upper surface. The buffer layer 552 can also
act to reduce a density of the defects due to lattice mismatch. The
buffer layer can comprise any III-nitride material, such as GaN,
In.sub.xAl.sub.yGa.sub.1-x-yN, and/or AlN. In some examples, the
composition of the buffer layer can vary throughout its thickness.
The buffer layer can also comprise one or more superlattices or
multiple layer structures with alternating layers of III-nitride
materials.
[0054] Due to the heterojunction between the GaN layer 554 and the
In.sub.xAl.sub.yGa.sub.1-x-yN layer 558, a two-dimensional electron
gas (2 DEG) forms in the GaN layer 554 near the
GaN/In.sub.xAl.sub.yGa.sub.1-x-yN interface. The 2 DEG 556 can
provide a high-electron mobility channel in a HEMT. Other layers
can be deposited over the semiconductor 500, including one or more
of a capping layer, a metallization layer, and an isolation layer.
Lateral patterning can be used to define lateral features such as
transistors in the semiconductor 500. The semiconductor 500 can be
an epi-wafer, and may include one or more non-epitaxial capping
layers. In some examples, the semiconductor 500 includes one or
more patterned features such as transistors. The semiconductor 500
can also include other layers (such as metal layers serving as
contacts and/or interconnects) over the III-nitride layer 548 as
well. In some examples, the semiconductor 500 is a portion of an
epi-wafer, such as a chip.
[0055] By physically burying contaminants and impurities, the
nucleation layer 536 improves the film quality of the III-nitride
layer 548, improving the performance of HEMT devices made using the
semiconductor 500. By compensating ionized acceptor contaminant
species, the nucleation layer 536 reduces or eliminates the
formation of a parasitic conductive channel, improving the
performance of HEMT devices made using the semiconductor 500.
[0056] FIG. 6 depicts a HEMT 600 manufactured using the methods
described herein. The HEMT 600 can be manufactured from the
semiconductor 500. The HEMT 600 includes a substrate 602 (e.g.,
102, 402, 502) and a nucleation layer 636 (e.g., 236, 436, 536).
The HEMT 600 also includes a III-nitride layer 648 (e.g., 348, 448,
548) over the nucleation layer 636. The III-nitride layer 648
includes a transition layer 650 (e.g, 550) over the nucleation
layer 636, a buffer layer 652 (e.g., 552) over the AN layer 650, a
GaN layer 654 (e.g., 554) over the buffer layer 652, and an
In.sub.xAl.sub.yGa.sub.1-x-yN (0 x, y 1) layer 658 (e.g., 558) over
the GaN layer 654. The In.sub.xAl.sub.yGa.sub.1-x-yN layer 658 can
have a constant composition (i.e., constant values of x and y)
through its thickness, or can have a varying composition (i.e.,
varying values of x and y) through its thickness. The HEMT 600 also
includes a 2 DEG 656 (e.g., 556) in the gallium nitride layer 654
near its interface with the In.sub.xAl.sub.yGa.sub.1-x-yN layer
658. The III-nitride layer 648 can have a composition different
than is depicted in FIG. 6. The III-nitride layer 648 in the HEMT
600 are laterally patterned using photolithography and etching
techniques. Metallic contacts are deposited on the III-nitride
layers to form a source contact 660, a drain contact 662, and a
gate contact 664. Interconnects (not shown) can connect the
contacts 660, 662, and 664 to a circuit. A gate voltage applied to
the gate contact 664 can modulate the conductivity of the channel
between the source contact 660 and the drain contact 662.
[0057] Because the 2 DEG 656 provides a channel with high mobility,
the HEMT 600 can be used for high-frequency switching. The
switching can be at frequencies higher than 1 GHz, 50 GHz, or 60
GHz. At these high frequencies, any parasitic capacitance of the
substrate 602 can reduce the performance of the HEMT 600. However,
the nucleation layer 636 of the HEMT 600 includes deep-level
dopants (e.g., 227) that act as traps and compensate for the
presence of ionized acceptors, reducing or substantially preventing
a parasitic channel and thus reducing or substantially preventing
parasitic capacitance of the substrate 602. Accordingly, deep-level
dopants (e.g., 227) in the nucleation layer 636 can improve the
performance of the HEMT 600 at high frequencies. The increase in
performance can be realized as one or both of operating at higher
frequencies and increased gain at a given frequency. By physically
burying contaminants and impurities, the nucleation layer 636
improves the film quality of the III-nitride layer 648, improving
the performance of HEMT devices made using the semiconductor
600.
[0058] FIG. 7 depicts a flowchart of a method 700 for growing
semiconductors with nucleation layers that contain compensating
deep-level dopants. The method 700 can be an MOCVD process and/or
an organometallic vapor phase epitaxy (OMVPE) process. In some
examples, the method 700 can be implemented using molecular beam
epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser
deposition (PLD), and/or physical vapor deposition (PVD) instead of
MOCVD. A substrate can be loaded directly into an epitaxial chamber
or using a transfer (load-lock) chamber. At 702, conditions in the
epitaxial chamber or load-lock chamber are adjusted to wafer
loading conditions. The substrate holder is cooled to room
temperature. A N.sub.2 purge gas flow is adjusted to near 0. At
704, one or more substrates (e.g., 102, 402, 502, 602) is loaded
into the epitaxial chamber or loaded into the load-lock chamber and
then transferred into the epitaxial chamber. If the load-lock
chamber is used, the epitaxial chamber remains under the base state
conditions.
[0059] At 706, the epitaxial chamber conditions are adjusted to
growth conditions for the nucleation layer (e.g., 236, 436, 536,
636). The one or more substrates (e.g., 102, 402, 502, 602) is
heated to a temperature of 550-1200.degree. C. The pressure in the
epitaxial chamber is adjusted to 40-760 Torr. A very low pressure
technique (<50 Torr) can be also employed. A purge gas flow of
H.sub.2, N.sub.2, or a mixture of both, is adjusted to 1-1000 slm
(standard liters per minute). In some examples, a carrier gas is
not used. The precursors flow rate for the nucleation layer growth
is controlled in the range of 1-500 .mu.mol/min. Depending on the
desired growth rate, the precursors flow rate can be also adjusted
in the wide range of 0.1-5000 .mu.mol/min.
[0060] At 708, the nucleation layer (e.g., 236, 436, 536, 636) is
grown over the one or more substrates. Step 708 is continued for a
predetermined time, corresponding to a desired thickness of the
nucleation layer. The desired thickness can be approximately 1
.mu.m, between 1 nm and 10 .mu.m, between 1 nm and 100 nm, between
10 nm and 1 .mu.m, between 100 nm and 1 .mu.m, and/or between 100
nm and 10 .mu.m. The nucleation layer includes deep-level dopants
(e.g., 227) to compensate for contaminant species (e.g., 118, 350)
that are present due to chamber contamination and/or diffusion. The
flow rate of the deep-level dopant precursor (e.g., 121) is
typically lower than the precursors flow rate for the main
constituents of the nucleation layer and can be constant during the
growth of the nucleation layer, or it can be adjusted during the
growth. This flow rate can be reduced, even to zero, as the chamber
walls become coated with silicon, blocking desorption of
contaminant species from residue layers (e.g., 114) on the chamber
walls. These conditions produce a concentration of deep-level
dopants at the surface of the nucleation layer (e.g., 236, 436,
536, 636) nearest the one or more substrates (e.g., 102, 402, 502,
602) that is higher than the concentration at the surface of the
nucleation layer nearest the III-nitride layer (e.g., 348, 448,
548, 648). Thus, the concentration of deep-level dopants is graded
and tailored to be high in regions where the ionized acceptor
concentration is high and low where the ionized acceptor
concentration is low.
[0061] In some examples, the method 700 does not include flowing
deep-level dopant precursors (e.g., 121) into the epitaxial
chamber, and the nucleation layer (e.g, 236, 436, 536, 636) does
not contain deep-level dopants. In these examples, the nucleation
layer serves to provide a clean surface for growth of the
III-nitride layers (e.g., 348, 448, 548, 648) but does not
compensate for impurities present. The nucleation layer can provide
a clean surface by burying impurities and defects present on the
surface of the one or more substrates (e.g., 102).
[0062] At 710, the epitaxial chamber conditions are adjusted to
conditions for III-nitride growth. The wafer (e.g., 102, 402, 605,
602) is heated to a temperature of about 550-1100.degree. C. The
pressure in the chamber is adjusted to 40-760 Torr. A very low
pressure technique (<50 Torr) can be also employed. A purge gas
flow of H.sub.2, N.sub.2, or a mixture of both, is adjusted to
1-1000 slm. In some examples, no purge gas can be used. The group
III element precursors flow rate is controlled in the range of
10-500 .mu.mol/min. The group V element precursor flow rate is
controlled in the range of 0.001-10 mol/min. At 712, III-nitride
layers (e.g., 348, 448, 548, 648) are grown over the nucleation
layer. The III-nitride layers can include multiple layers, and can
include non-III-V components.
[0063] At 714, the epitaxial chamber conditions are adjusted for
unloading the one or more substrates. If the load-lock chamber is
used for the substrate loading, the epitaxial chamber conditions
are adjusted to the base state conditions. If the substrate
unloading is carried out directly from the epitaxial chamber, the
wafer (e.g., 102, 402, 605, 602) is cooled to about room
temperature, or at least below about 450.degree. C. An N.sub.2
purge gas flow is adjusted to near 0. At 716, the one or more
substrates are unloaded from the growth chamber.
[0064] Although the above description discloses III-nitride layers
over a substrate that contains silicon, other material combinations
are possible. The substrate can be made of one or more materials
other than silicon. For example, the substrate can include one or
more of sapphire, GaAs, GaN, InP, and other materials. The
substrate can include a heterostructure between the nucleation
layer and the III-nitride layer. The heterostructure may include
multiple layers of different materials.
[0065] Examples of heterostructures include Si-on-insulator (SOI)
and Si-on-sapphire (SOS) substrates. A nucleation layer could be
grown over an SOI or an SOS substrate. The nucleation layer could
be between the oxide layer and the Si layer, or above the Si layer,
in an SOI or an SOS substrate. The Si layer of the SOI or SOS
substrate could itself be the nucleation layer. The nucleation
layer could be grown directly on the sapphire or handle wafer. A
nucleation layer could be grown homogeneously with a layer of the
same material but involved in a process similar to a
heterostructure growth process, such as an epitaxial layer transfer
process. In such an epitaxial layer transfer process, the epitaxial
layer could comprise the nucleation layer. Thus, the epitaxial
layer could include a first portion with deep-level dopants and a
second portion that is unintentionally doped, or all of the
epitaxial layer could be doped with deep-level dopants of constant
or varying concentration.
[0066] In general, the nucleation layer can compensate either
acceptor or donor contaminants by containing either deep-level
donors or deep-level acceptors, respectively. The acceptor
contaminants and ionized acceptor contaminants may be replaced with
donor contaminants and ionized donor contaminants that provide free
electrons to the semiconductor. The deep-level dopants may then
include deep-level acceptor states which trap the free electrons,
thus reducing the concentration of free electrons in the
semiconductor.
[0067] A first layer described and/or depicted herein as "on" or
"over" a second layer can be immediately adjacent to the second
layer, or one or more intervening layers can be between the first
and second layers. A first layer that is described and/or depicted
herein as "directly on" or "directly over" a second layer or a
substrate is immediately adjacent to the second layer or substrate
with no intervening layer present, other than possibly an
intervening alloy layer that may form due to mixing of the first
layer with the second layer or substrate. In addition, a first
layer that is described and/or depicted herein as being "on,"
"over," "directly on," or "directly over" a second layer or
substrate may cover the entire second layer or substrate, or a
portion of the second layer or substrate.
[0068] A substrate is placed on a substrate holder during layer
growth, and so a top surface or an upper surface is the surface of
the substrate or layer furthest from the substrate holder, while a
bottom surface or a lower surface is the surface of the substrate
or layer nearest to the substrate holder.
[0069] From the above description of the method it is manifest that
various techniques may be used for implementing the concepts of the
method without departing from its scope. The described embodiments
are to be considered in all respects as illustrative and not
restrictive. It should also be understood that the method is not
limited to the particular examples described herein, but can be
implemented in other examples without departing from the scope of
the claims. Similarly, while operations are depicted in the
drawings in a particular order, this should not be understood as
requiring that such operations be performed in the particular order
shown or in sequential order, or that all illustrated operations be
performed, to achieve desirable results.
* * * * *