U.S. patent application number 15/258300 was filed with the patent office on 2018-03-08 for wafer stacking to form a multi-wafer-bonded structure.
This patent application is currently assigned to Raytheon Company. The applicant listed for this patent is Raytheon Company. Invention is credited to Andrew Cahill, Paul A. Drake, Jonathan Getty, Daniel D. Lofgreen.
Application Number | 20180068843 15/258300 |
Document ID | / |
Family ID | 58709583 |
Filed Date | 2018-03-08 |
United States Patent
Application |
20180068843 |
Kind Code |
A1 |
Cahill; Andrew ; et
al. |
March 8, 2018 |
WAFER STACKING TO FORM A MULTI-WAFER-BONDED STRUCTURE
Abstract
In one aspect, a method includes heating a wafer chuck, heating
a first wafer, depositing a first epoxy along at least a portion of
a surface of the first wafer disposed on the wafer chuck, spinning
the wafer chuck to spread the first epoxy at least partially across
the first wafer, placing a second wafer on the first epoxy disposed
on the first wafer and bonding the second wafer to the first epoxy
under vacuum to form a two-wafer-bonded structure.
Inventors: |
Cahill; Andrew; (Goleta,
CA) ; Getty; Jonathan; (Goleta, CA) ;
Lofgreen; Daniel D.; (Santa Maria, CA) ; Drake; Paul
A.; (Murrieta, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Raytheon Company |
Waltham |
MA |
US |
|
|
Assignee: |
Raytheon Company
Waltham
MA
|
Family ID: |
58709583 |
Appl. No.: |
15/258300 |
Filed: |
September 7, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/67132 20130101;
H01L 21/187 20130101; H01L 21/56 20130101; H01L 21/6835 20130101;
H01L 21/02282 20130101; H01L 25/50 20130101; H01L 21/324 20130101;
H01L 21/6836 20130101; H01L 21/185 20130101 |
International
Class: |
H01L 21/02 20060101
H01L021/02; H01L 21/56 20060101 H01L021/56; H01L 21/324 20060101
H01L021/324 |
Claims
1-15. (canceled)
16. A multi-wafer-bonded stack, comprising: a first wafer having a
first surface; and a second wafer having a first surface bonded to
the first surface of the first wafer by a first epoxy, wherein the
first epoxy covers an entirety of the first surface of the first
wafer and an entirety of the first surface of the second wafer,
wherein the first epoxy is free of voids.
17. The multi-wafer-bonded stack of claim 16, further comprising a
third wafer bonded to the first wafer by a second epoxy, wherein
the second epoxy is free of voids.
18. The multi-wafer-bonded stack of claim 17, wherein the first
wafer is one of a controlled expansion (CE) wafer, a stainless
steel wafer or a titanium wafer, and wherein the second wafer is a
readout integrated circuit (ROIC) wafer.
19. The multi-wafer-bonded stack of claim 18, wherein the third
wafer is silicon.
20. The multi-wafer-bonded stack of claim 18, wherein the ROIC
wafer comprises indium bumps.
21. The multi-wafer-bonded stack of claim 17, wherein the first
epoxy and the second epoxy can withstand cryogenic temperatures of
-150.degree. C. or less.
22. A multi-wafer-bonded stack, comprising: a first wafer having a
first surface and a second surface, wherein the first wafer is one
of a controlled expansion (CE) wafer, a stainless steel wafer or a
titanium wafer; a second wafer having a first surface bonded to the
first surface of the first wafer by a first epoxy, wherein the
second wafer is a readout integrated circuit (ROIC) wafer; and a
third wafer having a first surface bonded to the second surface of
the first wafer by a second epoxy, wherein the first epoxy is free
of voids, wherein the first epoxy covers an entirety of the first
surface of the first wafer and an entirety of the first surface of
the second wafer, and wherein the second epoxy is free of voids,
wherein the second epoxy covers an entirety of the first surface of
the third wafer and an entirety of the second surface of the first
wafer.
23. The multi-wafer-bonded stack of claim 22, wherein the third
wafer is silicon.
24. The multi-wafer-bonded stack of claim 22, wherein the ROIC
wafer comprises indium bumps.
25. The multi-wafer-bonded stack of claim 22, wherein the first
epoxy and the second epoxy can withstand cryogenic temperatures of
-150.degree. C. or less.
Description
BACKGROUND
[0001] Flip chip devices are generally fabricated using integrated
circuits (ICs) that are formed on a wafer. Pads are added to the
surface of the ICs and solder balls are added to the pads. The ICs
are removed (e.g., diced) from the wafer. Additional materials
(sometimes called shim structures) are sometimes added to the flip
chips to reduce flexing of the ICs, during heating and cooling or
being exposed to mechanical stresses, for example. Then, the ICs
are flipped and the solder balls are bonded to connectors of
external circuitry.
SUMMARY
[0002] In one aspect, a method includes heating a wafer chuck,
heating a first wafer, depositing a first epoxy along at least a
portion of a surface of the first wafer disposed on the wafer
chuck, spinning the wafer chuck to spread the first epoxy at least
partially across the first wafer, placing a second wafer on the
first epoxy disposed on the first wafer and bonding the second
wafer to the first epoxy under vacuum to form a two-wafer-bonded
structure.
[0003] In another aspect, a multi-wafer-bonded stack includes a
first wafer and a second wafer bonded to the first wafer by a first
epoxy. The first epoxy is free of voids.
DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a flow diagram of an example of a process to stack
wafers to form a multi-wafer-bonded structure.
[0005] FIG. 2 is a diagram of an example of a first wafer with an
epoxy.
[0006] FIGS. 3A and 3B are diagrams of a wafer chuck used to apply
the epoxy to the first wafer.
[0007] FIG. 4A is a diagram of a second wafer and the first
wafer.
[0008] FIG. 4B is a diagram of the second wafer attached to the
first wafer to form a two-wafer-bonded structure.
[0009] FIG. 5A is a diagram of a third wafer with epoxy and the
two-wafer-bonded structure.
[0010] FIG. 5B is a diagram of the third wafer attached to the
two-wafer-bonded structure to form a three-wafer-bonded
structure.
[0011] FIG. 6 is a diagram of a centering ring.
DETAILED DESCRIPTION
[0012] Described herein are techniques used in stacking wafers to
form a multi-wafer-bonded structure. Unlike traditional flip chip
fabrication, additional material may be added at a wafer level
(i.e., wafers are added) to the integrated circuits (ICs) to reduce
flexing of the ICs, for example, during heating and cooling or
being exposed to mechanical stresses as opposed to adding the
additional material (e.g., shim structures) at an IC level. In one
example, the process enables a large number of ICs (e.g., 40 ICs)
to be handled at once. In one example, a multi-wafer-bonded
structure is described herein that is thermally matched to the
detector material. In another example, the multi-wafer bonded
structure includes one or more bond layers (e.g., epoxy layers)
that are uniform and free of voids (e.g., air gaps, air pockets,
air bubbles and so forth). While the techniques described herein
describe fabricating a three-wafer-bonded structure, the techniques
described herein may be used to fabricate multi-wafer-bonded
structurers having two or more wafers.
[0013] Referring to FIG. 1, process 100 is an example of a process
to stack wafers to form a multi-wafer-bonded structure. Process 100
deposits a first epoxy along at least a portion of a surface of a
first wafer to form a first wafer structure (102). Process 100,
under vacuum, bonds a second wafer to the first epoxy of the first
wafer to form a two-wafer-bonded structure (106).
[0014] Process 100 deposits a second epoxy along at least a portion
of a surface of a third wafer to form a second wafer structure
(108). In one example, the second epoxy is applied to the third
wafer using the same technique used in processing block 102.
Process 100, under vacuum, bonds the second epoxy of the third
wafer to the first wafer (110). In one example, the second epoxy of
the third wafer is bonded to the first wafer using the same
technique used in processing block 106. In one example, the first
epoxy is the same material as the second epoxy.
[0015] Process 100 heats the three-wafer-bonded structure to cure
the first and second epoxies (112).
[0016] In one example, the first and third wafers have about the
same coefficient of thermal expansion (CTE), while the second wafer
has a different CTE. In one example, the first, second and third
wafers are 8-inch wafers; however, the processes described herein
could be applied to a number of different-sized wafers. In some
examples, thicknesses of the wafers selected may vary.
[0017] In one example, after process 100 is completed the
three-wafer bonded structure is diced and attached to a
detector.
[0018] Referring to FIGS. 2, 3A and 3B, in one example, a one-wafer
structure 200 is formed that includes a wafer 214 and an epoxy 216.
In one example, the one-wafer structure 200 is formed by applying
the epoxy 216 to a heated wafer 214 on a heated spinning wafer
chuck 222 (FIG. 3A). In one example, the wafer chuck 222 and the
wafer 214 are heated to about 65.degree. C. In one example, the
wafer chuck 222 and the wafer 214 are heated separately using a hot
plate. In one example, the wafer chuck 222 spins at 500 rpms for 4
seconds as the epoxy is applied. In one example, the epoxy is a
bonding epoxy that can withstand cryogenic temperatures (e.g.,
-150.degree. C. or less).
[0019] The speed of the wafer chuck 222 is increased, for example,
allowing the epoxy 216 to be evenly distributed across the wafer
214 (FIG. 3B). In one example, the wafer chuck 222 spins at 5,000
rpms for 30 seconds.
[0020] In one example, the wafer 214 is a controlled expansion (CE)
wafer. In another example, the wafer 214 is a stainless steel
wafer. In a further example, the wafer 214 is a titanium wafer.
[0021] Referring to FIGS. 4A and 4B, a wafer 234 has a layer 236.
The wafer 234 is applied to the wafer structure 200. In one
example, the layer 236 includes bumps (e.g., indium bumps, not
shown) covered with photoresist. In one example, the wafer 234 is a
readout integrated circuit (ROIC) wafer. In one example, the bumps
are used for bonding to external circuitry (not shown), for
example, a detector (e.g., a flip chip device).
[0022] Prior to vacuum, contact between the wafer 234 and the epoxy
216 is minimized as much as possible. In one example, the wafer 234
is placed on or is positioned slightly above the epoxy 216. In one
particular example, a centering ring (e.g., a centering ring 600
(FIG. 6)) is used to suspend the wafer 234 over the epoxy 216. For
example, when the wafer 234 is allowed to naturally fall (e.g.,
from an inch or less above the epoxy 216) onto the surface of the
epoxy 216, the wafer 234 is suspended by air pockets like a hockey
puck on ice, for example. In another example, an arm, (e.g., a
robotic arm) is used to suspend the wafer 234 over the epoxy 216.
The wafer 234 and the wafer structure 200 are placed under vacuum
(e.g., using a vacuum oven) so that the wafer 234 is bonded to the
epoxy 216 to form a two-wafer-bonded structure 300 with no voids in
the epoxy 216 as shown in FIG. 4B.
[0023] Referring to FIGS. 5A and 5B, a one-wafer structure 400
includes a wafer 444 and an epoxy 446. In one example, the
one-wafer structure 400 is formed in the same manner as the
one-wafer structure 200 described herein. In one example, the epoxy
446 is about the same thickness as epoxy 216. In a further example,
the epoxy is a bonding epoxy that can withstand cryogenic
temperatures (e.g., -150.degree. C. or less). In one example, the
wafer 444 is a silicon wafer.
[0024] Prior to vacuum, contact between the wafer 214 and the epoxy
446 is minimized as much as possible. In one example, the
epoxy-coated side of the wafer 444 is placed on or is positioned
slightly above the wafer 214. In one particular example, a
centering ring (e.g., the centering ring 600 (FIG. 6)) is used to
suspend the wafer 444 over the wafer 214. The wafer structure 400
and the wafer structure 300 are placed under vacuum (e.g., using a
vacuum oven) so that the wafer 214 is bonded to the epoxy 446 to
form a three-wafer-bonded structure 500.
[0025] The three-wafer-bonded structure 500 is heated to cure the
epoxy 216 and the epoxy 446. For example, the three-wafer-bonded
structure 500 is heated using a hot plate.
[0026] Referring to FIG. 6, one example of a centering ring is the
centering ring 600. The centering ring includes gaps (e.g., a gap
602a, a gap 602b) used to allow a person to use fingers to center a
wafer over another wafer or wafer structure (e.g., center the wafer
234 over the wafer structure 200, center the wafer 444 over the
two-wafer structure 300 and so forth).
[0027] The processes described herein are not limited to the
specific examples described. For example, while the processes
described herein fabricate a three-wafer-bonded structure other
techniques may be used to fabricate any wafer-bonded structure
having two or more wafers. In other examples, the process 100 is
not limited to the specific processing order of FIG. 1. Rather, any
of the processing blocks of FIG. 1 may be re-ordered, combined or
removed, performed in parallel or in serial, as necessary, to
achieve the results set forth above.
[0028] The processes described herein are not limited to the
specific embodiments described. Elements of different embodiments
described herein may be combined to form other embodiments not
specifically set forth above. Other embodiments not specifically
described herein are also within the scope of the following
claims.
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