U.S. patent application number 15/600866 was filed with the patent office on 2018-02-22 for high loop-gain phemt regulator for linear rf power amplifier.
The applicant listed for this patent is Qorvo US, Inc.. Invention is credited to David Antopolsky, Peng Cheng, Swaminathan Muthukrishnan, Randy Naylor, Nancy Schaefer, Jeremiah J. Smith.
Application Number | 20180054167 15/600866 |
Document ID | / |
Family ID | 61192349 |
Filed Date | 2018-02-22 |
United States Patent
Application |
20180054167 |
Kind Code |
A1 |
Cheng; Peng ; et
al. |
February 22, 2018 |
HIGH LOOP-GAIN PHEMT REGULATOR FOR LINEAR RF POWER AMPLIFIER
Abstract
Voltage regulator circuitry includes a first gain stage, a
second gain stage, and a feedback stage. Feedback is provided
between the feedback stage, the second gain stage, and the first
gain stage in order to tightly regulate an output voltage of the
voltage regulator circuitry such that the output voltage is
independent of process variations present in the devices therein.
The voltage regulator circuitry is fabricated using a pseudomorphic
high electron mobility transistor (pHEMT) process in order to
reduce the size thereof and provide short turn-on times and low
quiescent current.
Inventors: |
Cheng; Peng; (Greensboro,
NC) ; Muthukrishnan; Swaminathan; (Waltham, MA)
; Antopolsky; David; (Sandy Springs, GA) ; Smith;
Jeremiah J.; (Richland, MI) ; Schaefer; Nancy;
(Ashland, MA) ; Naylor; Randy; (Pepperell,
MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Qorvo US, Inc. |
Greensboro |
NC |
US |
|
|
Family ID: |
61192349 |
Appl. No.: |
15/600866 |
Filed: |
May 22, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62377966 |
Aug 22, 2016 |
|
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|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03G 1/0052 20130101;
H03F 1/0216 20130101; G05F 1/575 20130101; H03F 3/72 20130101; H03G
3/3042 20130101; H03F 3/195 20130101; H03F 3/245 20130101 |
International
Class: |
H03F 1/02 20060101
H03F001/02; H03F 3/195 20060101 H03F003/195; H03F 3/24 20060101
H03F003/24; H03F 3/72 20060101 H03F003/72; H03G 3/00 20060101
H03G003/00; H03G 3/30 20060101 H03G003/30 |
Claims
1. Voltage regulator circuitry comprising: a first gain stage
comprising: a first transistor comprising a gate contact, a drain
contact coupled to a supply voltage node, and a source contact
coupled to a regulated output voltage node and to the gate contact
via a current setting resistor; and a second transistor comprising
a gate contact, a drain contact coupled to the gate contact of the
first transistor, and a source contact coupled to a ground node; a
second gain stage comprising: a third transistor comprising a gate
contact, a drain contact coupled to the gate contact of the second
transistor, and a source contact coupled to the ground node; and a
plurality of stacked gain stage diodes coupled in series between
the regulated output voltage node and the drain contact of the
third transistor such that an anode of a first one of the plurality
of stacked gain stage diodes is coupled to the regulated output
voltage node and a cathode of a last one of the plurality of
stacked gain stage diodes is coupled to the drain contact of the
third transistor; and a feedback stage comprising: a feedback
resistor coupled between the gate contact of the third transistor
and the ground node; and a plurality of stacked feedback diodes
coupled between the regulated output voltage node and the feedback
resistor such that an anode of a first one of the plurality of
stacked feedback diodes is coupled to the regulated output voltage
node and a cathode of a last one of the plurality of stacked
feedback diodes is coupled to the feedback resistor.
2. The voltage regulator circuitry of claim 1 wherein: the first
transistor is a depletion mode pseudomorphic high electron mobility
transistor (pHEMT); the second transistor and the third transistor
are enhancement mode pHEMTs; each one of the plurality of stacked
gain stage diodes is an enhancement mode pHEMT comprising a gate
contact, a source contact coupled to the gate contact, and a drain
contact, wherein the drain contact corresponds to an anode and the
connected gate contact and source contact correspond to a cathode;
and each one of the plurality of stacked feedback diodes is a
depletion mode pHEMT comprising a gate contact, a drain contact,
and a source contact coupled to the drain contact, wherein the gate
contact corresponds to an anode and the connected source contact
and drain contact correspond to a cathode.
3. The voltage regulator circuitry of claim 2 further comprising: a
first bypass transistor comprising a gate contact coupled to an
enable signal node, a drain contact coupled to a power supply
voltage, and a source contact coupled to the supply voltage node;
and a second bypass transistor comprising a gate contact coupled to
the enable signal node, a drain contact coupled to the ground node,
and a source contact coupled to a fixed potential.
4. The voltage regulator circuitry of claim 3 wherein: the first
bypass transistor is a depletion mode pHEMT; and the second bypass
transistor is an enhancement mode pHEMT.
5. The voltage regulator circuitry of claim 1 further comprising: a
first bypass transistor comprising a gate contact coupled to an
enable signal node, a drain contact coupled to a power supply
voltage, and a source contact coupled to the supply voltage node;
and a second bypass transistor comprising a gate contact coupled to
the enable signal node, a drain contact coupled to the ground node,
and a source contact coupled to a fixed potential.
6. The voltage regulator circuitry of claim 5 wherein: the first
bypass transistor is a depletion mode pHEMT; and the second bypass
transistor is an enhancement mode pHEMT.
7. The voltage regulator circuitry of claim 1 wherein a gain of the
voltage regulator is independent of a pinchoff voltage and a
transconductance of the first transistor, the second transistor,
and the third transistor.
8. Voltage regulator circuitry comprising: a first gain stage
comprising: a first transistor comprising a gate contact, a drain
contact coupled to a supply voltage node, and a source contact
coupled to a regulated output voltage node and to the gate contact
via a current setting resistor; and a second transistor comprising
a gate contact, a drain contact coupled to the gate contact of the
first transistor, and a source contact coupled to a ground node; a
second gain stage comprising: a third transistor comprising a gate
contact, a drain contact coupled to the gate contact of the second
transistor, and a source contact coupled to the ground node; and a
first plurality of stacked gain stage diodes coupled in series
between the regulated output voltage node and the drain contact of
the third transistor such that an anode of a first one of the first
plurality of stacked gain stage diodes is coupled to the regulated
output voltage node and a cathode of a last one of the first
plurality of stacked gain stage diodes is coupled to the drain
contact of the third transistor; a third gain stage comprising: a
fourth transistor comprising a gate contact, a drain contact
coupled to the gate contact of the third transistor, and a source
contact coupled to the ground node; and a second plurality of
stacked gain stage diodes coupled in series between the regulated
output voltage node and the drain contact of the fourth transistor
such that an anode of a first one of the second plurality of
stacked gain stage diodes is coupled to the regulated output
voltage node and a cathode of a last one of the second plurality of
stacked gain stage diodes is coupled to the drain contact of the
fourth transistor; and a feedback stage comprising: a feedback
resistor coupled between the gate contact of the fourth transistor
and the ground node; and a plurality of stacked feedback diodes
coupled between the regulated output voltage node and the feedback
resistor such that an anode of a first one of the plurality of
stacked feedback diodes is coupled to the regulated output voltage
node and a cathode of a last one of the plurality of stacked
feedback diodes is coupled to the feedback resistor.
9. The voltage regulator circuitry of claim 8 wherein: the first
transistor is a depletion mode pseudomorphic high electron mobility
transistor (pHEMT); the second transistor, the third transistor,
and the fourth transistor are enhancement mode pHEMTs; each one of
the first plurality of stacked gain stage diodes and the second
plurality of stacked gain stage diodes is an enhancement mode pHEMT
comprising a gate contact, a source contact coupled to the gate
contact, and a drain contact, wherein the drain contact corresponds
to an anode and the connected gate contact and drain contact
correspond to a cathode; and each one of the plurality of stacked
feedback diodes is a depletion mode pHEMT comprising a gate
contact, a drain contact, and a source contact coupled to the drain
contact, wherein the gate contact corresponds to an anode and the
connected source contact and drain contact correspond to a
cathode.
10. The voltage regulator circuitry of claim 9 further comprising:
a first bypass transistor comprising a gate contact coupled to an
enable signal node, a drain contact coupled to a power supply
voltage, and a source contact coupled to the supply voltage node;
and a second bypass transistor comprising a gate contact coupled to
the enable signal node, a drain contact coupled to the ground node,
and a source contact coupled to a fixed potential.
11. The voltage regulator circuitry of claim 10 wherein: the first
bypass transistor is a depletion mode pHEMT; and the second bypass
transistor is an enhancement mode pHEMT.
12. The voltage regulator circuitry of claim 11 further comprising
a stabilizer capacitor coupled between the drain contact of the
third transistor and the gate contact of the third transistor.
13. The voltage regulator circuitry of claim 10 further comprising
a stabilizer capacitor coupled between the drain contact of the
third transistor and the gate contact of the third transistor.
14. The voltage regulator circuitry of claim 8 further comprising:
a first bypass transistor comprising a gate contact coupled to an
enable signal node, a drain contact coupled to a power supply
voltage, and a source contact coupled to the supply voltage node;
and a second bypass transistor comprising a gate contact coupled to
the enable signal node, a drain contact coupled to the ground node,
and a source contact coupled to a fixed potential.
15. The voltage regulator circuitry of claim 14 wherein: the first
bypass transistor is a depletion mode pHEMT; and the second bypass
transistor is an enhancement mode pHEMT.
16. The voltage regulator circuitry of claim 15 further comprising
a stabilizer capacitor coupled between the drain contact of the
third transistor and the gate contact of the third transistor.
17. The voltage regulator circuitry of claim 14 further comprising
a stabilizer capacitor coupled between the drain contact of the
third transistor and the gate contact of the third transistor.
18. The voltage regulator circuitry of claim 8 further comprising a
stabilizer capacitor coupled between the drain contact of the third
transistor and the gate contact of the third transistor.
19. The voltage regulator circuitry of claim 18 wherein a gain of
the voltage regulator is independent of a pinchoff voltage and a
transconductance of the first transistor, the second transistor,
the third transistor, and the fourth transistor.
20. The voltage regulator circuitry of claim 8 wherein a gain of
the voltage regulator is independent of a pinchoff voltage and a
transconductance of the first transistor, the second transistor,
the third transistor, and the fourth transistor.
Description
RELATED APPLICATIONS
[0001] This application claims the benefit of provisional patent
application Ser. No. 62/377,966, filed Aug. 22, 2016, the
disclosure of which is hereby incorporated herein by reference in
its entirety.
FIELD OF THE DISCLOSURE
[0002] The present disclosure relates to voltage regulator
circuitry, and specifically to voltage regulator circuitry for
radio frequency (RF) power amplifiers.
BACKGROUND
[0003] Modern radio frequency (RF) systems generally require highly
linear RF power amplifiers in order to properly transmit signals.
To provide high linearity, RF power from an RF power amplifier must
remain constant over the entirety of a data frame despite changes
in duty cycle, ambient temperature, and supply voltage. Maintaining
a constant RF power generally requires a tightly controlled bias
signal to be provided to the RF power amplifier, which may be
difficult due to the dynamic signal environments in which modern RF
systems exist. Maintaining tight control over the bias signal will
generally reduce the error vector magnitude and other metrics of
linearity such as amplitude modulation AM to AM distortion of the
RF power amplifier and therefore allow the amplifier to meet the
stringent specifications of modern wireless communications
standards such as WiFi.
[0004] A power amplifier voltage regulator is generally responsible
for providing a bias signal to a power amplifier. As discussed
above, it is desirable for a power amplifier voltage regulator to
provide a highly stable bias signal that is not affected by process
variation of one or more components therein. Further, it is
desirable for a power amplifier voltage regulator to maintain a
temperature slope that is suited for the bias circuits of the power
amplifier with which it is used, achieve very short turn-on time
such that the power amplifier is able to accurately amplify
preambles of data frames, have a small size, and consume a low
quiescent current to reduce battery drain (e.g., less than 0.5
.mu.A). Generally, it is very difficult to design a power amplifier
voltage regulator that meets all of these criteria.
[0005] FIG. 1 is a functional schematic illustrating an idealized
power amplifier voltage regulator 10. The idealized power amplifier
voltage regulator 10 includes an operational amplifier 12, a first
feedback resistor R.sub.F, and a second feedback resistor R.sub.G.
The operational amplifier 12 includes a power supply voltage node
N.sub.VPS, a non-inverting input node N.sub.NI, an inverting input
node N.sub.I, and an output node N.sub.REG. A power supply voltage
V.sub.PS is provided to the power supply voltage node N.sub.VPS. An
input voltage V.sub.IN is provided to the non-inverting input node
N.sub.NI, and may be equal to the power supply voltage V.sub.PS. A
regulated output voltage V.sub.REG is provided at the output node
N.sub.REG. The inverting input node N.sub.I is coupled to the
junction between the first feedback resistor R.sub.F and the second
feedback resistor R.sub.G and thus receives a feedback signal
therefrom. Given the feedback structure of the idealized power
amplifier voltage regulator 10, the gain of the device can be
expressed by Equation (1):
G = V REG V I N = 1 + ( R F R G ) ( 1 ) ##EQU00001##
Those skilled in the art will appreciate that the operational
amplifier 12 will attempt to equalize the voltage at the
non-inverting input node N.sub.NI and the inverting input node
N.sub.I via the feedback formed between the output node N.sub.REG
and the inverting input node N.sub.I. The feedback provided at the
inverting input node N.sub.I effectively ensures that the regulated
output voltage V.sub.REG is tightly controlled regardless of
process variations inherent in the operational amplifier 12 and
tracks ambient temperature. If the operational amplifier 12 acts
ideally, then it will also provide short turn-on times and
relatively low quiescent current consumption.
[0006] Implementing the idealized voltage regulator circuitry in a
mobile device is a challenging task. Generally, standard
operational amplifiers are created via CMOS processes and are too
large for mobile applications. Accordingly, there is a need for
voltage regulator circuitry for a mobile device with a small
footprint that provides a tightly controlled output voltage that
tracks ambient temperature, short turn-on times, and low quiescent
current consumption.
SUMMARY
[0007] The present disclosure relates to voltage regulator
circuitry, and specifically to voltage regulator circuitry for
linear radio frequency (RF) power amplifiers. In one embodiment,
voltage regulator circuitry includes a first gain stage, a second
gain stage, and a feedback stage. The first gain stage includes a
first transistor with a gate contact, a drain contact coupled to a
supply voltage node, and a source contact coupled to a regulated
output voltage node and to the gate contact via a current setting
resistor and a second transistor with a gate contact, a drain
contact coupled to the gate contact of the first transistor, and a
source contact coupled to a ground node. The second gain stage
includes a third transistor with a gate contact, a drain contact
coupled to the gate contact of the second transistor, and a source
contact coupled to the ground node and a number of stacked gain
stage diodes coupled in series between the regulated output voltage
node and the drain contact of the third transistor such that an
anode of a first one of the stacked gain stage diodes is coupled to
the regulated output voltage node and a cathode of a last one of
the stacked gain stage diodes is coupled to the drain contact of
the third transistor. The feedback stage includes a feedback
resistor coupled between the gate contact of the third transistor
and the ground node and a number of stacked feedback diodes coupled
between the regulated output voltage node and the feedback resistor
such that an anode of a first one of the stacked feedback diodes is
coupled to the regulated output voltage node and a cathode of a
last one of the stacked feedback diodes is coupled to the feedback
resistor. Providing the voltage regulator circuitry in this manner
reduces the dependency of a regulated output voltage provided
therefrom on process variations that may occur in the components of
the circuitry.
[0008] In one embodiment, the first transistor, the second
transistor, and the third transistor are pseudomorphic high
electron mobility transistors (pHEMTs). Accordingly, the voltage
regulator circuitry may have a small footprint while providing
short turn-on times and low quiescent current consumption.
[0009] Those skilled in the art will appreciate the scope of the
present disclosure and realize additional aspects thereof after
reading the following detailed description of the preferred
embodiments in association with the accompanying drawing
figures.
BRIEF DESCRIPTION OF THE DRAWING FIGURES
[0010] The accompanying drawing figures incorporated in and forming
a part of this specification illustrate several aspects of the
disclosure, and together with the description serve to explain the
principles of the disclosure.
[0011] FIG. 1 is a functional schematic illustrating an idealized
voltage regulator.
[0012] FIG. 2 is a functional schematic illustrating voltage
regulator circuitry according to one embodiment of the present
disclosure.
[0013] FIG. 3 is a functional schematic illustrating voltage
regulator circuitry according to one embodiment of the present
disclosure.
DETAILED DESCRIPTION
[0014] The embodiments set forth below represent the necessary
information to enable those skilled in the art to practice the
embodiments and illustrate the best mode of practicing the
embodiments. Upon reading the following description in light of the
accompanying drawing figures, those skilled in the art will
understand the concepts of the disclosure and will recognize
applications of these concepts not particularly addressed herein.
It should be understood that these concepts and applications fall
within the scope of the disclosure and the accompanying claims.
[0015] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are only
used to distinguish one element from another. For example, a first
element could be termed a second element, and, similarly, a second
element could be termed a first element, without departing from the
scope of the present disclosure. As used herein, the term "and/or"
includes any and all combinations of one or more of the associated
listed items.
[0016] It will be understood that when an element such as a layer,
region, or substrate is referred to as being "on" or extending
"onto" another element, it can be directly on or extend directly
onto the other element or intervening elements may also be present.
In contrast, when an element is referred to as being "directly on"
or extending "directly onto" another element, there are no
intervening elements present. Likewise, it will be understood that
when an element such as a layer, region, or substrate is referred
to as being "over" or extending "over" another element, it can be
directly over or extend directly over the other element or
intervening elements may also be present. In contrast, when an
element is referred to as being "directly over" or extending
"directly over" another element, there are no intervening elements
present. It will also be understood that when an element is
referred to as being "connected" or "coupled" to another element,
it can be directly connected or coupled to the other element or
intervening elements may be present. In contrast, when an element
is referred to as being "directly connected" or "directly coupled"
to another element, there are no intervening elements present.
[0017] Relative terms such as "below" or "above" or "upper" or
"lower" or "horizontal" or "vertical" may be used herein to
describe a relationship of one element, layer, or region to another
element, layer, or region as illustrated in the Figures. It will be
understood that these terms and those discussed above are intended
to encompass different orientations of the device in addition to
the orientation depicted in the Figures.
[0018] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the disclosure. As used herein, the singular forms "a," "an," and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises," "comprising," "includes," and/or
"including" when used herein specify the presence of stated
features, integers, steps, operations, elements, and/or components,
but do not preclude the presence or addition of one or more other
features, integers, steps, operations, elements, components, and/or
groups thereof.
[0019] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this
disclosure belongs. It will be further understood that terms used
herein should be interpreted as having a meaning that is consistent
with their meaning in the context of this specification and the
relevant art and will not be interpreted in an idealized or overly
formal sense unless expressly so defined herein.
[0020] FIG. 2 shows voltage regulator circuitry 14 according to one
embodiment of the present disclosure. The voltage regulator
circuitry 14 includes a gain stage 16 and a feedback stage 18. The
gain stage 16 includes a first transistor Q.sub.1, a current
setting resistor R.sub.CS, a second transistor Q2, and a third
transistor Q.sub.3. The first transistor Q.sub.1 includes a gate
contact (G), a drain contact (D) coupled to a power supply voltage
node N.sub.VPS, and a source contact (S) coupled to the gate
contact (G) via the current setting resistor R.sub.CS and coupled
to a regulated output voltage node N.sub.VREG. The second
transistor Q.sub.2 includes a gate contact (G), a drain contact (D)
coupled to the source contact (S) of the first transistor Q.sub.1,
and a source contact (S). The third transistor Q.sub.3 includes a
gate contact (G), a drain contact (D) coupled to the source contact
(S) of the second transistor Q.sub.2, and a source contact coupled
to a ground node N.sub.G.
[0021] A first bypass transistor Q.sub.BP1 may be coupled between a
power supply voltage V.sub.PS and the power supply voltage node
N.sub.VPS. Specifically, a drain contact (D) of the first bypass
transistor Q.sub.BP1 may receive the power supply voltage V.sub.PS
and a source contact (S) may be coupled to the power supply voltage
node N.sub.VPS. A gate contact (G) of the first bypass transistor
Q.sub.BP1 may be coupled to an enable signal node N.sub.EN. A
second bypass transistor Q.sub.BP2 may be coupled between the
ground node N.sub.G and a fixed potential (e.g., ground).
Specifically, a drain contact (D) of the second bypass transistor
Q.sub.BP2 may be coupled to the ground node N.sub.G and a source
contact (S) may be coupled to a fixed potential (e.g., ground). A
gate contact (G) of the second bypass transistor Q.sub.BP2 may be
coupled to the enable signal node N.sub.EN via a reverse diode
connected transistor Q.sub.RD, which is configured to limit the
turn-on gate current provided from the enable signal node N.sub.EN
to the second bypass transistor Q.sub.BP2. The reverse diode
connected transistor Q.sub.RD may include a gate contact (G), a
drain contact (D) coupled to the enable signal node N.sub.EN, and a
source contact (S) coupled to the gate contact (G) of both the
second bypass transistor Q.sub.BP2 and the reverse diode connected
transistor Q.sub.RD.
[0022] The feedback stage 18 includes a feedback resistor R.sub.FB
and a stack of feedback diodes D.sub.FB. The feedback resistor
R.sub.FB is coupled between the gate contact (G) of the second
transistor Q.sub.2 and the gate contact (G) of the third transistor
Q.sub.3. The stack of feedback diodes D.sub.FB are coupled between
the regulated output voltage node N.sub.VREG and the gate contact
(G) of the second transistor Q.sub.2. Each one of the feedback
diodes D.sub.FB in the stack of feedback diodes may be a transistor
comprising a gate contact (G) corresponding to an anode of the
device, and a source contact (S) coupled to a drain contact (D)
corresponding to a cathode of the device. While only two feedback
diodes D.sub.FB are shown, any number of feedback diodes D.sub.FB
may be included in the stack of feedback diodes D.sub.FB.
[0023] The first transistor Q.sub.1, the second transistor Q.sub.2,
and the third transistor Q3 may be pseudomorphic high electron
mobility transistors (pHEMTs) in some embodiments. Specifically,
the first transistor Q.sub.1 and the third transistor Q.sub.3 may
be depletion mode pHEMTs, and the second transistor Q.sub.2 may be
an enhancement mode pHEMT. The first bypass transistor Q.sub.BP1,
the second bypass transistor Q.sub.BP2, and the reverse diode
connected transistor Q.sub.RD may also be pHEMTs. Specifically, the
first bypass transistor Q.sub.BP1 and the reverse connected diode
transistor Q.sub.RD may be a depletion mode pHEMT, and the second
bypass transistor Q.sub.BP2 may be an enhancement mode pHEMT. Each
one of the feedback diodes D.sub.FB may also be pHEMT devices.
Specifically, each one of the feedback diodes D.sub.FB may be
depletion mode pHEMT devices. Those skilled in the art will
appreciate that connecting a drain contact (D) and a source contact
(S) of a depletion mode pHEMT effectively creates a device that
behaves similar to a Schottky diode between a gate contact (G)
corresponding to an anode and the connected drain contact (D) and
source contact (S) corresponding to a cathode thereof.
[0024] As discussed above, the first bypass transistor Q.sub.BP1
may be a depletion mode pHEMT, while the second bypass transistor
Q.sub.BP2 may be an enhancement mode pHEMT. Accordingly, when no
enable signal EN is present at the enable signal node N.sub.EN, the
first bypass transistor Q.sub.BP1 may be in an on state while the
second bypass transistor Q.sub.BP2 is in an off state. Because the
second bypass transistor Q.sub.BP2 is in an off state, current
cannot flow through the gain stage 16, and the voltage regulator
circuitry 14 is powered off. When an enable signal EN suitable for
maintaining both the first bypass transistor Q.sub.BP1 and the
second bypass transistor Q.sub.BP2 in an off state is provided to
the enable signal node N.sub.EN, the voltage regulator circuitry 14
is similarly powered off. Maintaining the second bypass transistor
Q.sub.BP2, or the first bypass transistor Q.sub.BP1 and the second
bypass transistor Q.sub.BP2 in an off state prevents the
consumption of current when the device is inactive and thus may
prolong battery life of a mobile device in which the voltage
regulator circuitry 14 is provided. When an enable signal EN
suitable for turning on the first bypass transistor Q.sub.BP1 and
the second bypass transistor Q.sub.BP2, either partially or
completely, is provided to the enable signal node N.sub.EN, the
voltage regulator circuitry 14 is powered on. In some embodiments,
the enable signal EN in the active state is equal to the power
supply voltage V.sub.PS, however, any suitable enable signal EN may
be provided to power on the voltage regulator circuitry 14 without
departing from the principles of the present disclosure. As
discussed above, the reverse connected diode transistor Q.sub.RD
may limit the current flow from the enable signal node N.sub.EN to
the gate contact (G) of the second bypass transistor Q.sub.BP2 when
the voltage regulator circuitry 14 is powered on.
[0025] When the first bypass transistor Q.sub.BP1 and the second
bypass transistor Q.sub.BP2 are closed, the gain stage 16 is placed
between the power supply voltage V.sub.PS (or a portion thereof,
depending on the amount that the first bypass transistor Q.sub.BP1
is turned on) and a fixed potential (e.g., ground). The power
supply voltage V.sub.PS provided at the drain contact (D) of the
first transistor Q.sub.1 will turn on the device, providing a
portion of the supply voltage V.sub.PS to the regulated output
voltage node N.sub.VREG. This portion of the power supply voltage
V.sub.PS will be dropped across the current setting resistor
R.sub.CS and provided back to the gate contact (G) of the first
transistor Q.sub.1. This feedback loop effectively makes the first
transistor Q.sub.1 act as an active load and current source for the
second transistor Q.sub.2, such that a substantially constant
current is provided to the drain contact (D) of the second
transistor Q.sub.2.
[0026] The portion of the power supply voltage V.sub.PS provided at
the regulated output voltage node N.sub.VREG is further dropped
across the stacked feedback diodes D.sub.FB and provided to the
gate contact (G) of the second transistor Q.sub.2. Each one of the
stacked feedback diodes D.sub.FB effectively provides a voltage
drop that is dependent on temperature so as to provide a desired
relationship of a regulated output voltage V.sub.REG present at the
regulated output voltage node N.sub.VREG to ambient temperature.
The voltage across the stacked feedback diodes D.sub.FB is fed into
the gate contact (G) of the second transistor Q.sub.2 to
effectively create a feedback loop. Further, the voltage across the
stacked feedback diodes D.sub.FB is dropped across the feedback
resistor R.sub.FB and fed into the gate contact (G) of the third
transistor Q.sub.3, which in turn effectively provides a source
degeneration impedance for the second transistor Q.sub.2 in order
to increase the linearity thereof. The feedback between the source
contact (S) and the gate contact (G) of the first transistor
Q.sub.1, between the regulated output voltage node N.sub.VREG and
the second transistor Q.sub.2, and between the regulated output
voltage node N.sub.VREG and the third transistor Q.sub.3 may reduce
the impact of process variation on the regulated output voltage
V.sub.REG provided from the voltage regulator circuitry 14 and
provide a desired relationship between the regulated output voltage
V.sub.REG and ambient temperature.
[0027] Due to the fact that the voltage regulator circuitry 14 is
created using a pHEMT process, the size of the circuitry may be
minimized. Further, the pHEMT process and circuit topology may
provide short turn-on times and low quiescent current consumption.
Despite these benefits, the voltage regulator circuitry 14 shown in
FIG. 2 may fail to provide an adequate gain response. Accordingly,
FIG. 3 shows voltage regulator circuitry 20 according to an
additional embodiment of the present disclosure. The voltage
regulator circuitry 20 includes a first gain stage 22, a second
gain stage 24, a third gain stage 26, and a feedback stage 28.
[0028] The first gain stage 22 includes a first transistor Q.sub.1,
a current setting resistor R.sub.CS, and a second transistor
Q.sub.2. The first transistor Q.sub.1 includes a gate contact (G),
a drain contact (D) coupled to a power supply voltage node
N.sub.VPS, and a source contact (S) coupled to the gate contact (G)
via the current setting resistor R.sub.CS and coupled to a
regulated output voltage node N.sub.VREG. The second transistor
Q.sub.2 includes a gate contact (G), a drain contact (D) coupled to
the source contact (S) of the first transistor Q.sub.1, and a
source contact (S) coupled to a ground node N.sub.G.
[0029] A first bypass transistor Q.sub.BP1 may be coupled between a
power supply voltage V.sub.PS and the power supply voltage node
N.sub.VPS. Specifically, a drain contact (D) of the first bypass
transistor Q.sub.BP1 may receive the power supply voltage V.sub.PS
and a source contact (S) may be coupled to the power supply voltage
node N.sub.VPS. A gate contact (G) of the first bypass transistor
Q.sub.BP1 may be coupled to an enable signal node N.sub.EN. A
second bypass transistor Q.sub.BP2 may be coupled between the
ground node N.sub.G and a fixed potential (e.g., ground).
Specifically, a drain contact (D) of the second bypass transistor
Q.sub.BP2 may be coupled to the ground node N.sub.G and a source
contact (S) may be coupled to a fixed potential (e.g., ground). A
gate contact (G) of the second bypass transistor Q.sub.BP2 may be
coupled to the enable signal node N.sub.EN via a reverse connected
diode transistor Q.sub.RD, which is configured to limit the turn-on
gate current provided from the enable signal node N.sub.EN to the
second bypass transistor Q.sub.BP2. The reverse connected diode
transistor Q.sub.RD may include a gate contact (G), a drain contact
(D) coupled to the enable signal node N.sub.EN, and a source
contact (S) coupled to the gate contact (G) of both the second
bypass transistor Q.sub.BP2 and the reverse connected diode
transistor Q.sub.RD.
[0030] The second gain stage 24 includes a first stack of gain
stage diodes D.sub.GS and a third transistor Q.sub.3. The first
stack of gain stage diodes D.sub.GS are coupled anode-to-cathode
between the regulated output voltage node N.sub.VREG and the gate
contact (G) of the second transistor Q.sub.2. The third transistor
Q.sub.3 includes a gate contact (G), a drain contact (D) coupled to
the gate contact (G) of the second transistor Q.sub.2, and a source
contact (S) coupled to the ground node N.sub.G. In some
embodiments, a stabilizer capacitor C.sub.ST is coupled between the
gate contact (G) and the drain contact (D) of the third transistor
Q.sub.3.
[0031] The third gain stage 26 is similar to the second gain stage
24 and includes a second stack of gain stage diodes D.sub.GS and a
fourth transistor Q.sub.4. The second stack of gain stage diodes
D.sub.GS are coupled anode-to-cathode between the regulated output
voltage node N.sub.VREG and the gate contact (G) of the third
transistor Q.sub.3. The fourth transistor Q.sub.4 includes a gate
contact (G), a drain contact (D) coupled to the gate contact (G) of
the third transistor Q.sub.3, and a source contact (S) coupled to
the ground node N.sub.G.
[0032] The feedback stage 28 includes a stack of feedback diodes
D.sub.FB and a feedback resistor R.sub.FB. The stack of feedback
diodes D.sub.FB are coupled anode-to-cathode between the regulated
output voltage node N.sub.VREG and the gate contact (G) of the
fourth transistor Q.sub.4. The feedback resistor R.sub.FB is
coupled between the gate contact (G) of the fourth transistor
Q.sub.4 and the ground node N.sub.G.
[0033] The first transistor Q.sub.1, the second transistor Q.sub.2,
the third transistor Q.sub.3, and the fourth transistor Q.sub.4 may
be pHEMTs in some embodiments. Specifically, the first transistor
may be a depletion mode pHEMT and the second transistor Q.sub.2,
the third transistor Q.sub.3, and the fourth transistor Q.sub.4 may
be enhancement mode transistors. The first bypass transistor
Q.sub.BP1, the second bypass transistor Q.sub.BP2, and the reverse
connected diode transistor Q.sub.RD may also be pHEMTs.
Specifically, the first bypass transistor Q.sub.BP1 and the reverse
connected diode transistor Q.sub.RD may be depletion mode pHEMTs,
and the second bypass transistor Q.sub.BP2 may be an enhancement
mode pHEMT. Each one of the gain stage diodes D.sub.GS may also be
pHEMT devices. Specifically, each one of the gain stage diodes
D.sub.GS may be enhancement mode pHEMT devices. Those skilled in
the art will appreciate that connecting a drain contact (D) and a
gate contact (G) of an enhancement mode pHEMT creates a device that
behaves similar to a diode between the connected drain contact (D)
and gate contact (G) corresponding to an anode and a source contact
(S) corresponding to a cathode thereof.
[0034] As discussed above, the first bypass transistor Q.sub.BP1
may be a depletion mode pHEMT, while the second bypass transistor
Q.sub.BP2 may be an enhancement mode pHEMT. Accordingly, when no
enable signal EN is present at the enable signal node N.sub.EN, the
first bypass transistor Q.sub.BP1 may be in an on state while the
second bypass transistor Q.sub.BP2 is in an off state. Because the
second bypass transistor Q.sub.BP2 is in an off state, current
cannot flow through the gain stage 16, and the voltage regulator
circuitry 20 is powered off. When an enable signal suitable for
maintaining the first bypass transistor Q.sub.BP1 and the second
bypass transistor Q.sub.BP2 in an off state is provided to the
enable signal node N.sub.EN, the voltage regulator circuitry 20 is
similarly powered off. Maintaining the second bypass transistor
Q.sub.BP2, or the first bypass transistor Q.sub.BP1 and the second
bypass transistor Q.sub.BP2 in an off state prevents the
consumption of current when the device is inactive and thus may
prolong battery life of a mobile device in which the voltage
regulator circuitry 20 is provided. When the voltage regulator
circuitry 20 is powered on, an enable signal EN suitable for
turning on the first bypass transistor Q.sub.BP1 and the second
bypass transistor Q.sub.BP2, either partially or completely, is
provided to the enable signal node N.sub.EN. In some embodiments,
the enable signal EN is equal to the power supply voltage V.sub.PS,
however, any suitable enable signal EN may be provided to power on
the voltage regulator circuitry 20 without departing from the
principles of the present disclosure. As discussed above, the
reverse connected diode transistor Q.sub.RD may limit the current
flow from the enable signal node N.sub.EN to the gate contact (G)
of the second bypass transistor Q.sub.BP2 when the voltage
regulator circuitry 20 is powered on.
[0035] When the first bypass transistor Q.sub.BP1 and the second
bypass transistor Q.sub.BP2 are closed, the first gain stage 22 is
placed between the power supply voltage V.sub.PS (or a portion
thereof, depending on the amount that the first bypass transistor
Q.sub.BP1 is turned on) and a fixed potential (e.g., ground). The
power supply voltage V.sub.PS provided at the drain contact (D) of
the first transistor Q.sub.1 will turn on the device, providing a
portion of the supply voltage V.sub.PS to the regulated output
voltage node N.sub.VREG. This portion of the power supply voltage
V.sub.PS will be dropped across the current setting resistor
R.sub.CS and provided back to the gate contact (G) of the first
transistor Q.sub.1. This feedback loop effectively makes the first
transistor Q.sub.1 act as an active load and current source for the
second transistor Q.sub.2, such that a substantially constant
current is provided to the drain contact (D) of the second
transistor Q.sub.2.
[0036] The portion of the power supply voltage V.sub.PS provided at
the regulated output voltage node N.sub.VREG is further dropped
across the stacked feedback diodes D.sub.FB and the feedback
resistor R.sub.FB and provided to the gate contact (G) of the
fourth transistor Q.sub.4. Each one of the stacked feedback diodes
D.sub.FB effectively provides a voltage drop that is dependent on
temperature so as to provide a desired relationship of a regulated
output voltage V.sub.REG present at the regulated output voltage
node N.sub.VREG to ambient temperature. The voltage across the
stacked feedback diodes D.sub.FB is fed into the gate contact (G)
of the fourth transistor Q.sub.4 to effectively create a feedback
loop between the regulated output voltage node N.sub.VREG and the
gate contact (G) of the fourth transistor Q.sub.4.
[0037] The portion of the power supply voltage V.sub.PS provided at
the regulated output voltage node N.sub.VREG is further dropped
across the second set of stacked gain stage diodes D.sub.GS and
provided to the gate contact (G) of the third transistor Q.sub.3.
This voltage may change based on the impedance provided by the
fourth transistor Q.sub.4, which is controlled by the feedback
provided by the stacked feedback diodes D.sub.FB as discussed
above. Accordingly, another feedback loop is provided between the
regulated voltage output node N.sub.VREG and the gate contact (G)
of the third transistor Q.sub.3. The first set of stacked gain
stage diodes D.sub.GS similarly provide a feedback loop between the
regulated voltage output node N.sub.VREG and the gate contact (G)
of the second transistor Q.sub.2. The impedance of each one of the
gain stage diodes D.sub.GS can be expressed by Equation (2):
1/g.sub.m (2)
where g.sub.m is the transconductance of the pHEMT. The gain of
each one of the second gain stage 24 and the third gain stage 26,
which can be simplified as common source amplifiers, can be
expressed by Equation (3):
G=g.sub.mR.sub.D (3)
where R.sub.D is a drain resistance of the gain stage (in the
present case, the combined impedance of the gain stage diodes
D.sub.GS), which can be rewritten according to Equation 4:
G = g m ( 4 * 1 g m ) = 4 ( 4 ) ##EQU00002##
which, as illustrated, is independent of any factors that may
change due to process variations in the pHEMTs making up the gain
stage diodes and the transistors in each one of the gain stages. As
discussed above, it is highly desirable to decouple voltage control
in a voltage regulator for an RF power amplifier from process
variations that may occur in the fabrication thereof. By providing
the second gain stage 24 and the third gain stage 26 such that the
gain thereof is independent of process variations that may occur
therein, the gain of the voltage regulator circuitry 20 may be
increased significantly without sacrificing voltage control due to
process variation.
[0038] Due to the fact that the voltage regulator circuitry 20 is
created using a pHEMT process, the size of the circuitry may be
minimized. Further, the pHEMT process and circuit topology may
provide short turn-on times and low quiescent current consumption.
Notably, while three gain stages are shown in the voltage regulator
circuitry 20, any number of gain stages may be provided without
departing from the principles of the present disclosure. In one
embodiment, the third gain stage may be removed such that only the
first gain stage 22 and the second gain stage 24 are provided, and
the feedback stage 28 is coupled directly to the second gain stage
24 (e.g., by coupling the stacked feedback diodes D.sub.FB between
the regulated output voltage node N.sub.VREG and the gate contact
(G) of the third transistor Q.sub.3 and by coupling the feedback
resistor R.sub.FB between the gate contact (G) of the third
transistor Q.sub.3 and the ground node N.sub.G). In another
embodiment, at least a fourth gain stage is added between the third
gain stage 26 and the feedback stage 28. While a particular number
of gain stage diodes D.sub.GS and feedback diodes D.sub.FB are
shown in FIG. 3, any number of gain stage diodes D.sub.GS and any
number of feedback diodes D.sub.FB may be provided without
departing from the principles of the present disclosure.
[0039] Those skilled in the art will recognize improvements and
modifications to the preferred embodiments of the present
disclosure. All such improvements and modifications are considered
within the scope of the concepts disclosed herein and the claims
that follow.
* * * * *