U.S. patent application number 15/217019 was filed with the patent office on 2018-01-25 for implementing backdrilling elimination utilizing anti-electroplate coating.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Matthew S. Doyle, Joseph Kuczynski, Phillip V. Mann, Kevin M. O'Connell.
Application Number | 20180027665 15/217019 |
Document ID | / |
Family ID | 60934967 |
Filed Date | 2018-01-25 |
United States Patent
Application |
20180027665 |
Kind Code |
A1 |
Doyle; Matthew S. ; et
al. |
January 25, 2018 |
IMPLEMENTING BACKDRILLING ELIMINATION UTILIZING ANTI-ELECTROPLATE
COATING
Abstract
A method and structure are provided for implementing enhanced
via creation without creating a via barrel stub. The need to
backdrill vias during printed circuit board (PCB) manufacturing is
eliminated. After the vias have been drilled, but before plating, a
plug is inserted into each via and the plug is lowered to a depth
just below a desired signal trace layer. A thin anti-electroplate
coating is applied onto the walls of the via below the signal
trace. Then the plugs are removed and a standard board plating
process for the PCB is performed.
Inventors: |
Doyle; Matthew S.;
(Chatfield, MN) ; Kuczynski; Joseph; (North Port,
FL) ; Mann; Phillip V.; (Rochester, MN) ;
O'Connell; Kevin M.; (Rochester, MN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
60934967 |
Appl. No.: |
15/217019 |
Filed: |
July 22, 2016 |
Current U.S.
Class: |
174/258 |
Current CPC
Class: |
H05K 2201/015 20130101;
H05K 2203/143 20130101; H05K 3/425 20130101; H05K 1/034 20130101;
H05K 3/423 20130101; H05K 1/115 20130101 |
International
Class: |
H05K 3/42 20060101
H05K003/42; H05K 1/03 20060101 H05K001/03; H05K 1/11 20060101
H05K001/11 |
Claims
1. A method for implementing enhanced via creation without creating
a via barrel stub during printed circuit board (PCB) manufacturing
comprising: providing a printed circuit board (PCB); said printed
circuit board (PCB) having an internal conductive trace; forming a
via extending through the printed circuit board (PCB) including the
internal conductive trace; and inserting a plug into the via
extending from a first surface to below the internal conductive
trace; applying an anti-electroplate coating covering the walls of
the via below the signal trace; said anti-electroplate coating
eliminating via barrel stub creation during the PCB manufacturing;
and removing the plug and performing PCB plating.
2. The method as recited in claim 1 wherein applying an
anti-electroplate coating covering the walls of the via below the
signal trace includes applying said anti-electroplate coating by
vapor deposition.
3. The method as recited in claim 1 wherein applying an
anti-electroplate coating covering the walls of the via below the
signal trace includes applying said anti-electroplate coating
having a selected thickness in a range between 0.2 .mu.m and 0.5
.mu.m.
4. The method as recited in claim 1 wherein applying an
anti-electroplate coating covering the walls of the via below the
signal trace includes applying said anti-electroplate coating
formed of a chemically resistant polymer.
5. The method as recited in claim 1 wherein applying an
anti-electroplate coating covering the walls of the via below the
signal trace includes applying said anti-electroplate coating
formed of a hydrophobic polymer.
6. The method as recited in claim 1 wherein applying an
anti-electroplate coating covering the walls of the via below the
signal trace includes applying said anti-electroplate coating
formed of polytetrafluoroethylene (PTFE).
7. The method as recited in claim 6 includes applying said
polytetrafluoroethylene (PTFE) coating by vapor deposition.
8. The method as recited in claim 6 includes applying said
polytetrafluoroethylene (PTFE) coating having a selected thickness
in a range between 0.2 .mu.m and 0.5 .mu.m.
9. The method as recited in claim 1 wherein providing a printed
circuit board (PCB); said printed circuit board (PCB) having an
internal conductive trace includes a standard PCB manufacturing
process.
10. The method as recited in claim 1 wherein inserting a plug into
the via from a top surface extending below the internal conductive
trace includes said plug blocking said anti-electroplate coating
being applied to said internal conductive trace.
11. The method as recited in claim 1 wherein a standard PCB plating
process is performed responsive to removing the plug.
12. The method as recited in claim 1 wherein eliminating via
back-drilling enables improved yield and reliability of the
PCB.
13. A printed circuit board (PCB) structure produced by a method as
recited in claim 1.
14. A structure for implementing enhanced via creation without
creating a via barrel stub during printed circuit board (PCB)
manufacturing comprising: a printed circuit board (PCB); said
printed circuit board (PCB) having an internal conductive trace; a
via extending through the printed circuit board (PCB) and the
internal conductive trace; and an anti-electroplate coating
covering the walls of the via below the signal trace; said
anti-electroplate coating formed of a chemically resistant polymer
having a selected thickness of approximately 0.2 .mu.m, said
anti-electroplate coating remaining on the via walls, preventing
PCB plating from PCB plating process from taking hold on the
covered via walls, said anti-electroplate coating eliminating via
barrel stub creation during PCB manufacturing.
15-16. (canceled)
17. The structure as recited in claim 14 wherein said
anti-electroplate coating is formed of a hydrophobic polymer.
18. The structure as recited in claim 14 wherein said
anti-electroplate coating is formed of polytetrafluoroethylene
(PTFE).
19. The structure as recited in claim 18 wherein said
anti-electroplate coating is applied using vapor deposition onto
the walls of the via below the signal trace.
20. The structure as recited in claim 14 wherein said
anti-electroplate coating has a selected thickness less than 0.5
.mu.m.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to the data
processing field, and more particularly, relates to a method and
structure for implementing manufacture of a printed circuit board
(PCB) with enhanced via creation without creating a via barrel
stub, eliminating the need to back-drill.
DESCRIPTION OF THE RELATED ART
[0002] The computer hardware development industry has reached a
point wherein many computer interfaces are of sufficient switching
speed as to require signal routing layer change vias to be
back-drilled to remove via barrel stubs. Backdrilling is a
conventional technique used to remove the via barrel stub. Without
removal of the unnecessary section or length of a via barrel, some
amount of the propagating signal is reflected away from the
intended receiver, thereby significantly reducing the amount of
total energy effectively transferred from driver to receiver.
[0003] While there are known processes to mechanically remove these
stubs, once back-drilled, it is no longer possible to probe those
locations on the printed circuit board (PCB), cost of the PCB
increases substantially, and success of the process is
statistically less than ideal. These facts significantly complicate
our ability to manufacture cost-effective PCBs, measure high-speed
interfaces in the lab during system bring-up and model-to-hardware
correlation activities, and maximize the electrical performance of
our computer interfaces. When system errors occur in the field, the
field engineer cannot measure and confirm function at these PCB via
locations while at the customer's site.
[0004] A need exists for a method and structure for implementing
via creation that eliminates creation of a via barrel stub,
eliminating the need to back-drill, reducing PCB cost, and
maximizing interface margin.
[0005] As used in the following description and claims, the term
printed circuit board (PCB) should be understood to broadly include
a printed wiring board or other substrate, an interconnect
substrate, and various substrates including a plurality of
insulator layers, and internal conductive traces.
SUMMARY OF THE INVENTION
[0006] Principal aspects of the present invention are to provide a
method and structure for implementing manufacture of a printed
circuit board (PCB) with enhanced via creation without creating a
via barrel stub, eliminating the need to back-drill. Other
important aspects of the present invention are to provide such
method and structure substantially without negative effects and
that overcome many of the disadvantages of prior art
arrangements.
[0007] In brief, a method and structure are provided for
implementing enhanced via creation without creating a via barrel
stub. The need to backdrill during printed circuit board (PCB)
manufacturing is eliminated. After the vias have been drilled, but
before plating, a plug is inserted into each via and the plug is
lowered to a depth just below a desired signal trace layer. A thin
anti-electroplate coating is applied onto the walls of the via
below the signal trace. Then the plugs are removed and a board
plating process for the PCB is performed.
[0008] In accordance with features of the invention, the
anti-electroplate coating includes, for example, a Teflon coating
or a polytetrafluoroethylene (PTFE) coating, Teflon is a trade name
for PTFE.
[0009] In accordance with features of the invention, the Teflon
coating is applied, for example, using vapor deposition onto the
walls of the via below the signal trace.
[0010] In accordance with features of the invention, the coating
prevents the plating from creating via barrel stubs, thus
eliminating the need to backdrill each via after the plating
process.
[0011] In accordance with features of the invention, eliminating
back-drilling improves yield and late fail discoveries, both of
which can improve cost and reliability of boards.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The present invention together with the above and other
objects and advantages may best be understood from the following
detailed description of the preferred embodiments of the invention
illustrated in the drawings, wherein:
[0013] FIG. 1 illustrates an example structure for manufacturing a
printed circuit board (PCB) with enhanced via creation without
creating a via barrel stub, eliminating the need to back-drill in
accordance with the preferred embodiment;
[0014] FIG. 2 is a flow chart illustrating example steps for
implementing a structure embodying the enhanced via creation
without creating a via barrel stub in accordance with the preferred
embodiment; and
[0015] FIG. 3 illustrates an example structure for manufacturing a
printed circuit board (PCB) with enhanced via creation without
creating a via barrel stub, eliminating the need to back-drill in
accordance with the preferred embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] In the following detailed description of embodiments of the
invention, reference is made to the accompanying drawings, which
illustrate example embodiments by which the invention may be
practiced. It is to be understood that other embodiments may be
utilized and structural changes may be made without departing from
the scope of the invention.
[0017] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated features, integers,
steps, operations, elements, and/or components, but do not preclude
the presence or addition of one or more other features, integers,
steps, operations, elements, components, and/or groups thereof.
[0018] In accordance with features of the invention, a method and
structure are provided for implementing enhanced via creation
without creating a via barrel stub. The need to backdrill vias
during printed circuit board (PCB) manufacturing is eliminated.
After the vias have been drilled, but before plating, a plug is
inserted into each via and the plug is lowered to a depth just
below a desired signal trace layer. A thin anti-electroplate
coating is applied onto the walls of the via below the plug and the
signal trace. Then the plugs are removed and a board plating
process for the PCB is performed.
[0019] Having reference now to the drawings, in FIG. 1, there is
shown an example structure generally designated by reference
character 100 for manufacturing a printed circuit board (PCB) with
enhanced via creation without creating a via barrel stub,
eliminating the need to back-drill in accordance with the preferred
embodiment.
[0020] Structure 100 includes a printed circuit board (PCB) 102
having an internal conductive or signal trace 104. PCB 102 includes
an insulator substrate or insulator layers, with one or more
internal conductive traces 104. Structure 100 includes a via 106
extending through the printed circuit board (PCB) 102 and the
internal conductive trace 104. Structure 100 includes an
anti-electroplate coating 110 covering the walls of the via 106
below the signal trace 104. The anti-electroplate coating 110
eliminates via barrel stub creation during a PCB plating process
during PCB manufacturing. The anti-electroplate coating 110 is a
chemically resistant polymer and is hydrophobic. The
anti-electroplate coating 110 has a selected thickness, for
example, in a range between 0.2 .mu.m and 0.5 .mu.m.
[0021] The anti-electroplate coating 110 includes, for example, a
polytetrafluoroethylene (PTFE) coating (e.g., trade name Teflon),
that is applied for example, using vapor deposition onto the walls
of the via 106 below the signal trace 104.
[0022] "PTFE Deposition: View" by MNX MEMS & Nanotechnology
Exchange, detailing example vapor deposition of Teflon, is provided
at: https://www.mems-exchange.org/catalog/P3372/
[0023] The PTFE coating 110 prevents the PCB plating process from
creating via barrel stubs, thus eliminating the need to backdrill
each via after the plating process. Eliminating back-drilling
improves yield and late fail discoveries, both of which can improve
cost and reliability of boards.
[0024] In accordance with features of the invention, the printed
circuit board (PCB) 102 and via 106 are formed generally including
standard PCB manufacturing processes, including via drilling and
plating. However, the step of back-drilling at the end is removed
and the PCB process of the invention provides that after the vias
106 have been drilled, but before plating, a small plug 108 is
inserted into each via 106 extending to a defined depth just below
the desired signal trace layer 104. A thin coating 110 of Teflon is
then applied using vapor deposition onto the walls of the via 106
below the signal trace 104, and then the plugs 108 are removed. The
PCB 102 is then sent through the normal plating process. The
coating 110 prevents the plating from taking hold, thus eliminating
the need to backdrill each via after the plating process.
[0025] Referring now to FIG. 2, there is shown a flow chart
illustrating example steps generally designated by reference
character 200 for implementing a structure embodying the enhanced
via creation without creating a via barrel stub in accordance with
the preferred embodiment starting at a block 202.
[0026] As indicated at a block 202, a lamination is formed defining
the PCB 102 and at least one internal conductive traces 104.
[0027] As indicated at a block 204, vias 106 are drilled.
Conventional via drilling is performed.
[0028] As indicated at a block 206, the plugs 108 are inserted into
the via 106, with the plugs extending from a top or first surface
to a depth below the signal trace 104. The plugs 108 optionally are
configured as sprayers (like fuel injectors) to apply the Teflon
coating applied to the walls of the via 106 below plugs 108.
Optionally, individual plugs 108 having a specified length are
pushed flush with one side of the PCB 102, then moved or poked out
from the other PCB side. Optionally, individual plugs 108 are
mechanically inserted to a specific depth, the retracted.
Optionally, an array of plugs 108, typically of differing lengths
extending from a plate are all inserted at once, the removed.
[0029] As indicated at a block 208, the anti-electroplate coating
110 is applied to the walls of the via 106 below plugs 108 and the
signal trace 104, for example, by vapor deposition of Teflon.
[0030] As indicated at a block 210, the plugs 108 are removed from
the vias 106 after the anti-electroplate coating 110 is
applied.
[0031] As indicated at a block 212, the PCB plating process is
performed, using a conventional plating process.
[0032] As indicated at a block 214, conventional PCB finishing
processes are performed, advantageously eliminating the need to
backdrill each via after the plating process.
[0033] Referring now to FIG. 3, there is shown an example resulting
structure generally designated by reference character 300 resulting
from manufacturing a printed circuit board (PCB) with enhanced via
creation without creating a via barrel stub, eliminating the need
to back-drill in accordance with the preferred embodiment.
Structure 300 shows the plugs 108 removed from the vias 106 after
the anti-electroplate coating 110 is applied.
[0034] Structure 300 includes the printed circuit board (PCB) 102
having the internal conductive or signal trace 104. Structure 100
includes the via 106 extending through the printed circuit board
(PCB) 102 and the internal conductive trace 104. Structure 300
includes the anti-electroplate coating 110 covering the walls of
the via 106 below the signal trace 104. Structure 300 includes a
plating 302 applied during the PCB plating process that is
performed using a conventional plating process.
[0035] In accordance with features of the invention, the
alternative method for via creation eliminates creation of the via
barrel stub. Since the via barrel stub is not created, the need to
back-drill is eliminated, reducing PCB cost and maximizing
interface margin.
[0036] While the present invention has been described with
reference to the details of the embodiments of the invention shown
in the drawing, these details are not intended to limit the scope
of the invention as claimed in the appended claims.
* * * * *
References