U.S. patent application number 15/212821 was filed with the patent office on 2018-01-18 for obtaining state information of threads of a device.
The applicant listed for this patent is AMERICAN MEGATRENDS, INC.. Invention is credited to Thamarai Selvan Moorthy, Rajeswari Ravichandran, Pavithra Sachidanandam, Senathipathy Thangavel, Satheesh Thomas, Aruna Venkataraman.
Application Number | 20180018240 15/212821 |
Document ID | / |
Family ID | 60941043 |
Filed Date | 2018-01-18 |
United States Patent
Application |
20180018240 |
Kind Code |
A1 |
Thomas; Satheesh ; et
al. |
January 18, 2018 |
OBTAINING STATE INFORMATION OF THREADS OF A DEVICE
Abstract
In an aspect of the disclosure, a method, a computer-readable
medium, and an apparatus are provided. The apparatus may be an
embedded-system device. The embedded-system device determines a
respective operational state of each of one or more threads of a
process executing on the embedded-system device. The
embedded-system device stores the respective operational state of
each of the one or more threads in a thread state register in a
memory of the embedded-system device. The embedded-system device
stores information data associated with the respective operational
state of each of the one or more threads in the thread state
register. The embedded-system device determines that operation of
at least one thread of the one or more threads is abnormal. The
embedded-system device retrieves the stored operational states of
the one or more threads from the thread state register in response
to the determination. The embedded-system device outputs the
retrieved operational states.
Inventors: |
Thomas; Satheesh; (Dunwoody,
GA) ; Ravichandran; Rajeswari; (Duluth, GA) ;
Venkataraman; Aruna; (Duluth, GA) ; Sachidanandam;
Pavithra; (Duluth, GA) ; Thangavel; Senathipathy;
(Chennai, IN) ; Moorthy; Thamarai Selvan; (Erode,
IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
AMERICAN MEGATRENDS, INC. |
Norcross |
GA |
US |
|
|
Family ID: |
60941043 |
Appl. No.: |
15/212821 |
Filed: |
July 18, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 11/0715 20130101;
G06F 11/3017 20130101; G06F 11/302 20130101 |
International
Class: |
G06F 11/14 20060101
G06F011/14; G06F 9/48 20060101 G06F009/48 |
Claims
1. A method of operating an embedded-system device, comprising:
determining a respective operational state of each of one or more
threads of a process executing on the embedded-system device;
storing the respective operational state of each of the one or more
threads in a thread state register in a memory of the
embedded-system device; determining that operation of at least one
thread of the one or more threads is abnormal; retrieving the
stored operational states of the one or more threads from the
thread state register in response to the determination; and
outputting the retrieved operational states.
2. The method of claim 1, further comprising storing information
data associated with the respective operational state of each of
the one or more threads in the thread state register.
3. The method of claim 2, wherein the information data of the each
thread include a thread indicator of the each thread.
4. The method of claim 2, wherein the information data of the each
thread include at least one of an indicator of an iteration count,
an indicator of presence of an external loop, and an indicator of a
sub-function of the each thread.
5. The method of claim 1, wherein the operation of the at least one
thread is determined to be normal or abnormal periodically by a
monitor thread.
6. The method of claim 1, wherein the determining that the
operational state of the at least one thread is abnormal includes
determining that the operational state of the at least one thread
has not been updated for a predetermined time period.
7. The method of claim 1, wherein each of the one or more threads
operates in one or more operational states.
8. The method of claim 1, wherein the respective operational state
of each of the one or more threads is determined by the each
thread.
9. The method of claim 8, wherein the respective operational state
of each of the one or more threads is further determined based on a
respective function invoked by the each thread.
10. The method of claim 9, further comprising: the respective
function determining that the each thread has invoked the
respective function, wherein the respective operational state is
stored in the thread state register by the respective function in
association with the each thread.
11. The method of claim 10, wherein the respective operational
state is associated with the each thread by a thread indicator of
the each thread.
12. The method of claim 8, wherein the respective operational state
of each of the one or more threads is determined a plurality of
times throughout operation of the each thread when the each thread
executes one or more functions.
13. The method of claim 12, wherein the one or more functions
include at least one of a write function, a read function, a listen
function, a send function, and a wait function.
14. The method of claim 1, wherein the operational states of the
one or more threads are output to a non-volatile memory.
15. The method of claim 14, wherein the operational states of the
one or more threads that are output at different times are stored
in the non-volatile memory to maintain a history of the operational
states of the one or more threads.
16. The method of claim 14, further comprising: receiving a request
through an Intelligent Platform Management Interface (IPMI)
interface from another device; retrieving the operational states
stored in the non-volatile memory in response to the request; and
sending the retrieved operational states to the another device
through the IPMI interface.
17. An apparatus, the apparatus being an embedded-system device,
comprising: a memory; and at least one processor coupled to the
memory and configured to: determine a respective operational state
of each of one or more threads of a process executing on the
embedded-system device; store the respective operational state of
each of the one or more threads in a thread state register in a
memory of the embedded-system device; determine that operation of
at least one thread of the one or more threads is abnormal;
retrieve the stored operational states of the one or more threads
from the thread state register in response to the determination;
and output the retrieved operational states.
18. The apparatus of claim 17, wherein the at least one processor
is further configured to store information data associated with the
respective operational state of each of the one or more threads in
the thread state register.
19. A computer-readable medium storing computer executable code for
operating an embedded-system device, comprising code to: determine
a respective operational state of each of one or more threads of a
process executing on the embedded-system device; store the
respective operational state of each of the one or more threads in
a thread state register in a memory of the embedded-system device;
determine that operation of at least one thread of the one or more
threads is abnormal; retrieve the stored operational states of the
one or more threads from the thread state register in response to
the determination; and output the retrieved operational states.
20. The apparatus of claim 19, wherein the code is further
configured to store information data associated with the respective
operational state of each of the one or more threads in the thread
state register.
Description
BACKGROUND
Field
[0001] The present disclosure relates generally to computer
management devices, and more particularly, to techniques of
obtaining state information of threads of a device.
Background
[0002] Considerable developments have been made in the arena of
server management. An industry standard called Intelligent Platform
Management Interface (IPMI), described in, e.g., "IPMI: Intelligent
Platform Management Interface Specification, Second Generation,"
v.2.0, Feb. 12, 2004, defines a protocol, requirements and
guidelines for implementing a management solution for server-class
computer systems. The features provided by the IPMI standard
include power management, system event logging, environmental
health monitoring using various sensors, watchdog timers, field
replaceable unit information, in-band and out of band access to the
management controller, simple network management protocol (SNMP)
traps, etc.
[0003] A component that is normally included in a server-class
computer to implement the IPMI standard is known as a Baseboard
Management Controller (BMC). A BMC is a specialized microcontroller
embedded on the motherboard of the computer, which manages the
interface between the system management software and the platform
hardware. The BMC generally provides the "intelligence" in the IPMI
architecture.
[0004] A BMC may require a firmware image to make them operational.
"Firmware" is software that is stored in a read-only memory (ROM)
(which may be reprogrammable), such as a ROM, programmable
read-only memory (PROM), erasable programmable read-only memory
(EPROM), electrically erasable programmable read-only memory
(EEPROM), etc. Such firmware may be considered as an
embedded-system. The BMC may be considered an embedded-system
device. There is a need to more effectively debug threads of a
process of the BMC or other embedded-system devices.
SUMMARY
[0005] The following presents a simplified summary of one or more
aspects in order to provide a basic understanding of such aspects.
This summary is not an extensive overview of all contemplated
aspects, and is intended to neither identify key or critical
elements of all aspects nor delineate the scope of any or all
aspects. Its sole purpose is to present some concepts of one or
more aspects in a simplified form as a prelude to the more detailed
description that is presented later.
[0006] In an aspect of the disclosure, a method, a
computer-readable medium, and an apparatus are provided. The
apparatus may be an embedded-system device. The embedded-system
device determines a respective operational state of each of one or
more threads of a process executing on the embedded-system device.
The embedded-system device stores the respective operational state
of each of the one or more threads in a thread state register in a
memory of the embedded-system device. The embedded-system device
stores information data associated with the respective operational
state of each of the one or more threads in the thread state
register. The embedded-system device determines that operation of
at least one thread of the one or more threads is abnormal. The
embedded-system device retrieves the stored operational states of
the one or more threads from the thread state register in response
to the determination. The embedded-system device outputs the
retrieved operational states. In certain configurations, the
operational states of the one or more threads are output to a
non-volatile memory.
[0007] To the accomplishment of the foregoing and related ends, the
one or more aspects comprise the features hereinafter fully
described and particularly pointed out in the claims. The following
description and the annexed drawings set forth in detail certain
illustrative features of the one or more aspects. These features
are indicative, however, of but a few of the various ways in which
the principles of various aspects may be employed, and this
description is intended to include all such aspects and their
equivalents.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a diagram illustrating an embedded-system
device.
[0009] FIG. 2 is a diagram illustrating operational states of a
thread of a process.
[0010] FIG. 3 is a flow chart of a method (process) for obtaining
operational states.
[0011] FIG. 4 is a diagram illustrating an example of a hardware
implementation for an apparatus employing a processing system.
[0012] FIG. 5 shows a computer architecture for a computer.
DETAILED DESCRIPTION
[0013] The detailed description set forth below in connection with
the appended drawings is intended as a description of various
configurations and is not intended to represent the only
configurations in which the concepts described herein may be
practiced. The detailed description includes specific details for
the purpose of providing a thorough understanding of various
concepts. However, it will be apparent to those skilled in the art
that these concepts may be practiced without these specific
details. In some instances, well known structures and components
are shown in block diagram form in order to avoid obscuring such
concepts.
[0014] Several aspects of computer systems will now be presented
with reference to various apparatus and methods. These apparatus
and methods will be described in the following detailed description
and illustrated in the accompanying drawings by various blocks,
components, circuits, processes, algorithms, etc. (collectively
referred to as "elements"). These elements may be implemented using
electronic hardware, computer software, or any combination thereof.
Whether such elements are implemented as hardware or software
depends upon the particular application and design constraints
imposed on the overall system.
[0015] By way of example, an element, or any portion of an element,
or any combination of elements may be implemented as a "processing
system" that includes one or more processors. Examples of
processors include microprocessors, microcontrollers, graphics
processing units (GPUs), central processing units (CPUs),
application processors, digital signal processors (DSPs), reduced
instruction set computing (RISC) processors, systems on a chip
(SoC), baseband processors, field programmable gate arrays (FPGAs),
programmable logic devices (PLDs), state machines, gated logic,
discrete hardware circuits, and other suitable hardware configured
to perform the various functionality described throughout this
disclosure. One or more processors in the processing system may
execute software. Software shall be construed broadly to mean
instructions, instruction sets, code, code segments, program code,
programs, subprograms, software components, applications, software
applications, software packages, routines, subroutines, objects,
executables, threads of execution, procedures, functions, etc.,
whether referred to as software, firmware, middleware, microcode,
hardware description language, or otherwise.
[0016] Accordingly, in one or more example embodiments, the
functions described may be implemented in hardware, software, or
any combination thereof. If implemented in software, the functions
may be stored on or encoded as one or more instructions or code on
a computer-readable medium. Computer-readable media includes
computer storage media. Storage media may be any available media
that can be accessed by a computer. By way of example, and not
limitation, such computer-readable media can comprise a
random-access memory (RAM), a read-only memory (ROM), an
electrically erasable programmable ROM (EEPROM), optical disk
storage, magnetic disk storage, other magnetic storage devices,
combinations of the aforementioned types of computer-readable
media, or any other medium that can be used to store computer
executable code in the form of instructions or data structures that
can be accessed by a computer.
[0017] For an embedded-system device such as a BMC, debugging a
defect of the embedded system after the embedded-system device has
been shipped to a customer is a challenge. This is especially true
when the system embedded has multithreaded processes.
[0018] A thread of a process of an embedded-system device may be
stuck or hung due to a variety of reasons. In certain
circumstances, a particular thread of a process may be waiting
infinitely on another process or device to get a response needed in
order to execute the next instruction of the particular thread. In
certain circumstances, a particular thread of a process may be
waiting infinitely for another thread of the same process to get
the response needed to execute the next instruction.
[0019] Each thread in a process of an embedded-system device during
its operation may be considered as going through different
operational states. When the number of threads of the process is
large, and when the number of operational states for each thread
are large, the system embedded is complex, as the possible
combinations of states of different threads is large. As an
example, for a simple system process with 10 threads each having 2
states, the possible combinations are 2 by the power of 10, i.e.,
1024. IPMI processes in a BMC each may include more than 40 threads
and a large number of states. As such, there is a need to improve
computational support for debugging processes.
[0020] FIG. 1 is a diagram 100 illustrating an embedded-system
device 102. The embedded-system device 102 has a processor 112, a
memory 114, a memory driver 116, and a storage 117. The
embedded-system device 102 may support IPMI and may have an IPMI
interface 118. For example, the embedded-system device 102 may be a
baseboard management controller (BMC) that is in communication
with, through the IPMI interface 118, a host computer 190 and/or a
network device 194. The IPMI communication between the BMC and the
network device 194 may be carried over a network 160. The BMC may
manage the host computer 190.
[0021] Further, the storage 117 may store BMC firmware 120. When
the processor 112 executes the BMC firmware 120, the processor 112
loads code and data of one or more processes of the BMC firmware
120 into the memory 114. This example only shows 3 processes, i.e.,
processes 121-1, 121-2, 121-3, in the memory 114. It is understood
that any suitable number of processes may be executed by the
processor 112 and loaded into the memory 114. The memory 114, the
processor 112, the memory driver 116, the storage 117, and the IPMI
interface 118 may be in communication with each other through a
communication channel 110 such as a bus architecture. Further, each
of the processes 121-1, 121-2, 121-3 may have one or more threads.
This example shows that the process 121-1 has 4 threads, i.e.,
threads 122-1, 122-2, 122-3, 122-4.
[0022] As described supra, each of the threads of a process of the
processes 121-1, 121-2, 121-3 executed by the processor 112 may
have various operational states, and during its operation the
thread is in one of those states at a given time. FIG. 2 is a
diagram 200 illustrating operational states of the thread 122-1 of
the process 121-1. As shown, the thread 122-1 may have 5 different
operational states 222, 224, 226, 228, 230. During operation, the
thread 122-1 may transition from one of those states to another
(e.g., from the operational state-A 222 to the operational state-B
224).
[0023] Further, as an example, the thread 122-1 may perform, or may
call a routine that performs, one or more functions such as a write
function, a read function, a listen function, a send function, and
a wait function. The thread 122-1 may be in one of the operational
states 222, 224, 226, 228, 230 when one of the functions is
performed. For example, when the thread 122-1 is performing the
listen function, the thread 122-1 may accordingly be considered as
having been transitioned to the operational state-B 224 (e.g., a
listen state).
[0024] Referring back to FIG. 1, as described supra, the processor
112 utilizes the memory 114 to execute the BMC firmware 120, which
includes the processes 121-1, 121-2, 121-3. Each of the processes
121-1, 121-2, 121-3 occupies a specific memory area of the memory
114.
[0025] The threads 122-1, 122-2, 122-3, 122-4 each may, from time
to time, determine their respective current operational states. In
certain configurations, a thread may determine its operational
state periodically (e.g., every 5, 10, 15 seconds, etc.). For
example, the thread may periodically determine what function or
task the thread is performing, and then may determine the
operational state of the thread based on the function or task
(e.g., a write function) being performed.
[0026] In certain configurations, a process may include one or more
common routines. Each time a routine is called by a thread of the
process, the routine may determine the current operational state of
the thread. For example, the process 121-1 may have a PostToQ
routine, which in turn may be called by one or more functions
(e.g., a SendToX function, a SendToY function, a SendToZ function)
of the process. The one or more functions each may be called by one
or more of the threads 122-1, 122-2, 122-3, 122-4. A particular
thread may pass sufficient information identifying the particular
thread to a function being called. The function may further pass
the information to a routine being called. As such, the routine can
identify for which thread the routine is determining an operational
state.
[0027] Further, each time after determining the operational state
of a particular thread, the particular thread or a determining
routine may use a state variable to record the current operational
state of the thread. The state variable may be assigned one or more
values, each of which corresponds to an operational state of the
thread. For example, the variable may have a name of
"THREAD_OP_STATE" and may be an integer type; each operational
state of the thread may be assigned a specific integer value. For
example, the operational states 222, 224, 226, 228, 230 of the
thread 122-1 may be assigned values of 0-4.
[0028] Further, each process of the threads 122-1, 122-2, 122-3,
122-4 may provide a register in a memory sub-area within the memory
area utilized by that process for storing the state variables and,
optionally, information data associated with the state variables of
the threads of the process, as described infra. As an example, the
process 121-1 has a register 132 and the threads 122-1, 122-2,
122-3, 122-4 may store their state variables in the register 132,
respectively. Further, the location of the respective registers may
be determined dynamically by the processes 121-1, 121-2, 121-3
during the runtime.
[0029] In certain configurations, upon the first time a particular
thread (e.g., the thread 122-1) of a process (e.g., the process
121-1) determines the current operational state of the particular
thread, the particular thread sets the state variable of the
particular thread with a value corresponding to the current
operational state. Then, the particular thread may store the state
variable to the register of the process executing the particular
thread.
[0030] Subsequently, each time a thread (e.g., the thread 122-1)
determines its current operational state, the thread may update the
value of the state variable in the register (e.g., the register
132) of the process (e.g., the process 121-1). The updating
procedure does not have significant negative impact on the
performance of the process.
[0031] In addition to the state variable indicating an operational
state, a thread may also store information data associated with the
operational state in the register. For example, the thread 122-1
may be in a write operational state, and the information data may
indicates the medium or destination to which the data is written.
In certain configurations, the information data of the each thread
include a thread indicator (e.g., a thread index, as described
infra) of the each thread. In certain configurations, the
information data of the each thread include at least one of an
indicator of an iteration count, an indicator of presence of an
external loop, and an indicator of a sub-function of the each
thread.
[0032] As described supra, the register of a process may be used
utilized by the threads of the process to stores the state
variables and, if any, the associated information data of the
threads. Further, a thread index of a thread or other identifier
(e.g., name) of the thread may also be stored in the register 132
to identify the thread associated with a stored state variable and,
if any, the associated information data.
[0033] Further, a thread of a particular process can read the data
stored in the register of the particular process. The state
variable of a particular thread may be obtained from the register
based the thread index or other identifier of the particular
thread. Furthermore, the particular process may include a monitor
thread, which may, as described infra, read the data stored in the
register of the particular process. As an example, the process
121-1 includes a monitor thread 152.
[0034] In this example, the monitor thread 152 may monitor status
of the threads 122-1, 122-2, 122-3, 122-4 and determines whether
operation of any thread of the threads 122-1, 122-2, 122-3, 122-4
is abnormal. For example, the monitor thread 152 may check if a
particular process is still alive periodically (e.g., every 10
seconds, 30 seconds, 60 seconds, 90 seconds, etc.). When the
monitor thread 152 determines that any of the threads 122-1, 122-2,
122-3, 122-4 is stuck for a predetermined time period (e.g., 60
seconds or 90 seconds), the monitor thread 152 may decide to store,
in the storage 117 or any other suitable non-volatile memory, the
state variable and the associated information data of the
terminated process or the state variables and the associated
information data of all the threads. More specifically, the monitor
thread 152 reads the stored state variables and, if any, the
associated information data, from the register 132. The monitor
thread 152 may then store the state variables and the information
data to the storage 117 as a current copy. In certain
configurations, the monitor thread 152 determines that the
operation of a particular thread is abnormal when the monitor
thread 152 determines that the operational state of the particular
thread has not been updated for a predetermined time period (e.g.,
60 seconds).
[0035] The monitor thread 152 may, at more than occasions in a
single boot, determines that a thread of the threads 122-1, 122-2,
122-3, 122-4 has been stuck. The monitor thread 152 may be
configured to store a predetermined number (e.g., 5, 10, 15, etc.)
of copies of the state variables and the associated information
data in the storage 117. As such, the embedded-system device 102
maintains historical information of the states of the threads
122-1, 122-2, 122-3, 122-4 in a period of time. In certain
configurations, the stored copies may be erased after each time the
embedded-system device 102 is booted. In certain configurations,
the stored copies are not erased after a re-boot.
[0036] The copies stored in the storage 117 may be downloaded
through a data transfer protocol supported by the embedded-system
device 102. In one example, the embedded-system device 102 is a BMC
supporting IPMI. The embedded-system device 102 may receive an IPMI
command requesting copies of the state variables and the associated
information data of a particular process through the IPMI interface
118 from the network device 194 or the host computer 190. The
transfer process 126 may obtain the copies of the state variables
and information data of the particular process stored at the
storage 117. The transfer process 126 may provide, through the IPMI
interface 118 and in an IPMI response, those copies to the network
device 194 or the host computer 190.
[0037] In certain circumstances, the IPMI command may include one
or more parameters (e.g., a thread index or other identifiers)
indicating one or more target threads of a particular process
(e.g., the thread 122-1). The transfer process 126 may only include
the state variables and the information data of those target
threads in the IPMI response.
[0038] In another example, the embedded-system device 102 (e.g., a
BMC) may receive an IPMI command requesting the current state
variables and the associated information data, rather than the
historical data stored in the storage 117, of the process 121-1 (or
another particular process). The transfer process 126 may request
the monitor thread 152 to obtain the state variables and data from
the register 132 of the process 121-1. The transfer process 126 may
provide, through the IPMI interface 118 and in an IPMI response,
those copies to the network device 194 or the host computer
190.
[0039] FIG. 3 is a flow chart 300 of a method (process) for
obtaining operational states. The method may be performed by an
embedded-system device (e.g., the embedded-system device 102 and
the apparatus 102').
[0040] At operation 302, the embedded-system device determines a
respective operational state of each of one or more threads of a
process executing on the embedded-system device. At operation 304,
the embedded-system device stores the respective operational state
of each of the one or more threads in a thread state register in a
memory of the embedded-system device. At operation 306, the
embedded-system device stores information data associated with the
respective operational state of each of the one or more threads in
the thread state register. In certain configurations, the
information data of the each thread include a thread indicator of
the each thread. In certain configurations, the information data of
the each thread include at least one of an indicator of an
iteration count, an indicator of presence of an external loop, and
an indicator of a sub-function of the each thread.
[0041] In certain configurations, each of the one or more threads
operates in one or more operational states. In certain
configurations, the respective operational state of each of the one
or more threads is determined by the each thread. In certain
configurations, the respective operational state of each of the one
or more threads is further determined based on a respective
function invoked by the each thread. In certain configurations, the
respective function determines that the each thread has invoked the
respective function. The respective operational state is stored in
the thread state register by the respective function in association
with the each thread. In certain configurations, the respective
operational state is associated with the each thread by a thread
indicator of the each thread. In certain configurations, the
respective operational state of each of the one or more threads is
determined a plurality of times throughout operation of the each
thread when the each thread executes one or more functions. In
certain configurations, the one or more functions include at least
one of a write function, a read function, a listen function, a send
function, and a wait function.
[0042] At operation 308, the embedded-system device determines that
operation of at least one thread of the one or more threads is
abnormal. In certain configurations, the operation of the at least
one thread is determined to be normal or abnormal periodically by a
monitor thread. In certain configurations, the determining that the
operation of the at least one thread is abnormal includes
determining that the operational state of the at least one thread
has not been updated for a predetermined time period. At operation
310, the embedded-system device retrieves the stored operational
states of the one or more threads from the thread state register in
response to the determination. At operation 312, the
embedded-system device outputs the retrieved operational states. In
certain configurations, the operational states of the one or more
threads are output to a non-volatile memory.
[0043] In certain configurations, the operational states of the one
or more threads that are output at different times are stored in
the non-volatile memory to maintain a history of the operational
states of the one or more threads. At operation 314, the
embedded-system device receives a request through an IPMI interface
from another device; At operation 316, the embedded-system device
retrieves the operational states stored in the non-volatile memory
in response to the request. At operation 318, the embedded-system
device sends the retrieved operational states to the another device
through the IPMI interface.
[0044] FIG. 4 is a diagram 400 illustrating an example of a
hardware implementation for an apparatus 102' employing a
processing system 414. The processing system 414 may be implemented
with a bus architecture, represented generally by the bus 424. The
bus 424 may include any number of interconnecting buses and bridges
depending on the specific application of the processing system 414
and the overall design constraints. The bus 424 links together
various circuits including one or more processors and/or hardware
components, represented by the processor 404, the processes 121-1,
121-2, 121-3, the threads 122-1, 122-2, 122-3, 122-4, the monitor
thread 152, the register 132, the IPMI interface 118, the transfer
process 126, and the computer-readable medium/memory 406. In
particular, the computer-readable medium/memory 406 may include the
storage 117. The bus 424 may also link various other circuits such
as timing sources, peripherals, voltage regulators, and power
management circuits, which are well known in the art, and
therefore, will not be described any further.
[0045] The processing system 414 may be coupled to a network
controller 410. The network controller 410 provides a means for
communicating with various other apparatus over a network. The
network controller 410 receives a signal from the network, extracts
information from the received signal, and provides the extracted
information to the processing system 414, specifically the IPMI
interface 118. In addition, the network controller 410 receives
information from the processing system 414, specifically the IPMI
interface 118, and based on the received information, generates a
signal to be sent to the network. The processing system 414
includes a processor 404 coupled to a computer-readable
medium/memory 406. The processor 404 is responsible for general
processing, including the execution of software stored on the
computer-readable medium/memory 406. The software, when executed by
the processor 404, causes the processing system 414 to perform the
various functions described supra for any particular apparatus. The
computer-readable medium/memory 406 may also be used for storing
data that is manipulated by the processor 404 when executing
software. The processing system further includes at least one of
the processes 121-1, 121-2, 121-3, the threads 122-1, 122-2, 122-3,
122-4, the monitor thread 152, the register 132, the IPMI interface
118, the transfer process 126. The components may be software
components running in the processor 404, resident/stored in the
computer readable medium/memory 406, one or more hardware
components coupled to the processor 404, or some combination
thereof.
[0046] The apparatus 102' may be configured to include means for
performing each of the operations described supra referring to FIG.
3. The aforementioned means may be one or more of the
aforementioned components of the apparatus 102 and/or the
processing system 414 of the apparatus 102' configured to perform
the functions recited by the aforementioned means.
[0047] FIG. 5 and the following discussion are intended to provide
a brief, general description of one suitable computing environment
in which aspects of the embodiments described herein may be
implemented. In particular, FIG. 5 shows a computer architecture
for a computer 502 that may be utilized to embody the host computer
190, as described supra. It should be appreciated that the computer
architecture shown in FIG. 5 is merely illustrative and that other
types of computers and computing devices may also be utilized to
implement aspects of the embodiments presented herein.
[0048] While aspects presented herein include computer programs
that execute in conjunction with the execution of an operating
system, those skilled in the art will recognize that the
embodiments may also be implemented in combination with other
program modules and/or hardware devices. As described herein,
computer programs include routines, programs, components, data
structures, and other types of structures that perform particular
tasks or implement particular abstract data types. Moreover, those
skilled in the art will appreciate that the embodiments described
herein may be practiced with other computer system configurations,
including hand-held devices, multiprocessor systems,
microprocessor-based or programmable consumer electronics,
minicomputers, mainframe computers, and the like. The embodiments
described herein may also be practiced in distributed computing
environments where tasks are performed by remote processing devices
that are linked through a communications network. In a distributed
computing environment, program modules may be located in both local
and remote memory storage devices.
[0049] The computer 502 shown in FIG. 5 includes a baseboard, or
"motherboard," which is a printed circuit board to which a
multitude of components or devices may be connected by way of a
system bus or other electrical communication path. In one
illustrative embodiment, a CPU 522 operates in conjunction with a
chipset 552. The CPU 522 is a standard central processor that
performs arithmetic and logical operations necessary for the
operation of the computer. The server computer 502 may include a
multitude of CPUs 522.
[0050] The chipset 552 includes a north bridge 524 and a south
bridge 526. The north bridge 524 provides an interface between the
CPU 522 and the remainder of the computer 502. The north bridge 524
also provides an interface to a random access memory ("RAM") used
as the main memory 554 in the computer 502 and, possibly, to an
on-board graphics adapter 530. The north bridge 524 may also
include functionality for providing networking functionality
through a gigabit Ethernet adapter 528. The gigabit Ethernet
adapter 528 is capable of connecting the computer 502 to another
computer via a network. Connections which may be made by the
network adapter 528 may include LAN or WAN connections. LAN and WAN
networking environments are commonplace in offices, enterprise-wide
computer networks, intranets, and the internet. The north bridge
524 is connected to the south bridge 526.
[0051] The south bridge 526 is responsible for controlling many of
the input/output functions of the computer 502. In particular, the
south bridge 526 may provide one or more USB ports 532, a sound
adapter 546, an Ethernet controller 560, and one or more
general-purpose input/output (GPIO) pins 534. The south bridge 526
may also provide a bus for interfacing peripheral card devices such
as a graphics adapter 562. In one embodiment, the bus comprises a
PCI bus. The south bridge 526 may also provide a system management
bus 564 for use in managing the various components of the computer
502. Additional details regarding the operation of the system
management bus 564 and its connected components are provided
below.
[0052] The south bridge 526 is also operative to provide one or
more interfaces for connecting mass storage devices to the computer
502. For instance, according to an embodiment, the south bridge 526
includes a serial advanced technology attachment (SATA) adapter for
providing one or more SATA ports 536 and an ATA 100 adapter for
providing one or more ATA 100 ports 544. The SATA ports 536 and the
ATA 100 ports 544 may be, in turn, connected to one or more mass
storage devices such as the SATA disk drive 538 storing an
operating system 540 and application programs.
[0053] As known to those skilled in the art, an operating system
540 comprises a set of programs that control operations of a
computer and allocation of resources. An application program is
software that runs on top of the operating system software, or
other runtime environment, and uses computer resources to perform
application specific tasks desired by the user. According to one
embodiment of the invention, the operating system 540 comprises the
LINUX operating system. According to another embodiment of the
invention the operating system 540 comprises an operating system
within the WINDOWS family of operating systems from MICROSOFT
CORPORATION. According to another embodiment, the operating system
540 comprises the UNIX, LINUX, or SOLARIS operating system. It
should be appreciated that other operating systems may also be
utilized.
[0054] The mass storage devices connected to the south bridge 526,
and their associated computer storage media, provide non-volatile
storage for the computer 502. Although the description of computer
storage media contained herein refers to a mass storage device,
such as a hard disk or CD-ROM drive, it should be appreciated by
those skilled in the art that computer storage media can be any
available media that can be accessed by the computer 502.
[0055] By way of example, and not limitation, computer storage
media may comprise volatile and non-volatile, removable and
non-removable media implemented in any method or technology for
storage of information such as computer-readable instructions, data
structures, program modules or other data. Computer storage media
also includes, but is not limited to, RAM, ROM, EPROM, EEPROM,
flash memory or other solid state memory technology, CD-ROM, DVD,
HD-DVD, BLU-RAY, or other optical storage, magnetic cassettes,
magnetic tape, magnetic disk storage or other magnetic storage
devices, or any other medium which can be used to store the desired
information and which can be accessed by the computer.
[0056] According to embodiments, a low pin count (LPC) interface
may also be provided by the south bridge 526 for connecting a
"Super I/O" device 570. The Super I/O device 570 is responsible for
providing a number of input/output ports, including a keyboard
port, a mouse port, a serial interface 572, a parallel port, and
other types of input/output ports. The LPC interface may also
connect a computer storage media such as a ROM or a flash memory
such as a non-volatile random-access memory (NVRAM) 548 for storing
the firmware 550 that includes program code containing the basic
routines that help to start up the computer 502 and to transfer
information between elements within the computer 502.
[0057] As described briefly above, the south bridge 526 may include
a system management bus 564. The system management bus 564 may
include a BMC 566. The BMC 566 may be the embedded-system device
102. In general, the BMC 566 is a microcontroller that monitors
operation of the computer system 502. In a more specific
embodiment, the BMC 566 monitors health-related aspects associated
with the computer system 502, such as, but not limited to, the
temperature of one or more components of the computer system 502,
speed of rotational components (e.g., spindle motor, CPU Fan, etc.)
within the system, the voltage across or applied to one or more
components within the system 502, and the available or used
capacity of memory devices within the system 502. To accomplish
these monitoring functions, the BMC 566 is communicatively
connected to one or more components by way of the management bus
564. In an embodiment, these components include sensor devices 568
for measuring various operating and performance-related parameters
within the computer system 502. The sensor devices 568 may be
either hardware or software based components configured or
programmed to measure or detect one or more of the various
operating and performance-related parameters.
[0058] It should also be appreciated that the computer 502 may
comprise other types of computing devices, including hand-held
computers, embedded computer systems, personal digital assistants,
and other types of computing devices known to those skilled in the
art. It is also contemplated that the computer 502 may not include
all of the components shown in FIG. 5, may include other components
that are not explicitly shown in FIG. 5, or may utilize an
architecture completely different than that shown in FIG. 5.
[0059] It is understood that the specific order or hierarchy of
blocks in the processes/flowcharts disclosed is an illustration of
exemplary approaches. Based upon design preferences, it is
understood that the specific order or hierarchy of blocks in the
processes/flowcharts may be rearranged. Further, some blocks may be
combined or omitted. The accompanying method claims present
elements of the various blocks in a sample order, and are not meant
to be limited to the specific order or hierarchy presented.
[0060] The previous description is provided to enable any person
skilled in the art to practice the various aspects described
herein. Various modifications to these aspects will be readily
apparent to those skilled in the art, and the generic principles
defined herein may be applied to other aspects. Thus, the claims
are not intended to be limited to the aspects shown herein, but is
to be accorded the full scope consistent with the language claims,
wherein reference to an element in the singular is not intended to
mean "one and only one" unless specifically so stated, but rather
"one or more." The word "exemplary" is used herein to mean "serving
as an example, instance, or illustration." Any aspect described
herein as "exemplary" is not necessarily to be construed as
preferred or advantageous over other aspects. Unless specifically
stated otherwise, the term "some" refers to one or more.
Combinations such as "at least one of A, B, or C," "one or more of
A, B, or C," "at least one of A, B, and C," "one or more of A, B,
and C," and "A, B, C, or any combination thereof" include any
combination of A, B, and/or C, and may include multiples of A,
multiples of B, or multiples of C. Specifically, combinations such
as "at least one of A, B, or C," "one or more of A, B, or C," "at
least one of A, B, and C," "one or more of A, B, and C," and "A, B,
C, or any combination thereof" may be A only, B only, C only, A and
B, A and C, B and C, or A and B and C, where any such combinations
may contain one or more member or members of A, B, or C. All
structural and functional equivalents to the elements of the
various aspects described throughout this disclosure that are known
or later come to be known to those of ordinary skill in the art are
expressly incorporated herein by reference and are intended to be
encompassed by the claims. Moreover, nothing disclosed herein is
intended to be dedicated to the public regardless of whether such
disclosure is explicitly recited in the claims. The words "module,"
"mechanism," "element," "device," and the like may not be a
substitute for the word "means." As such, no claim element is to be
construed as a means plus function unless the element is expressly
recited using the phrase "means for."
* * * * *