U.S. patent application number 15/704413 was filed with the patent office on 2018-01-04 for semiconductor device.
This patent application is currently assigned to MITSUBISHI ELECTRIC CORPORATION. The applicant listed for this patent is MITSUBISHI ELECTRIC CORPORATION. Invention is credited to Katsumi NAKAMURA.
Application Number | 20180006160 15/704413 |
Document ID | / |
Family ID | 43049505 |
Filed Date | 2018-01-04 |
United States Patent
Application |
20180006160 |
Kind Code |
A1 |
NAKAMURA; Katsumi |
January 4, 2018 |
SEMICONDUCTOR DEVICE
Abstract
The first layer is located on the first electrode and has the
first conductivity type. The second layer is located on the first
layer and has the second conductivity type. The third layer is
located on the second layer. The second electrode is located on the
third layer. The fourth layer is located between the second layer
and the third layer, and has the second conductivity type. The
third layer includes the first portion and the second portion. The
first portion has the second conductivity type and has a peak value
of an impurity concentration higher than the peak value of the
impurity concentration in the second layer. The second portion has
the first conductivity type. The area of the second portion
accounts for not less than 20% and not more than 95% of the total
area of the first portion and the second portion.
Inventors: |
NAKAMURA; Katsumi;
(Chiyoda-ku, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MITSUBISHI ELECTRIC CORPORATION |
Chiyoda-ku |
|
JP |
|
|
Assignee: |
MITSUBISHI ELECTRIC
CORPORATION
Chiyoda-ku
JP
|
Family ID: |
43049505 |
Appl. No.: |
15/704413 |
Filed: |
September 14, 2017 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14688640 |
Apr 16, 2015 |
9786796 |
|
|
15704413 |
|
|
|
|
12716427 |
Mar 3, 2010 |
9035434 |
|
|
14688640 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/861 20130101;
H01L 29/36 20130101; H01L 29/0834 20130101; H01L 29/7397 20130101;
H01L 29/8618 20130101 |
International
Class: |
H01L 29/861 20060101
H01L029/861; H01L 29/36 20060101 H01L029/36; H01L 29/739 20060101
H01L029/739; H01L 29/08 20060101 H01L029/08 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 4, 2009 |
JP |
2009-135077 |
Claims
1. A semiconductor device comprising: a first electrode; a first
layer located on said first electrode and having a first
conductivity type; a second layer located on said first layer and
having a second conductivity type different from said first
conductivity type; a third layer located on said second layer and
having a first portion, said first portion having said second
conductivity type and having a peak value of an impurity
concentration higher than the peak value of the impurity
concentration in said second layer; a second electrode located on
said third layer; and a trench structure located in said first
portion and applied with an electric potential which is positive
with respect to an electric potential of said second electrode,
wherein said third layer includes a second portion having said
first conductivity type.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. Ser. No. 14/688,640,
filed Apr. 16, 2015, which is a division of U.S. Ser. No.
12/716,427 filed Mar. 3, 2010 (now U.S. Pat. No. 9,035,434), and
claims the benefit of priority under 35 U.S.C. .sctn.119 from
Japanese Patent Application No. 2009-135077 filed Jun. 4, 2009 the
entire contents of each of which are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
Field of the Invention
[0002] The present invention relates to a semiconductor device, and
particularly to a power semiconductor device.
Description of the Background Art
[0003] A power semiconductor device includes a high breakdown
voltage power module which can withstand a voltage of, for example,
600 V or higher. Such a power module may have a diode formed
thereon.
[0004] For example, Japanese Patent Laying-Open No. 02-066977
discloses a diode having a pn junction formed by an n.sup.- layer
adjacent to a p layer, in which an n.sup.+ region and a p.sup.+
region are located on the surface of the n.sup.- layer opposite to
the p.sup.+ layer. In addition, an n buffer layer is located
between the n.sup.- layer and the region including the n.sup.+
region and the p.sup.+ region. This document discloses that the
p.sup.+ region has an effect of reducing a reverse recovery current
of the diode and also shortening the reverse recovery time. It also
discloses that the n buffer layer can prevent the depletion layer
from extending to the n.sup.- layer during application of the
reverse voltage, which allows a reduction in thickness of the
n.sup.- layer, with the result that the reverse recovery
characteristics of the high breakdown voltage diode can be
improved.
[0005] Furthermore, for example, Japanese Patent Laying-Open No.
08-172205 discloses a diode including an n.sup.- semiconductor
layer formed on one main surface of an n-type semiconductor
substrate; an n.sup.+ cathode region formed on the surface layer of
the n.sup.- semiconductor layer; a trench extending from the
surface of the n.sup.+ cathode region through the n.sup.-
semiconductor layer to the n-type semiconductor substrate; a gate
electrode filling the trench with a gate oxide film interposed
therebetween; an insulation film formed on the gate electrode; a
cathode electrode in contact with the surface of the n.sup.+
cathode region interposed between the trenches; a p.sup.+ anode
region formed on a part of the surface layer of the n-type
semiconductor substrate; and an anode electrode in contact with the
p.sup.+ anode region. According to this document, as the gate
electrode is applied with a voltage which is negative with respect
to the cathode electrode, a breakdown of the diode and burning of
the switching transformer can be prevented when an overcurrent
flows through the diode.
[0006] With regard to the power diode, it is difficult to solve the
problems involved in both of the tasks of decreasing a forward
voltage drop (V.sub.F) and suppressing the oscillation at the time
of recovery (reverse recovery). For example, Japanese Patent
Laying-Open No. 02-066977 as described above merely discloses that
the recovery characteristics can be improved by providing a p.sup.+
region, but fails to disclose how to configure the p.sup.+ region
for allowing the above-described problems to be solved in a
balanced manner.
[0007] Furthermore, it may be desirable to especially decrease
V.sub.F depending on the use of the power diode. However, according
to the technique disclosed in Japanese Patent Laying-Open No.
08-172205 described above, the gate electrode is applied with a
voltage that is negative with respect to the cathode electrode,
which causes a problem of an increase in V.sub.F.
SUMMARY OF THE INVENTION
[0008] The present invention has been made in light of the
above-described problems, and an object of the present invention is
to provide a semiconductor device capable of decreasing V.sub.F and
suppressing the oscillation at the time of recovery. Furthermore,
another object of the present invention is to provide a
semiconductor device capable of particularly decreasing
V.sub.F.
[0009] A semiconductor device according to one aspect of the
present invention includes first and second electrodes, and first
to fourth layers. The first layer is located on the first electrode
and has a first conductivity type. The second layer is located on
the first layer and has a second conductivity type different from
the first conductivity type. The third layer is located on the
second layer. The second electrode is located on the third layer.
The fourth layer is located between the second layer and the third
layer, and has the second conductivity type. The third layer
includes first and second portions. The first portion has the
second conductivity type and has a peak value of an impurity
concentration higher than the peak value of the impurity
concentration in the second layer. The second portion has the first
conductivity type. An area of the second portion accounts for not
less than 20% and not more than 95% of a total area of the first
and the second portions.
[0010] A semiconductor device according to another aspect of the
present invention includes first and second electrodes, first to
third layers, and a trench structure. The first layer is located on
the first electrode and has a first conductivity type. The second
layer is located on the first layer and has a second conductivity
type different from the first conductivity type. The third layer is
located on the second layer and has a first portion. The first
portion has the second conductivity type and has a peak value of an
impurity concentration higher than the peak value of the impurity
concentration in the second layer. The second electrode is located
on the third layer. The trench structure is located in the first
portion and applied with an electric potential which is positive
with respect to an electric potential of the second electrode.
[0011] The semiconductor device according to an aspect of the
present invention allows a decrease in V.sub.F of a diode and also
allows suppression of the oscillation at the time of recovery.
[0012] The semiconductor device according to another aspect of the
present invention allows a decrease in V.sub.F of the diode.
[0013] The foregoing and other objects, features, aspects and
advantages of the present invention will become more apparent from
the following detailed description of the present invention when
taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a cross-sectional view schematically showing the
configuration of a diode as a semiconductor device according to the
first embodiment of the present invention.
[0015] FIG. 2 is a graph schematically showing impurity profiles
C.sub.A and C.sub.B along arrows D.sub.A and D.sub.B, respectively,
in FIG. 1.
[0016] FIG. 3 is a diagram showing a circuit used for each
simulation for the diode in FIG. 1 and a comparative example
thereof.
[0017] FIG. 4 is a graph showing an example of the simulations for
the recovery characteristic waveform with regard to each diode in
FIG. 1 and in the comparative example.
[0018] FIG. 5 is a graph showing an example of a relationship
J.sub.A1 between a voltage V.sub.AK and a current density J.sub.A
in the forward direction of the diode in FIG. 1, and an example of
a relationship J.sub.A0 between a voltage V.sub.AK and a current
density J.sub.A in the forward direction of the diode in the
comparative example.
[0019] FIG. 6 is a diagram showing an example of the cross point at
which relationships between voltage V.sub.AK and current density
J.sub.A cross each other in accordance with the temperature
change.
[0020] FIG. 7 is a graph schematically showing an example of a
relationship J.sub.R1 between a voltage V.sub.RA and a current
density J.sub.R in the reverse direction of the diode in FIG. 1,
and an example of a relationship J.sub.R0 between voltage V.sub.RA
and current density J.sub.R in the reverse direction of the diode
in the comparative example.
[0021] FIG. 8 is a graph schematically showing an electric field
intensity E and a carrier concentration CC at a point P.sub.B in
FIG. 4.
[0022] FIG. 9 is a graph showing an example of the relationship
between each of a surge voltage V.sub.surge and V.sub.F at the
rated current density in the diode in FIG. 1 and the ratio of a
width W.sub.P of a p layer to a width W.sub.C of a cathode
portion.
[0023] FIG. 10 is a graph showing an example of the recovery
characteristics of the diode in the case where width W.sub.P of the
p layer accounts for 0% of width W.sub.C of the cathode portion in
FIG. 1.
[0024] FIG. 11 is a graph showing an example of the recovery
characteristics of the diode in the case where width W.sub.P of the
p layer accounts for 10% of width W.sub.C of the cathode portion in
FIG. 1.
[0025] FIG. 12 is a graph showing an example of the recovery
characteristics of the diode in the case where width W.sub.P of the
p layer accounts for 20% of width W.sub.C of the cathode portion in
FIG. 1.
[0026] FIG. 13 is a graph showing an example of the recovery
characteristics of the diode in the case where width W.sub.P of the
p layer accounts for 50% of width W.sub.C of the cathode portion in
FIG. 1.
[0027] FIG. 14 is a graph showing an example of the relationship
between each of a maximum reverse voltage V.sub.RRM, V.sub.F at the
rated current density and surge voltage V.sub.surge in the diode in
FIG. 1, and a ratio C.sub.1/C.sub.3 of peak values C.sub.1 and
C.sub.3 of the impurity concentration in FIG. 2.
[0028] FIG. 15 is a graph showing an example of a characteristic
curve E.sub.REC1 illustrating trade-off characteristics between a
recovery loss E.sub.REC and V.sub.F at the rated current density of
the diode in FIG. 1 in the case where a peak value C.sub.2 is
higher than C.sub.1 in FIG. 2; an example of a characteristic curve
E.sub.REC2 illustrating the relationship between recovery loss
E.sub.REC and V.sub.F at the rated current density of the diode in
FIG. 1 in the case where peak value C.sub.1 is equal to peak value
C.sub.2 in FIG. 2; and an example of a characteristic curve
E.sub.REC0 illustrating the relationship between recovery loss
E.sub.REC and V.sub.F at the rated current density of the diode in
the comparative example.
[0029] FIG. 16 is a graph showing an example of the relationship
between V.sub.F at the rated current density in the diode in FIG. 1
and a ratio C.sub.2/C.sub.1 of peak values C.sub.1 and C.sub.2 of
the impurity concentration in FIG. 2.
[0030] FIG. 17 is a graph showing an example of a hole
concentration CCh1 and an electron concentration CCe1 along an
arrow D.sub.A (FIG. 1) in the ON state in the case where peak value
C.sub.2 is higher than C.sub.1 in FIG. 2; and an example of a hole
concentration CCh2 and an electron concentration CCe2 along arrow
D.sub.A (FIG. 1) in the ON state in the case where peak value
C.sub.1 is equal to C.sub.2 in FIG. 2.
[0031] FIG. 18 is a cross-sectional view schematically showing the
configuration of the diode as a semiconductor device in the second
embodiment of the present invention.
[0032] FIG. 19 is a cross-sectional view schematically showing the
configuration of a modification of the diode in FIG. 18.
[0033] FIG. 20 is a cross-sectional view schematically showing the
configuration of the diode as a semiconductor device in the third
embodiment of the present invention.
[0034] FIG. 21 is a cross-sectional view schematically showing the
configuration of the first modification of the diode in FIG.
20.
[0035] FIG. 22 is a cross-sectional view schematically showing the
configuration of the second modification of the diode in FIG.
20.
[0036] FIG. 23 is a graph showing an example of carrier
concentrations CC3 and CC0 in the ON state in each diode in FIG. 20
and in the comparative example.
[0037] FIG. 24 is a graph showing an example of a relationship
J.sub.A3 between voltage V.sub.AK and current density J.sub.A in
the forward direction of the diode in FIG. 20; and an example of a
relationship J.sub.A0 between voltage V.sub.AK and current density
J.sub.A in the forward direction of the diode in the comparative
example.
[0038] FIG. 25 is a graph showing an example of the relationship
between a trench depth y in FIG. 20 and V.sub.F at the rated
current density.
[0039] FIG. 26 is a cross-sectional view showing the configuration
of the diode in the comparative example.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0040] An embodiment of the present invention will be hereinafter
described with reference to the drawings.
First Embodiment
[0041] Referring to FIG. 1, a diode as a semiconductor device
according to the present embodiment includes an anode electrode 5
(the first electrode), a p layer 3 (the first layer), an n.sup.-
drift layer 1 (the second layer), an n layer 15 (the fourth layer),
a cathode layer CLa (the third layer), and a cathode electrode 4
(the second electrode). For example, p layer 3, n.sup.- drift layer
1, n layer 15, and cathode layer CLa are, for example, made of Si
to which conductive impurities are added.
[0042] P layer 3 is located on (in the figure, immediately below)
anode electrode 5 and has a p-type (the first conductivity
type).
[0043] N.sup.- drift layer 1 is located on (in the figure,
immediately below) p layer 3 to have a thickness of a dimension t3.
Furthermore, n.sup.- drift layer 1 has a conductivity type
different from a p-type, that is, an n-type (the second
conductivity type).
[0044] Cathode layer CLa is located on (in the figure, below)
n.sup.- drift layer 1 with n layer 15 interposed therebetween.
Cathode layer CLa is in a rectangular shape having a width W.sub.c
in plan view taken at right angles to the width direction. Cathode
layer CLa also includes an n.sup.+ region 2 (the first portion)
having an n-type and a p region 16 (the second portion) having a
p-type.
[0045] Furthermore, in the present embodiment, n.sup.+ region 2 and
p region 16 are each in a rectangular shape having a width W.sub.n
and a width W.sub.p, respectively, in plan view. Cathode layer CLa,
n.sup.+ region 2 and p region 16 are identical in length (at right
angles to the width) in plan view. Width W.sub.c, width W.sub.n and
width W.sub.p establish the relationship of
W.sub.c=W.sub.n+W.sub.p. Consequently, the ratio of the area of
n.sup.+ region 2 to the area of p region 16 in plan view is
W.sub.n:W.sub.p. Furthermore, cathode layer CLa is formed such that
the following expression is satisfied.
0.2.ltoreq.W.sub.p/W.sub.c.ltoreq.0.95
[0046] Accordingly, the area of p region 16 accounts for not less
than 20% and not more than 95% of the total area of n.sup.+ region
2 and p region 16 on n layer 15.
[0047] It is to be noted that a dimension t1 in the figure is
equivalent to each thickness of n.sup.+ region 2 and p region 16
which is, for example, 0.2 to 5 .mu.m. Furthermore, a dimension
t.sub.sub is equivalent to the entire thickness of the
semiconductor layer.
[0048] N layer 15 is located between n.sup.- drift layer 1 and
cathode layer CLa, and has an n-type (the second conductivity
type). Furthermore, n layer 15 has a thickness of a dimension
obtained by subtracting dimension t1 from a dimension t2 in the
figure, which is 1 to 50 .mu.m, for example. N layer 15 has an n
region 15n (the third portion) located on n.sup.+ region 2 and an n
region 15p (the fourth portion) located on p region 16. In
addition, n layer 15 substantially contains only the n-type
conductive impurities but does not substantially contain the p-type
conductive impurities.
[0049] Cathode electrode 4 is located on cathode layer CLa.
[0050] Referring to FIG. 2, impurity profiles C.sub.A and C.sub.B
each show a distribution of the impurity concentration in depths
D.sub.A and D.sub.B, respectively (FIG. 1). N.sup.+ region 2 has a
peak value C.sub.4 of an impurity concentration higher than a peak
value C.sub.0 of the impurity concentration in n.sup.- drift layer
1, and also higher than a peak value C.sub.3 of the impurity
concentration in p region 16. The ratio of a peak value C.sub.1 of
the impurity concentration in n region 15p to peak value C.sub.3 of
the impurity concentration in p region 16 is not less than 0.001
and not more than 0.1. N layer 15 has peak values C.sub.1 and
C.sub.2 of the impurity concentration higher than peak value
C.sub.0 of the impurity concentration in n.sup.- drift layer 1 and
lower than peak value C.sub.4 of the impurity concentration in
n.sup.+ region 2 of cathode layer CLa.
[0051] For example, the surface concentration of n.sup.+ region 2
is 1.times.10.sup.17 to 1.times.10.sup.21 cm.sup.-3, and the
surface concentration of p region 16 is 1.times.10.sup.16 to
1.times.10.sup.21 cm.sup.-3. Furthermore, peak values C.sub.1 and
C.sub.2 of the impurity concentration in n layer 15 each are
1.times.10.sup.16 to 1.times.10.sup.20 cm.sup.-3.
[0052] In the present embodiment, n layer 15 substantially contains
only the n-type conductive impurities, but does not substantially
contain the p-type conductive impurities. Thus, impurity profile
C.sub.B within a section between dimensions t1 and t2 in FIG. 2
shows the concentration of the n-type conductive impurities. In the
case where n region 15p also substantially contains the p-type
conductive impurities in addition to the n-type conductive
impurities, the impurity concentration means an effective impurity
concentration, that is, a concentration difference between the
p-type and n-type conductive impurities.
[0053] The diode according to a comparative example will then be
described.
[0054] Referring to FIG. 26, the diode in the comparative example
has a cathode layer CLb including n.sup.+ region 2, in place of
cathode layer CLa according to the present embodiment. N layer 15
is located immediately on cathode layer CLb. The following two
problems may be caused in this comparative example.
[0055] As to the first problem, during the recovery operation, it
is more likely that the hole concentration remaining on the side
close to n.sup.+ region 2 and n layer 15 decreases and a depletion
layer extends. The oscillation phenomenon occurs at the instant
when this depletion layer reaches n layer 15. Consequently, the
safe operating area (SOA) tolerance and the recovery tolerance are
reduced.
[0056] As to the second problem, in order to address the
oscillation phenomenon during recovery, it is necessary to delay
extension of the depletion layer from the junction of p layer
3/n.sup.- drift layer 1 serving as a main junction toward the
cathode side. This requires an increase in dimension t3
corresponding to the thickness of the n.sup.- drift layer in the
present comparative example. As a result, it becomes difficult to
improve the trade-off characteristics between a decrease in V.sub.F
and a recovery loss (E.sub.REC).
[0057] In the comparative example, dimension t3 is set to be
relatively short which causes the above-described first problem,
and dimension t3 is set to be relatively long which causes the
above-described second problem. Thus, in the present comparative
example, it is difficult to achieve an improvement of the trade-off
characteristics between a decrease in V.sub.F and recovery loss,
and also achieve an improvement of the SOA tolerance by suppression
of the oscillation phenomenon and the like.
[0058] In contrast, the present embodiment allows a decrease in
V.sub.F and also allows an improvement of the SOA tolerance while
ensuring a high breakdown voltage. In other words, it becomes
possible to decrease V.sub.F, improve the maximum reverse voltage,
and suppress the oscillation at the time of recovery.
[0059] Referring to FIG. 3, in order to verify the above-described
operations and effects, simulations were performed for the circuit
including a diode rated at 3300V class as an example of the
semiconductor device according to the present embodiment. This
circuit includes a diode DD, a transistor TR corresponding to an
IGBT (Insulated Gate Bipolar Transistor), coils LM, LAK and LCE,
resistances RL, RAK, RCE, and RG, power supplies VC and VG, and a
current source ION. Coil LM is provided for a parasitic inductance,
resistance RG is provided for the gate resistance of the IGBT, and
power supply VG is provided for the gate voltage of the IGBT.
Furthermore, coils LAK and LCE are provided for a wiring impedance
for providing matching between the measured results and the
simulation results. Resistances RL, RAK and RCE are provided for a
wiring-related resistance for providing matching between the
measured results and the simulation results. The simulation results
will be hereinafter described.
[0060] Referring to FIG. 4, with regard to the present example and
the comparative example, simulations were performed for the
recovery characteristic waveform, that is, changes over time of a
voltage V.sub.AK and a current density J.sub.A during the recovery.
The figure shows a voltage V.sub.AK1 and a current density J.sub.A1
in the case of the diode in the present example (FIG. 1), and shows
a voltage V.sub.AK0 and a current density J.sub.A0 in the case of
the diode in the comparative example (FIG. 26). In the present
example, the oscillation occurring during the recovery can be
suppressed as compared to the case in the comparative example.
Accordingly, a surge voltage V.sub.surge corresponding to a peak
voltage of voltage V.sub.AK which is not less than 5000V in the
comparative example can be suppressed approximately to 3000V in the
present example.
[0061] It is to be noted that the simulation conditions are set
such that coil LM is 12 .mu.m, power supply VC is 1700V, a rated
current density J.sub.AR is 90 A/cm.sup.2, and a current J.sub.F in
the forward direction is J.sub.AR/10, and a temperature is
298K.
[0062] Referring to FIG. 5, simulations were performed for the
characteristics of current density J.sub.A-voltage V.sub.AK. The
figure shows a relationship J.sub.A1 in the case of the diode in
the example (FIG. 1) according to the present embodiment, and a
relationship J.sub.A0 in the case of the diode in the comparative
example (FIG. 26). Furthermore, V.sub.F shows voltage V.sub.AK at
the time when current density J.sub.A corresponds to rated current
density J.sub.AR=90 A/cm.sup.2. According to the present example,
V.sub.F can be decreased as compared to the case in the comparative
example.
[0063] In addition, the characteristics of current density
J.sub.A-voltage V.sub.AK generally vary with temperature. The
characteristics of current density J.sub.A-voltage V.sub.AK at
temperatures of 25 C..degree. and 12 C..degree. are as shown in
FIG. 6, for example. It is to be noted that the point at which the
characteristic curves cross each other is assumed to be a cross
point CP.
[0064] Referring to FIG. 7, simulations were performed for the
characteristics in the reverse direction (current density
J.sub.R-voltage V.sub.RA). The figure shows a relationship J.sub.R1
in the case of the diode in the present example (FIG. 1) and a
relationship J.sub.R0 in the case of the diode in the comparative
example (FIG. 26). Furthermore, a maximum reverse voltage V.sub.RRM
is assumed to be a voltage V.sub.RA at the time when current
density J.sub.R=1.times.10.sup.-2 A/cm.sup.2. According to the
present example, maximum reverse voltage V.sub.RRM can be increased
as compared to the case in the comparative example.
[0065] In the case where n layer 15 substantially contains p-type
conductive impurities, maximum reverse voltage V.sub.RRM is
decreased. Conversely, in the case where n layer 15 substantially
contains only the n-type conductive impurities, maximum reverse
voltage V.sub.RRM is increased.
[0066] Mainly referring to FIG. 8, the distributions of an electric
field intensity E and a carrier concentration CC in the depth
direction of the device at a point P.sub.B (FIG. 4) were analyzed
by simulation. In the figure, the horizontal axis corresponds to a
depth along an arrow D.sub.A (FIG. 1). Furthermore, the figure
shows a hole concentration CCh1, an electron concentration CCe1 and
an electric field intensity E1 in the case of the diode in the
present example (FIG. 1), and also shows a hole concentration CCh0,
an electron concentration CCe0 and an electric field intensity E0
in the case of the diode in the comparative example (FIG. 26).
According to the configuration in the present example (FIG. 1),
when holes are injected from p region 16 located close to the
cathode side during the recovery phenomenon, hole concentration
CCh1 on the cathode side is improved as compared to the case of
hole concentration CCh0 in the comparative example. Consequently,
as indicated by an arrow RE in the figure, the electric-field
relaxation phenomenon occurs in which electric field intensity E on
the cathode side is reduced.
[0067] Mainly referring to FIGS. 9-13, in order to examine the
correlation (FIG. 9) of each of V.sub.F (FIG. 5) and surge voltage
V.sub.surge (FIG. 4) with a width ratio W.sub.p/W.sub.c (FIG. 1),
simulations (for example, FIGS. 10-13) were performed for the
recovery characteristic waveform (changes over time of a current
I.sub.A and voltage V.sub.AK during recovery) under various ratios
W.sub.p/W.sub.c.
[0068] As a result, in the case where width W.sub.p accounts for
20% or more of width W.sub.e, that is, in the case where the area
of p region 16 accounts for 20% or more of the total area of
n.sup.+ region 2 and p region 16 (FIG. 1), the oscillation is
suppressed during the recovery, which allows surge voltage
V.sub.surge to be remarkably suppressed to 3300V or lower that is a
rated voltage.
[0069] Furthermore, when width W.sub.p exceeds 95% of width
W.sub.c, V.sub.F increases rapidly which may affect the operation
of the diode. Conversely, as width W.sub.p is set to account for
95% or less of width W.sub.c, that is, as the area of p region 16
is set to account for 95% or less of the total area of n.sup.+
region 2 and p region 16, V.sub.F is remarkably suppressed.
[0070] Mainly referring to FIG. 14, the correlation of each of
maximum reverse voltage V.sub.RRM, V.sub.F and surge voltage
V.sub.surge with the ratio C.sub.1/C.sub.3 of peak values C.sub.1
and C.sub.3 (FIG. 2) of the impurity concentration was examined by
simulation. In light of the results shown in FIG. 9, width W.sub.p
was set to account for 20% of width W.sub.c such that the
oscillation during recovery might be suppressed.
[0071] The results of the simulations show that ratio
C.sub.1/C.sub.3 is set to be 1.times.10.sup.-1 or lower, to thereby
allow surge voltage V.sub.surge to be remarkably suppressed to
3300V or lower which corresponds to a rated voltage.
[0072] The results also show that ratio C.sub.1/C.sub.3 is set to
be 1.times.10.sup.-3 or more, to thereby allow maximum reverse
voltage V.sub.RRM (FIG. 7) to be maintained at 3300V or more which
corresponds to a rated voltage. It is considered that this is
because ratio C.sub.1/C.sub.3 is set to be 1.times.10.sup.-3 or
more, which allows suppression of extension of the depletion layer
from the junction of p layer 3/n.sup.- drift layer 1 serving as a
main junction toward the cathode side.
[0073] Referring to FIG. 15, simulations were performed to examine
the trade-off characteristics between recovery loss E.sub.REC
(mJ/Apulse) and V.sub.F (V). The figure shows a characteristic
curve E.sub.REC1 in the case where peak values C.sub.1 and C.sub.2
of the impurity concentration (FIG. 2) satisfy the relation of
C.sub.2<C.sub.1, and a characteristic curve E.sub.REC2 in the
case where peak values C.sub.1 and C.sub.2 satisfy the relation of
C.sub.2=C.sub.1. The figure also shows a characteristic curve
E.sub.REC0 in the case of the diode in the comparative example
(FIG. 26).
[0074] The results show that, as compared to the configuration
(characteristic curve E.sub.REC0) in the comparative example (FIG.
26), the configuration (characteristic curves E.sub.REC1 and
E.sub.REC2) in the present example (FIG. 1) serves to achieve an
improvement in the trade-off relationship between recovery loss
E.sub.REC and V.sub.F, and also achieve a further improvement
particularly in the case where peak values C.sub.1 and C.sub.2 of
the impurity concentration satisfy the relation of
C.sub.2>C.sub.1. In other words, it is found that the
above-described trade-off relationship can be improved while
maintaining dimension t3 (FIGS. 1 and 26) in terms of the SOA, that
is, without the need to decrease dimension t3.
[0075] It is to be noted that V.sub.F decreases with an increase in
ratio C.sub.2/C.sub.1 of the peak values of the impurity
concentration, as shown in FIG. 16.
[0076] FIG. 17 shows the simulation results of carrier
concentration CC in the ON state, that is, in the case where
current density J.sub.A is equal to rated current density J.sub.AR
(FIG. 5). In the figure, the horizontal axis corresponds to a depth
along arrow D.sub.A (FIG. 1). Furthermore, the figure shows hole
concentration CCh1 and electron concentration CCe1 in the case
where peak values C.sub.1 and C.sub.2 of the impurity concentration
satisfy the relation of C.sub.2>C.sub.1, and also shows a hole
concentration CCh2 and an electron concentration CCe2 in the case
where peak values C.sub.1 and C.sub.2 of the impurity concentration
satisfy the relation of C.sub.2=C.sub.1.
[0077] The results described above show that, when peak values
C.sub.1 and C.sub.2 satisfy the relation of C.sub.2>C.sub.1, the
carrier concentration near the cathode is increased in the ON
state. It is considered that this increase in carrier concentration
causes a decrease in V.sub.F (FIG. 16), with the result that the
trade-off relationship between recovery loss E.sub.REC and V.sub.F
(FIG. 15) is improved.
[0078] According to the present embodiment, V.sub.F is decreased,
the oscillation at the time of recovery is suppressed, and maximum
reverse voltage V.sub.RRM is improved, which will be hereinafter
described in detail.
[0079] According to the diode structure (FIG. 1) in the present
embodiment, when holes are injected from p region 16 during the
recovery phenomenon, hole concentration CCh1 (FIG. 8) on the
cathode side is increased above hole concentration CCh0 in the case
of the diode structure (FIG. 26) according to the comparative
example. Consequently, in the present embodiment, the electric
field on the cathode side is relaxed as indicated by arrow RE (FIG.
8) during the recovery, as compared to the case in the comparative
example, which allows suppression of extension of the depletion
layer from the junction of p layer 3/n.sup.- drift layer 1 serving
as a main junction toward the cathode side. Accordingly, the
oscillation phenomenon during the recovery is suppressed as shown
in FIG. 4, resulting in improvement of the SOA tolerance of the
diode. Thus, according to the diode of the present embodiment (FIG.
1), the oscillation can be suppressed by injecting holes from p
region 16 during the recovery phenomenon to thereby cause
electric-field relaxation (to suppress extension of the depletion
layer). Consequently, thickness t3 of n.sup.- drift layer 1 can be
reduced, and thus, the trade-off characteristics between recovery
loss E.sub.REC and V.sub.F can be improved as shown in FIG. 15.
[0080] The proportion of the area of p region 16 occupying the area
of cathode layer CLa in FIG. 1 (ratio W.sub.p/W.sub.c between
widths W.sub.p and W.sub.c in FIG. 1) serves as an important
parameter for facilitating hole injection from the cathode side
during the recovery operation. In other words, as shown in FIG. 4,
V.sub.F and surge voltage V.sub.surge greatly vary significantly
depending on this parameter. According to the present embodiment,
as the following expression (1) is satisfied, an excellent
operation of the diode can be ensured while suppressing the
oscillation at the time of recovery.
20%.ltoreq.ratio W.sub.p/W.sub.c.ltoreq.95% (1)
[0081] In the above expression (1), the upper limit value, 95%,
represents a condition for sufficiently decreasing V.sub.F (FIG. 9)
for practical application. Furthermore, the lower limit value, 20%,
represents a condition for remarkably suppressing a waveform surge
in the V.sub.AK waveform (FIGS. 10 to 13), that is, V.sub.surge
(FIG. 9), to not more than the value of the breakdown voltage class
(3300V in the above-described simulations). As expression (1) is
satisfied in this way, V.sub.F is decreased and the oscillation
during recovery is suppressed.
[0082] As described above, ratio C.sub.1/C.sub.3 (FIG. 14) of peak
values C.sub.1 and C.sub.3 (FIG. 2) of the impurity concentration
satisfies the following expression (2) while decreasing V.sub.F and
suppressing the oscillation at the time of recovery, which allows
maximum reverse voltage V.sub.RRM to be improved.
0.001.ltoreq.ratio C.sub.1/C.sub.3.ltoreq.0.1 (2)
[0083] In the above expression (2), the upper limit value, 0.1,
represents a condition for suppressing V.sub.surge to not more than
the value of the breakdown voltage class (3300V in the
above-described simulations) by injecting sufficient holes from p
region 16 of cathode layer CLa. Furthermore, the lower limit value,
0.001, represents a condition for preventing a decrease in maximum
reverse voltage V.sub.RRM resulting from the fact that the
depletion layer extending toward the cathode side from the junction
of p layer 3/n.sup.- drift layer 1 serving as a main junction
during application of a reverse bias reaches p region 16.
[0084] Furthermore, peak values C.sub.1 and C.sub.2 of the impurity
concentration (FIG. 2) satisfy the following expression (3), which
causes an increase in carrier concentration CC on the cathode side
(FIG. 17) at the time when the diode is in the ON state.
C.sub.2>C.sub.1 (3)
[0085] As described above, the increased carrier concentration CC
results in a decrease in V.sub.F (FIG. 16), and accordingly, the
trade-off characteristics between recovery loss E.sub.REC and
V.sub.F (FIG. 15) is improved.
[0086] In the case where the above-described relations (1) to (3)
are satisfied, a diode having particularly excellent
characteristics can be achieved as compared to the diode in the
comparative example (FIG. 26).
Second Embodiment
[0087] Referring to FIG. 18, a diode as a semiconductor device
according to the present embodiment includes an n-type diffusion
layer 17 (the fifth layer), a trench structure 26a, a diffusion
layer 18, an interlayer dielectric film 19, insulation films 20 and
23, a silicide layer 21a, and a barrier metal layer 22.
[0088] N-type diffusion layer 17 is located between a p layer 3 and
an n.sup.- drift layer 1, and has an n-type. Trench structure 26a
has a trench extending through p layer 3 and n-type diffusion layer
17 and also has a gate electrode 14 filling the trench with a gate
insulation film 12 interposed therebetween. Gate electrode 14 is
electrically insulated from an anode electrode 5 by interlayer
dielectric film 19. Silicide layer 21a serves to implement a low
contact resistance with an Si diffusion layer and is, for example,
made of TiSi.sub.2, CoSi or WSi. Barrier metal layer 22 is, for
example, made of TiN. Interlayer dielectric film 19 is made of a
silicate glass film to which boron, phosphorus and the like are
added.
[0089] It is to be noted that since the configurations other than
those described above are almost the same as the configuration
according to the above-described first embodiment, the same or
corresponding components are designated by the same reference
characters, and description thereof will not be repeated.
[0090] The method for manufacturing the diode according to the
present embodiment will then be described.
[0091] First, a substrate which is a thick n.sup.- drift layer 1 is
prepared. The impurity concentration of n.sup.- drift layer 1 is
determined depending on the breakdown voltage class and is set to
be 1.times.10.sup.12 to 1.times.10.sup.15 cm.sup.3 in 600 to 6500V
class, for example.
[0092] Then, p layer 3 is formed on the surface of this substrate
with n-type diffusion layer 17 interposed therebetween. For
example, p layer 3 has a peak concentration of 1.times.10.sup.16 to
1.times.10.sup.18 cm.sup.3 and a diffusion depth of 1 to 4 .mu.m.
The peak concentration of the impurities in n-type diffusion layer
17 is equal to or higher than the concentration of the impurities
in n.sup.- drift layer 1 and is equal to or lower than the peak
value of the impurity concentration in p layer 3. Then, p.sup.+
diffusion layer 18 is formed on the surface of the substrate on
which p layer 3 and n-type diffusion layer 17 are formed. P.sup.+
diffusion layer 18 has, for example, a surface concentration of
1.times.10.sup.18 to 1.times.10.sup.20 cm.sup.-3 and a diffusion
depth of approximately 0.5 .mu.m. Trench structure 26a and a
cathode layer CLa are then formed.
[0093] It is to be noted that p.sup.+ diffusion layer 18 may be
formed after trench structure 26a is formed.
[0094] The diode according to the present embodiment is used such
that the electric potential lower than that of a cathode electrode
4 is applied to gate electrode 14 when the reverse voltage is
applied to the diode. For the purpose of this, gate electrode 14 is
electrically connected to anode electrode 5, for example. In
addition, in the case where the electric potential of cathode
electrode 4 is rendered positive when a reverse voltage is applied
to the diode, gate electrode 14 may be grounded.
[0095] In this case, the simulation results show that a current
density J.sub.A at a cross point CP (FIG. 6) can be decreased.
Accordingly, the current density at cross point CP can be decreased
below the current density at which the diode is overloaded. In this
case, since the overloaded diode exhibits a positive temperature
coefficient at V.sub.F, the current concentration on the overloaded
diode can be prevented.
[0096] Furthermore, the amount of hole injection from p layer 3 at
the time when the device is turned on can be controlled by n-type
diffusion layer 17.
[0097] Furthermore, trench structure 26a serves as a quasi-field
plate structure, to facilitate extension of the depletion layer
from the junction between p layer 3 and n-type diffusion layer 17,
with the result that a maximum reverse voltage V.sub.RRM can be
maintained. Also, as trench structure 26a is formed deeper than the
interface between p layer 3 and n-type diffusion layer 17, maximum
reverse voltage V.sub.RRM can be more reliably maintained.
[0098] Furthermore, according to the diode in the comparative
example (FIG. 26), the trade-off characteristics between a recovery
loss E.sub.REC and V.sub.F are controlled generally by adjusting
the lifetime of carriers in n.sup.- drift layer 1. In contrast,
according to the present embodiment, the concentration in p layer 3
is adjusted to control the trade-off characteristics and expand the
controllable range of the trade-off characteristics, and thus,
eliminating the lifetime adjusting process, to thereby allow
simplification of the wafer process.
[0099] Referring to FIG. 19, a modification of the present
embodiment will be described. The diode according to the present
modification includes an n-type diffusion layer 17, a trench
structure 27, a p.sup.+ diffusion layer 18, silicide layers 21a and
21b, and a barrier metal layer 22b. Trench structure 27 includes a
trench extending through a p layer 3 and n-type diffusion layer 17
and also includes a gate electrode 14 filling the trench with a
gate insulation film 12 interposed therebetween. In addition, gate
electrode 14 is electrically connected to an anode electrode 5 and
has the same electric potential as that of anode electrode 5.
[0100] According to the present modification, gate electrode 14 is
applied with the same electric potential as that of anode electrode
5. Accordingly, when the voltage in the reverse direction is
applied to the diode, the electric potential lower than that of
cathode electrode 4 can be applied to gate electrode 14 without the
need to control the electric potential of gate electrode 14 from
outside the diode. Consequently, the effects similar to those in
the present embodiment can be achieved.
Third Embodiment
[0101] Referring to FIG. 20, the diode as a semiconductor device
according to the present embodiment includes an anode electrode 5
(the first electrode), a p layer 3 (the first layer), an n.sup.-
drift layer 1 (the second layer), an n layer 15 (the fourth layer),
a cathode layer CLb (the third layer), a cathode electrode 24 (the
second electrode), a trench structure 26b, an interlayer dielectric
film 19, insulation films 20 and 23, and a barrier metal layer
22.
[0102] P layer 3 is located on anode electrode 5 and has a p-type
(the first conductivity type). N.sup.- drift layer 1 is located on
p layer 3 and has a conductivity type different from the p-type,
that is, an n-type (the second conductivity type).
[0103] Cathode layer CLb is located on n.sup.- drift layer 1 with n
layer 15 interposed therebetween. Cathode layer CLb includes an n
region 2 (the first portion) having an n-type and having a peak
value of the impurity concentration higher than the peak value of
the impurity concentration in n.sup.- drift layer 1.
[0104] N layer 15 is located between n.sup.- drift layer 1 and
cathode layer CLb. N layer 15 having an n-type has a peak value of
the impurity concentration higher than the peak value of the
impurity concentration in n.sup.- drift layer 1, and also has a
peak value of the impurity concentration lower than the peak value
of the impurity concentration in n.sup.+ region 2.
[0105] Cathode electrode 24 is located on cathode layer CLb.
[0106] Trench structure 26b includes a trench extending through
n.sup.+ region 2 and n layer 15 and also includes a gate electrode
14 filling the trench with gate insulation film 12 interposed
therebetween. In other words, trench structure 26b is located in
n.sup.+ region 2 and n layer 15.
[0107] Gate electrode 14 and cathode electrode 24 are connected to
the positive terminal side and the negative electrode side,
respectively, of a voltage source 30. Thus, trench structure 26b is
configured such that the electric potential that is positive with
respect to the electric potential of cathode electrode 24 may be
applied.
[0108] It is to be noted that since the configurations other than
those described above are almost the same as the configuration
according to the above-described first embodiment, the same or
corresponding components are designated by the same reference
characters, and description thereof will not be repeated.
[0109] Furthermore, it may be possible to apply the structure
having cathode layer CLa in place of the above-described cathode
layer CLb (FIG. 21) or the structure without having n layer 15.
[0110] The simulations similar to those in the first embodiment
were performed in order to examine the characteristics of the diode
according to the present embodiment. The simulation results will be
hereinafter described.
[0111] Referring to FIG. 23, simulations were performed for a
carrier concentration CC in the ON state. The results show that a
carrier concentration CC3 of the diode (FIG. 20) in the example of
the present embodiment is higher than carrier concentration CC0 of
the diode in the comparative example (FIG. 26). In other words, it
is found that the carrier concentration near the cathode is
increased in the ON state. It is considered that this increase in
carrier concentration causes a decrease in V.sub.F.
[0112] Referring to FIG. 24, simulations were performed for the
characteristics of a current density J.sub.A-a voltage V.sub.AK.
The figure shows a current density J.sub.A3 in the case of the
diode in the present embodiment (FIG. 20) and a current density
J.sub.A0 in the case of the diode in the comparative example (FIG.
26). According to the present embodiment, it is found that the
characteristic curve of current density J.sub.A-voltage V.sub.AK
shifts in the direction in which voltage V.sub.AK is decreased on
the horizontal axis on the graph, as compared to the case in the
comparative example. In other words, it is found that V.sub.F can
be decreased.
[0113] Referring to FIG. 25, simulations were performed for the
correlation between a depth y of trench structure 26b and V.sub.F.
Consequently, it is found that V.sub.F can be further sufficiently
decreased by setting trench depth y to a dimension t2 or more. In
other words, it is found that V.sub.F can be further sufficiently
decreased by providing trench structure 26b so as to extend through
n.sup.+ region 2 and n layer 15.
[0114] According to the present embodiment, when a positive bias is
applied to trench structure 26b located on the cathode side, an
accumulation layer is formed on the sidewall of the trench, which
causes an effect similar to that obtained in the case where n.sup.+
region 2 is expanded. Therefore, the electron injection from the
cathode side can be facilitated at the time when the device is
turned on, and consequently, V.sub.F can be decreased.
[0115] Furthermore, V.sub.F can be further sufficiently decreased
by providing trench structure 26b so as to extend through n.sup.+
region 2 and n layer 15. In addition, in the modification (FIG.
22), trench structure 26b may be provided so as to extend through
n.sup.+ region 2.
[0116] Although the first and second conductivity types correspond
to a p-type and an n-type, respectively, in each of the
above-described embodiments, the present invention is not limited
thereto, but the first and second conductivity types may correspond
to an n-type and a p-type, respectively.
[0117] Although the diode has been described as a semiconductor
device in each of the above-described embodiments, the
semiconductor device according to the present invention is not
limited to a diode alone, but may be a power module including a
diode. Such a power module may include, for example, an IGBT.
[0118] Although the case where p layer 3, n.sup.- drift layer 1, n
layer 15, and cathode layer CLa are made of Si to which conductive
impurities are added has been described, similar effects can be
obtained even when a wide band gap material such as SiC or GaN is
used in place of Si.
[0119] Furthermore, although the case where the semiconductor
device of a high breakdown voltage rated at 3300V class has been
described as an example, the present invention can also be applied
to those of other breakdown voltage classes.
[0120] Although the present invention has been described and
illustrated in detail, it is clearly understood that the same is by
way of illustration and example only and is not to be taken by way
of limitation, the scope of the present invention being interpreted
by the terms of the appended claims.
* * * * *