U.S. patent application number 15/434867 was filed with the patent office on 2017-12-28 for optimized testing of a partially symmetric quantum-logic circuit.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Pawel Jasionowski.
Application Number | 20170372217 15/434867 |
Document ID | / |
Family ID | 58738132 |
Filed Date | 2017-12-28 |
United States Patent
Application |
20170372217 |
Kind Code |
A1 |
Jasionowski; Pawel |
December 28, 2017 |
OPTIMIZED TESTING OF A PARTIALLY SYMMETRIC QUANTUM-LOGIC
CIRCUIT
Abstract
A method and associated systems for using wreath products and
invariance groups to test a partially symmetric quantum-logic
circuits. A test system receives information that describes the
architecture of a quantum-logic circuit to be tested. The system
uses this information to hierarchically organize the circuit's
inputs into non-overlapping blocks. The system creates set of
groups associated with the blocks, and then generates an invariance
group that contains one or more invariant permutations of the
inputs by computing a wreath product of the set of groups. These
invariant permutations identify a minimal number of tests required
to verify the circuit for all possible input vectors. The system
then directs a test apparatus to perform the resulting optimized
test sequence upon the circuit.
Inventors: |
Jasionowski; Pawel;
(Wroclaw, PL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
58738132 |
Appl. No.: |
15/434867 |
Filed: |
February 16, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15194718 |
Jun 28, 2016 |
9665829 |
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15434867 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06N 10/00 20190101;
H03K 19/195 20130101 |
International
Class: |
G06N 99/00 20100101
G06N099/00; H03K 19/195 20060101 H03K019/195 |
Claims
1. A quantum-logic test-development system comprising a processor,
a memory coupled to the processor, and a computer-readable hardware
storage device coupled to the processor, the storage device
containing program code configured to be run by the processor via
the memory to implement a method for optimizing testing of a
partially symmetric quantum-logic circuit by using wreath products
and invariance groups, the method comprising: the system receiving
architectural information about a quantum-logic circuit capable of
being represented by a function f( ); the system evenly dividing a
set of inputs of the circuit into a set of non-intersecting
first-level blocks, where every first-level block contains a same
number of inputs; the system evenly partitioning the set of
first-level blocks into a set of non-intersecting second-level
blocks, where every second-level block contains a same number of
first-level blocks; the system creating a first-level group G1 that
comprises a set of first-level indices and a set of one or more
first-level permutation operations capable of being performed upon
the set of first-level indices; the system defining a second-level
group G2 that comprises a set of second-level indices and a set of
one or more second-level permutation operations capable of being
performed upon the set of second-level indices, where a number of
the set of second-level indices equals the number of first-level
blocks in each second-level block; and the system generating a
first wreath product G1 G2 as a function of the evenly dividing and
the evenly partitioning, where is an unrestricted wreath-product
operator, and where the first wreath product represents a first
invariance group of the function f( ).
2. The system of claim 1, where the first invariance group
comprises a set of invariant permutations that each identify a
permutation of at least two inputs of the set of inputs, and where
no output of the quantum-logic circuit changes state when the
quantum-logic circuit receives a permuted input vector generated by
performing a permutation of the set of invariant permutations upon
the circuit's most recent input vector.
3. The system of claim 2, further comprising: the system optimizing
a procedure for testing the quantum-logic circuit, where the
procedure comprises a series of tests that each verify correct
operation of the quantum-logic circuit in response to receiving a
distinct input vector of a set of input vectors, and where the
optimizing comprises deleting from the series of tests any test
that would attempt to verify correct operation of the quantum-logic
circuit in response to receiving a permuted input vector generated
by performing a permutation of the set of invariant permutations
upon an input vector already verified by another test of the series
of tests.
4. The system of claim 1, where the quantum-circuit has at least
sixteen inputs divided into at least eight non-intersecting
first-level blocks and at least four non-intersecting second-level
blocks, the method further comprising: the system evenly
apportioning, as a function of the architectural information, the
at least four second-level blocks into at least two
non-intersecting third-level blocks, where every third-level block
contains a same number of second-level blocks; the system
identifying a third-level group G3 that comprises a set of
third-level indices and a set of one or more third-level
permutation operations capable of being performed upon the set of
third-level indices, where a number of the set of third-level
indices equals the number of second-level blocks in each
third-level block; and the system generating a second wreath
product (G1 G2) G3, where the second wreath product represents a
second invariance group of the function f( ), where the second
invariance group comprises a second set of invariant permutations
that each identify a permutation of at least inputs of the at least
sixteen inputs, and where no output of the quantum-logic circuit
changes state when the quantum-logic circuit receives a permuted
input vector generated by performing a permutation of the second
set of invariant pemutations upon the circuit's most recent input
vector.
5. The system of claim 1, where the first wreath product equals the
group ((G.sub.1 x . . . G.sub.m)x H, X x Y), where x is a Cartesian
product operator, where m=the number of first-level blocks
contained in each second-level block, where each group G.sub.1 . .
. G.sub.m is an identical copy of the set of first-level indices,
where H=the set of second-level indices, where X=the set of
first-level permutation operations, and where Y=the set of
second-level permutation operations.
6. The system of claim 4, where the first wreath product equals the
group ((G.sub.1 x . . . x G.sub.m) x H, X x Y), where x is a
Cartesian product operator, where m=the number of first-level
blocks contained in each second-level block, where each group
G.sub.1 . . . G.sub.m is an identical copy of the set of
first-level indices, where H=the set of second-level indices, where
X=the set of first-level permutation operations, where Y=the set of
second-level permutation operations, where the second wreath
product equals the group ((H.sub.1 x . . . x H.sub.p) x L, X x Y x
Z)=(((G.sub.1 x G.sub.2 . . . x G.sub.m) x H.sub.1) x ((G.sub.m+1 x
G.sub.m+2 . . . x G.sub.2m) x H.sub.2 . . . x ((G.sub.(p-1)m+1 x
G.sub.p-1)m+2 . . . x G.sub.pm) x H.sub.p)) x L, X x Y x Z), where
p=the number of second-level blocks contained in each third-level
block, where each group H.sub.1 . . . H.sub.p is an identical copy
of the set of second-level indices, where L=the set of third-level
indices, and where Z=the set of third-level permutation
operations.
7. The system of claim 1, where the received architectural
information identifies a number of inputs of the circuit, a number
of outputs of the circuit, a number of states that may be assumed
by each input of the circuit, and a number of states that may be
assumed by each output of the circuit.
8. The system of claim 3, further comprising: the system directing
a test apparatus to perform the series of tests upon the
quantum-logic circuit, where the series of tests are selected as a
function of the optimized procedure for testing the circuit.
9. A method for optimizing testing of a partially symmetric
quantum-logic circuit by using wreath products and invariance
groups, the method comprising: receiving architectural information
about a quantum-logic circuit capable of being represented by a
function f( ); evenly dividing a set of inputs of the circuit into
a set of non-intersecting first-level blocks, where every
first-level block contains a same number of inputs; evenly
partitioning the set of first-level blocks into a set of
non-intersecting second-level blocks, where every second-level
block contains a same number of first-level blocks; creating a
first-level group G1 that comprises a set of first-level indices
and a set of one or more first-level permutation operations capable
of being performed upon the set of first-level indices; defining a
second-level group G2 that comprises a set of second-level indices
and a set of one or more second-level permutation operations
capable of being performed upon the set of second-level indices,
where a number of the set of second-level indices equals the number
of first-level blocks in each second-level block; and generating a
first wreath product G1 G2 as a function of the evenly dividing and
the evenly partitioning, where is an unrestricted wreath-product
operator, and where the first wreath product represents a first
invariance group of the function f( ).
10. The method of claim 9, where the first invariance group
comprises a set of invariant permutations that each identify a
permutation of at least two inputs of the set of inputs, and where
no output of the quantum-logic circuit changes state when the
quantum-logic circuit receives a permuted input vector generated by
performing a permutation of the set of invariant permutations upon
the circuit's most recent input vector.
11. The method of claim 10, further comprising: the system
optimizing a procedure for testing the quantum-logic circuit, where
the procedure comprises a series of tests that each verify correct
operation of the quantum-logic circuit in response to receiving a
distinct input vector of a set of input vectors, and where the
optimizing comprises deleting from the series of tests any test
that would attempt to verify correct operation of the quantum-logic
circuit in response to receiving a permuted input vector generated
by performing a permutation of the set of invariant permutations
upon an input vector already verified by another test of the series
of tests.
12. The method of claim 9, where the quantum-circuit has at least
sixteen inputs divided into at least eight non-intersecting
first-level blocks and at least four non-intersecting second-level
blocks, the method further comprising evenly apportioning, as a
function of the architectural information, all the at least four
second-level blocks into at least two non-intersecting third-level
blocks, where every third-level block contains a same number of
second-level blocks; identifying a third-level group G3 that
comprises a set of third-level indices and a set of one or more
third-level permutation operations capable of being performed upon
the set of third-level indices, where a number of the set of
third-level indices equals the number of second-level blocks in
each third-level block; and generating a second wreath product (G1
G2) G3, where the second wreath product represents a second
invariance group of the function f( ), where the second invariance
group comprises a second set of invariant permutations that each
identify a permutation of at least inputs of the at least sixteen
inputs, and where no output of the quantum-logic circuit changes
state when the quantum-logic circuit receives a permuted input
vector generated by performing a permutation of the second set of
invariant permutations upon the circuit's most recent input
vector.
13. The method of claim 9, where the first wreath product equals
the group ((G.sub.1 x . . . G.sub.m) x H, X x Y), where x is a
Cartesian product operator, where m=the number of first-level
blocks contained in each second-level block, where each group
G.sub.1 . . . G.sub.m is an identical copy of the set of
first-level indices, where H=the set of second-level indices, where
X=the set of first-level pe ion operations, and where Y=the set of
second-level permutation operations.
14. The method of claim 12, where the first wreath product equals
the group ((G.sub.1 x . . . G.sub.m) x H, X x Y), where x is a
Cartesian product operator, where m=the number of first-level
blocks contained in each second-level block, where each group
G.sub.1 . . . G.sub.m is an identical copy of the set of
first-level indices, where H=the set of second-level indices, where
X=the set of first-level permutation operations, where Y=the set of
second-level permutation operations, where the second wreath
product equals the group ((H.sub.1 x . . . x H.sub.p) x L, X x Y x
Z)=(((G.sub.1 x G.sub.2 . . . x G.sub.m) x H.sub.1) x ((G.sub.m+1 x
G.sub.m+2 . . . x G.sub.2m) x H.sub.2 . . . x ((G.sub.(p-1)m+1 x
G.sub.(p-1)m+2 . . . x G.sub.pm) x H.sub.p)) x L, X x Y x Z), where
p=the number of second-level blocks contained in each third-level
block, where each group H.sub.1 . . . H.sub.p is an identical copy
of the set of second-level indices, where L=the set of third-level
indices, and where Z=the set of third-level permutation
operations.
15. The method of claim 9, further comprising providing at least
one support service for at least one of creating, integrating,
hosting, maintaining, and deploying computer-readable program code
in the computer system, wherein the computer-readable program code
in combination with the computer system is configured to implement
the receiving, the evenly dividing, the evenly partitioning, the
creating, the defining, and the generating.
16. A computer program product, comprising a computer-readable
hardware storage device having a computer-readable program code
stored therein, the program code configured to be executed by a
quantum-logic test-development system comprising a processor, a
memory coupled to the processor, and a computer-readable hardware
storage device coupled to the processor, the storage device
containing program code configured to be run by the processor via
the memory to implement a method for optimizing testing of a
partially symmetric quantum-logic circuit by using wreath products
and invariance groups, the method comprising: the system receiving
architectural information about a quantum-logic circuit capable of
being represented by a function f( ); the system evenly dividing a
set of inputs of the circuit into a set of non-intersecting
first-level blocks, where every first-level block contains a same
number of inputs; the system evenly partitioning the set of
first-level blocks into a set of non-intersecting second-level
blocks, where every second-level block contains a same number of
first-level blocks; the system creating a first-level group G1 that
comprises a set of first-level indices and a set of one or more
first-level permutation operations capable of being performed upon
the set of first-level indices; the system defining a second-level
group G2 that comprises a set of second-level indices and a set of
one or more second-level permutation operations capable of being
performed upon the set of second-level indices, where a number of
the set of second-level indices equals the number of first-level
blocks in each second-level block; and the system generating a
first wreath product G1 G2 as a function of the evenly dividing and
the evenly partitioning, where is an unrestricted wreath-product
operator, and where the first wreath product is a first invariance
group of the function f( ), where the first wreath product equals
the group ((G.sub.1 x . . . G.sub.m) x H, X x Y), where x is a
Cartesian product operator, where m=the number of first-level
blocks contained in each second-level block, where each group
G.sub.1 . . . G.sub.m is an identical copy of the set of
first-level indices, where H=the set of second-level indices, where
X=the set of first-level permutation operations, and where Y=the
set of second-level permutation operations.
17. The computer program product of claim 16, where the first
invariance group comprises a set of invariant permutations that
each identify a permutation of at least two inputs of the set of
inputs, and where no output of the quantum-logic circuit changes
state when the quantum-logic circuit receives a permuted input
vector generated by performing a permutation of the set of
invariant permutations upon the circuit's most recent input
vector.
18. The computer program product of claim 16, further comprising:
the system optimizing a procedure for testing the quantum-logic
circuit, where the procedure comprises a series of tests that each
verify correct operation of the quantum-logic circuit in response
to receiving a distinct input vector of a set of input vectors, and
where the optimizing comprises deleting from the series of tests
any test that would attempt to verify correct operation of the
quantum-logic circuit in response to receiving a permuted input
vector generated by performing a permutation of the set of
invariant permutations upon an input vector already verified by
another test of the series of tests.
19. The computer program product of claim 16, where the
quantum-circuit has at least sixteen inputs divided into at least
eight non-intersecting first-level blocks and at least four
non-intersecting second-level blocks, the method further
comprising: the system evenly apportioning, as a function of the
architectural information, all the at least four second-level
blocks into at least two non-intersecting third-level blocks, where
every third-level block contains a same number of second-level
blocks; the system identifying a third-level group G3 that
comprises a set of third-level indices and a set of one or more
third-level permutation operations capable of being performed upon
the set of third-level indices, where a number of the set of
third-level indices equals the number of second-level blocks in
each third-level block; and the system generating a second wreath
product (G1 G2) G3, where the second wreath product represents a
second invariance group of the function f( ); where the second
invariance group comprises a second set of invariant permutations
that each identify a permutation of at least two inputs of the at
least sixteen inputs, and where no output of the quantum-logic
circuit changes state when the quantum-logic circuit receives a
permuted input vector generated by performing a permutation of the
second set of invariant permutations upon the circuit's most recent
input vector.
20. The computer program product of claim 19, where the second
wreath product equals the group ((H.sub.1 x . . . x H.sub.p) x L, X
x Y x Z)=(((G.sub.1 x G.sub.2 . . . x G.sub.m) x H.sub.1) x
((G.sub.m+1 x G.sub.m+2 . . . G.sub.2m) x H.sub.2 . . . x
((G.sub.(p-1)m+1 x G.sub.(p-1)m+2 . . . x G.sub.pm) x H.sub.p)) x
L, X x Y x Z), where p=the number of second-level blocks contained
in each third-level block, where each group H.sub.1 . . . H.sub.p
is an identical copy of the set of second-level indices, where
L=the set of third-level indices, and where Z=the set of
third-level permutation operations.
Description
[0001] This application is a continuation application claiming
priority to Ser. No. 15/194,718, filed Jun. 28, 2016.
TECHNICAL FIELD
[0002] The present invention relates to testing quantum-logic
circuits (also known as "q-modules") and in particular to using
group theory and wreath-product computations in order to optimize
testing of partially symmetric q-modules.
BACKGROUND
[0003] Unlike conventional binary logic, quantum logic is not
limited to binary states of 0 and 1. Because inputs and outputs of
a quantum-logic circuit may assume far more states than those of an
analogous binary-logic circuit, a far greater number of tests may
be required to fully verify correct operation of the quantum-logic
circuit. Testing a q-module comprising larger numbers of inputs and
states can therefore be prohibitively expensive or
resource-intensive.
BRIEF SUMMARY
[0004] A first embodiment of the present invention provides a
quantum-logic test-development system comprising a processor, a
memory coupled to the processor, and a computer-readable hardware
storage device coupled to the processor, the storage device
containing program code configured to be run by the processor via
the memory to implement a method for optimizing testing of a
partially symmetric quantum-logic circuit by using wreath products
and invariance groups, the method comprising:
[0005] the system receiving architectural information about a
quantum-logic circuit that has at least eight inputs and at least
one output, where the quantum-logic circuit performs operations
capable of being represented by a function f( );
[0006] the system, as a function of the architectural information,
evenly dividing all the at least eight inputs into at least four
non-intersecting first-level blocks, where every first-level block
contains a same number of inputs;
[0007] the system, as a function of the architectural information,
evenly partitioning all the at least four first-level blocks into
at least two non-intersecting second-level blocks, where every
second-level block contains a same number of first-level
blocks;
[0008] the system creating a first-level group G1 that comprises a
set of first-level indices and a set of one or more first-level
permutation operations capable of being performed upon the set of
first-level indices, where a number of the set of first-level
indices equals the number of inputs in each first-level block;
[0009] the system defining a second-level group G2 that comprises a
set of second-level indices and a set of one or more second-level
permutation operations capable of being performed upon the set of
second-level indices, where a number of the set of second-level
indices equals the number of first-level blocks in each
second-level block; and
[0010] the system generating a first wreath product G1 G2 as a
function of the evenly dividing and the evenly partitioning, where
is an unrestricted wreath-product operator, and where the first
wreath product represents a first invariance group of the function
f( ).
[0011] A second embodiment of the present invention provides method
for optimizing testing of a partially symmetric quantum-logic
circuit by using wreath products and invariance groups, the method
comprising:
[0012] receiving architectural information about a quantum-logic
circuit that has at least eight inputs and at least one output,
where the quantum-logic circuit performs operations capable of
being represented by a function f( );
[0013] evenly dividing, as a function of the architectural
information, all the at least eight inputs into at least four
non-intersecting first-level blocks, where every first-level block
contains a same number of inputs;
[0014] evenly partitioning, as a function of the architectural
information, all the at least four first-level blocks into at least
two non-intersecting second-level blocks, where every second-level
block contains a same number of first-level blocks;
[0015] creating a first-level group G1 that comprises a set of
first-level indices and a set of one or more first-level
permutation operations capable of being performed upon the set of
first-level indices, where a number of the set of first-level
indices equals the number of inputs in each first-level block;
[0016] defining a second-level group G2 that comprises a set of
second-level indices and a set of one or more second-level
permutation operations capable of being performed upon the set of
second-level indices, where a number of the set of second-level
indices equals the number of first-level blocks in each
second-level block; and
[0017] generating a first wreath product G1 G2 as a function of the
evenly dividing and the evenly partitioning, where is an
unrestricted wreath-product operator, and where the first wreath
product represents a first invariance group of the function f(
).
[0018] A third embodiment of the present invention provides a
computer program product, comprising a computer-readable hardware
storage device having a computer-readable program code stored
therein, the program code configured to be executed by a
quantum-logic test-development system comprising a processor, a
memory coupled to the processor, and a computer-readable hardware
storage device coupled to the processor, the storage device
containing program code configured to be run by the processor via
the memory to implement a method for optimizing testing of a
partially symmetric quantum-logic circuit by using wreath products
and invariance groups, the method comprising:
[0019] the system receiving architectural information about a
quantum-logic circuit that has at least eight inputs and at least
one output, where the quantum-logic circuit performs operations
capable of being represented by a function f( );
[0020] the system, as a function of the architectural information,
evenly dividing all the at least eight inputs into at least four
non-intersecting first-level blocks, where every first-level block
contains a same number of inputs;
[0021] the system, as a function of the architectural information,
evenly partitioning all the at least four first-level blocks into
at least two non-intersecting second-level blocks, where every
second-level block contains a same number of first-level
blocks;
[0022] the system creating a first-level group G1 that comprises a
set of first-level indices and a set of one or more first-level
permutation operations capable of being performed upon the set of
first-level indices, where a number of the set of first-level
indices equals the number of inputs in each first-level block;
[0023] the system defining a second-level group G2 that comprises a
set of second-level indices and a set of one or more second-level
permutation operations capable of being performed upon the set of
second-level indices, where a number of the set of second-level
indices equals the number of first-level blocks in each
second-level block; and
[0024] the system generating a first wreath product G1 G2 as a
function of the evenly dividing and the evenly partitioning, where
is an unrestricted wreath-product operator, and
[0025] where the first wreath product is a first invariance group
of the function f( ),
[0026] where the first wreath product equals the group ((G1.sub.1x
. . . G1.sub.m)x H, X x Y),
[0027] where x is a Cartesian product operator,
[0028] where m=the number of first-level blocks contained in each
second-level block,
[0029] where each group G.sub.1 . . . G.sub.m is an identical copy
of the set of first-level indices,
[0030] where H=the set of second-level indices,
[0031] where X=the set of first-level permutation operations,
and
[0032] where Y=the set of second-level permutation operations.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] FIG. 1 shows the structure of a computer system and computer
program code that may be used to implement a method for optimizing
testing of a partially symmetric quantum-logic circuit by using
wreath products and invariance groups in accordance with
embodiments of the present invention.
[0034] FIG. 2 is a flow chart that illustrates steps of a method
for optimizing testing of a partially symmetric quantum-logic
circuit by using wreath products and invariance groups in
accordance with embodiments of the present invention.
DETAILED DESCRIPTION
[0035] Embodiments of the present invention optimize the operation
of a test system or test application that verifies correct
operation of a partially symmetric quantum-logic circuit.
[0036] Testing a quantum-logic circuit (or "q-module") can be far
more time-consuming and resource-intensive than testing
conventional binary logic circuits because quantum logic is not
limited to two states. Where verifying operation of a two-input
binary AND circuit would require four tests, corresponding to four
possible binary inputs {00, 01, 10, and 11}, a two-input q-module
that supports four states A, B, C, and D, would require 16 tests to
test 16 possible input states {AA, AB, AC, AD, BA, BB, BC, BD, CA,
CB, CC, CD, DA, DB, DC, and DD}. Embodiments of the present
invention solve this technical problem by enhancing the operation
of a circuit-testing software application or a hardware
circuit-testing device.
[0037] The number of necessary tests needed to verify a q-module
increases as a geometric function of the circuit's number of states
or number of inputs. In general, a circuit with n inputs and t
states (t>1) would require t.sup.n tests in order to verify each
possible set of input values. An n-input binary-logic circuit that
supports only values of 0 and 1 would thus require only 2.sup.n
tests.
[0038] In general, permuting any inputs of an input vector x by
performing or applying a permutation .sigma. to x causes the
module's output to change. Consider, for example, a 3-input,
1-output q-module that receives a three-input input vector
x=(x.sub.1, x.sub.2, x.sub.3). Each of these three inputs can be in
any of four states {A,B,C,D} and the module's single output can be
in any of three state {E, F, G}. The three inputs may be ordered in
any of six distinct ways: (x.sub.1, x.sub.2, x.sub.3), (x.sub.1,
x.sub.3, x.sub.2), (x.sub.2, x.sub.1, x.sub.3), (x.sub.2, x.sub.3,
x.sub.1), (x.sub.3, x.sub.1, x.sub.2), and (x.sub.3, x.sub.2,
x.sub.1), each of which may be generated by performing one of six
possible permutations (including the trivial identity permutation
(id), which does not change the order of indices) upon an original
vector x=(x.sub.1, x.sub.2, x.sub.3). If, for example, inputs
x.sub.1, x.sub.2, and x.sub.3 are initially in states (A, B, C),
performing a permutation (2,3) upon the input vector would permute
the order of the last two of the three inputs, thus permuting the
input to (A, C, B). Such a permutation in general causes the
q-module's output to change.
[0039] A characteristic of some q-modules, however, is that certain
permutations of the module's inputs never produce a change to the
module's output state, regardless of the states of each input prior
to permutation. If this is true of all possible permutations of all
inputs, the circuit is said to be symmetrical. If it is true of
only a proper blocks of all possible permutations of inputs, the
circuit is said to be partially symmetrical. Note that nearly all
q-modules are symmetric with respect to an identity permutation
(id), which may consist of a permutation of 0 inputs. The identity
permutation may be mentioned in examples and embodiments described
in this document, but it should be considered a trivial case within
the context of the present invention.
[0040] This document will represent a permutation of an input
vector x as an ordered set of indices that each identify a position
of an element of x. Care should be taken not to confuse this
notation with that normally used to represent other types of
vectors or ordered sets.
[0041] Using these notation conventions, a permutation of an input
vector x=(x.sub.1, x.sub.2, x.sub.3) to (x.sub.3, x.sub.2, x.sub.1)
(a permutation of inputs x.sub.1 and x.sub.3, which exchanges
inputs associated with indices 1 and 3 of vector x) would be
represented as an ordered pair of indices (1,3) (the indices of
inputs x.sub.1 and x.sub.3).
[0042] Because permutation theory is known in the art, this
document will provide only a brief overview that may help readers
understand the notation used herein. Applying a permutation
.sigma.=(a,b,c,d) to a four-element vector x=(x1,x2,x3,x4)
rearranges the elements of x to a permuted vector xp. In this
example, {a,b,c,d} each represent in index of an element of x, and
because x has four elements, these indices can each assume a value
of 1 through 4.
[0043] A permutation is evaluated one index at a time, and a first
index identified by the permutation identifies a position in xp to
which should be moved an element identified by the first index. A
permutation is evaluated right-to-left in this manner, in circular
fashion, throughout the ordered set of indices that represents the
permutation. This procedure ends when continuing would create a
repetition.
[0044] Consider, for example, permutation .sigma.=(1,2). Here, the
permutation is notated as an ordered pair of index 1 and index 2 of
input vector x. Applying .sigma. to x=(x.sub.1, x.sub.2, x.sub.3)
performs the following procedure:
[0045] replace index #1 of x with x.sub.2 (index #2 of
x).fwdarw.(x.sub.2, x.sub.2, x.sub.3),
[0046] replace index #2 of x with x.sub.1 (index #1 of
x).fwdarw.(x.sub.2, x.sub.1, x.sub.3),
[0047] stop because rotating back to the first index of .sigma.
would create a repetitive operation. .sigma.(x) thus produces
permuted vector xp=(x2,x1,x3), which swaps x1 and x2 of x.
[0048] In a second example, a permutation of an input vector
x=(x.sub.1, x.sub.2, x.sub.3, x.sub.4) to (x.sub.3, x.sub.1,
x.sub.2, x.sub.4) can be represented as (1,3,2). As above,
.sigma.(x) generates permuted vector xp by the following
procedure:
[0049] replace index #1 of x with x.sub.3 (index #3 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.3, x.sub.4),
[0050] replace index #3 of x with x.sub.2 (index #2 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.2, x.sub.4),
[0051] replace index #2 of x with x.sub.2 (index #1 of
x).fwdarw.(x.sub.3, x.sub.1, x.sub.2, x.sub.4), and
[0052] stop because rotating back to the first index of .sigma.
would repeat a previously performed operation.
[0053] In a more complex example, permutation .sigma.=(1,3,2,4)
permutes input vector [0054] x=(x.sub.1, x.sub.2, x.sub.3, x.sub.4)
into vector [0055] xp=(x.sub.3, x.sub.4, x.sub.2, x.sub.1). As
before, .sigma.(x) generates xp by the following procedure:
[0056] replace index #1 of x with x.sub.3 (index #3 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.3, x.sub.4),
[0057] replace index #3 of x with x.sub.2 (index #2 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.2, x.sub.4),
[0058] replace index #2 of x with x.sub.4 (index #4 of
x).fwdarw.(x.sub.3, x.sub.4, x.sub.2, x.sub.4),
[0059] replace index #4 of x with x.sub.1 (index #1 of
x).fwdarw.(x.sub.3, x.sub.4, x.sub.2, x.sub.1),
[0060] stop because rotating back to the first index of .sigma.
would repeat a previously performed operation.
[0061] Expressed more formally, for any input vector (x)=(x.sub.1,
x.sub.2, x.sub.3, x.sub.4), the permutation of the indices of x
.sigma.(x)=permuted vector xp=(x.sub..sigma.(1), x.sub..sigma.(2),
x.sub..sigma.(3), x.sub..sigma.(4)). Here, if .sigma.=(1,3,2,4),
then .sigma.(x) transforms index 1 into 3, 3 into 2, 2 into 4 and 4
into 1. Therefore, .sigma.(1)=3, .sigma.(2)=4, .sigma.(3)=2,
.sigma.(4)=1, and xp=(x.sub..sigma.(1), x.sub..sigma.(2),
x.sub..sigma.(3), x.sub..sigma.(4))=(x.sub.3, x.sub.4, x.sub.2,
x.sub.1).
[0062] In another variation, a permutation be represented as two or
more ordered pairs, each of which is evaluated independently. For
example, performing permutation .sigma.(x)=(1,3)(2,4) upon vector
x=(x.sub.1, x.sub.2, x.sub.3, x.sub.4) to produce output
xp=(x.sub.3, x.sub.4, x.sub.1, x.sub.2) can be evaluated in two
steps:
[0063] (1,3):
[0064] replace index #1 of x with x.sub.3 (index #3 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.3, x.sub.4),
[0065] replace index #3 of x with x.sub.1 (index #1 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.1, x.sub.4),
[0066] stop because rotating back to the first index of .sigma.
would create a repetitive operation. .sigma.(x) thus produces
permuted vector xp=(x2,x1,x3), which swaps x1 and x2 of x.
[0067] (2,4):
[0068] replace index #2 of x with x.sub.4 (index #4 of
x).fwdarw.(x.sub.3, x.sub.4, x.sub.1, x.sub.4),
[0069] replace index #4 of x with x.sub.2 (index #2 of
x).fwdarw.(x.sub.3, x.sub.4, x.sub.1, x.sub.2),
[0070] stop because rotating back to the first index of .sigma.
would repeat a previously performed operation.
[0071] This permutation thus swaps a first division of x (x1, x2)
with a second division of x (x3,x4) without permuting the internal
order of inputs comprised by either division.
[0072] A set of "symmetric" permutations may be referred to as an
invariance group. If the previously described 3-input, 1-output,
4-state quantum circuit produces output E in response to receiving
an input vector x=(x.sub.1, x.sub.2, x.sub.3), applying any
permutation of an invariance group associated with that circuit
will not change the output. For example, if a permutation
.sigma.=(2,3) is a symmetric permutation (comprised by an
invariance group of the q-module), a permuted input vector
.sigma.(x)=(x.sub.1, x.sub.3, x.sub.2) will not result in a change
to the previous output E.
[0073] If a q-module is associated with a non-empty invariance
group of symmetric permutations, the module is said to be symmetric
and the invariance group is said to be a "Boolean function
invariance group" or a "symmetry group" of a function f( ) that
represents the q-module.
[0074] One property of an invariance group is that the permutations
contained by the group are invariant regardless of the initial
states of the permuted inputs. In the above example, the
one-permutation invariance group {(2,3)} specifies that permuting
the q-module's second and third inputs never changes the module's
output. So, for example, regardless of whether the states of the
module inputs change from (ABA) to (AAB), from (CCB) to (CBC), or
from (CBA) to (CAB), the output of the q-module does not
change.
[0075] Embodiments of the present invention employ this concept of
invariance groups to greatly reduce the number of input vectors x
that must be tested in order fully verify a q-module. Because
applying an invariant permutation to a q-module's input vector x is
known to leave the q-module's output unchanged, once that initial
vector x has been tested, any other vector that may be generated by
applying the invariant permutation to x is automatically deemed to
have been verified. When an invariance group of a partially
symmetric q-module comprises a significant number of permutations,
embodiments of the present invention may dramatically reduce the
number of tests required to fully verify the circuit.
[0076] FIG. 1 shows a structure of a computer system and computer
program code that may be used to implement a method for optimizing
testing of a partially symmetric quantum-logic circuit by using
wreath products and invariance groups in accordance with
embodiments of the present invention. FIG. 1 refers to objects
101-115.
[0077] Aspects of the present invention may take the form of an
entirely hardware embodiment, an entirely software embodiment
(including firmware, resident software, micro-code, etc.) or
embodiment combining software and hardware aspects that may all
generally be referred to herein as a "circuit," "module," or
"system."
[0078] The present invention may be a system, a method, and/or a
computer program product at any possible technical detail level of
integration. The computer program product may include a computer
readable storage medium (or media) having computer readable program
instructions thereon for causing a processor to carry out aspects
of the present invention.
[0079] The computer readable storage medium can be a tangible
device that can retain and store instructions for use by an
instruction execution device. The computer readable storage medium
may be, for example, but is not limited to, an electronic storage
device, a magnetic storage device, an optical storage device, an
electromagnetic storage device, a semiconductor storage device, or
any suitable combination of the foregoing. A non-exhaustive list of
more specific examples of the computer readable storage medium
includes the following: a portable computer diskette, a hard disk,
a random access memory (RAM), a read-only memory (ROM), an erasable
programmable read-only memory (EPROM or Flash memory), a static
random access memory (SRAM), a portable compact disc read-only
memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a
floppy disk, a mechanically encoded device such as punch-cards or
raised structures in a groove having instructions recorded thereon,
and any suitable combination of the foregoing. A computer readable
storage medium, as used herein, is not to be construed as being
transitory signals per se, such as radio waves or other freely
propagating electromagnetic waves, electromagnetic waves
propagating through a waveguide or other transmission media (e.g.,
light pulses passing through a fiber-optic cable), or electrical
signals transmitted through a wire.
[0080] Computer readable program instructions described herein can
be downloaded to respective computing/processing devices from a
computer readable storage medium or to an external computer or
external storage device via a network, for example, the Internet, a
local area network, a wide area network and/or a wireless network.
The network may comprise copper transmission cables, optical
transmission fibers, wireless transmission, routers, firewalls,
switches, gateway computers and/or edge servers. A network adapter
card or network interface in each computing/processing device
receives computer readable program instructions from the network
and forwards the computer readable program instructions for storage
in a computer readable storage medium within the respective
computing/processing device.
[0081] Computer readable program instructions for carrying out
operations of the present invention may be assembler instructions,
instruction-set-architecture (ISA) instructions, machine
instructions, machine dependent instructions, microcode, firmware
instructions, state-setting data, configuration data for integrated
circuitry, or either source code or object code written in any
combination of one or more programming languages, including an
object oriented programming language such as Smalltalk, C++, or the
like, and procedural programming languages, such as the "C"
programming language or similar programming languages. The computer
readable program instructions may execute entirely on the user's
computer, partly on the user's computer, as a stand-alone software
package, partly on the user's computer and partly on a remote
computer or entirely on the remote computer or server. In the
latter scenario, the remote computer may be connected to the user's
computer through any type of network, including a local area
network (LAN) or a wide area network (WAN), or the connection may
be made to an external computer (for example, through the Internet
using an Internet Service Provider). In some embodiments,
electronic circuitry including, for example, programmable logic
circuitry, field-programmable gate arrays (FPGA), or programmable
logic arrays (PLA) may execute the computer readable program
instructions by utilizing state information of the computer
readable program instructions to personalize the electronic
circuitry, in order to perform aspects of the present
invention.
[0082] Aspects of the present invention are described herein with
reference to flowchart illustrations and/or block diagrams of
methods, apparatus (systems), and computer program products
according to embodiments of the invention. It will be understood
that each block of the flowchart illustrations and/or block
diagrams, and combinations of blocks in the flowchart illustrations
and/or block diagrams, can be implemented by computer readable
program instructions.
[0083] These computer readable program instructions may be provided
to a processor of a general purpose computer, special purpose
computer, or other programmable data processing apparatus to
produce a machine, such that the instructions, which execute via
the processor of the computer or other programmable data processing
apparatus, create means for implementing the functions/acts
specified in the flowchart and/or block diagram block or blocks.
These computer readable program instructions may also be stored in
a computer readable storage medium that can direct a computer, a
programmable data processing apparatus, and/or other devices to
function in a particular manner, such that the computer readable
storage medium having instructions stored therein comprises an
article of manufacture including instructions which implement
aspects of the function/act specified in the flowchart and/or block
diagram block or blocks.
[0084] The computer readable program instructions may also be
loaded onto a computer, other programmable data processing
apparatus, or other device to cause a series of operational steps
to be performed upon the computer, other programmable apparatus or
other device to produce a computer implemented process, such that
the instructions which execute on the computer, other programmable
apparatus, or other device implement the functions/acts specified
in the flowchart and/or block diagram block or blocks.
[0085] The flowchart and block diagrams in the Figures illustrate
the architecture, functionality, and operation of possible
implementations of systems, methods, and computer program products
according to various embodiments of the present invention. In this
regard, each block in the flowchart or block diagrams may represent
a module, segment, or portion of instructions, which comprises one
or more executable instructions for implementing the specified
logical function(s). In some alternative implementations, the
functions noted in the blocks may occur out of the order noted in
the Figures. For example, two blocks shown in succession may, in
fact, be executed substantially concurrently, or the blocks may
sometimes be executed in the reverse order, depending upon the
functionality involved. It will also be noted that each block of
the block diagrams and/or flowchart illustration, and combinations
of blocks in the block diagrams and/or flowchart illustration, can
be implemented by special purpose hardware-based systems that
perform the specified functions or acts or carry out combinations
of special purpose hardware and computer instructions.
[0086] In FIG. 1, computer system 101 comprises a processor 103
coupled through one or more I/O Interfaces 109 to one or more
hardware data storage devices 111 and one or more I/O devices 113
and 115.
[0087] Hardware data storage devices 111 may include, but are not
limited to, magnetic tape drives, fixed or removable hard disks,
optical discs, storage-equipped mobile devices, and solid-state
random-access or read-only storage devices. I/O devices may
comprise, but are not limited to: input devices 113, such as
keyboards, scanners, handheld telecommunications devices,
touch-sensitive displays, tablets, biometric readers, joysticks,
trackballs, or computer mice; and output devices 115, which may
comprise, but are not limited to printers, plotters, tablets,
mobile telephones, displays, or sound-producing devices. Data
storage devices 111, input devices 113, and output devices 115 may
be located either locally or at remote sites from which they are
connected to I/O Interface 109 through a network interface.
[0088] Processor 103 may also be connected to one or more memory
devices 105, which may include, but are not limited to, Dynamic RAM
(DRAM), Static RAM (SRAM), Programmable Read-Only Memory (PROM),
Field-Programmable Gate Arrays (FPGA), Secure Digital memory cards,
SIM cards, or other types of memory devices.
[0089] At least one memory device 105 contains stored computer
program code 107, which is a computer program that comprises
computer-executable instructions. The stored computer program code
includes a program that implements a method for optimizing testing
of a partially symmetric quantum-logic circuit by using wreath
products and invariance groups in accordance with embodiments of
the present invention, and may implement other embodiments
described in this specification, including the methods illustrated
in FIGS. 1-2. The data storage devices 111 may store the computer
program code 107. Computer program code 107 stored in the storage
devices 111 is configured to be executed by processor 103 via the
memory devices 105. Processor 103 executes the stored computer
program code 107.
[0090] In some embodiments, rather than being stored and accessed
from a hard drive, optical disc or other writeable, rewriteable, or
removable hardware data-storage device 111, stored computer program
code 107 may be stored on a static, nonremovable, read-only storage
medium such as a Read-Only Memory (ROM) device 105, or may be
accessed by processor 103 directly from such a static,
nonremovable, read-only medium 105. Similarly, in some embodiments,
stored computer program code 107 may be stored as computer-readable
firmware 105, or may be accessed by processor 103 directly from
such firmware 105, rather than from a more dynamic or removable
hardware data-storage device 111, such as a hard drive or optical
disc.
[0091] Thus the present invention discloses a process for
supporting computer infrastructure, integrating, hosting,
maintaining, and deploying computer-readable code into the computer
system 101, wherein the code in combination with the computer
system 101 is capable of performing a method for optimizing testing
of a partially symmetric quantum-logic circuit by using wreath
products and invariance groups.
[0092] Any of the components of the present invention could be
created, integrated, hosted, maintained, deployed, managed,
serviced, supported, etc. by a service provider who offers to
facilitate a method for optimizing testing of a partially symmetric
quantum-logic circuit by using wreath products and invariance
groups. Thus the present invention discloses a process for
deploying or integrating computing infrastructure, comprising
integrating computer-readable code into the computer system 101,
wherein the code in combination with the computer system 101 is
capable of performing a method for optimizing testing of a
partially symmetric quantum-logic circuit by using wreath products
and invariance groups.
[0093] One or more data storage units 111 (or one or more
additional memory devices not shown in FIG. 1) may be used as a
computer-readable hardware storage device having a
computer-readable program embodied therein and/or having other data
stored therein, wherein the computer-readable program comprises
stored computer program code 107. Generally, a computer program
product (or, alternatively, an article of manufacture) of computer
system 101 may comprise the computer-readable hardware storage
device.
[0094] While it is understood that program code 107 for a method
for optimizing testing of a partially symmetric quantum-logic
circuit by using wreath products and invariance groups may be
deployed by manually loading the program code 107 directly into
client, server, and proxy computers (not shown) by loading the
program code 107 into a computer-readable storage medium (e.g.,
computer data storage device 111), program code 107 may also be
automatically or semi-automatically deployed into computer system
101 by sending program code 107 to a central server (e.g., computer
system 101) or to a group of central servers. Program code 107 may
then be downloaded into client computers (not shown) that will
execute program code 107.
[0095] Alternatively, program code 107 may be sent directly to the
client computer via e-mail. Program code 107 may then either be
detached to a directory on the client computer or loaded into a
directory on the client computer by an e-mail option that selects a
program that detaches program code 107 into the directory.
[0096] Another alternative is to send program code 107 directly to
a directory on the client computer hard drive. If proxy servers are
configured, the process selects the proxy server code, determines
on which computers to place the proxy servers' code, transmits the
proxy server code, and then installs the proxy server code on the
proxy computer. Program code 107 is then transmitted to the proxy
server and stored on the proxy server.
[0097] In one embodiment, program code 107 for a method for
optimizing testing of a partially symmetric quantum-logic circuit
by using wreath products and invariance groups is integrated into a
client, server and network environment by providing for program
code 107 to coexist with software applications (not shown),
operating systems (not shown) and network operating systems
software (not shown) and then installing program code 107 on the
clients and servers in the environment where program code 107 will
function.
[0098] The first step of the aforementioned integration of code
included in program code 107 is to identify any software on the
clients and servers, including the network operating system (not
shown), where program code 107 will be deployed that are required
by program code 107 or that work in conjunction with program code
107. This identified software includes the network operating
system, where the network operating system comprises software that
enhances a basic operating system by adding networking features.
Next, the software applications and version numbers are identified
and compared to a list of software applications and correct version
numbers that have been tested to work with program code 107. A
software application that is missing or that does not match a
correct version number is upgraded to the correct version.
[0099] A program instruction that passes parameters from program
code 107 to a software application is checked to ensure that the
instruction's parameter list matches a parameter list required by
the program code 107. Conversely, a parameter passed by the
software application to program code 107 is checked to ensure that
the parameter matches a parameter required by program code 107. The
client and server operating systems, including the network
operating systems, are identified and compared to a list of
operating systems, version numbers, and network software programs
that have been tested to work with program code 107. An operating
system, version number, or network software program that does not
match an entry of the list of tested operating systems and version
numbers is upgraded to the listed level on the client computers and
upgraded to the listed level on the server computers.
[0100] After ensuring that the software, where program code 107 is
to be deployed, is at a correct version level that has been tested
to work with program code 107, the integration is completed by
installing program code 107 on the clients and servers.
[0101] Embodiments of the present invention may be implemented as a
method performed by a processor of a computer system, as a computer
program product, as a computer system, or as a processor-performed
process or service for supporting computer infrastructure.
[0102] FIG. 2 is a flow chart that illustrates steps of a method
for optimizing testing of a partially symmetric quantum-logic
circuit by using wreath products and invariance groups in
accordance with embodiments of the present invention. FIG. 2 shows
elements identified by reference numbers 200-220.
[0103] In step 200, a processor of a quantum-logic test-development
system receives a description of a quantum-logic circuit, or
"q-module" with n inputs {x.sub.1 . . . x.sub.n}, each of which may
assume any of t states, and one output that can assume any of s
states. The operation performed by this q-module can be expressed
as a function f.sub.k(x) that maps each n-element input vector
x={x.sub.1, . . . , x.sub.n} onto one of the s output states.
[0104] In one example, a two-input, one-output quantum circuit
device has two inputs {x.sub.1, x.sub.2} that may each assume any
of three states {0, 1, 2}. The circuit's output f(x) may assume any
of four states {0, 1, 2, 3}. In this example, n=2, t=4, and the set
of all possible input vectors is {(00), (01), (02), (10), (11),
(12), (20), (21), (22)}.
[0105] In another example, inputs {x.sub.1, x.sub.2, x.sub.3} of a
3-input, 1-output-state q-module with output that can assume any of
s distinct states. The state of the three inputs are represented by
an input vector x=(x.sub.1, x.sub.2, x.sub.3) and the values (or
states) assumed by each input comprised by this vector may be
subject to permutations that include (id), (12), (13), (23), (123),
or (312). As described above, the inputs of the q-module may be
reordered by permutations into any of six possible distinct orders:
(x.sub.1, x.sub.2, x.sub.3), (x.sub.1, x.sub.3, x.sub.2), (x.sub.2,
x.sub.1, x.sub.3), (x.sub.2, x.sub.3, x.sub.1), (x.sub.3, x.sub.1,
x.sub.2), and (x.sub.3, x.sub.2, x.sub.1).
[0106] If the operation of the q-module can be represented by a
function f(x) that maps each possible input vector x onto a
corresponding value of s, one possible invariance group might
contain a set of permutations {(1,2),(2,3)}, which respectively
correspond to input permutations (x.sub.2, x.sub.1, x.sub.3) and
(x.sub.1, x.sub.3, x.sub.2). Because these permutations are
invariant, swapping either the first two inputs {x.sub.1, x.sub.2}
or the last two inputs {x.sub.2, x.sub.3 } will not change the
output of the q-module. For example, an input (010) would produce
the same output as would inputs (100) (permutation (x.sub.1,
x.sub.2)) and (001) (permutation (x.sub.2, x.sub.3)).
[0107] Because f(x.sub.1, x.sub.2, x.sub.3)=f(x.sub.2, x.sub.1,
x.sub.3)=f(x.sub.1, x.sub.3, x.sub.2) in this example, it is
possible to simultaneously test three input vectors by testing only
one of them.
[0108] In step 205, the system identifies a function f(x) that
represents the functionality performed by the q-module upon an
n-tuple input vector x that represents an ordered set of n inputs
of the q-module. The domain of function f consists of all inputs
x={x.sub.1, x.sub.2, . . . , x.sub.n} of the q-module, and the
value of any f(x.sub.1, x.sub.2, . . . , x.sub.n) is defined as an
output state of q-module for input vector x=(x.sub.1, x.sub.2, . .
. , x.sub.n).
[0109] Expressed more formally, the operation generated by a
quantum module M can be represented by function f:{0,1, . . . ,
t-1}.sup.n.fwdarw.{0, 1, . . . , s-1}, and the value of
f(x)=f(x.sub.1, x.sub.2, . . . , x.sub.n) is the output produced by
M in response to receiving input vector x=(x.sub.1, x.sub.2, . . .
, x.sub.n). The set S(f) of all possible permutations of M's inputs
that do not change the output of M is called an invariance group,
or a symmetry group, of f(x).
[0110] This may be stated as: [0111] f:{0,1, . . . ,
t-1}.sup.n.fwdarw.{0,1, . . . , s-1}, where t>1, s>1. [0112]
.sigma. is a permutation comprised by symmetric group S.sub.n,
where S.sub.n contains permutations of indexes of input vector
x=(x.sub.1, x.sub.2, . . . , x.sub.n). [0113] The action of
permutation .sigma. on f(x.sub.1, x.sub.2, . . . , x.sub.n) may be
expressed as: [0114] f.sup..sigma.(x.sub.1, x.sub.2, . . . ,
x.sub.n)=f(x.sub..sigma.(1), x.sub..sigma.(2), . . . ,
x.sub..sigma.(n)). That is, applying function f.sup..sigma. to an
input vector x is equivalent to applying function f(x) to an input
vector x.sup..sigma.={x.sub..sigma.(1), x.sub..sigma.(2), . . . ,
x.sub..sigma.(n)}, [0115] where x.sup..sigma.=a permuted set of
inputs created by applying permutation .sigma. to x. [0116]
S(f)={.sigma. .di-elect cons. S.sub.n: f=f.sup..sigma.}. That is,
S(f) is the set of all permutations .sigma. that, when performed
upon an input vector x, do not change the output value f( ). [0117]
The set of permutations S(f) is thus defined as the invariance
group, or symmetry group of f( ).
[0118] In step 207, the system divides the q-module's n inputs
{x.sub.1 . . . x.sub.n} into k blocks by any means known in the
art. This division may be performed as a function of the
architecture of the q-module and, in many cases, a person skilled
in the art may identify logical split points that divide the inputs
by referring to product documentation published by the manufacturer
of the q-module.
[0119] The examples described here refer this set of k blocks as
{A(i)}, i=1,2, . . . k. Each block contains the same number of
inputs. That is, |A(i)|=b for all i=1 . . . k, where b=n/k (the
total number of inputs divided by the number of blocks). In one
example, the inputs of a 15-input q-module might be divided into
five blocks, each of which contains any three ordered inputs. Two
examples of such a five-block division are:
A(1)=(x1, x2, x3), A(2)=(x4, x5, x6), . . . A(5)=(x13, x14,
x15)
and
A(1)=(x4, x6, x7), A(2)=(x1, x2, x15), . . . A(5)=(x12, x13,
x14)
[0120] Subsequent steps of FIG. 2 will generate an invariance group
of permutations of inputs n=b*k, where that invariance group
contain two types of permutations:
[0121] i) permutations that preserve the division of inputs into
blocks {A(i)} (permutations that permute only inputs that are in
the same block A(i)); and
[0122] ii) permutations that swap two or more blocks in their
entirety, but do not permute the internal order of inputs within
any of the swapped blocks. If, for example, A(1)={x.sub.1, x.sub.2,
x.sub.3} and A(2)={x.sub.4, x.sub.5, x.sub.6}, a permutation of
this type might be (1,4)(2,5)(3,6), resulting in a permutation of
input vector(x.sub.1, x.sub.2, x.sub.3, x.sub.4, x.sub.5, x.sub.6)
to (x.sub.4, x.sub.5, x.sub.6, x.sub.1, x.sub.2, x.sub.3). Here,
(1,4) exchanges inputs x.sub.1 and x.sub.4 (identified by the first
and fourth indices), (2,5) exchanges inputs x.sub.2 and x.sub.5
(identified by the second and fifth indices), and (3,6) exchanges
inputs x.sub.3 and x.sub.6 (identified by the third and sixth
indices).
[0123] In step 210, the system in a similar manner organizes the k
blocks {A(i)} into a set of m second-level blocks {B(j)}, j=1 . . .
m. This division may be performed as a function of the architecture
of the q-module and, in many cases, a person skilled in the art may
identify logical split points that divide the inputs by referring
to product documentation published by the manufacturer of the
q-module.
[0124] For example, given a 12-input q-module with inputs {x.sub.1
. . . x.sub.12}, {A(i)} might consist of k=4 three-element
first-level blocks=(x.sub.1, x.sub.2, x.sub.3) . . . (x.sub.10,
x.sub.11, x.sub.12), and {B(j)} might consist of m=2 second-level
blocks B(1)={A(1), A(2))} and B(2)={(A(3), A(4))}. As shown in the
below diagram, each of two second-level blocks B contains two
first-level blocks A, and each of four first level blocks A
contains three inputs x.
##STR00001##
[0125] Higher-level divisions of inputs may continue subdividing
blocks of inputs in this manner, creating a hierarchical structure,
where each level of the structure contains blocks that each group
two or more blocks at the next-highest level.
[0126] In step 215, the system identifies an invariance group of
function f( )as a wreath product of groups that each comprise one
of the blocks identified in steps 207 and 210. Here, each group can
be expressed as (G,X), where X is a set of data elements and G is a
set of permutation operations that may be performed upon the data
elements.
[0127] A wreath product is a specialized type of product that
generates an output group as a function of two input groups.
Although well-known in the art of group theory, this document will
briefly overview the operation of a wreath product for reasons of
readability, and because embodiments of the present invention apply
and interpret wreath-product operations in an unusual way.
[0128] As will be described below, the system derives a wreath
product of sets of groups that each represent the organization of
data elements of one level of the hierarchical structure of step
210. This wreath product may be interpreted as invariance group
S(f) of function f.sub.k( ) where f.sub.k( ) represents the
operation of the q-module where the q-module's inputs have been
divided into k first-level blocks {A(i)}.
[0129] This invariance group comprises permutations that may be
performed upon an input vector x to produce a permuted vector
x.sub.p, such that f.sub.k(x) and f.sub.k(x.sub.p) produce
identical output. That is, for any possible combination of input
states of a q-module, applying any permutation of S(f) to the
inputs of the q-module does not change the output of the
q-module.
[0130] In embodiments described in this document, the set S(f) of
invariant permutations includes only permutations that either
reorder inputs contained in only one block A(i), or else swap
entire blocks. In some embodiments, an invariant permutation may
perform both operations. No other invariant permutations may be
derived from the particular type of wreath product described here.
This wreath product is semi-recursive because it consists of nested
wreath product computations. In examples and embodiments described
in this document, a wreath product of two groups G and H will be
expressed as G H.
[0131] In one example, consider the set of divisions, similar to
those shown in the above diagram, but where 24 inputs of a q-module
have been divided into eight first-level blocks of three inputs,
and where those eight first-level blocks have been divided into two
second-level blocks. That is, n=12, k=8, b=3, m=3, and p=2.
[0132] Here, the total number of inputs n=b*m*p=3*4*2=(the number
of inputs b in each first-level block A(i))*(the number m of
first-level blocks A(i) in each second-level block B(i))*(the
number p of second-level blocks).
[0133] Embodiments of the present invention then construct a first
permutation group G=(G(1), X) that comprises a set X of three data
elements (that is, it comprises an ordered set of b indices, where
b equals the number of inputs in any block A(i)); and a set of
permutations G(1) that consists of all possible permutations that
may be applied to the b=3 inputs of block A(i).
[0134] Similarly, the system constructs a second permutation group
H=(H(1), Y) that comprises a set Y of two data elements (that is,
it comprises an ordered set of m indices, where m equals the number
of blocks {A(i)} contained in any block B(j)); and a set of
permutations H(1) that identifies all possible permutations that
may be applied to the m=2 blocks A(i) of each block B(j).
[0135] Finally, the system constructs a third permutation group
L=(L,Z) that comprises a set Z of two data elements (that is, it
comprises an ordered set of p indices, where p equals the number of
blocks B(j)); and a set of permutations L(1) that identifies all
possible permutations that may be applied to each of the m=2 blocks
B(j).
[0136] In this example, the wreath product of G and H may be
computed as:
G _ H _ = ( ( G 1 .times. G M ) .times. H , X .times. Y ) = ( ( G 1
.times. G 2 ) .times. H , X .times. Y ) ##EQU00001##
[0137] where x represents the Cartesian product operator, and each
G.sub.i, i=1 . . . m is an exact copy of G that operates upon a set
of b=3 three inputs. One way to conceptualize this constructions is
that the three inputs of G.sub.1 correspond respectively to inputs
x.sub.1, x.sub.2, x.sub.3 and the three inputs of G.sub.2
correspond respectively to inputs x.sub.4, x.sub.5, and
x.sub.6.
[0138] Similarly, the wreath product of G H L may be computed
as:
G _ H _ L _ = ( G _ H _ ) L = _ ( ( G 1 .times. G 2 ) .times. H ) L
_ = ( ( ( G 1 .times. G 2 ) .times. H 1 ) .times. ( ( G 3 .times. G
4 ) .times. H 2 ) .times. L , X .times. Y .times. Z ) = S ( f )
##EQU00002##
[0139] As at the previous level, each group (G H)(i)=((G.sub.1 x
G.sub.2) x H.sub.i), i=1 . . . p is an exact copy of previous
wreath product G H. Each of these wreath products G H may be
interpreted to correspond to one group of the p=2 blocks A(i). In
this example, (G H)(1) corresponds to blocks A(1) and A(2), and(G
H)(2) corresponds to block A(3) and A(4).
[0140] This wreath-product procedure can be extended to any number
of levels of divisions by extrapolating the examples above. At each
level of division, the invariance group is derived semi-recursively
by computing a wreath product of two groups, one of which is the
wreath product derived for the next-highest level. The final
invariance group S(f) of any function f(x) that represents
functionality of a q-module, where the module's inputs are divided
into z levels of blocks can be derived from Eq. (1):
S(f)=Grp.sub.1 Grp.sub.2 . . . Grp.sub.z (1)
[0141] where each Grp(i), i=1 . . . z corresponds to a level i and
comprises a set of elements contained in each block at level i and
a set of permutations that may be applied to that set of i-level
elements.
[0142] In one example, an invariance group S(f) is defined as the
set of permutations:
{id, (1,2), (3,4), (1,2)(3,4), (1,3)(2,4), (1,4)(2,3), (1,4,2,3),
(1,3,2,4)}={id, (1,2)}.intg.{id, (1,2)}
[0143] In this example, A.sup.u.sub.v represents a division of
level u that corresponds to an index of a corresponding division at
level u-1.
[0144] Eq. (1) generates the invariance group as a wreath product
of two groups: S(f)=G H, where both G and H={id, (1,2)}. Here,
because G comprises a set of all permutations of set {1,2}(that is,
m=2), the wreath product requires two identical copies of G,
referred to here as G.sub.1, which acts on set A.sup.1.sub.1={1,2}
and G.sub.2, which acts on set A.sup.1.sub.2={3,4}. As in previous
examples, each copy of G comprises permutations that act upon
inputs comprised by one of the first-level divisions A.sub.i and
permutations comprised by H each act on an entire first-level
division (not individual inputs).
[0145] This example can be extended to embodiments that comprise
three or more levels of divisions. As described above, G={id,(1,2)}
and H={id,(1,2)}, so:
G H={id,(1,2)}.intg.{id, (1,2)}
[0146] This computation may be extended to account for a third
level of divisions when deriving invariance group by defining a
third group L={id,(1,2)} and evaluation Eq. (1):
S(f)=G H L.
[0147] Here, group L acts upon on the set of indices of inputs
{1,2,3,4,5,6,7,8}, in the following way: The first level of blocks
comprise four blocks
A.sup.1.sub.1={x.sub.1, x.sub.2}, A.sup.1.sub.2={x.sub.3, x.sub.4},
A.sup.1.sub.3={x.sub.5, x.sub.6}, A.sup.1.sub.4={x.sub.7,
x.sub.8}
[0148] embodiments create four identical copies of group G denoted
G.sub.1, G.sub.2, G.sub.3, G.sub.4. Each of these four groups
contains the same two-index permutation comprised by the original
group G, and each acts on one first-level two-input division of
input vector x={x.sub.1, x.sub.2, x.sub.3, x.sub.4, x.sub.5,
x.sub.6, x.sub.7, x.sub.8}. Therefore:
[0149] G.sub.1={id,(1,2)} and acts on A.sup.1.sub.1={x.sub.1,
x.sub.2},
[0150] G.sub.2={id,(3,4)} and acts on A.sup.1.sub.2={x.sub.3,
x.sub.4},
[0151] G.sub.3={id,(5,6)} and acts on A.sup.1.sub.3={x.sub.5,
x.sub.6}, and
[0152] G.sub.4={id,(7,8)} and acts on A.sup.1.sub.4={x.sub.7,
x.sub.8}.
[0153] A second level of this construction is represented in a
similar manner by group H. Here, embodiments create two identical
copies of group H, denoted H.sub.1 and H.sub.2. As before,
[0154] H.sub.1={id,(1,2)} and acts on A.sup.2.sub.1={A.sup.1.sub.1,
A.sup.1.sub.2}, and
[0155] H.sub.2={id,(3,4)} and acts on A.sup.2.sub.2={A.sup.1.sub.3,
A.sup.1.sub.4}.
[0156] Finally third level of this construction is represented by
the group L={id,(1,2)}. Because there is only one set of divisions
at the third-level only one copy of L is required, where:
[0157] L.sub.1={id,(1,2)} and acts on {A.sup.2.sub.1,
A.sup.2.sub.2}.
[0158] The result of this computation produces a total of
2.sup.7=128 distinct permutations.
[0159] In step 220, the system uses the functions and invariance
group derived in step 215 as functions of the wreath products to
streamline the testing of the q-module. This invariance group
specifies a set of invariant or symmetrical permutations that, when
performed upon the q-module's inputs, do not cause the q-module's
output to change. And, as described above, a permutation that does
not cause the output to change does not have to be tested,
regardless of the state of any of the module's inputs prior to
performing the permutation.
[0160] In a simple example, consider a four input q-module with
inputs {x.sub.1, x.sub.2, x.sub.3, x.sub.4} that is described by a
function f( ). An invariance group S(f) for f has been identified
by dividing the inputs into layers of blocks and by performing the
semi-recursive wreath products described above. S(f) comprises an
invariant permutation (1,2).
[0161] If a testing procedure has confirmed that the module
produces correct output in response to receiving an input vector
x=(1011), it is known that the module will produce the same output
in response to receiving an input vector x.sub.p=(0111), where
x.sub.p is created by performing the permutation (1,2) upon x.
Therefore, the q-module does not have be tested with input (0111)
and the test case in which an input vector=(0111) can be
eliminated.
[0162] Similarly, if a testing procedure has confirmed that the
module produces correct output in response to receiving an input
vector x=(0100), it is known that the module will produce the same
output in response to receiving an input vector x.sub.p=(1000),
where x.sub.p is created by performing the permutation (1,2) upon
x. Therefore, the q-module does not have be tested with input
(1000) and the test case in which an input vector=(1000) can be
eliminated.
[0163] In a more complex example, consider a q-module in which each
input may assume either of two values {0,1}, where an invariance
group S(f) has been identified by means of Eq. (1):
S(f)={(id), (1,2), (3,4), (1,2)(3,4), (1,3)(2,4), (1,4)(2 3),
(1,4,2,3), (1,3,2,4)}
[0164] This set of permutations is a wreath product of 2 groups.
Permutations (1,2) and (3,4) each permute inputs at a first level,
inside a block of length b=2. Permutations (1,2)(3,4), (1,3)(2,4),
(1,4)(2,3), (1,4,2,3) and (1,3,2,4) each permute at a second level,
permuting (or swapping) entire blocks A.sub.1={1,2} and
A.sub.2={3,4}. Permutations (1,4,2,3), (1,3,2,4) act on the second
level as well.
[0165] For example, permutation (1,4,2,3) transforms (x.sub.1,
x.sub.2, x.sub.3, x.sub.4) into (x.sub.4, x.sub.3, x.sub.1,
x.sub.2) (4.fwdarw.1, 2.fwdarw.4, 3.fwdarw.2, 1.fwdarw.3),
effectively swapping elements of the first block at the first level
and swapping entire blocks A.sub.1 and A.sub.2 at the second level.
Similarly, permutation (1,3,2,4) transforms (x.sub.1, x.sub.2,
x.sub.3, x.sub.4) into (x.sub.3, x.sub.4, x.sub.2, x.sub.1)
(3.fwdarw.1, 2.fwdarw.3, 4.fwdarw.2, 1.fwdarw.4), in effect
swapping elements inside the second block at the first level and
swapping A.sub.1 and A.sub.2 at the second level.
[0166] In this embodiment, Equation (1) automatically selects only
that permutations that: i) permute elements only in the first block
(such as (1,2)); ii) permute elements only in the second block
(such as (3,4)); permute elements in the first block and in the
second block in a similar manner (such as (1,2)(3,4)); swap whole
blocks (such as (1,3)(2,4)); swap entire blocks and permute
elements inside both blocks (such as (1,4)(2,3)), swap entire
blocks and permute elements inside the first block (such as
(1,4,2,3)); or swap entire blocks and permute elements inside the
second block (such as (1,3,2,4)).
[0167] Table 1 illustrates this example for all possible values of
input vector x of the four-input, two-state q-module. The first
four columns identify all possible input states identified by
4-tuple input vector x, which represents inputs that may be
received by the q-module. The fifth column identifies whether a
test procedure is required to verify the output produced by
function f(x), which defines the expected operation of the
q-module, for each possible value of input vector x. Permutations
of previously verified vectors x that do not need to be tested are
identified by the term "NOTEST."
TABLE-US-00001 TABLE 1 x1 x2 x3 x4 f.sub.2(x1, x2, x3, x4) 0 0 0 0
TEST 0 0 0 1 TEST 0 0 1 0 NOTEST 0 0 1 1 TEST 0 1 0 0 NOTEST 0 1 0
1 TEST 0 1 1 0 NOTEST 0 1 1 1 TEST 1 0 0 0 NOTEST 1 0 0 1 NOTEST 1
0 1 0 NOTEST 1 0 1 1 NOTEST 1 1 0 0 NOTEST 1 1 0 1 NOTEST 1 1 1 0
NOTEST 1 1 1 1 TEST
For example, once input vector (0,1,0,1) has been verified, there
is no need to test the following permutations:
[0168] (0,1,0,1): the trivial permutation(id),
[0169] (1,0,0,1): permutation (1,2): swap x.sub.1 with x.sub.2,
[0170] (0,1,1,0): permutation (3,4): swap x.sub.3 with x.sub.4,
[0171] (1,0,1,0): permutation (1,2)(3,4): swap x.sub.1 with x.sub.2
and swap x.sub.3 with x.sub.4,
[0172] (0,1,0,1): permutation (1,3)(2,4): swap block (x.sub.1,
x.sub.2) with block (x.sub.3, x.sub.4),
[0173] (1,0,1,0): permutation (1,4)(2,3): swap block (x.sub.1,
x.sub.2) with block (x.sub.3, x.sub.4) and swap x.sub.1 with
x.sub.2 and swap x.sub.3 with x.sub.4,
[0174] (0,1,1,0): permutation (1,3,2,4): swap block (x.sub.1,
x.sub.2) with block (x.sub.3, x.sub.4) and swap x1 with x2 . As
described in previous examples, this permutation performs the
following procedure:
[0175] replace index #1 of x with x.sub.3 (index #3 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.3, x.sub.4),
[0176] replace index #3 of x with x.sub.2 (index #2 of
x).fwdarw.(x.sub.3, x.sub.2, x.sub.2, x.sub.4),
[0177] replace index #2 of x with x.sub.4 (index #4 of
x).fwdarw.(x.sub.3, x.sub.4, x.sub.2, x.sub.4),
[0178] replace index #4 of x with x.sub.1 (index #1 of
x).fwdarw.(x.sub.3, x.sub.4, x.sub.2, x.sub.1),
[0179] stop because rotating back to the first index of .sigma.
would repeat a previously performed operation,
[0180] (1,0,0,1): permutation (1,4,2,3): swap block (x.sub.1,
x.sub.2) with block (x.sub.3, x.sub.4) and swap x3. This
permutation performs the following procedure:
[0181] replace index #1 of x with x.sub.4 (index #4 of
x).fwdarw.(x.sub.4, x.sub.2, x.sub.3, x.sub.4),
[0182] replace index #4 of x with x.sub.2 (index #2 of
x).fwdarw.(x.sub.4, x.sub.2, x.sub.3, x.sub.2),
[0183] replace index #2 of x with x.sub.3 (index #3 of
x).fwdarw.(x.sub.4, x.sub.3, x.sub.3, x.sub.2),
[0184] replace index #3 of x with x.sub.1 (index #1 of
x).fwdarw.(x.sub.4, x.sub.3, x.sub.1, x.sub.2),
[0185] stop because rotating back to the first index of o would
repeat a previously performed operation.
Deleting duplicate input vectors produces a set of input vectors
{(0101), (0110), (1001), (1010)} that may be produced from each
other by applying invariant permutations of S(f) to vector (0101).
Once (0101) has been verified, no subsequent vectors in the table
need be tested. Table 1 illustrates this by noting that (0110),
(1001), (1010), all of which follow (0101) in the test sequence, do
not need to be tested. Applying these invariant permutations upon
other input vectors of Table 1 will similarly eliminate the need to
test other input vectors.
[0186] In a similar manner, an invariance group may be used to
reduce the total number of tests required to completely verify
other types of q-modules. In the above 4-input, 1-output-state
example, the total number of tests is reduced from 16 to 6, but
when the number of inputs or the number of possible input states of
a q-module increases, embodiments of the present invention may
allow very large numbers of tests to be eliminated.
* * * * *