U.S. patent application number 15/638432 was filed with the patent office on 2017-10-26 for wireless sensor reader.
The applicant listed for this patent is Endotronix, Inc.. Invention is credited to Harry Rowland, Balamurugan Sundaram, Roger Watkins.
Application Number | 20170309164 15/638432 |
Document ID | / |
Family ID | 42936490 |
Filed Date | 2017-10-26 |
United States Patent
Application |
20170309164 |
Kind Code |
A1 |
Rowland; Harry ; et
al. |
October 26, 2017 |
WIRELESS SENSOR READER
Abstract
A wireless sensor reader is provided to interface with a
wireless sensor. The wireless sensor reader transmits an excitation
pulse to cause the wireless sensor to generate a ring signal. The
wireless sensor reader receives and amplifies the ring signal and
sends the signal to a phase-locked loop. A voltage-controlled
oscillator in the phase-locked loop locks onto the ring signal
frequency and generates a count signal at a frequency related to
the ring signal frequency. The voltage-controlled oscillator is
placed into a hold mode where the control voltage is maintained
constant to allow the count signal frequency to be determined.
Inventors: |
Rowland; Harry; (Plainfield,
IL) ; Watkins; Roger; (Dunlap, IL) ; Sundaram;
Balamurugan; (Peoria, IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Endotronix, Inc. |
Woodbridge |
IL |
US |
|
|
Family ID: |
42936490 |
Appl. No.: |
15/638432 |
Filed: |
June 30, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15084054 |
Mar 29, 2016 |
9721463 |
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15638432 |
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13859444 |
Apr 9, 2013 |
9305456 |
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15084054 |
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13423693 |
Mar 19, 2012 |
8432265 |
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13859444 |
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12419326 |
Apr 7, 2009 |
8154389 |
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13423693 |
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12075858 |
Mar 14, 2008 |
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12419326 |
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60918164 |
Mar 15, 2007 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
A61B 2562/0219 20130101;
G08C 17/02 20130101; A61B 5/0031 20130101; A61B 5/7225 20130101;
A61B 5/6882 20130101; A61B 5/0215 20130101 |
International
Class: |
G08C 17/02 20060101
G08C017/02; A61B 5/00 20060101 A61B005/00; A61B 5/00 20060101
A61B005/00; A61B 5/0215 20060101 A61B005/0215 |
Claims
1. A wireless sensor reader comprising: a transmit circuit
configured to generate at least one excitation pulse to cause a
wireless sensor to emit at least one response signal; at least one
antenna configured to transmit said excitation pulse and receive
said response signal; a circuitry to process the response signal;
and a timing and control circuitry configured to activate at least
one of the transmit circuit, antenna, and circuitry to process the
response signal of the wireless sensor reader.
2. The wireless sensor reader of claim 1, wherein said wireless
sensor is configured to change its resonant frequency in proportion
to at least one sensed parameter.
3. The wireless sensor reader of claim 1, wherein said circuitry to
process the response signal comprises a phase-locked loop.
4. The wireless sensor reader of claim 3, wherein said phase-locked
loop circuit further includes circuitry for internal
calibration.
5. The wireless sensor reader of claim 1, wherein the timing and
control circuitry may place at least one of the transmit circuit,
antenna, and circuitry to process the response signal of the
wireless sensor reader in a reduced power mode after a specified
period of inactivity.
6. The wireless sensor reader of claim 5, wherein the specified
period of inactivity is adjustable.
7. The wireless sensor reader of claim 1, wherein the timing and
control circuitry includes a configuration buffer that receives
timing instructions from an external interface circuitry wherein
the instructions establish a timing period before entering into a
reduced power mode.
8. The wireless sensor reader of claim 1, wherein the timing and
control circuitry includes a wakeup timer to sequence the power up
of at least one of the transmit circuit, antenna, and circuitry to
process the response signal of the wireless sensor reader.
9. The wireless sensor reader of claim 1 further comprising a
transmit timer in communication with the transmit circuitry, a
receiver timer in communication with the antenna, a phase-locked
loop timer in communication with a phase-locked loop, and a
frequency counter timer in communication with a frequency
counter.
10. The wireless sensor reader of claim 9, wherein the timing and
control circuitry is in communication with the transmit timer, the
receiver timer, the phase-locked loop timer, and the frequency
counter timer.
11. A wireless sensor reader comprising: a transmit circuit
configured to generate at least one excitation pulse to cause a
wireless sensor to emit at least one response signal corresponding
to a sensed parameter value; at least one antenna configured to
transmit said at least one excitation pulse and receive said at
least one response signal; a receiver circuit for amplifying said
at least one received response signal; a phase-locked loop; a
frequency counter; a timing and control circuitry configured to
activate at least one of the transmit circuit, antenna, receiver
circuit, phase locked loop, and frequency counter of the wireless
sensor reader.
12. The wireless sensor reader of claim 11 wherein said wireless
sensor reader is a handheld device.
13. The wireless sensor reader of claim 11 further comprising a
battery for powering said wireless sensor reader.
14. The wireless sensor reader of claim 11, wherein the timing and
control circuitry is configured to instruct the frequency counter
to conduct a controlled interval count of a voltage controlled
oscillator frequency of the phase-locked loop, wherein after the
count, the phase locked loop is placed in sleep mode and the count
value is transferred to an external interface circuitry.
15. A system for reading a wireless sensor comprising: a wireless
sensor including at least one inductor and one capacitor configured
to change its resonant frequency in proportion to at least one
sensed parameter; and a reader for transmitting at least one
excitation pulse to said wireless sensor and to receive at least
one signal from said wireless sensor in response to said excitation
pulse, wherein the reader includes: a phase-locked loop circuit
configured to receive said response signal from said at least one
antenna, said phase-locked loop circuit including a
voltage-controlled oscillator configured to generate a count signal
at a frequency related to said response signal frequency; and a
timing and control circuitry to configure and activate components
of the reader.
16. The system of claim 15 wherein said timing and control
circuitry places each component of the reader in a powered-down
mode after a specified period of inactivity.
17. The system of claim 15 wherein said timing and control
circuitry further comprises a wakeup timer to communicate with a
transmit timer, a receive timer, a phase-locked loop timer, and a
frequency counter timer to wake up and control the respective
components of the wireless sensor reader.
18. The system of claim 15, wherein the timing and control
circuitry includes a configuration buffer that receives timing
instructions from an external interface circuitry wherein the
instructions establish a timing period before entering into a
reduced power mode.
19. The wireless sensor reader of claim 15, wherein the timing and
control circuitry includes a wakeup timer to sequence the power up
of at least one of the transmit circuit, antenna, and circuitry to
process the response signal of the wireless sensor reader.
20. The wireless sensor reader of claim 15 further comprising a
transmit timer in communication with a transmit circuitry, a
receiver timer in communication with an antenna, a phase-locked
loop timer in communication with the phase-locked loop circuitry,
and a frequency counter timer in communication with a frequency
counter, wherein the timing and control circuitry is in
communication with the transmit timer, the receiver timer, the
phase-locked loop timer, and the frequency counter timer.
Description
RELATED APPLICATIONS
[0001] This non-provisional application is a continuation of U.S.
patent application Ser. No. 15/084,054 filed on Mar. 29, 2016,
which is a continuation of U.S. patent application Ser. No.
13/859,444 filed on Apr. 9, 2013, which is a continuation of U.S.
patent application Ser. No. 13/423,693 filed on Mar. 19, 2012,
which is a continuation of U.S. patent application Ser. No.
12/419,326 filed on Apr. 7, 2009, which is a continuation-in-part
of U.S. patent application Ser. No. 12/075,858 filed on Mar. 14,
2008, which claims priority to U.S. Provisional Application No.
60/918,164 filed on Mar. 15, 2007 each of which are incorporated by
reference in their entirety.
TECHNICAL FIELD
[0002] This invention relates generally to reading passive wireless
sensors, and more particularly to a reader circuitry for exciting
and sensing data from passive wireless sensors.
BACKGROUND
[0003] Passive wireless sensor systems that employ resonant circuit
technology are known. These systems utilize a passive wireless
sensor in remote communication with excitation and reader
circuitry. Often the wireless sensor is implanted at a specific
location, such as within the human body, to detect and report a
sensed parameter. The sensed parameter varies the resonant circuit
frequency of the wireless sensor. The reader device samples the
resonant frequency of the wireless sensor to determine the sensed
parameter.
[0004] U.S. Pat. No. 4,127,110 by Bullara discloses a sensor for
measuring brain fluid pressure measurement. U.S. Pat. No. 4,206,762
by Cosman discloses a similar sensor for measuring internal
pressure. Specifically, the Cosman patent describes the use of a
grid dip system for wirelessly measuring the resonant frequency of
the sensor. In addition, the Cosman patent discloses the
possibility of a battery powered portable reader device.
[0005] Several methods of reading passive wireless sensors have
also been described in prior patents. For example, the Cosman
patent discloses an external oscillator circuit that uses the
implanted sensor for tuning, and a grid dip measurement system for
measurement of sensor resonant frequency. U.S. Pat. No. 6,015,386
by Kensey, et al., discloses a reader that excites the passive
sensor by transmitting frequency sweeps and uses a phase detector
on the transmit signal to detect the time during the sweep where
the transmitted frequency matches the resonance frequency of the
sensor. U.S. Pat. No. 6,206,835 by Spillman, et al., discloses a
medical implant application for reader technology disclosed in U.S.
Pat. No. 5,581,248 by Spillman, et al. This reader technology
detects a frequency dependent variable impedance loading effect on
the reader by the sensor's detected parameter. U.S. Pat. No.
7,432,723 by Ellis, et al., discloses a reader with energizing
loops each tuned to and transmitting different frequencies spaced
to ensure that the bandwidth of the sensor allows resonant
excitation of the sensor. Ellis uses a ring-down response from the
appropriate energizing loop to determine the sensor resonant
frequency.
[0006] Some readers utilize phased-locked-loop ("PLL") circuitry to
lock onto the sensor's resonant frequency. U.S. Pat. No. 7,245,117
by Joy, et al. discloses an active PLL circuit and signal
processing circuit that adjusts a transmitting PLL frequency until
the received signal phase and the transmitting PLL signal phase
match. When this match occurs, the transmitting PLL frequency is
equal to the sensor resonant frequency.
[0007] PLL circuits may incorporate sample and hold (S/H) functions
to sample the input frequency and hold the PLL at a given
frequency. PLLs with S/H may be used in a variety of applications.
For example, U.S. Pat. No. 4,531,526 by Genest discloses a reader
that uses a PLL circuit with a S/H circuit to adjust the
transmitted frequency of the reader to match the resonant frequency
received from the sensor. This is done to maximize sensor response
to the next transmission and measures the decay rate of the sensor
resonance amplitude to extract the sensor value. U.S. Pat. No.
4,644,420 by Buchan describes a PLL with a S/H used to sample a
tape data stream and maintain an appropriate sampling frequency for
evaluation of digital data pulses on the tape. U.S. Pat. No.
5,006,819 by Buchan, et al., provides additional enhancements to
this concept. U.S. Pat. No. 5,920,233 by Denny describes a
high-speed sampling technique using a S/H circuit with a PLL to
reduce the charge pump noise from the phase-frequency detector to
enhance the low-jitter performance of a frequency synthesizing
circuit. U.S. Pat. No. 4,511,858 by Charvit, et al., discloses a
PLL with a S/H circuit to pre-position the control voltage of a
voltage controlled oscillator when the PLL lock frequency is being
changed. This is done to enhance the response speed of the PLL when
changing the desired synthesized frequency. U.S. Pat. No. 6,570,457
by Fischer and U.S. Pat. No. 6,680,654 by Fischer, et al., disclose
a PLL with S/H circuitry to enhance PLL frequency stepping as well
as offset correction feature. U.S. Pat. No. 3,872,455 by Fuller, et
al. discloses a PLL having a digital S/H to freeze the frequency
display and preload the frequency counter when a PLL phase lock is
detected.
[0008] Current designs for passive sensor readers, such as those
disclosed above, suffer from a number of deficiencies. Swept
frequency sensor readers similar to those described in the Cosman,
Kensey, Ellis and Spillman patents require relatively wide
bandwidth allowance by the government body regulating radio
transmissions. This limits other uses of the spectrum and makes
interference a potential issue. Readers that track the resonant
frequency of a passive resonant sensor with a variable frequency
transmitter, such as Genest, Ellis, and Joy also suffer from
similar problems. Moreover, the amount of electrical power needed
for transmissions, signal processing, sampling, and tracking the
resonant frequency of a sensor using digitally controlled frequency
tracking or swept frequency systems is significant and limits the
ability to use battery power in a reader, as well as limiting the
longevity of batteries in a battery powered reader. Accordingly, an
improved passive sensor reader is needed in the art.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Reference to the detailed description is taken in connection
with the following illustrations:
[0010] FIG. 1 illustrates a block diagram of a passive wireless
sensor system;
[0011] FIG. 2 illustrates a block diagram of the reader
circuitry;
[0012] FIG. 3 illustrates a block diagram of the timing and control
portion of the reader circuitry;
[0013] FIG. 4 illustrates a block diagram of the transmit portion
of the reader circuitry;
[0014] FIG. 5 illustrates a block diagram of the receive portion of
the reader circuitry;
[0015] FIG. 6 illustrates a block diagram of the phase locked loop
portion of the reader circuitry; and
[0016] FIG. 7 illustrates a block diagram of the frequency counter
portion of the reader circuitry.
SUMMARY
[0017] A reader device is provided to interface with a wireless
sensor. The reader emits a short pulse of energy or a short burst
of radio frequency energy to cause the wireless sensor to ring.
Immediately after the transmission, the reader receives and
amplifies the sensor signal, then sends the signal to a
phase-locked loop ("PLL") that locks to the sensor ring frequency.
Once the PLL has locked to the ring frequency, the PLL's voltage
controlled oscillator ("VCO") is placed in a hold mode to maintain
the VCO frequency at the locked frequency. The VCO frequency is
counted to determine the sensor resonant frequency.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0018] A passive wireless sensor system including a reader 10 in
remote communication with a sensor 12 is provided. The reader is
capable of exciting the sensor 12 by transmitting a signal, such as
a radio frequency ("RF") pulse, at or near the resonant frequency
of the sensor 12. (See FIG. 1.) The sensor 12 may emit a ring
frequency for a short period of time in response to the excitation
pulse from the reader 10.
[0019] The sensor 12 may be a passive device, capable of emitting a
ring signal in response to an excitation signal at or near the
resonant frequency of the sensor 12. The sensor 12 may be
configured to sense a specific parameter. For example, the sensor
12 may include a fixed inductor and a capacitor that varies based
on the sensed parameter. The varying capacitance alters the
resonant and ring frequencies of the sensor 12. It should be
appreciated, however, that the sensor 12 may be any wireless sensor
known in the art capable of remote communication with the reader
10. Further, while the sensor 12 is described as an RF resonant
sensor, it will be appreciated that the sensor 12 may be a
acoustically resonant sensor, optically resonant sensor, or other
similar sensor known in the art. The corresponding reader 10 may
employ corresponding signals to activate the sensor 12. Further,
the sensor 12 may be an active sensor or a passive sensor.
[0020] The reader 10 may excite the sensor 12 by transmitting an
excitation pulse 14 in the vicinity of the sensor 12. For example,
the reader may emit a radio frequency ("RF") excitation pulse 14 at
or near the resonant frequency of the sensor 12. The sensor 12 may
emit a ring signal 16 in response to the excitation pulse 14. The
reader 10 may determine the frequency of the ring signal 16 in
order to determine the sensed parameter value.
[0021] The reader 10 may also communicate with a data interface 17.
The reader 10 and data interface 17 may be connected directly or
indirectly, or may communicate via a remote connection. The reader
10 may send information, such as data related to the sensor 12, to
the data interface 17. The reader 10 may further send information
regarding the status of the reader 10 to the data interface 17. The
data interface 17 may provide configuration information to the
reader 10. For example, the data interface 17 may provide
information regarding schedules and intervals for sampling the
sensor 12.
[0022] The data interface 17 may communicate with a remote data
system 18 to exchange status and control signals, as well as
provide sensor data. The remote data system 18 may include a data
gathering module 19 to receive data from the data interface 17, a
data logging module 20 to store the received data, and a data
display 21 to display the sensor data.
[0023] The reader 10 includes circuitry to send the excitation
pulse 14, receive the ring signal 16, and process the ring signal
16. (FIG. 2.) For example, the reader 10 includes a timing and
control circuitry 22 to configure and activate the other circuits
in the reader 10. The solid arrows between the timing and control
circuitry 22 represent the control interfaces, such as digital or
low-frequency signals. The timing and control circuitry 22 further
generates an RF signal (illustrated as the broken line arrow) that
is sent to a transmit circuitry 24. The transmit circuitry 24
receives the RF signal and sends out the excitation pulse 14 to
excite the sensor 12. The timing and control circuitry 22 may only
provide the RF signal to the transmit circuitry 24 during the
intervals when the excitation pulse is being transmitted to prevent
leakage or coupling.
[0024] The reader 10 further includes an antenna 26 connected to
the transmit circuitry 24 and a receive circuitry 28. The transmit
circuitry 24 utilizes the antenna 26 for transmitting the
excitation pulse 14, while the receive circuitry 28 utilizes the
antenna 26 for receiving the ring signal 16. In an embodiment, the
antenna 26 is connected to both the transmit circuitry 24 and the
receive circuitry 28 at all times instead of being switched between
transmit and receive. This shared antenna 26 design requires
special consideration to prevent damage to the receive circuitry
28. Specifically, care must be taken not to overload the very
sensitive amplifier stages of the receive circuitry 28.
Additionally, the reader 10 requires a fast transition between the
extreme overdrive condition present while the transmit circuitry 24
is driving the antenna 26 and the low voltage condition present at
the antenna 26 during the receive and amplify phases. For instance,
the voltage at the antenna 26 may exceed 200 volts peak-to-peak
during transmission of the excitation pulse, and may be
single-digit millivolts, decaying rapidly to micro-volts, during
reception immediately following the excitation pulse 14. While the
reader 10 is described as having a shared antenna 26, it will be
appreciated that the reader 10 may incorporate more than one
antenna to separately perform the functions of transmitting the
excitation pulse 14 and receiving the ring signal 16.
[0025] The reader 10 further includes a PLL 30 to receive and lock
onto the ring signal 16. The receive circuitry 28 may amplify and
condition the ring signal 16 before sending it to the PLL 30. The
PLL 30 includes a voltage controlled oscillator ("VCO") 32 that
operates at a frequency higher than the ring signal 16 frequency.
The VCO 32 interfaces with a frequency counter 34 which counts the
VCO 32 frequency, and provides the count to a external interface
circuitry 36 for transfer to the data interface 17. By operating
the VCO 32 at a higher frequency than the ring signal 16, the time
required to count and record the VCO 32 frequency may be
significantly decreased.
[0026] Each component of the reader 10 is designed to operate
efficiently and reduce power consumption. To that end, the reader
10 includes a reduced power mode to conserve power. The timing and
control circuitry 22 controls the power status of each component by
way of a wakeup timer 38 connected to each component. (FIG. 3.) In
reduced power mode, some components may be completely powered down
while other components may operate in a sleep mode where power
remains to maintain configuration but the circuit becomes static to
minimize power consumption.
[0027] The timing and control circuitry 22 may place each component
of the reader 10 in a sleep or powered-down mode after a specified
period of inactivity, such as a few milliseconds when the reader 10
is not sampling the sensor 12. However, it will be appreciated that
the specified period of time before entering into reduced power
mode may be adjustable. For example, the timing and control
circuitry 22 may include a configuration buffer 40 that receives
timing instructions from the external interface circuitry 36. The
instructions establish the timing period before entering into
reduced power mode, and other timing periods for the wakeup timer
38.
[0028] The wakeup timer 38 may wake up each component of the reader
10 at the appropriate time to ensure that each component is in an
operational state when needed. Specifically, the wakeup timer 38
may communicate with a transmit timer 42, a receive timer 46, a PLL
timer 48, and a frequency counter timer 50 to wake up and control
the respective components of the reader 10. Once initiated, each of
these timers may control and power up the respective component.
When configured, the wakeup timer 38 may delay for a specified
interval, which may be zero seconds, before sending an initiate
signal 52 to start the other timers. As illustrated in FIG. 3, the
initiate signal 52 is not shown as a continuous line from the
wakeup timer 38 to the respective timers in order to prevent line
crossings and minimize confusion.
[0029] Once initiated, the transmit timer 42 establishes proper
sequence and period to the power control 54, damp control 56, Q
control 58, and RF enable 60 signals to properly sequence the
transmit circuitry 24 and transmit frequency generator 44. The
power control signal 54 controls the power status and sleep status
of the transmit circuitry 24. The damp control signal 56 controls
the activation of a damping circuit in the transmit circuitry 24 to
quickly dissipate antenna 26 energy at the end of a transmission
period. The Q control signal 58 controls a switching circuit in the
transmit circuitry 24 to reduce the Q of the antenna 26 during
reception of the ring signal 16. The RF enable signal allows the
transmit frequency generator 44 to send an RF signal to the
transmit circuitry 24. In an embodiment, the transmit frequency
generator 44 only provides the RF signal to the transmit circuitry
24 during periods where the transmit circuitry 24 is transmitting
an excitation pulse 14.
[0030] The receive timer 46 is configured to establish proper
sequence and period to the power control signal 62 to properly
sequence the receive circuitry 28.
[0031] The PLL timer 48 establishes proper sequence and period to
the power control 64 and S/H mode 66 signals to properly sequence
the PLL 30. The power control signal 64 controls the power status
and sleep status of the PLL 30. The S/H mode signal 66 controls a
sample and hold circuit in the PLL 30, used to cause the PLL to
lock onto the transmitted frequency then onto the ring signal 16
frequency, then hold the VCO 32 frequency at the locked frequency
until counting is complete.
[0032] The frequency counter timer 50 establishes proper sequence
and count interval to the power control 68 and start/stop count 70
signals to properly sequence the frequency counter 34. The power
control signal 68 controls the power status and sleep status of the
frequency counter 34. The start/stop count signal 70 controls the
time that the frequency counter 34 begins and ends counting the VCO
32 frequency.
[0033] The transmit circuitry 24 is configured to transmit the
excitation pulse 14 to the sensor 12 by way of the antenna 26.
(FIG. 4.) The excitation pulse 14 may be a fixed or rapidly varying
frequency burst at or near the resonant frequency of the sensor 12.
For example, the excitation pulse 14 may be a fixed frequency burst
within several bandwidths of the sensor 12 resonant frequency.
Alternatively, the excitation pulse 14 may be a fixed or rapidly
varying frequency burst or sweep of a very short duration at or
near a frequency harmonically related to the sensor 12 resonant
frequency. The excitation pulse 14 may also be an ultra-wide band
pulse. This plurality of excitation pulse 14 approaches is
effective because the ring signal 16 is received when the
excitation pulse 14 transmissions have ceased. Therefore,
excitation pulse 14 transmissions may be limited to frequency
bands, amplitudes, and modulation schemes acceptable to regulatory
government bodies. Radio frequency regulations generally may not
apply to the sensor 12 as the sensor 12 is a purely passive
device.
[0034] The excitation pulse 14 does not require significant
transmission time because a single short transmission of energy
results in a single and complete sample of the ring signal 16.
Power consumption may be reduced by using a lower transmission duty
cycle, thereby reducing the duty cycle of transmit, receive,
counting, and digital processing circuitry. By reducing power
consumption battery power becomes a much more viable option to
power the system.
[0035] The excitation pulse 14 may be configured to maximize
several system parameters. For example, if a fixed frequency
excitation pulse 14 is used, the frequency of the burst may be
configured to maximize parameters such as maximum allowable
transmit peak power, maximum freedom from in-band or near-band
interference during the "receive" interval while the PLL is being
locked to the ring signal 16, maximum worldwide acceptance of a
particular frequency for reader transmissions for the desired
sensor purpose, or other such criteria.
[0036] A level shifter 72 of the transmit circuitry 24 receives
control signals 54, 56, 58 and the RF signal 60 from the timing and
control circuitry 22. The level shifter 72 buffers the inputs and
convert control logic levels to circuit drive levels. A transmit
driver 74 amplifies the RF signal 60 to provide sufficient power to
drive the antenna 26. The Q control circuit 76 is activated during
receive to reduce the Q of the combined antenna 26 and tuning and
D.C. block 82. A damping circuit 78 is briefly activated
immediately at the end of transmission of the excitation pulse 14
to absorb energy in the antenna and allow the antenna to respond to
the ring signal 16. The damping circuit 78 may provide a different
Q factor to the antenna to improve reception of the ring signal 16.
The power control circuitry 80 controls the power-on and sleep mode
for components in the transmit circuitry 24. The tuning and D.C.
block 82 adjusts tuning for the antenna 26 and prevents direct
current from improperly biasing the damping circuit 78. The RF
output or excitation pulse 14 from the transmit circuitry is routed
to both the antenna 26 and the receive circuitry 28.
[0037] Once the excitation pulse 14 is transmitted by the transmit
circuitry 24, the receive circuitry 28 is configured to listen for
the ring signal 16. With reference to FIG. 5, a high Z buffer/clamp
84 includes a high impedance ("high Z") input device that limits
the effect of the receive circuitry 28 on the tuning performed by
the tuning and D.C. block 82. The high Z buffer/clamp 84 further
serves to protect the amplifier stages 86 from the extreme voltages
present on the antenna 26 during transmission of the excitation
pulse 14. Voltages at the antenna 26 may reach upwards of 200 volts
peak-to-peak during transmission of the excitation pulse, requiring
only approximately 60 pico-farads of capacitance to tune the
antenna 26. In an embodiment, a 1 pico-farad capacitor is used as a
high impedance input current limiting device on a 13.5 mega-hertz
transmit circuit. Low capacitance diode junctions that shunt
over-voltage to the power supply and under-voltage to ground may be
used as clamping devices.
[0038] The amplifier stages 86 amplify the ring signal 16 to a
sufficient level to drive the PLL 30 input. Careful design of the
amplifier stages 86 is required to achieve adequate transient
response when the transmitted excitation pulse 14 signal is removed
and damped, and the low level ring signal 16 is received. Common
gate amplifier stages with low Q tuned reactive drain loads may be
used to condition the high Z buffer/clamp 84 output, followed by
several filters interspersed between high gain amplifier stages.
The filters may be either resistor-capacitor ("RC") filters or
inductor-capacitor ("LC") filters. In an embodiment, the filters
may all be RC bandpass filters. Another common gate amplifier stage
with low Q tuned reactive drain load may be used for final bandpass
conditioning prior to feeding the signal to the PLL 30 input. This
design enables all of these amplifier types to perform from
extremely low signal input levels to extremely high signal input
levels without signal distortion such as frequency doubling or
halving due to stage saturation characteristics, as well as the
excellent high input impedance achievable with the common-gate
amplifier stages and the outstanding transient response
characteristics of the RC filter interspersed between high gain
amplifier stages. Special care must be taken in stage-to-stage
power and signal isolation to prevent unwanted oscillations due to
the extreme gain associated with the amplifier stages 86.
[0039] Power control circuitry 88 may apply and remove power to and
from the amplifier stages 86 and the buffer in the high Z
buffer/clamp 84 to reduce power consumption. It should be noted
that the high Z buffer/clamp 84 is designed to provide full
protection even with power removed as excess energy will merely
power up the amplifier stages 86 until dissipated. The input
impedance is high enough to limit excess energy to prevent
overpowering the amplifier stages 86. In an embodiment, the receive
circuitry 28 is active during the transmission of the excitation
pulse 14 to decrease the time required for the PLL 30 to lock onto
the ring signal 16.
[0040] The PLL 30 receives the amplified and conditioned ring
signal 16 from the receive circuitry 28. With reference to FIGS. 5
and 6, the RF signal from the receive circuitry 28 amplifier stages
86 feeds an RF buffer 90 of the PLL 30. The RF buffer 90 may feed
the RF signal to an optional RF divider 92 that divides the RF
signal frequency by an integer value. (FIG. 6.) The RF divider 92
then feeds the RF signal to a first input of a phase frequency
detector 94. The output of the frequency detector 94 feeds a
sample-and-hold (S/H) error amplifier 96. The S/H error amplifier
96 controls the frequency of the VCO 32. The output of the VCO 32
feeds the VCO divider 98, which output in turn feeds a second input
to the phase frequency detector 94. The PLL 30 may include an
output buffer 102 to reduce loading of the VCO 32 while forwarding
the VCO signal frequency to the frequency counter 34. The VCO
divider 98 allows the VCO 32 to operate at a frequency
significantly higher than the ring frequency 16. As a result, the
time required to count and record the VCO signal frequency may be
significantly reduced. Moreover, the shorter count interval reduces
VCO drift during counting and allows a higher sample rate.
[0041] The phase frequency detector 94 is configured to determine
the frequency and phase error between the divided RF signal and the
divided VCO signal. This is best accomplished by filtering and
amplifying the RF signal that is fed to the S/H error amplifier 96.
Further, the S/H feature may optimally forward the filtered and
amplified signal to control the VCO 32. In this manner, a closed
control loop is formed that causes the VCO 32 frequency to equal to
the ring signal 16 frequency times the VCO divider 98 integer
divided by the RF divider 92 integer. The PLL 30 may include
additional frequency dividers to optimize the circuit design and
increase the potential VCO 32 frequency range.
[0042] The PLL timer 48 sends a S/H mode control signal 66 to the
S/H error amplifier 96 of the PLL 30. The S/H mode control signal
66 may place the VCO 32 in a sample mode. In an embodiment, the VCO
32 is placed in sample mode for a predetermined length of time. In
sample mode, the VCO signal frequency is adjusted to match the ring
signal frequency, as described above. When the S/H mode control
signal 66 is placed in the hold mode, the S/H error amplifier 96
will hold its output constant, causing the control voltage to the
VCO 32 to be approximately constant over a length of time
sufficient to count the VCO signal frequency.
[0043] The power control signal from the PLL timer 48 to the power
control circuitry 104 determines whether the PLL 30 is in a power
on or a sleep/power-off mode to conserve electrical power.
Depending on the specific PLL that is used, a control and
communication link (not shown) may be required to set the RF
divider 92 integer, the VCO divider 98 integer, and the phase
frequency detector 94 outputs and output configurations. The
communications link may be specific to the particular PLL 30
used.
[0044] The frequency counter 34 includes counter stages 106, a
counter buffer 108, and a power control circuitry 110. The
frequency counter timer 50 sends a start/stop control input to the
counter stages 106 and counter buffer 108. The frequency counter
timer 50 also sends a power control input to the power control
circuitry 110. The counter stages 106 count the VCO signal
frequency from the PLL 30 output buffer 102. The counter stages 106
start counting when the start/stop control commands start, and end
when the start/stop control commands stop. When the start/stop
control commands stop, the counter buffer 108 is loaded with the
count value from the counter stages 106. The power control
circuitry 110 controls the power-on and sleep modes for components
in the frequency counter 34. The counter buffer 108 output may
supply a count input to the external interface circuitry 36. The
ring frequency 16, and subsequently the sensed parameter, may be
determined from the frequency count.
[0045] In operation, the reader 10 sequences as follows. During
periods of time when the sensor 12 is not being sampled, all
components of the reader 10 are placed in reduced power mode. The
wakeup timer 38 in the timing and control circuitry 22 is
configured for a particular sample delay or sample interval. At the
specified time, the wakeup timer 38 initiates a sample sequence.
Specifically, the wakeup timer 38 powers up or wakes up each
component of the reader at appropriate times to ensure each
component is in an operational state when needed.
[0046] The external interface circuitry 36 consumes minimal power
when not actively communicating so is maintained in a ready
condition at all times. The timing and control circuitry 22
provides the RF signal to the transmit circuitry 24 for a short
period of time, such as approximately 20 microseconds. The RF
signal from the timing and control circuitry 22 is then secured and
the transmit circuitry 24 is controlled to damp the antenna 26
quickly. The transmit circuitry 24 is then placed in an appropriate
mode to allow reception of the ring signal 16 at the antenna 26. In
an embodiment, when the antenna 26 is configured to receive the
ring signal 16, the antenna 26 damping is greater than the ring
signal 16 damping.
[0047] During transmission of the excitation pulse 14, the receive
circuitry 28 receives, conditions, and clamps the transmitted RF
signal at the antenna 26. Once transmission of the excitation pulse
14 ceases and the antenna 26 is configured to receive the ring
signal 16, the receive circuitry transitions into a high-gain
reception mode to receive the ring signal 16 from the antenna 26.
The PLL 30 is in sample mode to allow the RF buffer 90 to receive
the conditioned output of the receive circuitry 28. When the
antenna 26 begins to receive the ring signal 16, the PLL 30 shifts
from locking onto the transmitted excitation pulse 14 frequency to
locking onto the ring signal 16 frequency. After a time interval
sufficient for the PLL 30 to lock onto the ring signal 16
frequency, the PLL 30 is shifted to hold mode to maintain VCO 32
frequency at ring signal 16 frequency. The receive circuitry 28 and
transmit circuitry 24 are powered down or placed in sleep mode as
appropriate.
[0048] Once the PLL 30 is in hold mode, the timing and control
circuitry 22 instructs the frequency counter 34 to conduct a
controlled interval count of the VCO 32 frequency. Upon completion
of the count, the PLL 30 components are powered down or placed in
sleep mode as appropriate and the count value is transferred to the
external interface circuitry 36. The frequency counter 34
components are then powered down or placed in sleep mode as
appropriate, and subsequently the timing and control circuitry 22
components are powered down or placed in sleep mode as appropriate.
If programmed for interval sampling, the timing and control
circuitry 22 wakeup timer 38 counts until the next sample is due.
Otherwise, the timing and control circuitry 22 awaits a wakeup
command with any other needed instructions from the external
interface circuitry 36.
[0049] The embodiment of the invention has been described above
and, obviously, modifications and alternations will occur to others
upon reading and understanding this specification. The claims as
follows are intended to include all modifications and alterations
insofar as they are within the scope of the claims or the
equivalent thereof.
* * * * *