U.S. patent application number 15/485552 was filed with the patent office on 2017-10-19 for pattern based estimation of errors in adc.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to Visvesvaraya Pentakota Appala, Shagun Dusad, Roswald Francis, Viswanathan Nagarajan, Sai Aditya Nurani, Srinivas Kumar Reddy Naru, Neeraj Shrivastava, Rishi Soundararajan, Ani Xavier.
Application Number | 20170302287 15/485552 |
Document ID | / |
Family ID | 60039582 |
Filed Date | 2017-10-19 |
United States Patent
Application |
20170302287 |
Kind Code |
A1 |
Reddy Naru; Srinivas Kumar ;
et al. |
October 19, 2017 |
PATTERN BASED ESTIMATION OF ERRORS IN ADC
Abstract
The disclosure provides an analog to digital converter (ADC).
The ADC includes a flash ADC. The flash ADC generates a flash
output in response to an input signal, and an error correction
block generates a known pattern. A selector block is coupled to the
flash ADC and the error correction block, and generates a plurality
of selected signals in response to the flash output and the known
pattern. A digital to analog converter (DAC) is coupled to the
selector block, and generates a coarse analog signal in response to
the plurality of selected signals. A residue amplifier is coupled
to the DAC, and generates a residual analog signal in response to
the coarse analog signal, the input signal and an analog PRBS
(pseudo random binary sequence) signal. A residual ADC generates a
residual code in response to the residual analog signal.
Inventors: |
Reddy Naru; Srinivas Kumar;
(Markapur, IN) ; Appala; Visvesvaraya Pentakota;
(Bangalore, IN) ; Dusad; Shagun; (Bangalore,
IN) ; Shrivastava; Neeraj; (Bangalore, IN) ;
Nagarajan; Viswanathan; (Bangalore, IN) ; Xavier;
Ani; (Bangalore, IN) ; Soundararajan; Rishi;
(Bangalore, IN) ; Nurani; Sai Aditya; (Bangalore,
IN) ; Francis; Roswald; (Bangalore, IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
60039582 |
Appl. No.: |
15/485552 |
Filed: |
April 12, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03M 1/164 20130101;
H03M 1/361 20130101; H03M 1/1038 20130101; H03M 1/1205 20130101;
H03M 1/06 20130101; H03M 1/109 20130101 |
International
Class: |
H03M 1/06 20060101
H03M001/06; H03M 1/12 20060101 H03M001/12 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 19, 2016 |
IN |
201641013525 |
Claims
1. An analog to digital converter (ADC) comprising: a flash ADC
configured to generate a flash output in response to an input
signal; an error correction block configured to generate a known
pattern; a selector block coupled to the flash ADC and the error
correction block, and configured to generate a plurality of
selected signals in response to the flash output and the known
pattern; a digital to analog converter (DAC) coupled to the
selector block, and configured to generate a coarse analog signal
in response to the plurality of selected signals; a residue
amplifier coupled to the DAC, and configured to generate a residual
analog signal in response to the coarse analog signal, the input
signal and an analog PRBS (pseudo random binary sequence) signal;
and a residual ADC configured to generate a residual code in
response to the residual analog signal.
2. The ADC of claim 1 further comprising: a secondary multiplexer
coupled to the error correction block and configured to generate a
digital PRBS signal in response to the known pattern, a coarse PRBS
signal and a secondary control signal, wherein the error correction
block is configured to provide the coarse PRBS signal and the
secondary control signal to the secondary multiplexer; and a
secondary DAC element coupled to the secondary multiplexer, and
configured to generate the analog PRBS signal in response to the
digital PRBS signal.
3. The ADC of claim 1, wherein the residual code is averaged over T
cycles to measure an averaged code generated by the ADC, where T is
an integer.
4. The ADC of claim 1, wherein: the selector block is configured to
receive a plurality of control signals from the error correction
block; and the error correction block is configured to receive the
flash output and the residual code.
5. The ADC of claim 1, wherein: the selector comprises a plurality
of primary multiplexers, and each primary multiplexer is configured
to generate a selected signal of the plurality of selected signals
in response to the known pattern, the flash output and a control
signal of the plurality of control signals; and the DAC comprises a
plurality of primary DAC elements, and each of the primary DAC
element is configured to receive the selected signal.
6. The ADC of claim 1, wherein the ADC is configured to operate in
a startup mode and a steady-state mode, wherein in the startup mode
the error correction block is configured to measure a coarse gain
error, a fine gain error, a PRBS error, a memory error and a DAC
mismatch error, and the error correction block is configured to
generate a corrected PRBS design value based on the coarse gain
error, the fine gain error, the PRBS error, the memory error and
the DAC mismatch error, and wherein the error correction block is
configured to use the corrected PRBS design value in the
steady-state mode to measure the input signal.
7. The ADC of claim 6, wherein the error correction block is
configured to provide the known pattern to a primary DAC element of
the plurality of primary DAC elements, and the flash ADC is
configured to provide a predefined set of bits to the remaining
primary DAC elements.
8. The ADC of claim 7, wherein the error correction block is
configured to measure the coarse gain error from the averaged code
generated by the ADC, a step size of the DAC and a reference
averaged code.
9. The ADC of claim 6, wherein the error correction block is
configured to provide the known pattern to each primary DAC element
over M loops, where M is an integer and M is equal to a number of
primary DAC elements, and in each loop of M loops: the error
correction block configured to provide the known pattern to a
primary DAC element of the plurality of primary DAC elements; the
flash ADC configured to provide the predefined set of bits to the
remaining primary DAC elements; and the error correction block
configured to measure the averaged code generated by the ADC.
10. The ADC of claim 9, wherein the error correction block is
configured to measure the fine gain error from the averaged code
generated by the ADC in each loop of the M loops, the step size of
the DAC and the reference averaged code.
11. The ADC of claim 10, wherein the error correction block is
configured to measure a mismatch of a first primary DAC element of
the plurality of primary DAC elements from the coarse gain error,
the fine gain error, the step size of the DAC and the averaged code
generated by the ADC in a first loop of M loops, wherein the known
pattern is provided to the first DAC element in the first loop.
12. The ADC of claim 6, wherein the error correction block is
configured to provide the known pattern to the secondary
multiplexer, and the digital PRBS signal is equal to known pattern,
and the error correction block is configured to measure the
averaged code generated by the ADC.
13. The ADC of claim 12, wherein the error correction block is
configured to measure the PRBS error from the averaged code
generated by the ADC, the fine gain error, the coarse gain error,
the reference averaged code and a magnitude of the coarse PRBS
signal.
14. The ADC of claim 6, wherein the error correction block is
configured to provide the known pattern to a primary DAC element of
the plurality of primary DAC elements, and the flash ADC is
configured to provide the predefined set of bits to the remaining
primary DAC elements, and the error correction block is configured
to measure a sub-averaged code generated by the ADC, the
sub-averaged code is average of residual code generated when
consecutive bits in the known pattern undergo a state transition
over T cycles.
15. The ADC of claim 14, wherein the error correction block is
configured to measure the memory error from the sub-averaged code
generated by the ADC, the step size of the DAC, the coarse gain
error, the fine gain error and the reference averaged code.
16. A method of converting an input signal in an analog to digital
converter (ADC) comprising: generating a flash output in response
to the input signal; generating a known pattern by an error
correction block; generating a plurality of selected signals in
response to the flash output and the known pattern; generating a
coarse analog signal by a digital to analog converter (DAC) in
response to the plurality of selected signals; generating a
residual analog signal in response to the coarse analog signal, the
input signal and an analog PRBS (pseudo random binary sequence)
signal; generating a residual code in response to the residual
analog signal; and averaging the residual code over T cycles to
generate an averaged code, where T is an integer.
17. The method of claim 16 further comprising: multiplexing the
known pattern and a coarse PRBS signal to generate a digital PRBS
signal; and generating the analog PRBS signal in response to the
digital PRBS signal.
18. The method of claim 16, wherein the DAC comprises a plurality
of primary DAC elements, and each of the primary DAC element is
configured to receive a selected signal of the plurality of
selected signals.
19. The method of claim 16 further comprising operating the ADC in
a startup mode and a steady-state mode, wherein the startup mode
comprises: measuring a coarse gain error, a fine gain error, a PRBS
error, a memory error and a DAC mismatch error; and generating a
corrected PRBS design value based on the coarse gain error, the
fine gain error, the PRBS error, the memory error and the DAC
mismatch error.
20. The method of claim 19 further comprising: providing the known
pattern to a primary DAC element of the plurality of primary DAC
elements; providing a predefined set of bits to the remaining
primary DAC elements; measuring the averaged code generated by the
ADC; and measuring the coarse gain error from the averaged code
generated by the ADC, a step size of the DAC and a reference
averaged code.
21. The method of claim 19 further comprising: operating the ADC in
M loops, where M is an integer and M is equal to a number of DAC
elements; providing the known pattern to a primary DAC element of
the plurality of primary DAC elements in each loop of M loops;
providing the predefined set of bits to the remaining primary DAC
elements in each loop; measuring the averaged code generated by the
ADC in each loop; and measuring the fine gain error from the
averaged code generated by the ADC in each loop of the M loops, the
step size of the DAC and the reference averaged code
22. The method of claim 21 further comprising measuring a mismatch
of a first DAC element of the plurality of DAC elements from the
coarse gain error, the fine gain error, the step size of the DAC
and the averaged code generated by the ADC in a first loop of M
loops, wherein the known pattern is provided to the first DAC
element in the first loop.
23. The method of claim 19 further comprising: providing the known
pattern as the digital PRBS signal; generating the analog PRBS
signal from the digital PRBS signal; measuring the averaged code
generated by the ADC; and measuring the PRBS error from the
averaged code generated by the ADC, the fine gain error, the coarse
gain error, the reference averaged code and a magnitude of the
coarse PRBS signal.
24. The method of claim 19 further comprising: providing the known
pattern to a primary DAC element of the plurality of primary DAC
elements; providing the predefined set of bits to the remaining
primary DAC elements; measuring a sub-averaged code generated by
the ADC, the sub-averaged code is average of residual code
generated when consecutive bits in the known pattern undergo a
state transition over T cycles; and measuring the memory error from
the sub-averaged code generated by the ADC, the step size of the
DAC, the coarse gain error, the fine gain error and the reference
averaged code.
25. A computing device comprising: a processing unit; a memory
module coupled to the processing unit; and a plurality of logic
units coupled to the processing unit and the memory module, at
least one logic unit of the plurality of logic units comprising an
ADC, the ADC comprising: a flash ADC configured to generate a flash
output in response to an input signal; an error correction block
configured to generate a known pattern; a selector block coupled to
the flash ADC and the error correction block, and configured to
generate a plurality of selected signals in response to the flash
output and the known pattern; a digital to analog converter (DAC)
coupled to the selector block, and configured to generate a coarse
analog signal in response to the plurality of selected signals; a
residue amplifier coupled to the DAC, and configured to generate a
residual analog signal in response to the coarse analog signal, the
input signal and an analog PRBS (pseudo random binary sequence)
signal; and a residual ADC configured to generate a residual code
in response to the residual analog signal.
Description
CROSS REFERENCES TO RELATED APPLICATIONS
[0001] This application claims priority from India provisional
patent application No. 201641013525 filed on Apr. 19, 2016 which is
hereby incorporated by reference in its entirety.
TECHNICAL FIELD
[0002] The present disclosure is generally related to analog to
digital converters (ADCs), and more particularly to pattern based
estimation of errors in the ADC.
BACKGROUND
[0003] Wireless base stations are changing from conventional radio
frequency (RF) signal chains to RF sampling ADC, thus avoiding use
of multiple components such as mixers and filters. RF sampling ADC
enables majority of signal processing in digital domain instead of
utilizing expensive analog signal chains. RF sampling ADC also
enables complete spectral sampling and multi-band support.
[0004] An RF sampling ADC that supports a sampling rate of the
order of giga-sample-per-second (GSPS) requires multiple pipelined
ADCs. To minimize the power consumption of RF sampling ADC, residue
amplifiers are shared between a set of interleaved channels of
pipelined ADCs. A residue amplifier is an open loop amplifier, and
a hold time of the residue amplifier for each interleaved channel
is of the order of 300 ps with no reset phase. This results in
significant settling and memory errors.
[0005] Due to open loop amplifier structure of the residue
amplifier, an amplifier gain is different from an ideal value. The
error in amplifier gain, settling errors and memory errors vary
across devices and across temperature. These errors result in
degradation of RF sampling ADC performance.
SUMMARY
[0006] According to an aspect of the disclosure, an analog to
digital converter (ADC) is disclosed. The ADC includes a flash ADC.
The flash ADC generates a flash output in response to an input
signal, and an error correction block generates a known pattern. A
selector block is coupled to the flash ADC and the error correction
block, and generates a plurality of selected signals in response to
the flash output and the known pattern. A digital to analog
converter (DAC) is coupled to the selector block, and generates a
coarse analog signal in response to the plurality of selected
signals. A residue amplifier is coupled to the DAC, and generates a
residual analog signal in response to the coarse analog signal, the
input signal and an analog PRBS (pseudo random binary sequence)
signal. A residual ADC generates a residual code in response to the
residual analog signal.
BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS
[0007] FIG. 1 illustrates an analog to digital converter (ADC),
according to an embodiment;
[0008] FIG. 2 is a flowchart to illustrate a method of converting
an input signal in an analog to digital converter (ADC), according
to an embodiment;
[0009] FIG. 3 illustrates a timing diagram of an ADC, according to
an embodiment; and
[0010] FIG. 4 illustrates a computing device, according to an
embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0011] FIG. 1 illustrates an analog to digital converter (ADC) 100,
according to an embodiment. In one example, the ADC is a pipeline
ADC. The ADC 100 includes a flash ADC 106, an error correction
block 110, a selector block 116, a digital to analog converter
(DAC) 130, a residue amplifier 150, and a residual ADC 158. The ADC
100 also includes a secondary multiplexer 140 and a secondary DAC
element 146. The flash ADC 106 receives an input signal 102. The
selector block 116 is coupled to the flash ADC 106 and the error
correction block 110. The DAC 130 is coupled to the selector block
116.
[0012] The residue amplifier 150 is coupled to the DAC 130 and the
secondary DAC element 146. The residual ADC 158 is coupled to the
residue amplifier 150. The error correction block 110 is coupled to
the residual ADC 158 and the flash ADC 106. The secondary
multiplexer 140 is coupled to the error correction block 110, and
the secondary DAC element 146 is coupled between the secondary
multiplexer 140 and the residue amplifier 150. The selector block
116 includes a plurality of primary multiplexers illustrated as
118A, 118B to 118N. The selector block 116 receives a plurality of
control signals illustrated as C1 122A, C2 122B to CN 122N.
[0013] Each primary multiplexer receives a control signal from the
error correction block 110. For example, the primary multiplexer
118A receives the control signal C1 122A, and the primary
multiplexer 118N receives the control signal CN 122N. The DAC 130
includes a plurality of primary DAC elements illustrated as primary
DAC element 1 132A, primary DAC element 2 132B to primary DAC
element N 13N2N. The ADC 100 may include one or more additional
components known to those skilled in the relevant art and are not
discussed here for simplicity of the description.
[0014] The operation of the ADC 100 illustrated in FIG. 1 is
explained now. The flash ADC 106 generates a flash output 112 in
response to the input signal 102. The error correction block 110
generates a known pattern 120. The selector block 116 generates a
plurality of selected signals 124A, 124B to 124N in response to the
flash output 112 and the known pattern 120. Each primary
multiplexer of the plurality of primary multiplexers 118A to 118N
generates a selected signal in response to the known pattern 120,
the flash output 112 and a control signal. For example, the primary
multiplexer 118A generates the selected signal 124A in response to
the flash output 112, the known pattern 120 and the control signal
C1 122A.
[0015] The known pattern 120 is a predefined set of bits. In one
example, the known pattern 120 is defined as per the specification
of a device using the ADC 100. In another example, the known
pattern 120 is pre-programmed by a chip manufacturer. The DAC 130
generates a coarse analog signal 136 in response to the plurality
of selected signals 124A to 124N received from the selector block
116. Each primary DAC element in the DAC 130 receives a selected
signal. For example, the primary DAC element 1 132A receives the
selected signal 124A, and the primary DAC element N 132N receives
the selected signal 124N.
[0016] The secondary multiplexer 140 generates a digital PRBS
(pseudo random binary sequence) signal 144 in response to the known
pattern 120, a coarse PRBS signal 138 and a secondary control
signal 142. The secondary multiplexer 140 receives the coarse PRBS
signal 138 and the secondary control signal 142 from the error
correction block 110. The secondary DAC element 146 generates an
analog PRBS signal 148 in response to the digital PRBS signal 144.
The residue amplifier 150 generates a residual analog signal 154 in
response to the coarse analog signal 136, the input signal 102 and
the analog PRBS signal 148.
[0017] The residual ADC 158 generates a residual code 160 in
response to the residual analog signal 154 received from the
residue amplifier 150. The residual code 160 is averaged over T
cycles to measure an averaged code generated by the ADC 100. T is
an integer. The error correction block 110 receives the flash
output 112 and the residual code 160.
[0018] The ADC 100 operates in a startup mode and a steady-state
mode. In the startup mode, the error correction block 110 measures
a coarse gain error, a fine gain error, a PRBS error, a memory
error and a DAC mismatch error. The coarse gain error and the fine
gain error are associated with the residue amplifier 150. The PRBS
error is associated with the secondary DAC element 146. The memory
error is associated with the residue amplifier 150, and the DAC
mismatch error is associated with each primary DAC element in the
DAC 130.
[0019] The error correction block 110 generates a corrected PRBS
design value based on the coarse gain error, the fine gain error,
the PRBS error, the memory error and the DAC mismatch error. The
error correction block 110 use the corrected PRBS design value in
the steady-state to measure the input signal 102.
[0020] The measurement of coarse gain error by the error correction
block 110 is discussed now. The error correction block 110 provides
the known pattern 120 to a primary DAC element in the DAC 130, and
the flash ADC 106 provides a predefined set of bits to the
remaining primary DAC elements in the DAC 130. For example, the
error correction block 110 provides the control signal C1 122A to
the primary multiplexer 118A such that it generates the known
pattern 120 which is received by the primary DAC element 1 132A.
The error correction block 110 also provides the control signals to
the remaining primary multiplexers such that they generate the
predefined set of bits provided by the flash ADC 106. These
predefined set of bits are received by the remaining primary DAC
elements 132B to 132N.
[0021] The predefined set of bits is a set of zeroes and/or a set
of ones. In one example, the flash ADC 106 provides equivalent set
of zeroes and ones to the remaining primary DAC elements 132B to
132N. The error correction block 110 measures the hence generated
averaged code by the ADC 100. The averaged code generated by the
ADC 100 is the residual code 160 averaged over T cycles.
[0022] The error correction block 110 measures the coarse gain
error from the averaged code generated by the ADC 100, a step size
of the DAC 130 and a reference averaged code. In one example, the
reference averaged code is a design parameter known to the
designer. In another example, the reference averaged code is
predefined by a user. In one example the coarse gain error is
defined by the following equation:
G coarse_err = C actual - C ref S ( 1 ) ##EQU00001##
where, G.sub.coarse.sub._.sub.err is the coarse gain error,
C.sub.actual is the averaged code generated by the ADC 100,
C.sub.ref is the reference averaged code and S is the step size of
the DAC 130. In another example, the reference averaged code is a
function of the step size of the DAC 130 and a gain of the residue
amplifier 150.
[0023] The measurement of fine gain error by the error correction
block 110 is discussed now. The error correction block 110 provides
the known pattern 120 to each primary DAC element over M loops. M
is an integer and M is equal to a number of primary DAC elements.
In each loop, the error correction block 110 provides the known
pattern 120 to a primary DAC element, and the flash ADC 106
provides the predefined set of bits to the remaining primary DAC
elements. The error correction block 110 thereafter measures the
averaged code generated by the ADC 100 in each loop.
[0024] For example, in a first loop of M loops, the error
correction block 110 provides the known pattern 120 to the primary
DAC element 1 132A, and the flash ADC 106 provides the predefined
set of bits to the remaining primary DAC elements 132B to 132N. The
error correction block 110 measures the averaged code generated by
the ADC 100 in the first loop. In a second loop of M loops, the
error correction block 110 provides the known pattern 120 to the
primary DAC element 2 132B, and the flash ADC 106 provides the
predefined set of bits to the remaining primary DAC elements 132A
and 132C to 132N. The error correction block 110 measures the
averaged code generated by the ADC 100 in the second loop.
[0025] The error correction block 110 measures the fine gain error
from the averaged code generated by the ADC 100 in each loop of the
M loops, the step size of the DAC 130 and the reference averaged
code. In one example, the fine gain error is defined by the
following equation:
G fine _err = 1 M .SIGMA. C actual_M - C ref S ( 2 )
##EQU00002##
where, G.sub.fine.sub._.sub.err is the fine gain error,
C.sub.actual is the averaged code generated by the ADC 100 in the
Mth loop, C.sub.ref is the reference averaged code and S is the
step size of the DAC 130.
[0026] The measurement of DAC mismatch error is discussed now. The
error correction block 110 measures a mismatch associated with a
primary DAC element of the plurality of primary DAC elements in the
DAC 130. The error correction block 110 measures a mismatch of a
first primary DAC element from the coarse gain error, the fine gain
error, the step size of the DAC 130 and the averaged code generated
by the ADC 100 in a first loop of M loops. The known pattern 120 is
provided to the first DAC element in the first loop.
[0027] For example, in a first loop of M loops, the error
correction block 110 provides the known pattern 120 to the primary
DAC element 1 132A, and the flash ADC 106 provides the predefined
set of bits to the remaining primary DAC elements 132B to 132N. The
error correction block 110 measures the averaged code generated by
the ADC 100 in the first loop. The error correction block 110
measures the mismatch of the primary DAC element 1 132A from the
coarse gain error, the fine gain error, the step size of the DAC
130 and the averaged code generated by the ADC 100 in the first
loop of M loops. In one example, the coarse gain error is measured
as per equation 1, and the fine gain error is measured as per
equation 2. In one example, the DAC mismatch error is defined by
the following equation:
S mismatch = C actual_M G + G coarse_err + G fine_err - S ( 3 )
##EQU00003##
where, S.sub.mismatch is the mismatch associated with the DAC
element, G.sub.fine.sub._.sub.err is the fine gain error,
G.sub.coarse.sub._.sub.err is the coarse gain error,
C.sub.actual.sub._.sub.M is the averaged code generated by the ADC
100 in the Mth loop, G is the gain of the residue amplifier 150 and
S is the step size of the DAC 130.
[0028] The measurement of PRBS error is explained now. The error
correction block 110 provides the known pattern 120 to the
secondary multiplexer 140 and the secondary control signal 142 to
the secondary multiplexer 140. The digital PRBS signal 144
generated by the secondary multiplexer 140 is equal to the known
pattern 120. The error correction block 110 measures the averaged
code generated by the ADC 100.
[0029] The error correction block 110 measures the PRBS error from
the averaged code generated by the ADC 100, the fine gain error,
the coarse gain error, the reference averaged code and a magnitude
of the coarse PRBS signal 138. In one version, the coarse gain
error is measured as per equation 1, and the fine gain error is
measured as per equation 2. In one example, the PRBS error is
defined by the following equation:
D error = C actual G + G coarse_err + G fine_err - D ( 4 )
##EQU00004##
where, D.sub.error is the PRBS error, G.sub.fine.sub._.sub.err is
the fine gain error, G.sub.coarse.sub._.sub.err is the coarse gain
error, G is the gain of the residue amplifier 150, C.sub.actual is
the averaged code generated by the ADC 100, D is the magnitude of
the coarse PRBS signal 138.
[0030] The measurement of memory error is explained now. The error
correction block 110 provides the known pattern 120 to a primary
DAC element in the DAC 130, and the flash ADC 106 provides the
predefined set of bits to the remaining primary DAC elements in the
DAC 130. For example, the error correction block 110 provides the
control signal C1 122A to the primary multiplexer 118A such that it
generates the known pattern 120 which is received by the primary
DAC element 1 132A. The error correction block 110 also provides
the control signals to the remaining primary multiplexers such that
they generate the predefined set of bits provided by the flash ADC
106. These predefined set of bits are received by the remaining
primary DAC elements 132B to 132N.
[0031] The predefined set of bits is a set of zeroes and/or a set
of ones. In one example, the flash ADC 106 provides equivalent set
of zeroes and ones to the remaining primary DAC elements 132B to
132N. The error correction block 110 measures a sub-averaged code
generated by the ADC 100. The sub-averaged code is average of
residual code generated when consecutive bits in the known pattern
120 undergo a state transition over T cycles.
[0032] The error correction block 110 measures the memory error
from the sub-averaged code generated by the ADC 100, the step size
of the DAC 130, the coarse gain error, the fine gain error and the
reference averaged code. In one example, the reference averaged
code is a design parameter known to the designer. In another
example, the reference averaged code is predefined by a user. In
one example the memory error is defined by the following
equation:
M error = C mem_actual S ( G + G coarse_err + G fine_err ) ( 5 )
##EQU00005##
where, M.sub.error is the memory error, G.sub.coarse.sub._.sub.err
is the coarse gain error, C.sub.mem.sub._.sub.actual is the
sub-averaged code generated by the ADC 100,
G.sub.fine.sub._.sub.err is the fine gain error, G is the gain of
the residue amplifier 150 and S is the step size of the DAC 130. In
another example, the reference averaged code is a function of the
step size of the DAC 130 and a gain of the residue amplifier
150.
[0033] The error correction block 110 measures the coarse gain
error, the fine gain error, the PRBS error, the memory error and
the DAC mismatch error as described above in the startup mode. The
error correction block 110 generates the corrected PRBS design
value based on the coarse gain error, the fine gain error, the PRBS
error, the memory error and the DAC mismatch error. The error
correction block 110 use the corrected PRBS design value in the
steady-state to measure the input signal 102.
[0034] The ADC 100 provides a unique approach of measuring all the
associated errors in the startup mode, and using the results of the
startup mode to determine the input signal 102 in the steady-state
mode. Trimming of PRBS error, coarse gain error and DAC mismatch
error is not required in the ADC 100 as all these errors are
measured in the startup mode. Hence, a test time of the ADC 100 is
significantly reduced. This also results in saving of larger number
of fuses.
[0035] The time taken by the ADC 100 in startup mode is very less
as the known pattern 120 is used to determine all the associated
errors. Hence, a power up time of the ADC 100 is significantly
reduced.
[0036] FIG. 2 is a flowchart 200 to illustrate a method of
converting an input signal in an analog to digital converter (ADC),
according to an embodiment. The flowchart 200 is explained in
connection with the ADC 100. At step 202, a flash output is
generated in response to the input signal. In ADC 100, the flash
ADC 106 generates a flash output 112 in response to the input
signal 102. At step 204, a known pattern is generated by an error
correction block. The error correction block 110, in ADC 100,
generates a known pattern 120. The known pattern 120 is a
predefined set of bits. In one example, the known pattern 120 is
defined as per the specification of a device using the ADC 100. In
another example, the known pattern 120 is pre-programmed by a chip
manufacturer.
[0037] At step 206, a plurality of selected signals is generated in
response to the flash output and the known pattern. In ADC 100, the
selector block 116 generates a plurality of selected signals 124A,
124B to 124N in response to the flash output 112 and the known
pattern 120. Each primary multiplexer of the plurality of primary
multiplexers 118A to 118N generates a selected signal in response
to the known pattern 120, the flash output 112 and a control
signal. For example, the primary multiplexer 118A generates the
selected signal 124A in response to the flash output 112, the known
pattern 120 and the control signal C1 122A.
[0038] At step 208, a coarse analog signal is generated by a
digital to analog converter (DAC) in response to the plurality of
selected signals. The DAC 130, in ADC 100, generates a coarse
analog signal 136 in response to the plurality of selected signals
124A to 124N received from the selector block 116. The DAC 130
includes a plurality of primary DAC elements illustrated as primary
DAC element 1 132A, primary DAC element 2 132B to primary DAC
element N 132N. Each primary DAC element in the DAC 130 receives a
selected signal. For example, the primary DAC element 1 132A
receives the selected signal 124A, and the primary DAC element N
132N receives the selected signal 124N.
[0039] A residual analog signal is generated in response to the
coarse analog signal, the input signal and an analog PRBS (pseudo
random binary sequence) signal, at step 210. In ADC 100, the
secondary multiplexer 140 multiplexes the known pattern 120 and a
coarse PRBS signal 138 to generate a digital PRBS (pseudo random
binary sequence) signal 144. The secondary multiplexer 140 receives
a secondary control signal 142 as a selection signal from the error
correction block 110. The secondary multiplexer 140 receives the
coarse PRBS signal 138 and the known pattern 120 from the error
correction block 110. The secondary DAC element 146 generates an
analog PRBS signal 148 in response to the digital PRBS signal 144.
The residue amplifier 150 generates a residual analog signal 154 in
response to the coarse analog signal 136, the input signal 102 and
the analog PRBS signal 148.
[0040] At step 212, a residual code is generated in response to the
residual analog signal. The residual code is averaged over T cycles
to generate an averaged code, at step 214. T is an integer. In ADC
100, the residual ADC 158 generates a residual code 160 in response
to the residual analog signal 154 received from the residue
amplifier 150. The residual code 160 is averaged over T cycles to
measure an averaged code generated by the ADC 100. T is an integer.
The error correction block 110 receives the flash output 112 and
the residual code 160.
[0041] The ADC operates in a startup mode and a steady-state mode.
In the startup mode, a coarse gain error, a fine gain error, a PRBS
error, a memory error and a DAC mismatch error are measured. A
corrected PRBS design value is generated based on the coarse gain
error, the fine gain error, the PRBS error, the memory error and
the DAC mismatch error. The corrected PRBS design value is used in
the steady-state to measure the input signal.
[0042] The known pattern 120 is provided to a primary DAC element
in the DAC, and a predefined set of bits is provided to the
remaining primary DAC elements in the DAC. The predefined set of
bits is a set of zeroes and/or a set of ones. In ADC 100, the flash
ADC 106 provides equivalent set of zeroes and ones to the remaining
primary DAC elements 132B to 132N. The error correction block 110
measures the hence generated averaged code by the ADC 100. The
averaged code generated by the ADC 100 is the residual code 160
averaged over T cycles.
[0043] The coarse gain error is measured from the averaged code
generated by the ADC, a step size of the DAC and a reference
averaged code. In one example, the reference averaged code is a
design parameter known to the designer. In another example, the
reference averaged code is predefined by a user.
[0044] The measurement of fine gain error is discussed now. The
known pattern is provided to each primary DAC element over M loops.
M is an integer and M is equal to a number of primary DAC elements.
In each loop, the known pattern is provided to a primary DAC
element, and the predefined set of bits are provided to the
remaining primary DAC elements. Thereafter, the averaged code
generated by the ADC in each loop is measured. The fine gain error
is measured from the averaged code generated by the ADC in each
loop of the M loops, the step size of the DAC and the reference
averaged code.
[0045] The measurement of DAC mismatch error is discussed now. A
mismatch of a first primary DAC element is measured from the coarse
gain error, the fine gain error, the step size of the DAC and the
averaged code generated by the ADC in a first loop of M loops. The
known pattern is provided to the first DAC element in the first
loop.
[0046] The measurement of PRBS error is explained now. The known
pattern is provided as the digital PRBS signal. The analog PRBS
signal is generated from the digital PRBS signal. The averaged code
generated by the ADC is measured. The PRBS error is measured from
the averaged code generated by the ADC, the fine gain error, the
coarse gain error, the reference averaged code and a magnitude of
the coarse PRBS signal.
[0047] The measurement of memory error is explained now. The known
pattern is provided to a primary DAC element in the DAC, and the
predefined set of bits is provided to the remaining primary DAC
elements in the DAC. A sub-averaged code generated by the ADC is
measured. The sub-averaged code is average of residual code
generated when consecutive bits in the known pattern undergo a
state transition over T cycles. The memory error is measured from
the sub-averaged code generated by the ADC, the step size of the
DAC, the coarse gain error, the fine gain error and the reference
averaged code. In one example, the reference averaged code is a
design parameter known to the designer. In another example, the
reference averaged code is predefined by a user. In yet another
example, the reference averaged code is a function of the step size
of the DAC and a gain of the residue amplifier.
[0048] The ADC, described through flowchart 200, provides a unique
approach of measuring all the associated errors in the startup
mode, and using the results of the startup mode to determine the
input signal in the steady-state mode. Trimming of PRBS error,
coarse gain error and DAC mismatch error is not required in the ADC
as all these errors are measured in the startup mode. Hence, a test
time of the ADC is significantly reduced. This also results in
saving of larger number of fuses. The time taken by the ADC in
startup mode is very less as the known pattern is used to determine
all the associated errors. Hence, a power up time of the ADC is
significantly reduced.
[0049] FIG. 3 illustrates a timing diagram of an ADC, according to
an embodiment. The timing diagram is explained in connection with
the ADC 100. The figure illustrates a startup mode 302 and a
steady-state mode 304. In the startup mode 302, the ADC measures a
coarse gain error 312, a fine gain error 314, a DAC mismatch error
316, a PRBS error 318 and a memory error 320 in that order. In one
version, the ADC does not measure one or more of these errors. In
another version, the ADC measure one or more of these errors
simultaneously. In yet another version, the order followed by ADC
in measurement of these errors in predefined by a designer.
[0050] The coarse gain error, the fine gain error and the memory
error are associated with the residue amplifier 150 in ADC 100. The
PRBS error is associated with the secondary DAC element 146. The
DAC mismatch error is associated with each primary DAC element in
the DAC 130. The ADC first measures coarse gain error from an
averaged code generated by the ADC, a step size of the DAC and a
reference averaged code. The averaged code generated by the ADC 100
is the residual code 160 averaged over T cycles. In one example,
the reference averaged code is a design parameter known to the
designer.
[0051] This is followed by measurement of fine gain error by the
ADC. In ADC 100, the fine gain error is measured from the averaged
code generated by the ADC 100 in each loop of the M loops, the step
size of the DAC 130 and the reference averaged code. The ADC
measure the DAC mismatch error associated with each DAC element
after measurement of the fine gain error. A mismatch of a first
primary DAC element is measured from the coarse gain error, the
fine gain error, the step size of the DAC and the averaged code
generated by the ADC in a first loop of M loops.
[0052] The ADC measures PRBS error from the averaged code generated
by the ADC, the fine gain error, the coarse gain error, the
reference averaged code and a magnitude of the coarse PRBS signal.
The ADC measures the memory error after computing PRBS error. The
memory error is measured from the sub-averaged code generated by
the ADC, the step size of the DAC 130, the coarse gain error, the
fine gain error and the reference averaged code. A corrected PRBS
design value is generated based on the coarse gain error, the fine
gain error, the PRBS error, the memory error and the DAC mismatch
error. The corrected PRBS design value is used by the ADC in the
steady-state mode 304 to measure the input signal.
[0053] FIG. 4 illustrates a computing device 400, according to an
embodiment. The computing device 400 is, or is incorporated into, a
mobile communication device, such as a mobile phone, a personal
digital assistant, a transceiver, a personal computer, or any other
type of electronic system. The computing device 400 may include one
or more additional components known to those skilled in the
relevant art and are not discussed here for simplicity of the
description.
[0054] In some embodiments, the computing device 400 comprises a
megacell or a system-on-chip (SoC) which includes a processing unit
412 such as a CPU (Central Processing Unit), a memory module 414
(e.g., random access memory (RAM)) and a tester 410. The processing
unit 412 can be, for example, a CISC-type (Complex Instruction Set
Computer) CPU, RISC-type CPU (Reduced Instruction Set Computer), or
a digital signal processor (DSP).
[0055] The memory module 414 (which can be memory such as RAM,
flash memory, or disk storage) stores one or more software
applications 430 (e.g., embedded applications) that, when executed
by the processing unit 412, performs any suitable function
associated with the computing device 400. The tester 410 comprises
logic that supports testing and debugging of the computing device
400 executing the software applications 430.
[0056] For example, the tester 410 can be used to emulate a
defective or unavailable component(s) of the computing device 400
to allow verification of how the component(s), were it actually
present on the computing device 400, would perform in various
situations (e.g., how the component(s) would interact with the
software applications 430). In this way, the software applications
430 can be debugged in an environment which resembles
post-production operation.
[0057] The processing unit 412 typically comprises memory and logic
which store information frequently accessed from the memory module
414. The computing device 400 includes a plurality of logic units
illustrated as 420a, 420b to 420n. The plurality of logic units are
coupled to the processing unit 412 and the memory module 414. A
logic unit can be, for example, one of the following, but not
limited to, a transmitter, a receiver, and a delta sigma modulator.
At least one logic unit of the plurality of logic units includes an
analog to digital converter (ADC) 418. The ADC 418 is similar in
connection and operation to the ADC 100. The ADC 418 includes a
flash ADC, an error correction block, a selector block, a digital
to analog converter (DAC), a residue amplifier, and a residual ADC.
The ADC 418 also includes a secondary multiplexer and a secondary
DAC element.
[0058] The flash ADC generates a flash output in response to an
input signal. The error correction block generates a known pattern.
The selector block generates a plurality of selected signals in
response to the flash output and the known pattern. The known
pattern is a predefined set of bits. The DAC generates a coarse
analog signal in response to the plurality of selected signals
received from the selector block.
[0059] The secondary multiplexer generates a digital PRBS (pseudo
random binary sequence) signal in response to the known pattern, a
coarse PRBS signal and a secondary control signal. The secondary
DAC element generates an analog PRBS signal in response to the
digital PRBS signal. The residue amplifier generates a residual
analog signal in response to the coarse analog signal, the input
signal and the analog PRBS signal. The residual ADC generates a
residual code in response to the residual analog signal received
from the residue amplifier. The residual code is averaged over T
cycles to measure an averaged code generated by the ADC 418. T is
an integer.
[0060] The ADC 418 operates in a startup mode and a steady-state
mode. In the startup mode, the error correction block measures a
coarse gain error, a fine gain error, a PRBS error, a memory error
and a DAC mismatch error. The error correction block generates a
corrected PRBS design value based on the coarse gain error, the
fine gain error, the PRBS error, the memory error and the DAC
mismatch error. The error correction block use the corrected PRBS
design value in the steady-state to measure the input signal.
[0061] The ADC 418 provides a unique approach of measuring all the
associated errors in the startup mode, and using the results of the
startup mode to determine the input signal in the steady-state
mode. Trimming of PRBS error, coarse gain error and DAC mismatch
error is not required in the ADC 418 as all these errors are
measured in the startup mode. Hence, a test time of the ADC 418 is
significantly reduced. This also results in saving of larger number
of fuses. The time taken by the ADC 418 in startup mode is very
less as the known pattern is used to determine all the associated
errors. Hence, a power up time of the ADC 418 is significantly
reduced.
[0062] Modifications are possible in the described embodiments, and
other embodiments are possible, within the scope of the claims.
* * * * *