U.S. patent application number 15/353925 was filed with the patent office on 2017-10-12 for thin film transistor substrate, a display device including the same, and a method of manufacturing the same.
The applicant listed for this patent is SAMSUNG DISPLAY CO., LTD.. Invention is credited to ILJEONG LEE, Wangwoo Lee, Youngwoo Park.
Application Number | 20170294520 15/353925 |
Document ID | / |
Family ID | 59998340 |
Filed Date | 2017-10-12 |
United States Patent
Application |
20170294520 |
Kind Code |
A1 |
LEE; ILJEONG ; et
al. |
October 12, 2017 |
THIN FILM TRANSISTOR SUBSTRATE, A DISPLAY DEVICE INCLUDING THE
SAME, AND A METHOD OF MANUFACTURING THE SAME
Abstract
A thin film transistor substrate including a substrate; a
semiconductor layer disposed on the substrate, the semiconductor
layer including a channel region, and a source region and a drain
region at first and second sides of the channel region; a gate
electrode disposed on the semiconductor layer; a gate insulating
layer disposed between the gate electrode and the semiconductor
layer; and a first insulating layer disposed on the substrate, the
first insulating layer exposes the upper surface of the gate
electrode and surrounds the gate electrode.
Inventors: |
LEE; ILJEONG; (Yongin-Si,
KR) ; Park; Youngwoo; (Yongin-Si, KR) ; Lee;
Wangwoo; (Yongin-Si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG DISPLAY CO., LTD. |
Yongin-si |
|
KR |
|
|
Family ID: |
59998340 |
Appl. No.: |
15/353925 |
Filed: |
November 17, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/1255 20130101;
H01L 29/78696 20130101; H01L 29/7869 20130101; H01L 27/1259
20130101; H01L 29/401 20130101; H01L 29/66969 20130101; H01L
27/3262 20130101; H01L 27/1248 20130101; H01L 27/1225 20130101;
H01L 29/42384 20130101 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 29/40 20060101 H01L029/40; H01L 29/66 20060101
H01L029/66; H01L 29/786 20060101 H01L029/786; H01L 27/12 20060101
H01L027/12 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 12, 2016 |
KR |
10-2016-0044926 |
Claims
1. A thin film transistor substrate, comprising: a substrate; a
semiconductor layer disposed on the substrate, the semiconductor
layer comprising a channel region, and a source region and a drain
region at first and second sides of the channel region; a gate
electrode disposed on the semiconductor layer; a gate insulating
layer disposed between the gate electrode and the semiconductor
layer; and a first insulating layer disposed on the substrate,
wherein the first insulating layer exposes an upper surface of the
gate electrode and surrounds the gate electrode.
2. The thin film transistor substrate of claim 1, further
comprising: a first hole in the first insulating layer, wherein the
gate electrode is disposed within the first hole.
3. The thin film transistor substrate of claim 1, wherein the upper
surface of the gate electrode and an upper surface of the first
insulating layer meet at the same plane.
4. The thin film transistor substrate of claim 1, further
comprising: a second insulating layer disposed on the upper surface
of the gate electrode and an upper surface of the first insulating
layer.
5. The thin film transistor substrate of claim 4, further
comprising: an auxiliary electrode disposed on the second
insulating layer, wherein the auxiliary electrode contacts the gate
electrode via a contact hole in the second insulating layer.
6. The thin film transistor substrate of claim 5, further
comprising: an electrode disposed on the second insulating layer,
wherein the electrode is electrically connected to at least one of
the source region and the drain region.
7. The thin film transistor substrate of claim 6, wherein the
electrode comprises: a first electrode layer contacting at least
one of the source region and the drain region; and a second
electrode layer disposed on the first electrode layer, wherein the
second electrode layer contacts the first electrode layer.
8. The thin film transistor substrate of claim 7, wherein the first
electrode layer comprises a same material as the gate
electrode.
9. The thin film transistor substrate of claim 7, further
comprising: a second hole disposed in the first insulating layer
and exposing at least one of the source region and the drain
region, wherein the first electrode layer is disposed within the
second hole.
10. The thin film transistor substrate of claim 7, wherein the
first insulating layer surrounds the first electrode layer and
exposes an upper surface of the first electrode layer.
11. The thin film transistor substrate of claim 7, wherein the
second electrode layer is disposed on the second insulating layer,
the second electrode layer contacting the first electrode layer via
a hole in the second insulating layer.
12. The thin film transistor substrate of claim 1, wherein the
upper surface of the gate electrode has a width greater than a
width of a lower surface of the gate electrode.
13. The thin film transistor substrate of claim 1, wherein a length
of the semiconductor layer in a first direction is greater than a
length of the gate insulating layer in the first direction.
14. A display device, comprising: the thin film transistor
substrate of claim 1; and a display element disposed on the thin
film transistor substrate.
15. The display device of claim 14, wherein the display element
comprises an organic light-emitting diode.
16. The display device of claim 14, wherein the display element
comprises a liquid crystal capacitor.
17. A method of manufacturing a thin film transistor substrate, the
method comprising: forming a semiconductor layer on a substrate,
the semiconductor layer comprising a channel region, and a source
region and a drain region at first and second sides of the channel
region; forming a gate insulating layer on the semiconductor layer;
forming a first preliminary insulating layer on the gate insulating
layer; forming a first hole in the first preliminary insulating
layer; forming a metallic layer on the first preliminary insulating
layer, the metallic layer comprising a first portion filling the
first hole; and removing the first preliminary insulating layer and
the metallic layer, wherein a portion of the first preliminary
insulating layer and at least a portion of the first portion of the
metallic layer remain, and wherein the remaining portion of the
first preliminary insulating layer is a first insulating layer
covering the semiconductor layer and the gate insulating layer, and
the remaining portion of the first portion of the metallic layer is
a gate electrode.
18. The method of claim 17, wherein the first insulating layer
surrounds the gate electrode and exposes an upper surface of the
gate electrode.
19. The method of claim 17, wherein the gate insulating layer is
exposed via the first hole.
20. The method of claim 17, wherein the removing of the first
preliminary insulating layer and the metallic layer is performed
using chemical mechanical polishing (CMP).
21. The method of claim 17, wherein an upper surface of the gate
electrode and an upper surface of the first insulating layer meet
at the same plane.
22. The method of claim 17, wherein the forming of the first hole
is performed using dry etching.
23. The method of claim 17, further comprising: forming a second
insulating layer, the second insulating layer covering the gate
electrode and the first insulating layer.
24. The method of claim 23, further comprising: forming an
auxiliary electrode on the second insulating layer, the auxiliary
electrode contacting the gate electrode via a hole in the second
insulating layer.
25. The method of claim 23, further comprising: forming a second
hole in the first preliminary insulating layer, the forming of the
second hole and the forming of the first hole being performed by a
same process.
26. The method of claim 25, wherein the second hole exposes at
least one of the source region and the drain region; a second
portion of the metallic layer fills the second hole; and the
removing of the first preliminary insulating layer and the metallic
layer leaves at least a portion of the second portion of the
metallic layer.
27. The method of claim 26, wherein the first insulating layer
surrounds at least a portion of the first portion of the metallic
layer, and wherein the first insulating layer exposes an upper
surface of at least a portion of the first portion of the metallic
layer.
28. The method of claim 26, further comprising: forming an
electrode layer on the second insulating layer, the electrode layer
contacting at least a portion of the second portion of the metallic
layer via a hole in the second insulating layer.
29. The method of claim 17, wherein the forming of the
semiconductor layer and the forming of the gate insulating layer
are performed by a same mask process.
30. The method of claim 17, further comprising: performing wet
washing on the first preliminary insulating layer, wherein the
first hole is disposed in the first preliminary insulating layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority under 35 U.S.C. .sctn.119
to Korean Patent Application No. 10-2016-0044926, filed on Apr. 12,
2016 in the Korean Intellectual Property Office, the disclosure of
which is incorporated by reference herein in its entirety.
Technical Field
[0002] The present invention relates to a thin film transistor
substrate, a display device including the same, and a method of
manufacturing the same.
Discussion of Related Art
[0003] The usage of display devices has diversified as they are
being increasingly provided with a light weight and slim profile.
As the display devices are made lighter and slimmer, a high
resolution and large size screens are desired. To achieve this,
thin film transistors are being miniaturized. However, as the thin
film transistors shrink, their characteristics may deteriorate.
SUMMARY
[0004] An exemplary embodiment of the present invention provides a
thin film transistor substrate. The thin film transistor substrate
includes a substrate; a semiconductor layer disposed on the
substrate, the semiconductor layer including a channel region, and
a source region and a drain region at first and second sides of the
channel region; a gate electrode disposed on the semiconductor
layer; a gate insulating layer disposed between the gate electrode
and the semiconductor layer; and a first insulating layer disposed
on the substrate. The first insulating layer exposes an upper
surface of the gate electrode and surrounds the gate electrode.
[0005] According to an exemplary embodiment of the present
invention, the thin film transistor substrate may further include a
first hole. The first hole may be in the first insulating layer.
The gate electrode may be disposed within the first hole.
[0006] According to an exemplary embodiment of the present
invention, the upper surface of the gate electrode and an upper
surface of the first insulating layer may meet at the same
plane.
[0007] According to an exemplary embodiment of the present
invention, the thin film transistor substrate may further include a
second insulating layer. The second insulating layer may be
disposed on the upper surface of the gate electrode and an upper
surface of the first insulating layer.
[0008] According to an exemplary embodiment of the present
invention, the thin film transistor substrate may further include
an auxiliary electrode. The auxiliary electrode may be disposed on
the second insulating layer. The auxiliary electrode may contact
the gate electrode via a contact hole in the second insulating
layer.
[0009] According to an exemplary embodiment of the present
invention, the thin film transistor substrate may further include
an electrode. The electrode may be disposed on the second
insulating layer. The electrode may be electrically connected to at
least one of the source region and the drain region.
[0010] According to an exemplary embodiment of the present
invention, the electrode may include a first electrode layer. The
first electrode layer may contact at least one of the source region
or the drain region. The electrode may further include a second
electrode layer. The second electrode layer may be disposed on the
first electrode layer. The second electrode layer may contact the
first electrode layer.
[0011] According to an exemplary embodiment of the present
invention, the first electrode layer may include a same material as
the gate electrode.
[0012] According to an exemplary embodiment of the present
invention, the thin film transistor substrate may further include a
second hole. The second hole may be disposed in the first
insulating layer. The second hole may expose at least one of the
source region and the drain region. The first electrode layer may
be disposed within the second hole.
[0013] According to an exemplary embodiment of the present
invention, the first insulating layer may surround the first
electrode layer. The first insulating layer may expose an upper
surface of the first electrode layer.
[0014] According to an exemplary embodiment of the present
invention, the second electrode layer may be disposed on the second
insulating layer. The second electrode layer may contact the first
electrode layer via a hole in the second insulating layer.
[0015] According to an exemplary embodiment of the present
invention, the upper surface of the gate electrode may have a width
greater than a width of a lower surface of the gate electrode.
[0016] According to an exemplary embodiment of the present
invention, the semiconductor layer may have a length greater than a
length of the gate insulating layer in a direction as that of the
length of the semiconductor layer.
[0017] Exemplary embodiments of the present invention provide a
display device. The display device includes a thin film transistor
substrate according to exemplary embodiments of the present
invention and a display element disposed on the thin film
transistor substrate.
[0018] According to an exemplary embodiment of the present
invention, the display element may include an organic
light-emitting diode.
[0019] According to an exemplary embodiment of the present
invention, the display element may include a liquid crystal
capacitor.
[0020] An exemplary embodiment of the present invention provides a
method of manufacturing a thin film transistor substrate. The
method of manufacturing a thin film transistor substrate includes
forming a semiconductor layer on a substrate, the semiconductor
layer including a channel region, and a source region and a drain
region at first and second sides of the channel region; forming a
gate insulating layer on the semiconductor layer; forming a first
preliminary insulating layer on the gate insulating layer; forming
a first hole in the first preliminary insulating layer; forming a
metallic layer on the first preliminary insulating layer, the
metallic layer including a first portion filling the first hole;
and removing the first preliminary insulating layer and the
metallic layer, in which a portion of the first preliminary
insulating layer and at least a portion of the first portion of the
metallic layer remains. The remaining portion of the first
preliminary insulating layer is a first insulating layer covering
the semiconductor layer and the gate insulating layer. The
remaining portion of the first portion of the metallic layer is a
gate electrode.
[0021] According to an exemplary embodiment of the present
invention, the first insulating layer may surround the gate
electrode. The first insulating layer may expose an upper surface
of the gate electrode.
[0022] According to an exemplary embodiment of the present
invention, the gate insulating layer may be exposed via the first
hole.
[0023] According to an exemplary embodiment of the present
invention, the removing of the first preliminary insulating layer
and the metallic layer may be performed using chemical mechanical
polishing.
[0024] According to an exemplary embodiment of the present
invention, the forming of the first hole may be performed using dry
etching.
[0025] According to an exemplary embodiment of the present
invention, an upper surface of the gate electrode and an upper
surface of the first insulating layer may meet at the same
plane.
[0026] According to an exemplary embodiment of the present
invention, the forming of the first hole may be performed using dry
etching.
[0027] According to an exemplary embodiment of the present
invention, the method may further include forming a second
insulating layer. The second insulating layer may cover the gate
electrode and the first insulating layer.
[0028] According to an exemplary embodiment of the present
invention, the method may further include forming an auxiliary
electrode on the second insulating layer. The auxiliary electrode
may contact the gate electrode via a hole in the second insulating
layer.
[0029] According to an exemplary embodiment of the present
invention, the method may further include forming a second hole in
the first preliminary insulating layer. The forming of the second
hole and the forming of the first hole may be performed by a same
process.
[0030] According to an exemplary embodiment of the present
invention, the second hole may expose at least one of the source
region and the drain region. A second portion of the metallic layer
may fill the second hole. The removing of the first preliminary
insulating layer and the metallic layer may leave at least a
portion of the second portion of the metallic layer.
[0031] According to an exemplary embodiment of the present
invention, the first insulating layer may surround at least a
portion of the first portion. The firs insulating layer may also
expose an upper surface of at least a portion of the first portion
of the metallic layer.
[0032] According to an exemplary embodiment of the present
invention, the method may further include forming an electrode
layer on the second insulating layer. The electrode layer may
contact at least a portion of the second portion of the metallic
layer via a hole in the second insulating layer.
[0033] According to an exemplary embodiment of the present
invention, the forming of the semiconductor layer and the forming
of the gate insulating layer may be performed by a same mask
process.
[0034] According to an exemplary embodiment of the present
invention, the method may further include performing wet washing on
the first preliminary insulating layer in which the first hole. The
first hole may be disposed in the first preliminary insulating
layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] These and/or other features of the present invention will
become more apparent by describing in detail exemplary embodiments
thereof with reference to the accompanying drawings, in which:
[0036] FIG. 1 is a cross-sectional view illustrating a thin film
transistor substrate according to an exemplary embodiment of the
present invention;
[0037] FIGS. 2A to 7 are cross-sectional views illustrating a
method of manufacturing a thin film transistor substrate according
to an exemplary embodiment of the present invention;
[0038] FIG. 8 is a cross-sectional view illustrating a
manufacturing process according to a comparative example;
[0039] FIG. 9 is a plan view illustrating a display device
including a thin film transistor substrate according to an
exemplary embodiment of the present invention;
[0040] FIG. 10 is an equivalent circuit diagram illustrating a
pixel of one pixel region according to an exemplary embodiment of
the present invention;
[0041] FIG. 11 is a cross-sectional view illustrating a pixel
according to an exemplary embodiment of the present invention;
[0042] FIG. 12 is an equivalent circuit diagram illustrating a
pixel of one pixel region according to an exemplary embodiment of
the present invention; and
[0043] FIG. 13 is a cross-sectional view illustrating a pixel
according to an exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0044] Exemplary embodiments of the present invention will now be
described in reference to the drawings. The present invention may,
however, be embodied in many different forms and should not be
construed as limited to the embodiments set forth herein. In the
drawings, like references numerals may refer to like elements
throughout.
[0045] As used herein, the singular forms "a" "an" and "the" are
intended to include the plural forms as well, unless the context
clearly indicates otherwise.
[0046] Sizes of elements in the drawings may be exaggerated for
convenience of explanation.
[0047] It is to be understood that a specific process order may be
performed differently from the described order. For example, two
consecutively described processes may be performed substantially at
the same time or performed in an order opposite to the described
order.
[0048] It will be understood that when a layer, region, or
component is referred to as being "connected" to another layer,
region, or component, it may be "directly connected" to the other
layer, region, or component or may be "indirectly connected" to the
other layer, region, or component with other layer, region, or
component interposed therebetween.
[0049] FIG. 1 is a cross-sectional view illustrating a thin film
transistor (TFT) substrate according to an exemplary embodiment of
the present invention.
[0050] Referring to FIG. 1, the TFT substrate may include a
substrate 100. The TFT substrate may further include a thin film
transistor (TFT) TR disposed above the substrate 100. The TFT TR
may be a top gate-type TFT in which a gate electrode 230 is
disposed above a semiconductor layer 210. A buffer layer 101 may be
disposed between the semiconductor layer 210 and the substrate 100.
The buffer layer 101 may include SiOx and/or SiNx. The buffer layer
101 may increase the prevention of impurities from penetrating into
the semiconductor layer 210.
[0051] The semiconductor layer 210 may include, for example,
amorphous silicon (a-Si) or polycrystalline silicon (poly-Si).
According to an exemplary embodiment of the present invention, the
semiconductor layer 210 may include an oxide of at least one of
indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V),
hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium
(Ti), and zinc (Zn). The semiconductor layer 210 may include a
channel region 210c. The semiconductor layer 210 may further
include a source region 210s and a drain region 210d. The source
region 210s and the drain region 210d may be disposed on either
side of the channel region 210c, respectively.
[0052] A gate insulating layer 103 may be disposed over the channel
region 210c of the semiconductor layer 210. The gate insulating
layer 103 may include an inorganic material such as SiOx, SiNx,
SiON, aluminum oxide (Al.sub.2O.sub.3), CuOx, tetraterbium
heptaoxide (Tb.sub.4O.sub.7), yttrium(III) oxide (Y.sub.2O.sub.3),
niobium(V) oxide (Nb.sub.2O.sub.5), and praseodymium(III) oxide
(Pr.sub.2O.sub.3). A length L2 of the gate insulating layer 103 in
a first direction from the source region 210s to the drain region
210d of the semiconductor layer 210 may be less than a length L1 of
the semiconductor layer 210. Accordingly, the length L2 of the gate
insulating layer 103 in the first direction from the source region
210s to the drain region 210d of the semiconductor layer 210 may be
substantially the same as a length of the channel region 210c in
the same direction.
[0053] A gate electrode 230 may be disposed above and overlap the
channel region 210c of the semiconductor layer 210. The gate
insulating layer 103 may be disposed between the gate electrode 230
and the channel region 210c. The gate electrode 230 may be disposed
in a first hole H1. The first hole H1 may be inside a first
insulating layer 105. The first insulating layer may be disposed on
the substrate 100 and the buffer layer 101. According to an
exemplary embodiment of the present invention, the gate electrode
230 may have a reverse tapered shape in which the width of an upper
surface thereof is greater than the width of a lower surface
thereof.
[0054] The gate electrode 230 may include at least one of copper
(Cu), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd),
gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium
(Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti),
tungsten (W), and silver (Ag).
[0055] The first insulating layer 105 may surround the gate
electrode 230. The first insulating layer 105 may also expose an
upper surface of the gate electrode 230. The first insulating layer
105 may include an inorganic insulating material including SiOx,
SiNx, aluminum oxide (Al.sub.2O.sub.3), CuOx, tetraterbium
heptaoxide (Tb.sub.4O.sub.7), yttrium(III) oxide (Y.sub.2O.sub.3),
niobium(V) oxide (Nb.sub.2O.sub.5), and praseodymium(III) oxide
(Pr.sub.2O.sub.3). Alternatively, the first insulating layer 105
may include at least one organic insulating material including one
of polyimide (PI), polyamide (PA), an acrylic resin,
benzocyclobutene (BCB), and a phenol resin. Alternatively, the
first insulating layer 105 may include a multi-layered structure.
The multi-layered structure may include an organic insulating
material and an inorganic insulating material. The organic
insulating material and the inorganic insulating material may be
alternatively stacked.
[0056] An upper surface of the first insulating layer 105 and an
upper surface of the gate electrode 230 may be arranged above
substantially the same plane in a vertical cross-section by a
manufacturing process described herein. The first insulating layer
105 and the gate electrode 230 may be manufactured by chemical
mechanical polishing (CMP), therefore, the upper surface of the
first insulating layer 105 and the upper surface of the gate
electrode 230 may be arranged above substantially the same plane.
The upper surface of the first insulating layer 105 may have
substantially uniform roughness. The upper surface of the gate
electrode 230 may have substantially uniform roughness.
[0057] A first distance D1 which may be referred to as a first
distance from the substrate 100 to the upper surface of the gate
electrode 230 may be substantially the same as a second distance D2
which may be referred to as a second distance from the substrate
100 to the upper surface of the first insulating layer 105.
Accordingly, the first distance D1 may be substantially the same as
the second distance D2. A difference between the first distance D1
and the second distance D2 may be less than about 100 .ANG..
[0058] The gate electrode 230 may be connected to an auxiliary
electrode 250. The auxiliary electrode 250 may be disposed above a
second insulating layer 107. The auxiliary electrode 250 may
contact the upper surface of the gate electrode 230 via a hole
passing through the second insulating layer 107.
[0059] The auxiliary electrode 250 may include at least one of
copper (Cu), magnesium (Mg), aluminum (Al), platinum (Pt),
palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium
(Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo),
titanium (Ti), tungsten (W), and silver (Ag).
[0060] At least one of the source region 210s and the drain region
210d of the semiconductor layer 210 may be connected to an
electrode 270. The electrode 270 may include a plurality of
electrode layers. For example, the electrode 270 may include a
first electrode layer 271 and a second electrode layer 272.
[0061] The first electrode layer 271 may include substantially the
same material as the gate electrode 230. An upper surface of the
first electrode layer 271 may be disposed above substantially the
same plane as the upper surface of the gate electrode 230 and the
upper surface of the first insulating layer 105. The upper surface
of the first electrode layer 271, the upper surface of the first
insulating layer 105, and the upper surface of the gate electrode
230 may be arranged above substantially the same plane by a
manufacturing process described herein. Since the first electrode
layer 271, the first insulating layer 105, and the gate electrode
230 may be manufactured by chemical mechanical polishing (CMP), the
upper surface of the first electrode layer 271, the upper surface
of the first insulating layer 105, and the upper surface of the
gate electrode 230 may be arranged above substantially the same
plane. Accordingly, the upper surface of the first electrode layer
271, the upper surface of the first insulating layer 105, and the
upper surface of the gate electrode 230 may have substantially
uniform roughness.
[0062] A distance from the substrate 100 to the upper surface of
the first electrode layer 271 may be substantially the same as the
first distance D1 from the substrate 100 to the upper surface of
the gate electrode 230. Accordingly, the distance from the
substrate 100 to the upper surface of the first electrode layer 271
may be substantially the same as the first distance D1 from the
substrate 100 to the upper surface of the gate electrode 230. A
difference between the distance and the first distance D1 may be
less than about 100 .ANG..
[0063] The second electrode layer 272 may include substantially the
same material as the auxiliary electrode 250. The second electrode
layer 272 may be disposed above the second insulating layer 107.
The second electrode layer 272 may contact the first electrode
layer 271 via a hole passing through the second insulating layer
107.
[0064] According to an exemplary embodiment of the present
invention, the gate electrode 230 may be manufactured to have a
fine line width via dry etching and chemical mechanical polishing
(CMP).
[0065] FIGS. 2A to 7 are cross-sectional views illustrating a
method of manufacturing a thin film transistor (TFT) substrate
according to an exemplary embodiment of the present invention.
[0066] FIGS. 2A to 2C illustrate a first mask process according to
an exemplary embodiment of the present invention.
[0067] Referring to FIG. 2A, a semiconductor material layer 210p'
and an insulating material layer 103p'' may be sequentially formed
above the substrate 100.
[0068] The substrate 100 may include various materials such as a
plastic material including polyethylene terephthalate (PET),
polyethylene naphthalate (PEN), and polyimide (Pl); however,
exemplary embodiments of the present invention are not limited
thereto.
[0069] The buffer layer 101 may be formed above the substrate 100.
This may be done before forming the semiconductor material layer
210p'. The buffer layer 101 may increase the prevention of
impurities from passing through the substrate 100 and penetrating
into the semiconductor material layer 210p'. The buffer layer 101
may include SiOx and/or SiNx. The buffer layer 101 may include a
single layer or multiple layers.
[0070] The semiconductor material layer 210p' may include a
silicon-based material such as amorphous silicon (a-Si) or
polycrystalline silicon (poly-Si). Alternatively, the semiconductor
material layer 210p' may include an oxide of at least one of indium
(In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium
(Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti),
and zinc (Zn).
[0071] The insulating material layer 103p'' may include an
inorganic material such as SiOx, SiNx, SiON, aluminum oxide
(Al.sub.2O.sub.3), CuOx, tetraterbium heptaoxide (Tb.sub.4O.sub.7),
yttrium(III) oxide (Y.sub.2O.sub.3), niobium(V) oxide
(Nb.sub.2O.sub.5), and praseodymium(III) oxide (Pr.sub.2O.sub.3).
The insulating material layer 103p'' may be formed using various
deposition methods such as plasma-enhanced chemical vapor
deposition (PECVD), atmospheric pressure chemical vapor deposition
(APCVD), and low pressure chemical vapor deposition (LPCVD);
however, exemplary embodiments of the present invention are not
limited thereto.
[0072] A photosensitive material such as a photoresist may be
coated above the insulating material layer 103p''. A photoresist
layer PR from which a solvent has been removed may be formed by
pre-baking or soft baking. In order to pattern the photoresist
layer PR, a half-tone mask M may be used. The half-tone mask M may
have a predetermined pattern and may be aligned above the substrate
100. An exposure to irradiating light in a predetermined wavelength
band may be performed on the photoresist layer PR.
[0073] The half-tone mask M may include a light-transmission
portion M11, a light-blocking portion M12, and a semi-transmission
portion M13. The light-transmission portion M11 may transmit light
in a predetermined wavelength band, the light-blocking portion M12
may block irradiated light, and the semi-transmission portion M13
may transmit only a portion of irradiated light.
[0074] FIG. 2B illustrates a first photoresist pattern PR1
remaining after performing a developing process in which an exposed
portion of the photoresist layer PR is removed.
[0075] Referring to FIGS. 2A and 2B, a patterned insulating
material layer 103p' and the semiconductor layer 210 may be formed
by patterning the insulating material layer 103p'' and the
semiconductor layer 210p' using the first photoresist pattern PR1
as a mask.
[0076] Referring to FIGS. 2A to 2C, a portion of the first
photoresist pattern PR1 corresponding to the semi-transmission
portion M13 may be removed by ashing. A thickness of a portion of
the first photoresist pattern PR1 corresponding to the
light-blocking portion M12 may be reduced by ashing. Accordingly, a
second photoresist pattern PR2 may be formed.
[0077] The gate insulating layer 103 may be formed by patterning
the patterned insulating material layer 103p' using the second
photoresist pattern PR2 as a mask. The length L2 of the gate
insulating layer 103 may be less than the length L1 of the
semiconductor layer 210.
[0078] The semiconductor layer 210 may be doped or plasma-processed
using the second photoresist pattern PR2 as a mask. According to an
exemplary embodiment of the present invention, when the
semiconductor layer 210 includes a silicon-based material, the
semiconductor layer 210 may be doped with impurities by using the
second photoresist pattern PR2 as a mask. A non-doped region of the
semiconductor layer 210 that is masked by the second photoresist
pattern PR2 may become the channel region 210c. The doped regions
may become the source region 210s and the drain region 210d,
respectively. According to an exemplary embodiment of the present
invention, when the semiconductor layer 210 includes an oxide, the
semiconductor layer 210 may become a conductor by performing a
plasma process using the second photoresist pattern PR2 as a mask.
A non-processed region of the semiconductor layer 210 that is
masked by the second photoresist pattern PR2 may become the channel
region 210c. The conductive regions may become the source region
210s and the drain region 210d, respectively. Afterwards, the
second photoresist pattern PR2 may be removed.
[0079] FIG. 3 illustrates a second mask process according to an
exemplary embodiment of the present invention.
[0080] Referring to FIG. 3, a first preliminary insulating layer
105p may be formed above the semiconductor layer 210 and the gate
insulating layer 103. A first hole H1 and second holes H2 may be
formed by using a mask. According to an exemplary embodiment of the
present invention, the first hole H1 and the second holes H2 may
have a reverse tapered shape in which a width increases toward an
upper portion thereof; however, exemplary embodiments of the
present invention are not limited thereto.
[0081] The first preliminary insulating layer 105p may include an
inorganic insulating material including SiOx, SiNx, aluminum oxide
(Al.sub.2O.sub.3), CuOx, tetraterbium heptaoxide (Tb.sub.4O.sub.7),
yttrium(III) oxide (Y.sub.2O.sub.3), niobium(V) oxide
(Nb.sub.2O.sub.5), and praseodymium(III) oxide (Pr.sub.2O.sub.3).
Alternatively, the first preliminary insulating layer 105p may
include at least one organic insulating material including one of
polyimide (PI), polyamide (PA), an acrylic resin, benzocyclobutene
(BCB), and a phenol resin. Alternatively, the first preliminary
insulating layer 105p may include a multi-layered structure
including an organic insulating material and an inorganic
insulating material. The organic insulating material and the
inorganic insulating material may be alternatively stacked.
[0082] The first hole H1 may overlap the channel region 210c and
expose the gate insulating layer 103. The second holes H2 may
expose at least one of the source region 210s and the drain region
210d of the semiconductor layer 210.
[0083] The first hole H1 and the second holes H2 may be formed by
dry etching. Isotropic or anisotropic dry etching may be used. The
gate electrode 230 may be disposed within the first hole H1. The
line width of the gate electrode 230 may be determined by the width
W1 of the first hole H1. For example, the width W1 of the first
hole H1 may be the line width of the gate electrode 230. If the
first hole H1 is formed by wet etching, an undercut may occur.
Furthermore, fine etching may be difficult to perform and
manufacturing a TFT TR suitable for a high resolution display
device may become unobtainable. However, in the etching process
according to an exemplary embodiment of the present invention,
since the first hole H1 may be formed by dry etching, the width W1
of the first hole H1 or the fine line width of the gate electrode
230 to be formed within the first hole H1 may be adjusted.
[0084] A wet washing process may be performed on the first
preliminary insulating layer 105p including the first hole H1 and
the second holes H2. The wet washing process may use buffered oxide
etchant (BOE).
[0085] FIGS. 4 and 5 illustrate a process of forming the gate
electrode 230 according to an exemplary embodiment of the present
invention.
[0086] Referring to FIG. 4, a metallic layer ML may be formed above
the first preliminary insulating layer 105p. The metallic layer ML
may include at least one of copper (Cu), magnesium (Mg), aluminum
(Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni),
neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium
(Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and silver
(Ag). The metallic layer ML may be substantially entirely formed
above the first preliminary insulating layer 105p. A first portion
ML1 of the metallic layer ML may fill the first hole H1. A second
portion ML2 of the metallic layer ML may fill the second holes
H2.
[0087] Referring to FIG. 5, a portion of the first preliminary
insulating layer 105p and a portion of the metallic layer ML may be
removed. The portion of the first preliminary insulating layer 105p
and the portion of the metallic layer ML may be substantially
simultaneously removed by a polishing process, such as chemical
mechanical polishing (CMP).
[0088] Through chemical mechanical polishing (CMP), at least a
portion of the first portion ML1 of the metallic layer ML inside
the first hole H1 may remain and may become the gate electrode 230.
A remaining portion of the first preliminary insulating layer 105p
may become the first insulating layer 105. At least a portion of
the second portion ML2 of the metallic layer ML inside the second
holes H2 may remain and may become the first electrode layers 271.
The first insulating layer 105 may have a thickness T2 less than a
thickness T1 of the first preliminary insulating layer 105p.
[0089] The upper surface of the gate electrode 230 and the upper
surface of the first insulating layer 105 may be arranged above
substantially the same plane by the chemical mechanical polishing
(CMP) process. For example, the upper surface of the gate electrode
230 and the upper surface of the first insulating layer 105 may
have substantially uniform roughness. The upper surface of the gate
electrode 230 and the upper surface of the first insulating layer
105 may be located above the substantially the same plane.
Furthermore, the first distance D1 from the substrate 100 to the
upper surface of the gate electrode 230 may be substantially the
same as the second distance D2 from the substrate 100 to the upper
surface of the first insulating layer 105.
[0090] Since the gate electrode 230 may be disposed inside the
first hole H1 in the first insulating layer 105 and may directly
contact the lateral surface of the first insulating layer 105
surrounding the first hole H1, the line width W2 of the gate
electrode 230 may be substantially the same as the width W1 of the
first hole H1.
[0091] Since the first electrode layer 271 may be formed during
substantially the same process as the gate electrode 230, the upper
surface of the first electrode layer 271 may be arranged above
substantially the same plane as the upper surface of the gate
electrode 230 and the upper surface of first insulating layer 105.
For example, the upper surface of the first electrode layer 271,
the upper surface of the gate electrode 230, and the upper surface
of the first insulating layer 105 may have substantially uniform
roughness and may be arranged above substantially the same plane.
Therefore, a distance from the substrate 100 to the first electrode
layer 271 may be substantially the same as the first distance
D1.
[0092] FIG. 6 illustrates a third mask process according to an
exemplary embodiment of the present invention.
[0093] Referring to FIG. 6, the second insulating layer 107
covering the gate electrode 230, the first electrode layer 271, and
the first insulating layer 105 may be formed, and a third hole H3
and fourth holes H4 may be formed by using a mask.
[0094] The second insulating layer 107 may include an inorganic
insulating material including at least one of SiOx, SiNx, aluminum
oxide (Al.sub.2O.sub.3), CuOx, tetraterbium heptaoxide
(Tb.sub.4O.sub.7), yttrium(lll) oxide (Y.sub.2O.sub.3), niobium(V)
oxide (Nb.sub.2O.sub.5), and praseodymium(lll) oxide
(Pr.sub.2O.sub.3). Alternatively, the second insulating layer 107
may include at least one organic insulating material including one
of polyimide (Pl), polyamide (PA), an acrylic resin,
benzocyclobutene (BCB), and a phenol resin. Alternatively, the
second insulating layer 107 may include a multi-layered structure
in which an organic insulating material and an inorganic insulating
material may be alternatively stacked.
[0095] The third hole H3 may expose the gate electrode 230. The
third hole H3 may be formed by dry etching. The fourth holes H4 may
expose the first electrode layers 271. The fourth holes H4 may be
formed by dry etching.
[0096] FIG. 7 illustrates a fourth mask process according to an
exemplary embodiment of the present invention.
[0097] Referring to FIG. 7, the auxiliary electrode 250 and the
second electrode layers 272 may be formed by forming and patterning
a metallic layer above the second insulating layer 107.
[0098] The auxiliary electrode 250 may be electrically connected to
the gate electrode 230 by contacting the upper surface of the gate
electrode 230. The second electrode layer 272 may be electrically
connected to the first electrode layer 271 by contacting the first
electrode layer 271. The first electrode layer 271 and the second
electrode layer 272 may configure the electrode 270 through
contacting each other.
[0099] FIG. 8 is a cross-sectional view illustrating a
manufacturing process according to a comparative example.
[0100] Referring to FIG. 8, after a gate electrode 23 is formed by
forming a metallic layer above a semiconductor layer 21 and
patterning the metallic layer via wet etching, a source region 21s
and a drain region 21d are formed at both sides of a channel region
21c, which is a non-doped region, by doping the semiconductor layer
21 with impurities using the gate electrode 23 as a mask. An
interlayer insulating layer 104 including a first through hole TH1
exposing the gate electrode 23 and second through holes TH2
respectively exposing the source region 21s and the drain region
21d is formed. An auxiliary electrode 25 and electrodes 27 are
formed by forming and patterning a metallic layer above the
interlayer insulating layer 104.
[0101] Prior to forming the metallic layer, the source region 21s
and the drain region 21d of the semiconductor layer 21 exposed via
the second through holes TH2 may be washed by buffered oxide
etchant (BOE). The buffered oxide etchant (BOE) may include
hydrogen fluoride (HF). The buffered oxide etchant (BOE) may damage
metal. Therefore, the gate electrode 23 exposed via the first
through hole TH1 may be damaged by the buffered oxide etchant
(BOE). For example, a chemically resistant characteristic of the
gate electrode 23 including aluminum (Al) or copper (Cu)
deteriorates against the buffered oxide etchant (BOE), so that the
driving characteristic of a TFT TR' may deteriorate. Although
titanium nitride (TiN) and other compounds may be included the gate
electrode 23, the characteristic of the TFT TR' may deteriorate due
to particles generated during a sputtering process of forming the
titanium nitride (TiN).
[0102] However, according to an exemplary embodiment of the present
invention as described with reference to FIGS. 2A to 7, since a wet
washing process may be performed prior to the formation of the gate
electrode 230, it may prevent the gate electrode 230 from being
damaged by the buffered oxide etchant (BOE). Additionally, the TFT
TR may be formed irrespective of the metal type forming the gate
electrode 230.
[0103] As illustrated in FIG. 8, when the gate electrode 23 is
formed by forming and patterning the metallic layer, the patterning
process may be performed by wet etching. Since the gate electrode
23 is formed by wet etching, an undercut may occur and it may be
difficult to finely adjust a line width.
[0104] However, according to an exemplary embodiment of the present
invention as described with reference to FIGS. 2A to 7, by forming
the first hole H1 in the first preliminary insulating layer 105p
via dry etching, metal may fill the first hole H1. The gate
electrode 230 may also be formed by chemical mechanical polishing
(CMP). Therefore, it may be possible to finely adjust the line
width of the gate electrode 230 irrespective of a metal type
forming the gate electrode 230.
[0105] FIG. 9 is a plan view of a display device 1 including a thin
film transistor (TFT) substrate according to an exemplary
embodiment of the present invention.
[0106] Referring to FIG. 9, the display device 1 may include an
active area AA and a dead area DA. The dead area DA may surround
the active area AA. The active area AA may include pixel areas PA.
A pixel may be provided to substantially each pixel area PA.
According to an exemplary embodiment of the present invention, the
display device 1 may be an organic light-emitting display device;
however, exemplary embodiments of the present invention are not
limited thereto. Substantially each pixel area PA may include a
pixel circuit and an organic light-emitting diode (OLED). The
organic light-emitting diode (OLED) may be connected to the pixel
circuit.
[0107] FIG. 10 is an equivalent circuit diagram of a pixel of a
pixel region according to an exemplary embodiment of the present
invention. FIG. 11 is a cross-sectional view of a pixel according
to an exemplary embodiment of the present invention.
[0108] Referring to FIG. 10, substantially each pixel PX may
include a first thin film transistor (TFT) TR1, a second thin film
transistor (TFT) TR2, a storage capacitor Cst, and an organic light
emitting diode OLED. The organic light-emitting diode OLED may emit
light of predetermined brightness by using a driving current
l.sub.oled.
[0109] The first TFT TR1 may output a data signal applied to a j-th
data line DLj in response to a gate signal applied to an i-th gate
line GLi. The second TFT TR2 may control a driving current flowing
through the organic light-emitting diode OLED in response to the
amount of charge stored in the storage capacitor Cst. A pixel PX
may receive a first voltage ELVDD and a second voltage ELVSS. The
first voltage ELVDD and the second voltage ELVSS may have different
voltage levels, respectively. An electrode of the storage capacitor
Cst may be connected to a power line PL.
[0110] Referring to FIG. 11, the second TFT TR2 may be
substantially the same as the TFT TR as described with reference to
FIGS. 1 to 7.
[0111] According to an exemplary embodiment of the present
invention, the auxiliary electrode 250 may be connected to the gate
electrode 230 of the second TFT TR2. The auxiliary electrode 250
may serve as a bridge wiring and may connect the second TFT TR2 to
another TFT (e.g. the first TFT TR1). Alternatively, the auxiliary
electrode 250 may service as a bride wiring and may connect the
second TFT TR2 to other electrical element, such as the storage
capacitor Cst. The electrode 270 connected to the source region
210s of the second TFT TR2 may be connected to the power line PL.
The electrode 270 connected to the drain region 210d may be
connected to a pixel electrode 310 of the organic light-emitting
diode OLED. The pixel electrode 310 may be connected to the second
TFT TR2 via a hole formed in a planarization layer 109.
[0112] The pixel electrode 310 of the organic light-emitting diode
OLED may receive a voltage corresponding to the first voltage ELVDD
from the second TFT TR2. An opposite electrode 330 of the organic
light-emitting diode OLED may receive the second voltage ELVSS.
Accordingly, the organic light-emitting diode OLED may emit light.
An emission layer 320 of the organic light-emitting diode OLED may
be disposed between the pixel electrode 310 and the opposite
electrode 330. The emission layer 320 may be exposed via a
pixel-defining layer 110. The emission layer 320 may emit a
predetermined light.
[0113] Although FIG. 11 illustrates the second TFT TR2 as
substantially the same as the TFT TR as described with reference to
FIGS. 1 to 7, exemplary embodiments of the present invention are
not limited thereto. According to an exemplary embodiment of the
present invention, the first TFT TR1 may have substantially the
same structure as the TFT TR as described with reference to FIGS. 1
to 7. The TFT TR1 may also be formed by substantially the same
process. Although the display device as described with reference to
FIGS. 9 to 11 may be an organic light-emitting display device,
exemplary embodiments of the present invention are not limited
thereto. According to an exemplary embodiment of the present
invention, the display device may be a liquid crystal display
device
[0114] FIG. 12 is an equivalent circuit diagram of a pixel of one
pixel region according to an exemplary embodiment of the present
invention. FIG. 13 is a cross-sectional view of one pixel according
to an exemplary embodiment of the present invention. The display
device according to an exemplary embodiment of the present
invention illustrated in FIGS. 12 and 13 may be a liquid crystal
display device; however, exemplary embodiments of the present
invention are not limited thereto.
[0115] Referring to FIG. 12, substantially each pixel PX may
include a TFT TR3, a storage capacitor Cst, and a liquid crystal
capacitor Clc. The liquid crystal capacitor Clc may be a display
element. The storage capacitor Cst may be parallel-connected to the
liquid crystal capacitor Clc.
[0116] The TFT TR3 may be connected to a gate line GLi and a data
line DLj. The TFT TR3 may output a data signal applied to the data
line DLj in response to a gate signal applied to the gate line GLi.
The liquid crystal capacitor Clc may be charged with a voltage
corresponding to a data signal.
[0117] Referring to FIG. 13, the TFT TR3 may be substantially the
same as the TFT TR as described with reference to FIGS. 1 to 7.
[0118] The liquid crystal capacitor Clc may include a liquid
crystal layer LC disposed between the first electrode 410 and the
second electrode 420. For example, the first electrode 410 of the
liquid crystal capacitor Clc may be connected to the TFT TR3 via a
hole passing through the planarization layer 109. The second
electrode 420 may be disposed below an upper substrate 500;
however, exemplary embodiments of the present invention are not
limited thereto. The upper substrate 500 may include a color filter
CF and a black matrix BM. According to an exemplary embodiment of
the present invention, the first electrode 410 and the second
electrode 420 may be disposed above the substrate 100.
[0119] In an exemplary embodiment of the present invention, the TFT
substrate may include the case where a TFT or a TFT TR as
illustrated in FIG. 1 has been formed above the substrate 100. The
TFT substrate may include the case where the planarization layer
109 has been formed above a TFT TR2 and a TFT TR3 as illustrated in
FIGS. 11 and 13. Furthermore, the TFT substrate may include where
pixel electrodes 310 and 410 have been formed above a TFT TR2 and a
TFT TR3.
[0120] While the present invention has been particularly shown and
described in reference to exemplary embodiments thereof, it will be
understood by those of ordinary skill in the art that various
changes in form and details and equivalents thereof may be made
therein without departing from the spirit and scope of the
inventive concept as defined by the following claims.
* * * * *