U.S. patent application number 15/474336 was filed with the patent office on 2017-10-05 for semiconductor device and display device.
This patent application is currently assigned to Japan Display Inc.. The applicant listed for this patent is Japan Display Inc.. Invention is credited to Masato HIRAMATSU, Toshihiko ITOGA, Yasukazu KIMURA, Takuma NISHINOHARA.
Application Number | 20170287999 15/474336 |
Document ID | / |
Family ID | 59961194 |
Filed Date | 2017-10-05 |
United States Patent
Application |
20170287999 |
Kind Code |
A1 |
KIMURA; Yasukazu ; et
al. |
October 5, 2017 |
SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
Abstract
A display device includes a substrate having flexibility, a
transistor having a gate insulating film and further having a
semiconductor layer and a gate electrode that sandwich the gate
insulating film, the transistor formed in an area where the
substrate is bent, and a gate wiring line so formed on the
substrate as to be connected to the gate electrode, and the gate
electrode has an area that is present in an area where the gate
electrode overlaps with the semiconductor layer and is thinner than
at least part of the gate wiring line.
Inventors: |
KIMURA; Yasukazu;
(Minato-ku, JP) ; HIRAMATSU; Masato; (Minato-ku,
JP) ; NISHINOHARA; Takuma; (Minato-ku, JP) ;
ITOGA; Toshihiko; (Minato-ku, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Japan Display Inc. |
Minato-ku |
|
JP |
|
|
Assignee: |
Japan Display Inc.
Minato-ku
JP
|
Family ID: |
59961194 |
Appl. No.: |
15/474336 |
Filed: |
March 30, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/124 20130101;
H01L 51/0097 20130101; H01L 27/3262 20130101; H01L 27/3276
20130101; H01L 2251/5338 20130101; H01L 29/78645 20130101; H01L
27/1214 20130101; Y02E 10/549 20130101; H01L 27/1218 20130101 |
International
Class: |
H01L 27/32 20060101
H01L027/32; H01L 51/00 20060101 H01L051/00 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 1, 2016 |
JP |
2016-074492 |
Claims
1. A semiconductor device comprising: a substrate having
flexibility; a transistor having a gate insulating film and further
having a semiconductor layer and a gate electrode that sandwich the
gate insulating film, is formed in an area where the substrate is
bent; and a gate wiring line so formed on the substrate but in an
area where the gate wiring line does not overlap with the
semiconductor layer as to be connected to the gate electrode,
wherein the gate electrode has an area that is present in an area
where the gate electrode overlaps with the semiconductor layer and
is thinner than at least part of the gate wiring line.
2. The semiconductor device according to claim 1, wherein the area
where the gate electrode overlaps with the semiconductor layer has
a planar shape having a lengthwise axis and a widthwise axis
perpendicular to the lengthwise axis, and a direction in which the
substrate is bent in the area where the transistor is formed
coincides with a direction in which the widthwise axis is bent.
3. The semiconductor device according to claim 1, wherein a step is
formed in a surface of the gate electrode on a side opposite the
gate insulating film so that the gate electrode has a recess.
4. A display device comprising: a substrate having flexibility; a
plurality of pixels provided on the substrate to form a display
area; a transistor having a gate insulating film and further having
a semiconductor layer and a gate electrode that sandwich the gate
insulating film, is formed in an area where the substrate is bent;
and a gate wiring line so formed on the substrate but in an area
where the gate wiring line does not overlap with the semiconductor
layer as to be connected to the gate electrode, wherein the gate
electrode has an area that is present in an area where the gate
electrode overlaps with the semiconductor layer and is thinner than
at least part of the gate wiring line.
5. The display device according to claim 4, wherein the area where
the gate electrode overlaps with the semiconductor layer has a
shape having a lengthwise axis and a widthwise axis perpendicular
to the lengthwise axis, and a direction in which the substrate is
bent in the area where the transistor is formed coincides with a
direction in which the widthwise axis is bent.
6. The display device according to claim 4, wherein a step is
formed in a surface of the gate electrode on a side opposite the
gate insulating film so that the gate electrode has a recess.
7. The display device according to claim 4, wherein each of the
plurality of pixels is provided with the transistor.
8. A display device comprising: a substrate having a bending part;
a plurality of pixels provided on a display area, each of the
plurality of pixels at the bending part including a transistor
having a gate insulating film, a semiconductor layer and a gate
electrode; and a gate wiring line being connected to the gate
electrode, wherein the gate insulating film is between the
semiconductor layer and the pixel electrode, the gate wiring line
does not overlap with the semiconductor layer in plan view, the
gate electrode has an area overlaps with the semiconductor layer in
plan view, and the gate electrode is thinner than the gate wiring
line.
9. The display device according to claim 8, wherein the substrate
has flexibility.
10. The display device according to claim 8, wherein the area where
the gate electrode overlaps with the semiconductor layer has a
shape having a lengthwise axis and a widthwise axis perpendicular
to the lengthwise axis, and a direction in which the substrate is
bent in the area where the transistor is formed coincides with a
direction in which the widthwise axis is bent.
11. The display device according to claim 8, wherein a step is
formed in a surface of the gate electrode on a side opposite the
gate insulating film so that the gate electrode has a recess.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority from Japanese
application JP2016-074492 filed on Apr. 1, 2016, the content of
which is hereby incorporated by reference into this
application.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] The present invention relates to a semiconductor device and
a display device.
2. Description of the Related Art
[0003] There is a known display device including a substrate having
flexibility and a gate electrode and a semiconductor layer that are
provided on the substrate and so disposed as to be superimposed on
each other to form the gate of a transistor. In the display device,
in a case where the direction in which the substrate is bent
coincides with the direction in which a lengthwise axis of the gate
electrode is bent, the characteristics of the transistor
undesirably change in some cases due to bending stress repeatedly
induced in the gate electrode. JP 2008-505352 A, which has been
made in view of the problem described above, discloses a
configuration in which the transistor is skillfully so arranged
that the direction in which the substrate is bent does not coincide
with the direction in which the lengthwise axis of the gate
electrode is bent.
[0004] In the configuration disclosed in JP 2008-505352 A, however,
the transistor is arranged in a restricted manner, undesirably
resulting in decrease in design flexibility.
SUMMARY OF THE INVENTION
[0005] An object of the invention is to lower bending stress
induced in a gate electrode with no restriction on the arrangement
of a transistor.
[0006] A semiconductor device according an aspect of the invention
includes a substrate having flexibility, a transistor having a gate
insulating film and further having a semiconductor layer and a gate
electrode that sandwich the gate insulating film, the transistor
formed in an area where the substrate is bent, and a gate wiring
line so formed on the substrate but in an area where the gate
wiring line does not overlap with the semiconductor layer as to be
connected to the gate electrode, and the gate electrode has an area
that is present in an area where the gate electrode overlaps with
the semiconductor layer and is thinner than at least part of the
gate wiring line.
[0007] A display device according to another aspect of the
invention includes a substrate having flexibility, a plurality of
pixels provided on the substrate to form a display area, a
transistor having a gate insulating film and further having a
semiconductor layer and a gate electrode that sandwich the gate
insulating film, the transistor formed in an area where the
substrate is bent, and a gate wiring line so formed on the
substrate but in an area where the gate wiring line does not
overlap with the semiconductor layer as to be connected to the gate
electrode, and the gate electrode has an area that is present in an
area where the gate electrode overlaps with the semiconductor layer
and is thinner than at least part of the gate wiring line.
[0008] A display device according to a substrate having a bending
part, a plurality of pixels provided on a display area, each of the
plurality of pixels at the bending part including a transistor
having a gate insulating film, a semiconductor layer and a gate
electrode; and gate wiring line being connected to the gate
electrode, wherein the gate insulating film is between the
semiconductor layer and the pixel electrode, the gate wiring line
does not overlap with the semiconductor layer in plan view, the
gate electrode has an area overlaps with the semiconductor layer in
plan view, and the gate electrode is thinner than the gate wiring
line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a perspective view of a display device in an
embodiment of the invention.
[0010] FIG. 2 is a plan view of the display device in the present
embodiment.
[0011] FIG. 3 is a circuit diagram showing a pixel circuit in the
present embodiment.
[0012] FIG. 4 is a plan transparent view of the display device
viewed from the side facing a display area of the display
device.
[0013] FIG. 5 is an enlarged view of an area surrounded by a broken
line D in FIG. 4.
[0014] FIG. 6 is a cross-sectional view taken along the line VI-VI
in FIGS. 4 and 5.
[0015] FIG. 7A describes the process of reducing the thickness of a
gate electrode in the present embodiment.
[0016] FIG. 7B describes the process of reducing the thickness of
the gate electrode in the present embodiment.
[0017] FIG. 7C describes the process of reducing the thickness of
the gate electrode in the present embodiment.
[0018] FIG. 7D describes the process of reducing the thickness of
the gate electrode in the present embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0019] An embodiment of the invention (hereinafter referred to as
present embodiment) will be described below with reference to the
drawings. The disclosed embodiment is presented only by way of
example, and an appropriate change with the substance of the
invention maintained that a person skilled in the art can readily
conceive of, of course, falls within the scope of the invention.
Further, to make the illustration in the drawings clearer, the
width, thickness, shape, and other factors of each portion are
diagrammatically drawn as compared with those in an actual aspect
in some cases, but such a diagrammatically drawn portion is
presented only by way of example and is not intended to limit the
interpretation of the invention. In the present specification and
drawings, the same element having been described in a figure having
been shown has the same reference character and will not be
described in detail as appropriate in some cases.
[0020] Further, in the present embodiment, when a positional
relationship between a component and another component is defined,
the words "on" and "below" suggest not only a case where the
another component is disposed immediately on or below the
component, but also a case where the component is disposed on or
below the another component with a third component interposed
therebetween.
[Overview of Display Device]
[0021] An overview of a display device 100 according to the present
embodiment will first be described with reference to FIGS. 1 and 2.
FIG. 1 is a perspective view of the display device in the present
embodiment, and FIG. 2 is a plan view of the display device in the
present embodiment.
[0022] The display device 100 in the present embodiment includes a
substrate 10, which has a display area A, where a plurality of
pixels P are each provided with a light emitting element and the
pixels P are arranged in a matrix, a counter substrate 20, which
faces the substrate 10, and a driver IC 30 (integrated circuit) and
an FPC (flexible printed circuits) 40, which are provided in an
exposed area of the substrate 10, as shown in FIGS. 1 and 2. The
substrate 10 is divided into the display area A and a peripheral
area B, which is located around the display area A. The pixels P
are arranged in a matrix in the display area A of the substrate 10,
and each of the plurality of pixels P is provided with a pixel
circuit that will be described in the present embodiment. The FPC
40 is provided with a terminal section 50, which is connected to a
controller circuit that controls a drive circuit. In the present
embodiment, to make the display device 100 flexible, the substrate
10 is formed of a substrate having flexibility. The substrate 10
may be made, for example, of a polyimide resin.
[0023] With reference to FIG. 2, in the display area A, gate wiring
lines 61 are arranged in an X direction (lateral direction) in FIG.
2, and signal lines 62 and power supply lines 63 are arranged in a
Y direction (longitudinal direction) in FIG. 2, with the gate
wiring lines 61 and the signal lines 62/power supply lines 63
arranged in a matrix. The pixels P correspond to the areas
surrounded by the gate wiring lines 61, the signal lines 62, and
the power supply lines 63. In FIG. 2, the pixels P are so drawn not
as to coincide with the areas surrounded by the gate wiring lines
61, the signal lines 62, and the power supply lines 63 for ease of
illustration, but the pixel areas may overlap with the wiring lines
in a plan view.
[Circuit Diagram of Pixel]
[0024] The pixel circuit in the present embodiment will next be
described with reference to FIG. 3.
[0025] The pixel circuit in the present embodiment is formed of a
capacitor C, a TFT (thin film transistor) 1 and a TFT 2, a gate
wiring line Vgate, a signal line Vsig, and a power supply line Vdd,
as shown in FIG. 3. The gate of the TFT 2 is connected to the gate
wiring line Vgate, the source of the TFT 2 is connected to the
signal line Vsig, and the drain of the TFT 2 is connected to one
end of the capacitor C and the gate of the TFT 1. When
predetermined voltage is applied to the gate of the TFT 2, the TFT
2 provides the gate of the TFT 1 with potential according to the
signal line Vsig. The voltage between the gate and the source of
the TFT 1 is maintained by the capacitor C, and the TFT 1 supplies
the anode of an OLED (organic light emitting diode) with current
corresponding to the charge in the capacitor C via the power supply
line Vdd. The cathode of the OLED is connected to a ground
electrode or a negative-potential electrode.
[Configuration of Pixel]
[0026] The structure of each of the pixels P in the present
embodiment will next be described with reference to FIG. 4. FIG. 4
is a plan transparent view of the display device viewed from the
side facing the display area of the display device and shows an
area where one pixel P is disposed.
[0027] As shown in FIG. 4, in the pixel P, a low-temperature
polysilicon (LTPS) layer 21, a semiconductor layer 22, and an
electrode layer 35 are formed on the same insulating layer. The
LTPS layer 21 serves as a channel semiconductor layer of a TFT that
supplies the OLED with current via the power supply line 63, and
the TFT corresponds to the TFT 1 in the circuit diagram of FIG. 3.
The LTPS layer 21 may be replaced with a layer made of any of a
variety of types of polycrystalline silicon.
[0028] The semiconductor layer 22 serves as a channel semiconductor
layer of a TFT that provides the capacitor C with potential
according to the signal line 62, and the TFT corresponds to the TFT
2 in the circuit diagram of FIG. 3. The semiconductor layer 22 may
be made, for example, of an oxide semiconductor containing, indium,
zinc, tin, orgallium or polysilicon. The semiconductor layer 22 is
formed of a semiconductor layer 22a, which extends in the X
direction and forms the source of the TFT 2, and a semiconductor
layer 22b, which extends in the Y direction and forms the drain of
the TFT 2.
[0029] The combination of the TFT 1 made of a low-temperature
polysilicon and the TFT 2 made of an oxide semiconductor is
presented by way of example. Instead, the combination of the TFT 1
made of an oxide semiconductor and the TFT 2 made of a
low-temperature polysilicon may be employed. Still instead, each of
the TFT 1 and the TFT 2 may be made of a low-temperature
polysilicon or an oxide semiconductor.
[0030] In FIG. 4, the gate wiring lines 61 are linearly formed in
the X direction (lateral direction) and each has an area where the
gate wiring line 61 overlaps with the semiconductor layer 22b, and
part of the gate wiring line 61 extends in the Y direction
(longitudinal direction) to form an area that overlaps with the
semiconductor layer 22a. In the present embodiment described in the
following sections, the gate wiring line 61 is divided into the
following portions: the area that extends in the X direction and
does not overlap with the semiconductor layer 22 is defined as a
gate wiring line 61a; the area that includes the area overlapping
with the semiconductor layer 22a is defined as a gate electrode
61b; and the area that includes the area overlapping with the
semiconductor layer 22b is defined as a gate electrode 61c.
[0031] The electrode layer 35 is electrically connected to the
power supply line 63 and forms one end of the capacitor C in the
circuit diagram of FIG. 3. An electrode layer 36 is electrically
connected to the drain of the TFT 2 via a jumper wiring line 64 and
forms the other end of the capacitor C. The electrodes layer 35 and
36, specifically, portions thereof facing each other with an
insulating layer interposed therebetween form the capacitor C.
[0032] The signal line 62 is so formed as to extend in the Y
direction in FIG. 4 in parallel to the power supply line 63. The
semiconductor layer 22a and the signal line 62 overlap with each
other and are electrically connected to each other via a via 75,
which is formed in the area where the semiconductor layer 22a and
the signal line 62 overlap with each other. The semiconductor layer
22b is electrically connected to the jumper wiring line 64 via a
via 77, and the electrode layer 36 is electrically connected to the
jumper wiring line 64 via a via 78.
[0033] The TFT 2 has a gate formed in the area where the gate
electrode 61b and the semiconductor layer 22a overlap with each
other and another gate in the area where the gate electrode 61c and
the semiconductor layer 22b overlap with each other (each of the
areas is also called a TFT channel section), and the vias 75 and 77
serve as the source electrode and the drain electrode of the TFT 2,
respectively. As described above, the present embodiment is
described with reference to the TFT2 having two gates or what is
called a double-gate transistor, but not necessarily. The number of
gates may be one or three or more.
[0034] The gate of the TFT1 is formed in the area where the LTPS
layer 21 and the electrode layer 36 overlap with each other. The
LTPS layer 21 and the power supply line 63 are electrically
connected to each other via a via 74, and an anode contact hole 71
is formed in the LTPS layer 21, so that predetermined current is
supplied via the power supply line 63 to the OLED.
[0035] The electrode layers 35 and 36 form the areas facing each
other with an insulating layer interposed therebetween to form the
capacitor C. In the view of the circuit diagram of FIG. 3, the
electrode layer 35 forms the electrode of the capacitor C on the
side facing the power supply line Vdd, and the electrode layer 36
forms the electrode of the capacitor C on the side facing the drain
of the TFT 2 and the gate of the TFT 1. The electrode layer 36 is
electrically connected to the jumper wiring line 64 via the via 78,
so that the electrode layer 36 is electrically connected to the
semiconductor layer 22b. The electrode layer 35 has an area that
overlaps with the power supply line 63 and is electrically
connected to the power supply line 63 via a via 76 formed in the
area.
[0036] Although not shown, a planarizing layer and the anode of the
OLED are formed on the signal line 62, the power supply line 63,
and the jumper wiring line 64. The anode is formed in the pixel
area surrounded by the gate wiring lines 61 on the upper and lower
sides and the signal line 62 and the power supply line 63 on the
left and right sides. A bank is formed around the anode and around
the anode contact hole 71. As described above, in the present
embodiment, the two different types of TFT, the TFT 1 having a
channel semiconductor layer made of LTPS and the TFT 2 having a
channel semiconductor layer made of an oxide semiconductor, are
disposed on the same insulating layer, as shown in FIG. 4.
[Structure of Gate Electrode]
[0037] The structure of the gate electrode 61b in the present
embodiment will next be described in detail with reference to FIGS.
5 and 6. FIG. 5 is an enlarged view of the area surrounded by a
broken line D in FIG. 4. FIG. 6 is a cross-sectional view taken
along the line VI-VI in FIGS. 4 and 5. FIG. 6 shows a cross section
of the gate electrode 61b and the semiconductor layer 22a, which
form one of the gates of the double-gate TFT 2 and will be
described below. The other gate of the TFT 2 that is formed by the
gate electrode 61c and the semiconductor layer 22b has the same
cross-sectional shape and will therefore not be illustrated. A
device including the transistor TFT2, the gate wiring line 61a, and
the substrate 10 (see FIG. 1 and other figures) shown in FIG. 5 is
defined as a semiconductor device. The display device 100 includes
the semiconductor device and is so defined as a device having the
display area A, which has the plurality of pixels P arranged on the
substrate 10, with each of the plurality of pixels P including the
transistor TFT2 and the gate wiring line 61a shown in FIG. 5.
[0038] As shown in FIG. 5, the gate wiring line 61a is so formed as
to extend in the X direction, the gate electrode 61b is so formed
as to be connected to the gate wiring line 61a and extend in the Y
direction in such a way that the gate electrode 61b overlaps with
the semiconductor layer 22a, and the gate electrode 61c is so
formed as to be connected to the gate wiring line 61a and extend in
the X direction in such a way that the gate electrode 61c overlaps
with the semiconductor layer 22b. The gates of the TFT 2 are formed
in the area where the gate electrode 61b overlaps with the
semiconductor layer 22a and in the area where the gate electrode
61c overlaps with the semiconductor layer 22b. The gate electrode
61b has a planar shape having a lengthwise axis extending in the Y
direction and a widthwise axis perpendicular to the lengthwise
axis. Similarly, the area where the gate electrode 61b overlaps
with the semiconductor layer 22a has a planar shape having a
lengthwise axis extending in the Y direction and a widthwise axis
perpendicular to the lengthwise axis. The gate electrode 61c has a
planar shape having a lengthwise axis extending in the X direction
and a widthwise axis perpendicular to the lengthwise axis.
Similarly, the area where the gate electrode 61c overlaps with the
semiconductor layer 22b has a planar shape having a lengthwise axis
extending in the X direction and a widthwise axis perpendicular to
the lengthwise axis.
[0039] A gate insulating film 23 is so provided on the
semiconductor layer 22a as to cover the semiconductor layer 22a, as
shown in FIG. 6. The gate wiring line 61a and the gate electrode
61b are provided on the gate insulating film 23, and the gate
insulating film 23 is so provided as to be sandwiched between the
semiconductor layer 22a and the gate electrode 61b.
[0040] In the present embodiment, to make the display device 100
flexible, the substrate 10, on which the gate electrode 61b and
other components are provided, is formed of a substrate having
flexibility. The TFT 2 is formed in a bendable area of the
substrate 10. In general, among the gate electrodes 61b and 61c,
the semiconductor layer 22, and the gate insulating film 23, which
form the TFT 2, each of the gate electrodes 61b and 61c has the
largest film thickness, and it is therefore believed that the gate
electrodes 61b and 61c are prone to a mechanical defect and other
disadvantageous phenomena due to bending stress induced therein.
Therefore, when the substrate 10 is repeatedly bent, the
characteristics of the TFT 2 could undesirably change due to the
bending stress induced in the gate electrodes 61b and 61c. For
example, if the threshold voltage, starting characteristics, and
other characteristics of the TFT 2 change, the changes affect image
display operation, possibly resulting in decrease in the life of
the display device 100.
[0041] To avoid the situation described above, in the present
embodiment, a step is formed in a surface of the gate electrode 61b
on a side opposite the gate insulating film 23 so that the gate
electrode 61b has a recess 612a, as shown in FIG. 6. In other
words, the gate electrode 61b has an area that is thinner than the
gate wiring line 61a and located in the area where the gate
electrode 61b overlaps with the semiconductor layer 22a. The recess
612a is provided at least in the area where the gate electrode 61b
overlaps with the semiconductor layer 22a. Specifically, the recess
612a is so configured that H>h is satisfied, where H represents
the thickness of the gate wiring line 61a, and h represents the
thickness of the reduced thickness area (recess 612a) of the gate
electrode 61b. Although not illustrated in the form of a
cross-sectional view, the gate electrode 61c also has a recess 612a
in the area where the gate electrode 61c overlaps with the
semiconductor layer 22b, as in the case of the gate electrode
61b.
[0042] As described above, each of the gate electrodes 61b and 61c
formed in the bendable area of the substrate 10 is configured to
have a reduced thickness area, whereby stress induced in the gate
electrodes 61b and 61c when the substrate 10 is bent can be lowered
with no limitation on the arrangement of the TFT 2. As a result,
variation in the characteristics of the TFT 2 can be suppressed.
Further, in the present embodiment, low resistance of the gate
wiring line 61a can be maintained because the thickness of the gate
wiring line 61a is not reduced.
[0043] In a case where the configuration described above is
employed and the TFT 2 is so arranged that the direction in which
the substrate 10 is bent coincides with the direction in which the
widthwise axis of the area where the gate electrode 61b overlaps
with the semiconductor layer 22a is bent, variation in the
characteristics of the TFT 2 that occurs in the gate electrode 61b
can be further suppressed. In the present embodiment, the entire
recesses 612a of the gate electrodes 61b and 61c overlap with the
semiconductor layers 22a and 22b, respectively, but not
necessarily. The recesses 612a may instead be so formed that at
least part thereof overlaps with the semiconductor layers 22a and
22b. Further, the number of recesses 612a provided in each of the
gate electrodes 61b and 61c is not limited to one. For example, a
plurality of recesses 612a may be formed alongside in the
lengthwise axis direction of the gate electrodes 61b and 61c
(direction in which gate electrodes 61b and 61c extend).
[0044] Further, as shown in FIG. 6, the gate wiring line 61 is
formed of an aluminum layer 611 and a titanium layer 612 in the
present embodiment. The reduced thickness portion of the gate
electrode 61b is formed only of the aluminum layer 611. Aluminum
(Al) is a metal that excels in extensibility and crack resistance
against force due to bending stress, as compared with titanium
(Ti). As described above, not only simply forming the reduced
thickness portion in the gate electrode 61b but also forming the
reduced thickness portion of the gate electrode 61b by using only
the aluminum layer 611 allows the stress induced in the gate
electrode 61b when the substrate 10 is bent to be lowered. In the
present embodiment, the thickness of the aluminum layer 611 is set
at about 250 nm, and the thickness of the titanium layer 612 is set
at about 150 nm.
[Process of Reducing Thickness of Gate Electrode]
[0045] The process of reducing the thickness of the gate electrodes
in the present embodiment will next be described with reference to
FIGS. 7A to 7D. FIGS. 7A to 7D describe the process of reducing the
thickness of the gate electrodes in the present embodiment and show
cross sections corresponding to the VI-VI cross section in FIGS. 4
and 5. In the following description, the process of reducing the
thickness of the gate electrode 61b will be described, and the
process of reducing the thickness of the gate electrode 61c will
not be described because the gate electrodes 61b and 61c are
processed in the same manner.
[0046] The insulating film 23 is first so formed as to cover the
semiconductor layer 22a. Further, the aluminum layer 611 is formed
on the insulating film 23, and the titanium layer 612 is formed on
the aluminum layer 611. The aluminum layer 611 and the titanium
layer 612 form the gate wiring line 61 (gate wiring line 61a and
gate electrode 61b) described above. A resist 70 is then applied
onto the titanium layer 612 to achieve the state shown in FIG.
7A.
[0047] A resist pattern that conforms to the gate wiring line 61 is
then formed by light exposure . In this process, a recess 70a is so
formed that the thickness of the resist that will form the gate
electrode 61b, which is so provided as to overlap with the
semiconductor layer 22a, is smaller than the thickness of the other
portion, for example, in photolithography using a halftone mask to
achieve the state shown in FIG. 7B. In this state, the gate wiring
line 61 is patterned in accordance with the shape of the resist 70.
Part of the resist 70 including the reduced thickness portion is
then removed by ashing using oxygen, so that the resist in the
portion corresponding to the recess 70a is taken away, and the
titanium layer 612 is exposed.
[0048] Only the titanium layer 612 of the gate electrode 61b in the
reduced thickness portion is then removed by dry etching using a
fluorine radical. That is, only the aluminum layer 611 is left as
the reduced thickness portion of the gate electrode 61b to achieve
the state shown in FIG. 7C. Since an aluminum fluoride has a high
boiling point, etching using a fluorine radical allows selective
removal of only titanium.
[0049] The resist is then completely removed by etching using
oxygen. After the steps described above, the thickness of only part
of the gate electrode 61b is reduced, and the recess 612a can thus
be formed, as shown in FIGS. 7D and 6.
[0050] In the present embodiment, the TFT 2 is a top-gate TFT. The
TFT 2 may instead be a TFT having a different structure, for
example, a bottom-gate TFT.
[0051] While there have been described what are at present
considered to be certain embodiments of the invention, it will be
understood that various modifications may be made thereto, and it
is intended that the appended claims cover all such modifications
as fall within the true spirit and scope of the invention.
* * * * *